31977 lines
2.8 MiB
31977 lines
2.8 MiB
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Wed Jul 8 03:34:12 2026
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| Host : fedora running 64-bit unknown
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| Command : report_timing -delay_type max -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/timing_setup_paths.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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Timing Report
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Slack (MET) : 0.167ns (required time - arrival time)
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Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: ext_ram_data[18]
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(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Max at Slow Process Corner
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Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%))
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Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
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Output Delay: 0.300ns
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Clock Path Skew: -3.858ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
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Source Clock Delay (SCD): -2.418ns
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Clock Pessimism Removal (CPR): -0.601ns
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Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.122ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.858 -2.418
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SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
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SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
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net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
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SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
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SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
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net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
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SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
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SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
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net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
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SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
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SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
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net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
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SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
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SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
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net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0
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SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0
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SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
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0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
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net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18]
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SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0
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SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O
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net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1
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SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4
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SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O
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net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
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SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
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SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
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net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I
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AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
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AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
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net (fo=1, unset) 0.000 13.188 ext_ram_data[18]
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AB17 r ext_ram_data[18] (INOUT)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 20.000 20.000 r
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clock source latency -5.674 14.326
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propagated clock network latency
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0.000 14.326
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clock pessimism -0.601 13.725
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clock uncertainty -0.071 13.654
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output delay -0.300 13.354
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-------------------------------------------------------------------
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required time 13.354
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arrival time -13.188
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-------------------------------------------------------------------
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slack 0.167
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Slack (MET) : 0.167ns (required time - arrival time)
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Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: ext_ram_data[18]
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(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Max at Slow Process Corner
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Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%))
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Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
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Output Delay: 0.300ns
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Clock Path Skew: -3.858ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
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Source Clock Delay (SCD): -2.418ns
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Clock Pessimism Removal (CPR): -0.601ns
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Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.122ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.858 -2.418
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SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
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SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
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net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
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SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
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SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
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net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
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SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
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SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
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net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
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SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
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SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
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net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
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SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
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SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
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net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0
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SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0
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SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
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0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
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net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18]
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SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0
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SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O
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net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1
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SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4
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SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O
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net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
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SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
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SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
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net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I
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AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
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AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
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net (fo=1, unset) 0.000 13.188 ext_ram_data[18]
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AB17 r ext_ram_data[18] (INOUT)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 20.000 20.000 r
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clock source latency -5.674 14.326
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propagated clock network latency
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0.000 14.326
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clock pessimism -0.601 13.725
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clock uncertainty -0.071 13.654
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output delay -0.300 13.354
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-------------------------------------------------------------------
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required time 13.354
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arrival time -13.188
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-------------------------------------------------------------------
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slack 0.167
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Slack (MET) : 0.167ns (required time - arrival time)
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Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: ext_ram_data[18]
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(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Max at Slow Process Corner
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Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%))
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Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
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Output Delay: 0.300ns
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Clock Path Skew: -3.858ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
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Source Clock Delay (SCD): -2.418ns
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Clock Pessimism Removal (CPR): -0.601ns
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Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.122ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.858 -2.418
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SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
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SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
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net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
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SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
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SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
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net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
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SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
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SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
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net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
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SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
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SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
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net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
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SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
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SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
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net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0
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SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0
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SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
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0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
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net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18]
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SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0
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SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O
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net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1
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SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4
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SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O
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net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
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SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
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SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
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net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I
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AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
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AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
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net (fo=1, unset) 0.000 13.188 ext_ram_data[18]
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AB17 r ext_ram_data[18] (INOUT)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.188
|
|
-------------------------------------------------------------------
|
|
slack 0.167
|
|
|
|
Slack (MET) : 0.167ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0
|
|
SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18]
|
|
SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0
|
|
SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O
|
|
net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1
|
|
SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4
|
|
SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O
|
|
net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.188 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.188
|
|
-------------------------------------------------------------------
|
|
slack 0.167
|
|
|
|
Slack (MET) : 0.167ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0
|
|
SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18]
|
|
SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0
|
|
SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O
|
|
net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1
|
|
SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4
|
|
SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O
|
|
net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.188 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.188
|
|
-------------------------------------------------------------------
|
|
slack 0.167
|
|
|
|
Slack (MET) : 0.167ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0
|
|
SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18]
|
|
SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0
|
|
SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O
|
|
net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1
|
|
SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4
|
|
SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O
|
|
net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.188 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.188
|
|
-------------------------------------------------------------------
|
|
slack 0.167
|
|
|
|
Slack (MET) : 0.167ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0
|
|
SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18]
|
|
SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0
|
|
SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O
|
|
net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1
|
|
SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4
|
|
SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O
|
|
net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.188 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.188
|
|
-------------------------------------------------------------------
|
|
slack 0.167
|
|
|
|
Slack (MET) : 0.167ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0
|
|
SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18]
|
|
SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0
|
|
SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O
|
|
net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1
|
|
SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4
|
|
SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O
|
|
net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.188 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.188
|
|
-------------------------------------------------------------------
|
|
slack 0.167
|
|
|
|
Slack (MET) : 0.167ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0
|
|
SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18]
|
|
SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0
|
|
SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O
|
|
net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1
|
|
SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4
|
|
SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O
|
|
net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.188 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.188
|
|
-------------------------------------------------------------------
|
|
slack 0.167
|
|
|
|
Slack (MET) : 0.167ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0
|
|
SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O
|
|
net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18]
|
|
SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0
|
|
SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O
|
|
net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1
|
|
SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4
|
|
SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O
|
|
net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18]
|
|
SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0
|
|
SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O
|
|
net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I
|
|
AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I
|
|
AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.188 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.188
|
|
-------------------------------------------------------------------
|
|
slack 0.167
|
|
|
|
Slack (MET) : 0.284ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0
|
|
SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O
|
|
net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22]
|
|
SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0
|
|
SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O
|
|
net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1
|
|
SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4
|
|
SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O
|
|
net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22]
|
|
SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0
|
|
SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O
|
|
net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I
|
|
Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I
|
|
Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.070 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.070
|
|
-------------------------------------------------------------------
|
|
slack 0.284
|
|
|
|
Slack (MET) : 0.284ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0
|
|
SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O
|
|
net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22]
|
|
SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0
|
|
SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O
|
|
net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1
|
|
SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4
|
|
SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O
|
|
net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22]
|
|
SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0
|
|
SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O
|
|
net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I
|
|
Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I
|
|
Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.070 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.070
|
|
-------------------------------------------------------------------
|
|
slack 0.284
|
|
|
|
Slack (MET) : 0.284ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0
|
|
SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O
|
|
net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22]
|
|
SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0
|
|
SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O
|
|
net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1
|
|
SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4
|
|
SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O
|
|
net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22]
|
|
SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0
|
|
SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O
|
|
net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I
|
|
Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I
|
|
Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.070 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.070
|
|
-------------------------------------------------------------------
|
|
slack 0.284
|
|
|
|
Slack (MET) : 0.284ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0
|
|
SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O
|
|
net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22]
|
|
SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0
|
|
SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O
|
|
net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1
|
|
SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4
|
|
SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O
|
|
net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22]
|
|
SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0
|
|
SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O
|
|
net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I
|
|
Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I
|
|
Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.070 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.070
|
|
-------------------------------------------------------------------
|
|
slack 0.284
|
|
|
|
Slack (MET) : 0.284ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0
|
|
SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O
|
|
net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22]
|
|
SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0
|
|
SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O
|
|
net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1
|
|
SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4
|
|
SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O
|
|
net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22]
|
|
SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0
|
|
SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O
|
|
net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I
|
|
Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I
|
|
Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.070 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.070
|
|
-------------------------------------------------------------------
|
|
slack 0.284
|
|
|
|
Slack (MET) : 0.284ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0
|
|
SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O
|
|
net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22]
|
|
SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0
|
|
SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O
|
|
net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1
|
|
SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4
|
|
SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O
|
|
net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22]
|
|
SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0
|
|
SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O
|
|
net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I
|
|
Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I
|
|
Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.070 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.070
|
|
-------------------------------------------------------------------
|
|
slack 0.284
|
|
|
|
Slack (MET) : 0.284ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0
|
|
SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O
|
|
net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22]
|
|
SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0
|
|
SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O
|
|
net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1
|
|
SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4
|
|
SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O
|
|
net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22]
|
|
SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0
|
|
SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O
|
|
net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I
|
|
Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I
|
|
Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.070 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.070
|
|
-------------------------------------------------------------------
|
|
slack 0.284
|
|
|
|
Slack (MET) : 0.284ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0
|
|
SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O
|
|
net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22]
|
|
SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0
|
|
SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O
|
|
net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1
|
|
SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4
|
|
SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O
|
|
net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22]
|
|
SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0
|
|
SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O
|
|
net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I
|
|
Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I
|
|
Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.070 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.070
|
|
-------------------------------------------------------------------
|
|
slack 0.284
|
|
|
|
Slack (MET) : 0.284ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0
|
|
SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O
|
|
net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22]
|
|
SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0
|
|
SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O
|
|
net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1
|
|
SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4
|
|
SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O
|
|
net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22]
|
|
SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0
|
|
SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O
|
|
net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I
|
|
Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I
|
|
Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.070 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.070
|
|
-------------------------------------------------------------------
|
|
slack 0.284
|
|
|
|
Slack (MET) : 0.284ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5
|
|
SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O
|
|
net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0
|
|
SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0
|
|
SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O)
|
|
0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O
|
|
net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22]
|
|
SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0
|
|
SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O
|
|
net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1
|
|
SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4
|
|
SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O
|
|
net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22]
|
|
SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0
|
|
SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O
|
|
net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I
|
|
Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I
|
|
Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.070 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.070
|
|
-------------------------------------------------------------------
|
|
slack 0.284
|
|
|
|
Slack (MET) : 0.377ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.977 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.977
|
|
-------------------------------------------------------------------
|
|
slack 0.377
|
|
|
|
Slack (MET) : 0.377ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.977 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.977
|
|
-------------------------------------------------------------------
|
|
slack 0.377
|
|
|
|
Slack (MET) : 0.377ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.977 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.977
|
|
-------------------------------------------------------------------
|
|
slack 0.377
|
|
|
|
Slack (MET) : 0.377ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.977 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.977
|
|
-------------------------------------------------------------------
|
|
slack 0.377
|
|
|
|
Slack (MET) : 0.377ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.977 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.977
|
|
-------------------------------------------------------------------
|
|
slack 0.377
|
|
|
|
Slack (MET) : 0.377ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.977 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.977
|
|
-------------------------------------------------------------------
|
|
slack 0.377
|
|
|
|
Slack (MET) : 0.377ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.977 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.977
|
|
-------------------------------------------------------------------
|
|
slack 0.377
|
|
|
|
Slack (MET) : 0.377ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.977 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.977
|
|
-------------------------------------------------------------------
|
|
slack 0.377
|
|
|
|
Slack (MET) : 0.377ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.977 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.977
|
|
-------------------------------------------------------------------
|
|
slack 0.377
|
|
|
|
Slack (MET) : 0.377ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.977 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.977
|
|
-------------------------------------------------------------------
|
|
slack 0.377
|
|
|
|
Slack (MET) : 0.414ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.940 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.940
|
|
-------------------------------------------------------------------
|
|
slack 0.414
|
|
|
|
Slack (MET) : 0.414ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.940 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.940
|
|
-------------------------------------------------------------------
|
|
slack 0.414
|
|
|
|
Slack (MET) : 0.414ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.940 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.940
|
|
-------------------------------------------------------------------
|
|
slack 0.414
|
|
|
|
Slack (MET) : 0.414ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.940 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.940
|
|
-------------------------------------------------------------------
|
|
slack 0.414
|
|
|
|
Slack (MET) : 0.414ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.940 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.940
|
|
-------------------------------------------------------------------
|
|
slack 0.414
|
|
|
|
Slack (MET) : 0.414ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.940 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.940
|
|
-------------------------------------------------------------------
|
|
slack 0.414
|
|
|
|
Slack (MET) : 0.414ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.940 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.940
|
|
-------------------------------------------------------------------
|
|
slack 0.414
|
|
|
|
Slack (MET) : 0.414ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.940 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.940
|
|
-------------------------------------------------------------------
|
|
slack 0.414
|
|
|
|
Slack (MET) : 0.414ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.940 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.940
|
|
-------------------------------------------------------------------
|
|
slack 0.414
|
|
|
|
Slack (MET) : 0.414ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.940 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.940
|
|
-------------------------------------------------------------------
|
|
slack 0.414
|
|
|
|
Slack (MET) : 0.424ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1
|
|
SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1
|
|
SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1]
|
|
SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1
|
|
SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O
|
|
net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3
|
|
SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2
|
|
SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O
|
|
net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O
|
|
net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I
|
|
L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I
|
|
L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.931 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.931
|
|
-------------------------------------------------------------------
|
|
slack 0.424
|
|
|
|
Slack (MET) : 0.424ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1
|
|
SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1
|
|
SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1]
|
|
SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1
|
|
SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O
|
|
net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3
|
|
SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2
|
|
SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O
|
|
net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O
|
|
net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I
|
|
L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I
|
|
L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.931 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.931
|
|
-------------------------------------------------------------------
|
|
slack 0.424
|
|
|
|
Slack (MET) : 0.424ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1
|
|
SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1
|
|
SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1]
|
|
SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1
|
|
SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O
|
|
net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3
|
|
SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2
|
|
SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O
|
|
net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O
|
|
net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I
|
|
L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I
|
|
L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.931 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.931
|
|
-------------------------------------------------------------------
|
|
slack 0.424
|
|
|
|
Slack (MET) : 0.424ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1
|
|
SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1
|
|
SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1]
|
|
SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1
|
|
SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O
|
|
net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3
|
|
SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2
|
|
SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O
|
|
net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O
|
|
net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I
|
|
L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I
|
|
L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.931 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.931
|
|
-------------------------------------------------------------------
|
|
slack 0.424
|
|
|
|
Slack (MET) : 0.424ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1
|
|
SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1
|
|
SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1]
|
|
SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1
|
|
SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O
|
|
net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3
|
|
SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2
|
|
SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O
|
|
net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O
|
|
net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I
|
|
L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I
|
|
L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.931 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.931
|
|
-------------------------------------------------------------------
|
|
slack 0.424
|
|
|
|
Slack (MET) : 0.424ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1
|
|
SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1
|
|
SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1]
|
|
SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1
|
|
SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O
|
|
net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3
|
|
SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2
|
|
SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O
|
|
net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O
|
|
net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I
|
|
L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I
|
|
L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.931 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.931
|
|
-------------------------------------------------------------------
|
|
slack 0.424
|
|
|
|
Slack (MET) : 0.424ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1
|
|
SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1
|
|
SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1]
|
|
SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1
|
|
SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O
|
|
net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3
|
|
SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2
|
|
SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O
|
|
net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O
|
|
net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I
|
|
L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I
|
|
L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.931 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.931
|
|
-------------------------------------------------------------------
|
|
slack 0.424
|
|
|
|
Slack (MET) : 0.424ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1
|
|
SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1
|
|
SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1]
|
|
SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1
|
|
SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O
|
|
net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3
|
|
SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2
|
|
SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O
|
|
net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O
|
|
net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I
|
|
L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I
|
|
L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.931 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.931
|
|
-------------------------------------------------------------------
|
|
slack 0.424
|
|
|
|
Slack (MET) : 0.424ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1
|
|
SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1
|
|
SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1]
|
|
SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1
|
|
SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O
|
|
net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3
|
|
SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2
|
|
SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O
|
|
net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O
|
|
net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I
|
|
L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I
|
|
L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.931 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.931
|
|
-------------------------------------------------------------------
|
|
slack 0.424
|
|
|
|
Slack (MET) : 0.424ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1
|
|
SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1
|
|
SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1]
|
|
SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1
|
|
SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O
|
|
net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3
|
|
SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2
|
|
SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O
|
|
net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O
|
|
net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I
|
|
L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I
|
|
L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.931 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.931
|
|
-------------------------------------------------------------------
|
|
slack 0.424
|
|
|
|
Slack (MET) : 0.431ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20]
|
|
SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1
|
|
SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O
|
|
net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1
|
|
SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4
|
|
SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O
|
|
net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.923 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.923
|
|
-------------------------------------------------------------------
|
|
slack 0.431
|
|
|
|
Slack (MET) : 0.431ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20]
|
|
SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1
|
|
SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O
|
|
net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1
|
|
SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4
|
|
SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O
|
|
net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.923 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.923
|
|
-------------------------------------------------------------------
|
|
slack 0.431
|
|
|
|
Slack (MET) : 0.431ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20]
|
|
SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1
|
|
SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O
|
|
net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1
|
|
SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4
|
|
SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O
|
|
net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.923 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.923
|
|
-------------------------------------------------------------------
|
|
slack 0.431
|
|
|
|
Slack (MET) : 0.431ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20]
|
|
SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1
|
|
SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O
|
|
net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1
|
|
SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4
|
|
SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O
|
|
net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.923 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.923
|
|
-------------------------------------------------------------------
|
|
slack 0.431
|
|
|
|
Slack (MET) : 0.431ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20]
|
|
SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1
|
|
SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O
|
|
net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1
|
|
SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4
|
|
SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O
|
|
net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.923 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.923
|
|
-------------------------------------------------------------------
|
|
slack 0.431
|
|
|
|
Slack (MET) : 0.431ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20]
|
|
SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1
|
|
SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O
|
|
net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1
|
|
SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4
|
|
SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O
|
|
net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.923 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.923
|
|
-------------------------------------------------------------------
|
|
slack 0.431
|
|
|
|
Slack (MET) : 0.431ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20]
|
|
SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1
|
|
SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O
|
|
net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1
|
|
SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4
|
|
SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O
|
|
net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.923 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.923
|
|
-------------------------------------------------------------------
|
|
slack 0.431
|
|
|
|
Slack (MET) : 0.431ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20]
|
|
SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1
|
|
SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O
|
|
net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1
|
|
SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4
|
|
SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O
|
|
net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.923 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.923
|
|
-------------------------------------------------------------------
|
|
slack 0.431
|
|
|
|
Slack (MET) : 0.431ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20]
|
|
SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1
|
|
SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O
|
|
net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1
|
|
SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4
|
|
SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O
|
|
net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.923 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.923
|
|
-------------------------------------------------------------------
|
|
slack 0.431
|
|
|
|
Slack (MET) : 0.431ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1
|
|
SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1
|
|
SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O
|
|
net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20]
|
|
SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1
|
|
SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O
|
|
net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1
|
|
SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4
|
|
SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O
|
|
net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20]
|
|
SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0
|
|
SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O
|
|
net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I
|
|
AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I
|
|
AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.923 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.923
|
|
-------------------------------------------------------------------
|
|
slack 0.431
|
|
|
|
Slack (MET) : 0.455ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[25]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T
|
|
AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T
|
|
AC17 OBUFT (TriStatE_obuft_T_O)
|
|
3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.899 ext_ram_data[25]
|
|
AC17 r ext_ram_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.899
|
|
-------------------------------------------------------------------
|
|
slack 0.455
|
|
|
|
Slack (MET) : 0.455ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[25]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T
|
|
AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T
|
|
AC17 OBUFT (TriStatE_obuft_T_O)
|
|
3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.899 ext_ram_data[25]
|
|
AC17 r ext_ram_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.899
|
|
-------------------------------------------------------------------
|
|
slack 0.455
|
|
|
|
Slack (MET) : 0.455ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[25]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T
|
|
AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T
|
|
AC17 OBUFT (TriStatE_obuft_T_O)
|
|
3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.899 ext_ram_data[25]
|
|
AC17 r ext_ram_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.899
|
|
-------------------------------------------------------------------
|
|
slack 0.455
|
|
|
|
Slack (MET) : 0.455ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[25]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T
|
|
AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T
|
|
AC17 OBUFT (TriStatE_obuft_T_O)
|
|
3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.899 ext_ram_data[25]
|
|
AC17 r ext_ram_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.899
|
|
-------------------------------------------------------------------
|
|
slack 0.455
|
|
|
|
Slack (MET) : 0.455ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[25]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T
|
|
AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T
|
|
AC17 OBUFT (TriStatE_obuft_T_O)
|
|
3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.899 ext_ram_data[25]
|
|
AC17 r ext_ram_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.899
|
|
-------------------------------------------------------------------
|
|
slack 0.455
|
|
|
|
Slack (MET) : 0.455ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[25]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T
|
|
AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T
|
|
AC17 OBUFT (TriStatE_obuft_T_O)
|
|
3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.899 ext_ram_data[25]
|
|
AC17 r ext_ram_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.899
|
|
-------------------------------------------------------------------
|
|
slack 0.455
|
|
|
|
Slack (MET) : 0.455ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[25]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T
|
|
AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T
|
|
AC17 OBUFT (TriStatE_obuft_T_O)
|
|
3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.899 ext_ram_data[25]
|
|
AC17 r ext_ram_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.899
|
|
-------------------------------------------------------------------
|
|
slack 0.455
|
|
|
|
Slack (MET) : 0.455ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[25]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T
|
|
AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T
|
|
AC17 OBUFT (TriStatE_obuft_T_O)
|
|
3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.899 ext_ram_data[25]
|
|
AC17 r ext_ram_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.899
|
|
-------------------------------------------------------------------
|
|
slack 0.455
|
|
|
|
Slack (MET) : 0.455ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[25]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T
|
|
AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T
|
|
AC17 OBUFT (TriStatE_obuft_T_O)
|
|
3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.899 ext_ram_data[25]
|
|
AC17 r ext_ram_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.899
|
|
-------------------------------------------------------------------
|
|
slack 0.455
|
|
|
|
Slack (MET) : 0.455ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[25]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T
|
|
AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T
|
|
AC17 OBUFT (TriStatE_obuft_T_O)
|
|
3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.899 ext_ram_data[25]
|
|
AC17 r ext_ram_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.899
|
|
-------------------------------------------------------------------
|
|
slack 0.455
|
|
|
|
Slack (MET) : 0.477ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[28]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1
|
|
SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1
|
|
SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O
|
|
net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28]
|
|
SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0
|
|
SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O
|
|
net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1
|
|
SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3
|
|
SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O
|
|
net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28]
|
|
SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0
|
|
SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O
|
|
net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I
|
|
N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I
|
|
N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.877 base_ram_data[28]
|
|
N22 r base_ram_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.877
|
|
-------------------------------------------------------------------
|
|
slack 0.477
|
|
|
|
Slack (MET) : 0.477ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[28]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1
|
|
SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1
|
|
SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O
|
|
net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28]
|
|
SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0
|
|
SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O
|
|
net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1
|
|
SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3
|
|
SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O
|
|
net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28]
|
|
SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0
|
|
SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O
|
|
net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I
|
|
N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I
|
|
N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.877 base_ram_data[28]
|
|
N22 r base_ram_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.877
|
|
-------------------------------------------------------------------
|
|
slack 0.477
|
|
|
|
Slack (MET) : 0.477ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[28]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1
|
|
SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1
|
|
SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O
|
|
net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28]
|
|
SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0
|
|
SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O
|
|
net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1
|
|
SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3
|
|
SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O
|
|
net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28]
|
|
SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0
|
|
SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O
|
|
net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I
|
|
N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I
|
|
N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.877 base_ram_data[28]
|
|
N22 r base_ram_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.877
|
|
-------------------------------------------------------------------
|
|
slack 0.477
|
|
|
|
Slack (MET) : 0.477ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[28]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1
|
|
SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1
|
|
SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O
|
|
net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28]
|
|
SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0
|
|
SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O
|
|
net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1
|
|
SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3
|
|
SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O
|
|
net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28]
|
|
SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0
|
|
SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O
|
|
net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I
|
|
N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I
|
|
N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.877 base_ram_data[28]
|
|
N22 r base_ram_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.877
|
|
-------------------------------------------------------------------
|
|
slack 0.477
|
|
|
|
Slack (MET) : 0.477ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[28]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1
|
|
SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1
|
|
SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O
|
|
net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28]
|
|
SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0
|
|
SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O
|
|
net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1
|
|
SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3
|
|
SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O
|
|
net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28]
|
|
SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0
|
|
SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O
|
|
net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I
|
|
N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I
|
|
N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.877 base_ram_data[28]
|
|
N22 r base_ram_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.877
|
|
-------------------------------------------------------------------
|
|
slack 0.477
|
|
|
|
Slack (MET) : 0.477ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[28]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1
|
|
SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1
|
|
SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O
|
|
net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28]
|
|
SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0
|
|
SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O
|
|
net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1
|
|
SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3
|
|
SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O
|
|
net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28]
|
|
SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0
|
|
SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O
|
|
net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I
|
|
N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I
|
|
N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.877 base_ram_data[28]
|
|
N22 r base_ram_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.877
|
|
-------------------------------------------------------------------
|
|
slack 0.477
|
|
|
|
Slack (MET) : 0.477ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[28]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1
|
|
SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1
|
|
SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O
|
|
net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28]
|
|
SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0
|
|
SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O
|
|
net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1
|
|
SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3
|
|
SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O
|
|
net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28]
|
|
SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0
|
|
SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O
|
|
net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I
|
|
N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I
|
|
N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.877 base_ram_data[28]
|
|
N22 r base_ram_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.877
|
|
-------------------------------------------------------------------
|
|
slack 0.477
|
|
|
|
Slack (MET) : 0.477ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[28]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1
|
|
SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1
|
|
SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O
|
|
net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28]
|
|
SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0
|
|
SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O
|
|
net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1
|
|
SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3
|
|
SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O
|
|
net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28]
|
|
SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0
|
|
SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O
|
|
net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I
|
|
N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I
|
|
N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.877 base_ram_data[28]
|
|
N22 r base_ram_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.877
|
|
-------------------------------------------------------------------
|
|
slack 0.477
|
|
|
|
Slack (MET) : 0.477ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[28]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1
|
|
SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1
|
|
SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O
|
|
net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28]
|
|
SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0
|
|
SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O
|
|
net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1
|
|
SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3
|
|
SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O
|
|
net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28]
|
|
SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0
|
|
SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O
|
|
net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I
|
|
N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I
|
|
N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.877 base_ram_data[28]
|
|
N22 r base_ram_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.877
|
|
-------------------------------------------------------------------
|
|
slack 0.477
|
|
|
|
Slack (MET) : 0.477ns (required time - arrival time)
|
|
Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[28]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%))
|
|
Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.418ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.858 -2.418
|
|
SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C
|
|
SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q
|
|
net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1]
|
|
SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2
|
|
SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O
|
|
net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5]
|
|
SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1
|
|
SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O
|
|
net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0
|
|
SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4
|
|
SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O
|
|
net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3]
|
|
SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3
|
|
SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O
|
|
net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1
|
|
SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1
|
|
SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O)
|
|
0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O
|
|
net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28]
|
|
SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0
|
|
SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O
|
|
net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1
|
|
SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3
|
|
SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O
|
|
net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28]
|
|
SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0
|
|
SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O
|
|
net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I
|
|
N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I
|
|
N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.877 base_ram_data[28]
|
|
N22 r base_ram_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.877
|
|
-------------------------------------------------------------------
|
|
slack 0.477
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T
|
|
M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
M20 OBUFT (TriStatE_obuft_T_O)
|
|
3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[21]
|
|
M20 r base_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T
|
|
M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
M20 OBUFT (TriStatE_obuft_T_O)
|
|
3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[21]
|
|
M20 r base_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T
|
|
M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
M20 OBUFT (TriStatE_obuft_T_O)
|
|
3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[21]
|
|
M20 r base_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T
|
|
M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
M20 OBUFT (TriStatE_obuft_T_O)
|
|
3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[21]
|
|
M20 r base_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T
|
|
M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
M20 OBUFT (TriStatE_obuft_T_O)
|
|
3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[21]
|
|
M20 r base_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T
|
|
M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
M20 OBUFT (TriStatE_obuft_T_O)
|
|
3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[21]
|
|
M20 r base_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T
|
|
M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
M20 OBUFT (TriStatE_obuft_T_O)
|
|
3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[21]
|
|
M20 r base_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T
|
|
M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
M20 OBUFT (TriStatE_obuft_T_O)
|
|
3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[21]
|
|
M20 r base_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T
|
|
M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
M20 OBUFT (TriStatE_obuft_T_O)
|
|
3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[21]
|
|
M20 r base_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T
|
|
M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
M20 OBUFT (TriStatE_obuft_T_O)
|
|
3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[21]
|
|
M20 r base_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 0.555ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%))
|
|
Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.954ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.322ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.954 -2.322
|
|
SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C
|
|
SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q
|
|
net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0]
|
|
SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0
|
|
SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3]
|
|
SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1]
|
|
net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27]
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5
|
|
SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 12.799 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -12.799
|
|
-------------------------------------------------------------------
|
|
slack 0.555
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.716ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%))
|
|
Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.105ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O
|
|
net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in
|
|
SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2
|
|
SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2
|
|
SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O
|
|
net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin
|
|
SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2
|
|
SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O
|
|
net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in
|
|
SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O
|
|
net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O
|
|
net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3
|
|
SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2
|
|
SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O
|
|
net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in
|
|
SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4
|
|
SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O
|
|
net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok
|
|
SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2
|
|
SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O
|
|
net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0
|
|
SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2
|
|
SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O
|
|
net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en
|
|
SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1
|
|
SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O
|
|
net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0
|
|
SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2
|
|
SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O
|
|
net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0
|
|
SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.566 28.214
|
|
clock pessimism -0.498 27.716
|
|
clock uncertainty -0.074 27.642
|
|
SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28]
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -24.757
|
|
-------------------------------------------------------------------
|
|
slack 2.716
|
|
|
|
Slack (MET) : 2.751ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5
|
|
SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0
|
|
SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O
|
|
net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0
|
|
SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0
|
|
SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O
|
|
net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0
|
|
SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4
|
|
SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O
|
|
net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120]
|
|
SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.725 28.373
|
|
clock pessimism -0.498 27.875
|
|
clock uncertainty -0.074 27.801
|
|
SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170]
|
|
-------------------------------------------------------------------
|
|
required time 27.878
|
|
arrival time -25.127
|
|
-------------------------------------------------------------------
|
|
slack 2.751
|
|
|
|
Slack (MET) : 2.751ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5
|
|
SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0
|
|
SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O
|
|
net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0
|
|
SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0
|
|
SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O
|
|
net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0
|
|
SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4
|
|
SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O
|
|
net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120]
|
|
SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.725 28.373
|
|
clock pessimism -0.498 27.875
|
|
clock uncertainty -0.074 27.801
|
|
SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170]
|
|
-------------------------------------------------------------------
|
|
required time 27.878
|
|
arrival time -25.127
|
|
-------------------------------------------------------------------
|
|
slack 2.751
|
|
|
|
Slack (MET) : 2.751ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5
|
|
SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0
|
|
SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O
|
|
net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0
|
|
SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0
|
|
SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O
|
|
net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0
|
|
SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4
|
|
SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O
|
|
net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120]
|
|
SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.725 28.373
|
|
clock pessimism -0.498 27.875
|
|
clock uncertainty -0.074 27.801
|
|
SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170]
|
|
-------------------------------------------------------------------
|
|
required time 27.878
|
|
arrival time -25.127
|
|
-------------------------------------------------------------------
|
|
slack 2.751
|
|
|
|
Slack (MET) : 2.751ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5
|
|
SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0
|
|
SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O
|
|
net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0
|
|
SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0
|
|
SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O
|
|
net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0
|
|
SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4
|
|
SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O
|
|
net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120]
|
|
SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.725 28.373
|
|
clock pessimism -0.498 27.875
|
|
clock uncertainty -0.074 27.801
|
|
SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170]
|
|
-------------------------------------------------------------------
|
|
required time 27.878
|
|
arrival time -25.127
|
|
-------------------------------------------------------------------
|
|
slack 2.751
|
|
|
|
Slack (MET) : 2.751ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5
|
|
SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0
|
|
SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O
|
|
net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0
|
|
SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0
|
|
SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O
|
|
net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0
|
|
SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4
|
|
SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O
|
|
net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120]
|
|
SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.725 28.373
|
|
clock pessimism -0.498 27.875
|
|
clock uncertainty -0.074 27.801
|
|
SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170]
|
|
-------------------------------------------------------------------
|
|
required time 27.878
|
|
arrival time -25.127
|
|
-------------------------------------------------------------------
|
|
slack 2.751
|
|
|
|
Slack (MET) : 2.751ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5
|
|
SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0
|
|
SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O
|
|
net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0
|
|
SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0
|
|
SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O
|
|
net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0
|
|
SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4
|
|
SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O
|
|
net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120]
|
|
SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.725 28.373
|
|
clock pessimism -0.498 27.875
|
|
clock uncertainty -0.074 27.801
|
|
SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170]
|
|
-------------------------------------------------------------------
|
|
required time 27.878
|
|
arrival time -25.127
|
|
-------------------------------------------------------------------
|
|
slack 2.751
|
|
|
|
Slack (MET) : 2.751ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5
|
|
SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0
|
|
SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O
|
|
net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0
|
|
SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0
|
|
SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O
|
|
net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0
|
|
SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4
|
|
SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O
|
|
net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120]
|
|
SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.725 28.373
|
|
clock pessimism -0.498 27.875
|
|
clock uncertainty -0.074 27.801
|
|
SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170]
|
|
-------------------------------------------------------------------
|
|
required time 27.878
|
|
arrival time -25.127
|
|
-------------------------------------------------------------------
|
|
slack 2.751
|
|
|
|
Slack (MET) : 2.751ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5
|
|
SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0
|
|
SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O
|
|
net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0
|
|
SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0
|
|
SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O
|
|
net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0
|
|
SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4
|
|
SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O
|
|
net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120]
|
|
SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.725 28.373
|
|
clock pessimism -0.498 27.875
|
|
clock uncertainty -0.074 27.801
|
|
SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170]
|
|
-------------------------------------------------------------------
|
|
required time 27.878
|
|
arrival time -25.127
|
|
-------------------------------------------------------------------
|
|
slack 2.751
|
|
|
|
Slack (MET) : 2.751ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5
|
|
SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0
|
|
SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O
|
|
net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0
|
|
SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0
|
|
SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O
|
|
net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0
|
|
SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4
|
|
SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O
|
|
net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120]
|
|
SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.725 28.373
|
|
clock pessimism -0.498 27.875
|
|
clock uncertainty -0.074 27.801
|
|
SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170]
|
|
-------------------------------------------------------------------
|
|
required time 27.878
|
|
arrival time -25.127
|
|
-------------------------------------------------------------------
|
|
slack 2.751
|
|
|
|
Slack (MET) : 2.751ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5
|
|
SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0
|
|
SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O
|
|
net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0
|
|
SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0
|
|
SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O
|
|
net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0
|
|
SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4
|
|
SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O
|
|
net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120]
|
|
SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.725 28.373
|
|
clock pessimism -0.498 27.875
|
|
clock uncertainty -0.074 27.801
|
|
SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170]
|
|
-------------------------------------------------------------------
|
|
required time 27.878
|
|
arrival time -25.127
|
|
-------------------------------------------------------------------
|
|
slack 2.751
|
|
|
|
Slack (MET) : 2.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O
|
|
net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2
|
|
SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0
|
|
SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O
|
|
net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0
|
|
SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4
|
|
SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O
|
|
net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0
|
|
SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3
|
|
SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O
|
|
net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127]
|
|
SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.812 28.460
|
|
clock pessimism -0.498 27.962
|
|
clock uncertainty -0.074 27.888
|
|
SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177]
|
|
-------------------------------------------------------------------
|
|
required time 27.919
|
|
arrival time -25.165
|
|
-------------------------------------------------------------------
|
|
slack 2.754
|
|
|
|
Slack (MET) : 2.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O
|
|
net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2
|
|
SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0
|
|
SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O
|
|
net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0
|
|
SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4
|
|
SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O
|
|
net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0
|
|
SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3
|
|
SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O
|
|
net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127]
|
|
SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.812 28.460
|
|
clock pessimism -0.498 27.962
|
|
clock uncertainty -0.074 27.888
|
|
SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177]
|
|
-------------------------------------------------------------------
|
|
required time 27.919
|
|
arrival time -25.165
|
|
-------------------------------------------------------------------
|
|
slack 2.754
|
|
|
|
Slack (MET) : 2.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O
|
|
net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2
|
|
SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0
|
|
SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O
|
|
net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0
|
|
SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4
|
|
SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O
|
|
net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0
|
|
SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3
|
|
SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O
|
|
net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127]
|
|
SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.812 28.460
|
|
clock pessimism -0.498 27.962
|
|
clock uncertainty -0.074 27.888
|
|
SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177]
|
|
-------------------------------------------------------------------
|
|
required time 27.919
|
|
arrival time -25.165
|
|
-------------------------------------------------------------------
|
|
slack 2.754
|
|
|
|
Slack (MET) : 2.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O
|
|
net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2
|
|
SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0
|
|
SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O
|
|
net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0
|
|
SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4
|
|
SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O
|
|
net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0
|
|
SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3
|
|
SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O
|
|
net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127]
|
|
SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.812 28.460
|
|
clock pessimism -0.498 27.962
|
|
clock uncertainty -0.074 27.888
|
|
SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177]
|
|
-------------------------------------------------------------------
|
|
required time 27.919
|
|
arrival time -25.165
|
|
-------------------------------------------------------------------
|
|
slack 2.754
|
|
|
|
Slack (MET) : 2.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O
|
|
net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2
|
|
SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0
|
|
SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O
|
|
net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0
|
|
SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4
|
|
SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O
|
|
net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0
|
|
SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3
|
|
SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O
|
|
net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127]
|
|
SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.812 28.460
|
|
clock pessimism -0.498 27.962
|
|
clock uncertainty -0.074 27.888
|
|
SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177]
|
|
-------------------------------------------------------------------
|
|
required time 27.919
|
|
arrival time -25.165
|
|
-------------------------------------------------------------------
|
|
slack 2.754
|
|
|
|
Slack (MET) : 2.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O
|
|
net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2
|
|
SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0
|
|
SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O
|
|
net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0
|
|
SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4
|
|
SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O
|
|
net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0
|
|
SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3
|
|
SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O
|
|
net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127]
|
|
SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.812 28.460
|
|
clock pessimism -0.498 27.962
|
|
clock uncertainty -0.074 27.888
|
|
SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177]
|
|
-------------------------------------------------------------------
|
|
required time 27.919
|
|
arrival time -25.165
|
|
-------------------------------------------------------------------
|
|
slack 2.754
|
|
|
|
Slack (MET) : 2.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O
|
|
net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2
|
|
SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0
|
|
SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O
|
|
net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0
|
|
SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4
|
|
SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O
|
|
net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0
|
|
SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3
|
|
SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O
|
|
net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127]
|
|
SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.812 28.460
|
|
clock pessimism -0.498 27.962
|
|
clock uncertainty -0.074 27.888
|
|
SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177]
|
|
-------------------------------------------------------------------
|
|
required time 27.919
|
|
arrival time -25.165
|
|
-------------------------------------------------------------------
|
|
slack 2.754
|
|
|
|
Slack (MET) : 2.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O
|
|
net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2
|
|
SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0
|
|
SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O
|
|
net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0
|
|
SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4
|
|
SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O
|
|
net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0
|
|
SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3
|
|
SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O
|
|
net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127]
|
|
SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.812 28.460
|
|
clock pessimism -0.498 27.962
|
|
clock uncertainty -0.074 27.888
|
|
SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177]
|
|
-------------------------------------------------------------------
|
|
required time 27.919
|
|
arrival time -25.165
|
|
-------------------------------------------------------------------
|
|
slack 2.754
|
|
|
|
Slack (MET) : 2.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O
|
|
net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2
|
|
SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0
|
|
SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O
|
|
net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0
|
|
SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4
|
|
SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O
|
|
net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0
|
|
SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3
|
|
SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O
|
|
net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127]
|
|
SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.812 28.460
|
|
clock pessimism -0.498 27.962
|
|
clock uncertainty -0.074 27.888
|
|
SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177]
|
|
-------------------------------------------------------------------
|
|
required time 27.919
|
|
arrival time -25.165
|
|
-------------------------------------------------------------------
|
|
slack 2.754
|
|
|
|
Slack (MET) : 2.754ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%))
|
|
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O
|
|
net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2
|
|
SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0
|
|
SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O
|
|
net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0
|
|
SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4
|
|
SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O
|
|
net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0
|
|
SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3
|
|
SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O
|
|
net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127]
|
|
SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.812 28.460
|
|
clock pessimism -0.498 27.962
|
|
clock uncertainty -0.074 27.888
|
|
SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177]
|
|
-------------------------------------------------------------------
|
|
required time 27.919
|
|
arrival time -25.165
|
|
-------------------------------------------------------------------
|
|
slack 2.754
|
|
|
|
Slack (MET) : 2.789ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O
|
|
net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2
|
|
SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1
|
|
SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O
|
|
net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0
|
|
SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O
|
|
net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184]
|
|
SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3
|
|
SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O
|
|
net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134]
|
|
SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.821 28.469
|
|
clock pessimism -0.498 27.971
|
|
clock uncertainty -0.074 27.897
|
|
SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184]
|
|
-------------------------------------------------------------------
|
|
required time 27.928
|
|
arrival time -25.138
|
|
-------------------------------------------------------------------
|
|
slack 2.789
|
|
|
|
Slack (MET) : 2.789ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O
|
|
net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2
|
|
SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1
|
|
SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O
|
|
net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0
|
|
SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O
|
|
net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184]
|
|
SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3
|
|
SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O
|
|
net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134]
|
|
SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.821 28.469
|
|
clock pessimism -0.498 27.971
|
|
clock uncertainty -0.074 27.897
|
|
SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184]
|
|
-------------------------------------------------------------------
|
|
required time 27.928
|
|
arrival time -25.138
|
|
-------------------------------------------------------------------
|
|
slack 2.789
|
|
|
|
Slack (MET) : 2.789ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O
|
|
net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2
|
|
SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1
|
|
SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O
|
|
net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0
|
|
SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O
|
|
net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184]
|
|
SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3
|
|
SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O
|
|
net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134]
|
|
SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.821 28.469
|
|
clock pessimism -0.498 27.971
|
|
clock uncertainty -0.074 27.897
|
|
SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184]
|
|
-------------------------------------------------------------------
|
|
required time 27.928
|
|
arrival time -25.138
|
|
-------------------------------------------------------------------
|
|
slack 2.789
|
|
|
|
Slack (MET) : 2.789ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O
|
|
net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2
|
|
SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1
|
|
SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O
|
|
net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0
|
|
SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O
|
|
net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184]
|
|
SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3
|
|
SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O
|
|
net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134]
|
|
SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.821 28.469
|
|
clock pessimism -0.498 27.971
|
|
clock uncertainty -0.074 27.897
|
|
SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184]
|
|
-------------------------------------------------------------------
|
|
required time 27.928
|
|
arrival time -25.138
|
|
-------------------------------------------------------------------
|
|
slack 2.789
|
|
|
|
Slack (MET) : 2.789ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O
|
|
net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2
|
|
SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1
|
|
SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O
|
|
net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0
|
|
SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O
|
|
net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184]
|
|
SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3
|
|
SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O
|
|
net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134]
|
|
SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.821 28.469
|
|
clock pessimism -0.498 27.971
|
|
clock uncertainty -0.074 27.897
|
|
SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184]
|
|
-------------------------------------------------------------------
|
|
required time 27.928
|
|
arrival time -25.138
|
|
-------------------------------------------------------------------
|
|
slack 2.789
|
|
|
|
Slack (MET) : 2.789ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O
|
|
net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2
|
|
SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1
|
|
SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O
|
|
net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0
|
|
SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O
|
|
net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184]
|
|
SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3
|
|
SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O
|
|
net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134]
|
|
SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.821 28.469
|
|
clock pessimism -0.498 27.971
|
|
clock uncertainty -0.074 27.897
|
|
SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184]
|
|
-------------------------------------------------------------------
|
|
required time 27.928
|
|
arrival time -25.138
|
|
-------------------------------------------------------------------
|
|
slack 2.789
|
|
|
|
Slack (MET) : 2.789ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O
|
|
net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2
|
|
SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1
|
|
SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O
|
|
net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0
|
|
SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O
|
|
net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184]
|
|
SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3
|
|
SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O
|
|
net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134]
|
|
SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.821 28.469
|
|
clock pessimism -0.498 27.971
|
|
clock uncertainty -0.074 27.897
|
|
SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184]
|
|
-------------------------------------------------------------------
|
|
required time 27.928
|
|
arrival time -25.138
|
|
-------------------------------------------------------------------
|
|
slack 2.789
|
|
|
|
Slack (MET) : 2.789ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O
|
|
net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2
|
|
SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1
|
|
SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O
|
|
net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0
|
|
SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O
|
|
net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184]
|
|
SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3
|
|
SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O
|
|
net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134]
|
|
SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.821 28.469
|
|
clock pessimism -0.498 27.971
|
|
clock uncertainty -0.074 27.897
|
|
SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184]
|
|
-------------------------------------------------------------------
|
|
required time 27.928
|
|
arrival time -25.138
|
|
-------------------------------------------------------------------
|
|
slack 2.789
|
|
|
|
Slack (MET) : 2.789ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O
|
|
net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2
|
|
SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1
|
|
SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O
|
|
net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0
|
|
SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O
|
|
net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184]
|
|
SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3
|
|
SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O
|
|
net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134]
|
|
SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.821 28.469
|
|
clock pessimism -0.498 27.971
|
|
clock uncertainty -0.074 27.897
|
|
SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184]
|
|
-------------------------------------------------------------------
|
|
required time 27.928
|
|
arrival time -25.138
|
|
-------------------------------------------------------------------
|
|
slack 2.789
|
|
|
|
Slack (MET) : 2.789ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O
|
|
net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2
|
|
SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1
|
|
SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O
|
|
net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0
|
|
SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2
|
|
SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O
|
|
net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184]
|
|
SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3
|
|
SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O
|
|
net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134]
|
|
SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.821 28.469
|
|
clock pessimism -0.498 27.971
|
|
clock uncertainty -0.074 27.897
|
|
SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184]
|
|
-------------------------------------------------------------------
|
|
required time 27.928
|
|
arrival time -25.138
|
|
-------------------------------------------------------------------
|
|
slack 2.789
|
|
|
|
Slack (MET) : 2.822ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.731 28.379
|
|
clock pessimism -0.498 27.881
|
|
clock uncertainty -0.074 27.807
|
|
SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.836
|
|
arrival time -25.013
|
|
-------------------------------------------------------------------
|
|
slack 2.822
|
|
|
|
Slack (MET) : 2.822ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.731 28.379
|
|
clock pessimism -0.498 27.881
|
|
clock uncertainty -0.074 27.807
|
|
SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.836
|
|
arrival time -25.013
|
|
-------------------------------------------------------------------
|
|
slack 2.822
|
|
|
|
Slack (MET) : 2.822ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.731 28.379
|
|
clock pessimism -0.498 27.881
|
|
clock uncertainty -0.074 27.807
|
|
SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.836
|
|
arrival time -25.013
|
|
-------------------------------------------------------------------
|
|
slack 2.822
|
|
|
|
Slack (MET) : 2.822ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.731 28.379
|
|
clock pessimism -0.498 27.881
|
|
clock uncertainty -0.074 27.807
|
|
SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.836
|
|
arrival time -25.013
|
|
-------------------------------------------------------------------
|
|
slack 2.822
|
|
|
|
Slack (MET) : 2.822ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.731 28.379
|
|
clock pessimism -0.498 27.881
|
|
clock uncertainty -0.074 27.807
|
|
SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.836
|
|
arrival time -25.013
|
|
-------------------------------------------------------------------
|
|
slack 2.822
|
|
|
|
Slack (MET) : 2.822ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.731 28.379
|
|
clock pessimism -0.498 27.881
|
|
clock uncertainty -0.074 27.807
|
|
SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.836
|
|
arrival time -25.013
|
|
-------------------------------------------------------------------
|
|
slack 2.822
|
|
|
|
Slack (MET) : 2.822ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.731 28.379
|
|
clock pessimism -0.498 27.881
|
|
clock uncertainty -0.074 27.807
|
|
SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.836
|
|
arrival time -25.013
|
|
-------------------------------------------------------------------
|
|
slack 2.822
|
|
|
|
Slack (MET) : 2.822ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.731 28.379
|
|
clock pessimism -0.498 27.881
|
|
clock uncertainty -0.074 27.807
|
|
SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.836
|
|
arrival time -25.013
|
|
-------------------------------------------------------------------
|
|
slack 2.822
|
|
|
|
Slack (MET) : 2.822ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.731 28.379
|
|
clock pessimism -0.498 27.881
|
|
clock uncertainty -0.074 27.807
|
|
SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.836
|
|
arrival time -25.013
|
|
-------------------------------------------------------------------
|
|
slack 2.822
|
|
|
|
Slack (MET) : 2.822ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%))
|
|
Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 )
|
|
Source Clock Delay (SCD): -2.502ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.774 -2.502
|
|
SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C
|
|
SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q
|
|
net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5]
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3
|
|
SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O
|
|
net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0
|
|
SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1]
|
|
SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3]
|
|
net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out
|
|
SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4
|
|
SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O
|
|
net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30]
|
|
SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3
|
|
SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S
|
|
SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
|
|
net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
|
|
SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0
|
|
SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
|
|
net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
|
|
SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0
|
|
SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
|
|
net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
|
|
SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5
|
|
SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3
|
|
SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O
|
|
net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12]
|
|
SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2
|
|
SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O
|
|
net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0
|
|
SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0]
|
|
SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3]
|
|
net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0
|
|
SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI
|
|
SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2]
|
|
net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0]
|
|
SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0
|
|
SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O
|
|
net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0
|
|
SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2
|
|
SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O
|
|
net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7]
|
|
SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0
|
|
SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
|
|
net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0]
|
|
SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2
|
|
SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O
|
|
net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0]
|
|
SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5
|
|
SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O
|
|
net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0
|
|
SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5
|
|
SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O
|
|
net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7]
|
|
SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2
|
|
SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O
|
|
net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0
|
|
SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0]
|
|
SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
|
|
net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
|
|
SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI
|
|
SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
|
|
net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12]
|
|
SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0
|
|
SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
|
|
net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
|
|
SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1
|
|
SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
|
|
net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
|
|
SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3
|
|
SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
|
|
net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
|
|
SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5
|
|
SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
|
|
net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
|
|
SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4
|
|
SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O
|
|
net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4
|
|
SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1
|
|
SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O
|
|
net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1
|
|
SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4
|
|
SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O
|
|
net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0
|
|
SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3
|
|
SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O
|
|
net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114]
|
|
SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.731 28.379
|
|
clock pessimism -0.498 27.881
|
|
clock uncertainty -0.074 27.807
|
|
SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164]
|
|
-------------------------------------------------------------------
|
|
required time 27.836
|
|
arrival time -25.013
|
|
-------------------------------------------------------------------
|
|
slack 2.822
|
|
|
|
Slack (MET) : 4.581ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 14.588ns (logic 0.606ns (4.154%) route 13.982ns (95.846%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.151ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.132ns = ( 17.868 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 10.475 12.101 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X85Y50 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.868
|
|
clock pessimism -0.507 17.361
|
|
clock uncertainty -0.071 17.290
|
|
SLICE_X85Y50 FDCE (Recov_fdce_C_CLR) -0.609 16.681 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 16.681
|
|
arrival time -12.101
|
|
-------------------------------------------------------------------
|
|
slack 4.581
|
|
|
|
Slack (MET) : 5.171ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 14.003ns (logic 0.606ns (4.328%) route 13.397ns (95.672%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.146ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 9.890 11.515 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X77Y52 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.547 17.873
|
|
clock pessimism -0.507 17.366
|
|
clock uncertainty -0.071 17.295
|
|
SLICE_X77Y52 FDCE (Recov_fdce_C_CLR) -0.609 16.686 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 16.686
|
|
arrival time -11.515
|
|
-------------------------------------------------------------------
|
|
slack 5.171
|
|
|
|
Slack (MET) : 5.624ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 13.646ns (logic 0.606ns (4.441%) route 13.040ns (95.559%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 9.533 11.158 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X90Y57 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X90Y57 FDCE (Recov_fdce_C_CLR) -0.523 16.782 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 16.782
|
|
arrival time -11.158
|
|
-------------------------------------------------------------------
|
|
slack 5.624
|
|
|
|
Slack (MET) : 6.450ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in
|
|
SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.835 18.160
|
|
clock pessimism -0.507 17.654
|
|
clock uncertainty -0.071 17.583
|
|
SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 16.974
|
|
arrival time -10.524
|
|
-------------------------------------------------------------------
|
|
slack 6.450
|
|
|
|
Slack (MET) : 6.450ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in
|
|
SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.835 18.160
|
|
clock pessimism -0.507 17.654
|
|
clock uncertainty -0.071 17.583
|
|
SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 16.974
|
|
arrival time -10.524
|
|
-------------------------------------------------------------------
|
|
slack 6.450
|
|
|
|
Slack (MET) : 6.450ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.141ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in
|
|
SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.835 18.160
|
|
clock pessimism -0.507 17.654
|
|
clock uncertainty -0.071 17.583
|
|
SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 16.974
|
|
arrival time -10.524
|
|
-------------------------------------------------------------------
|
|
slack 6.450
|
|
|
|
Slack (MET) : 6.650ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -10.047
|
|
-------------------------------------------------------------------
|
|
slack 6.650
|
|
|
|
Slack (MET) : 6.650ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -10.047
|
|
-------------------------------------------------------------------
|
|
slack 6.650
|
|
|
|
Slack (MET) : 6.654ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -10.043
|
|
-------------------------------------------------------------------
|
|
slack 6.654
|
|
|
|
Slack (MET) : 6.654ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -10.043
|
|
-------------------------------------------------------------------
|
|
slack 6.654
|
|
|
|
Slack (MET) : 6.654ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -10.043
|
|
-------------------------------------------------------------------
|
|
slack 6.654
|
|
|
|
Slack (MET) : 6.654ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -10.043
|
|
-------------------------------------------------------------------
|
|
slack 6.654
|
|
|
|
Slack (MET) : 6.814ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.884
|
|
-------------------------------------------------------------------
|
|
slack 6.814
|
|
|
|
Slack (MET) : 6.814ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.884
|
|
-------------------------------------------------------------------
|
|
slack 6.814
|
|
|
|
Slack (MET) : 6.814ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.884
|
|
-------------------------------------------------------------------
|
|
slack 6.814
|
|
|
|
Slack (MET) : 6.814ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.884
|
|
-------------------------------------------------------------------
|
|
slack 6.814
|
|
|
|
Slack (MET) : 6.881ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in
|
|
SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.844 18.169
|
|
clock pessimism -0.507 17.663
|
|
clock uncertainty -0.071 17.592
|
|
SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 16.983
|
|
arrival time -10.102
|
|
-------------------------------------------------------------------
|
|
slack 6.881
|
|
|
|
Slack (MET) : 6.881ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in
|
|
SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.844 18.169
|
|
clock pessimism -0.507 17.663
|
|
clock uncertainty -0.071 17.592
|
|
SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg
|
|
-------------------------------------------------------------------
|
|
required time 16.983
|
|
arrival time -10.102
|
|
-------------------------------------------------------------------
|
|
slack 6.881
|
|
|
|
Slack (MET) : 6.947ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.751
|
|
-------------------------------------------------------------------
|
|
slack 6.947
|
|
|
|
Slack (MET) : 6.947ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.751
|
|
-------------------------------------------------------------------
|
|
slack 6.947
|
|
|
|
Slack (MET) : 6.947ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.751
|
|
-------------------------------------------------------------------
|
|
slack 6.947
|
|
|
|
Slack (MET) : 6.947ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.751
|
|
-------------------------------------------------------------------
|
|
slack 6.947
|
|
|
|
Slack (MET) : 6.955ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.743
|
|
-------------------------------------------------------------------
|
|
slack 6.955
|
|
|
|
Slack (MET) : 6.955ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.743
|
|
-------------------------------------------------------------------
|
|
slack 6.955
|
|
|
|
Slack (MET) : 6.955ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.743
|
|
-------------------------------------------------------------------
|
|
slack 6.955
|
|
|
|
Slack (MET) : 6.955ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.743
|
|
-------------------------------------------------------------------
|
|
slack 6.955
|
|
|
|
Slack (MET) : 6.955ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.743
|
|
-------------------------------------------------------------------
|
|
slack 6.955
|
|
|
|
Slack (MET) : 6.955ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.743
|
|
-------------------------------------------------------------------
|
|
slack 6.955
|
|
|
|
Slack (MET) : 6.967ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in
|
|
SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.844 18.169
|
|
clock pessimism -0.507 17.663
|
|
clock uncertainty -0.071 17.592
|
|
SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 17.069
|
|
arrival time -10.102
|
|
-------------------------------------------------------------------
|
|
slack 6.967
|
|
|
|
Slack (MET) : 6.967ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in
|
|
SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.844 18.169
|
|
clock pessimism -0.507 17.663
|
|
clock uncertainty -0.071 17.592
|
|
SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 17.069
|
|
arrival time -10.102
|
|
-------------------------------------------------------------------
|
|
slack 6.967
|
|
|
|
Slack (MET) : 6.967ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in
|
|
SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.844 18.169
|
|
clock pessimism -0.507 17.663
|
|
clock uncertainty -0.071 17.592
|
|
SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 17.069
|
|
arrival time -10.102
|
|
-------------------------------------------------------------------
|
|
slack 6.967
|
|
|
|
Slack (MET) : 6.996ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -9.702
|
|
-------------------------------------------------------------------
|
|
slack 6.996
|
|
|
|
Slack (MET) : 6.996ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -9.702
|
|
-------------------------------------------------------------------
|
|
slack 6.996
|
|
|
|
Slack (MET) : 6.996ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -9.702
|
|
-------------------------------------------------------------------
|
|
slack 6.996
|
|
|
|
Slack (MET) : 6.996ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -9.702
|
|
-------------------------------------------------------------------
|
|
slack 6.996
|
|
|
|
Slack (MET) : 6.996ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -9.702
|
|
-------------------------------------------------------------------
|
|
slack 6.996
|
|
|
|
Slack (MET) : 7.098ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.601
|
|
-------------------------------------------------------------------
|
|
slack 7.098
|
|
|
|
Slack (MET) : 7.098ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.601
|
|
-------------------------------------------------------------------
|
|
slack 7.098
|
|
|
|
Slack (MET) : 7.098ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.601
|
|
-------------------------------------------------------------------
|
|
slack 7.098
|
|
|
|
Slack (MET) : 7.098ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.134ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.559 17.885
|
|
clock pessimism -0.507 17.378
|
|
clock uncertainty -0.071 17.307
|
|
SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 16.698
|
|
arrival time -9.601
|
|
-------------------------------------------------------------------
|
|
slack 7.098
|
|
|
|
Slack (MET) : 7.115ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -9.583
|
|
-------------------------------------------------------------------
|
|
slack 7.115
|
|
|
|
Slack (MET) : 7.115ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -9.583
|
|
-------------------------------------------------------------------
|
|
slack 7.115
|
|
|
|
Slack (MET) : 7.115ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -9.583
|
|
-------------------------------------------------------------------
|
|
slack 7.115
|
|
|
|
Slack (MET) : 7.115ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -9.583
|
|
-------------------------------------------------------------------
|
|
slack 7.115
|
|
|
|
Slack (MET) : 7.115ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.558 17.884
|
|
clock pessimism -0.507 17.377
|
|
clock uncertainty -0.071 17.306
|
|
SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]
|
|
-------------------------------------------------------------------
|
|
required time 16.697
|
|
arrival time -9.583
|
|
-------------------------------------------------------------------
|
|
slack 7.115
|
|
|
|
Slack (MET) : 7.136ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.561
|
|
-------------------------------------------------------------------
|
|
slack 7.136
|
|
|
|
Slack (MET) : 7.136ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.561
|
|
-------------------------------------------------------------------
|
|
slack 7.136
|
|
|
|
Slack (MET) : 7.143ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.414ns (logic 0.606ns (4.882%) route 11.808ns (95.118%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.301 9.926 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in
|
|
SLICE_X18Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.844 18.169
|
|
clock pessimism -0.507 17.663
|
|
clock uncertainty -0.071 17.592
|
|
SLICE_X18Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 17.069
|
|
arrival time -9.926
|
|
-------------------------------------------------------------------
|
|
slack 7.143
|
|
|
|
Slack (MET) : 7.222ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.133ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.560 17.886
|
|
clock pessimism -0.507 17.379
|
|
clock uncertainty -0.071 17.308
|
|
SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 16.699
|
|
arrival time -9.478
|
|
-------------------------------------------------------------------
|
|
slack 7.222
|
|
|
|
Slack (MET) : 7.222ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.133ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.560 17.886
|
|
clock pessimism -0.507 17.379
|
|
clock uncertainty -0.071 17.308
|
|
SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 16.699
|
|
arrival time -9.478
|
|
-------------------------------------------------------------------
|
|
slack 7.222
|
|
|
|
Slack (MET) : 7.222ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.133ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.560 17.886
|
|
clock pessimism -0.507 17.379
|
|
clock uncertainty -0.071 17.308
|
|
SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 16.699
|
|
arrival time -9.478
|
|
-------------------------------------------------------------------
|
|
slack 7.222
|
|
|
|
Slack (MET) : 7.222ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[3]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.133ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.560 17.886
|
|
clock pessimism -0.507 17.379
|
|
clock uncertainty -0.071 17.308
|
|
SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 16.699
|
|
arrival time -9.478
|
|
-------------------------------------------------------------------
|
|
slack 7.222
|
|
|
|
Slack (MET) : 7.262ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[28]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[28]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.553 17.879
|
|
clock pessimism -0.507 17.372
|
|
clock uncertainty -0.071 17.301
|
|
SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 16.692
|
|
arrival time -9.431
|
|
-------------------------------------------------------------------
|
|
slack 7.262
|
|
|
|
Slack (MET) : 7.262ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[29]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[29]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.553 17.879
|
|
clock pessimism -0.507 17.372
|
|
clock uncertainty -0.071 17.301
|
|
SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time 16.692
|
|
arrival time -9.431
|
|
-------------------------------------------------------------------
|
|
slack 7.262
|
|
|
|
Slack (MET) : 7.262ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[30]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[30]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.553 17.879
|
|
clock pessimism -0.507 17.372
|
|
clock uncertainty -0.071 17.301
|
|
SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time 16.692
|
|
arrival time -9.431
|
|
-------------------------------------------------------------------
|
|
slack 7.262
|
|
|
|
Slack (MET) : 7.262ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[31]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.140ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[31]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.553 17.879
|
|
clock pessimism -0.507 17.372
|
|
clock uncertainty -0.071 17.301
|
|
SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[31]
|
|
-------------------------------------------------------------------
|
|
required time 16.692
|
|
arrival time -9.431
|
|
-------------------------------------------------------------------
|
|
slack 7.262
|
|
|
|
Slack (MET) : 7.267ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[24]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[24]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.429
|
|
-------------------------------------------------------------------
|
|
slack 7.267
|
|
|
|
Slack (MET) : 7.267ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[25]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[25]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[25]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.429
|
|
-------------------------------------------------------------------
|
|
slack 7.267
|
|
|
|
Slack (MET) : 7.267ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[26]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[26]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[26]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.429
|
|
-------------------------------------------------------------------
|
|
slack 7.267
|
|
|
|
Slack (MET) : 7.267ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[27]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[27]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[27]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.429
|
|
-------------------------------------------------------------------
|
|
slack 7.267
|
|
|
|
Slack (MET) : 7.267ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[28]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[28]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.429
|
|
-------------------------------------------------------------------
|
|
slack 7.267
|
|
|
|
Slack (MET) : 7.267ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[29]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[29]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.429
|
|
-------------------------------------------------------------------
|
|
slack 7.267
|
|
|
|
Slack (MET) : 7.267ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[30]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[30]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.429
|
|
-------------------------------------------------------------------
|
|
slack 7.267
|
|
|
|
Slack (MET) : 7.267ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[31]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[31]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[31]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.429
|
|
-------------------------------------------------------------------
|
|
slack 7.267
|
|
|
|
Slack (MET) : 7.288ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[3]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in
|
|
SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.844 18.169
|
|
clock pessimism -0.507 17.663
|
|
clock uncertainty -0.071 17.592
|
|
SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.565 17.027 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 17.027
|
|
arrival time -9.740
|
|
-------------------------------------------------------------------
|
|
slack 7.288
|
|
|
|
Slack (MET) : 7.330ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in
|
|
SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.844 18.169
|
|
clock pessimism -0.507 17.663
|
|
clock uncertainty -0.071 17.592
|
|
SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 17.069
|
|
arrival time -9.740
|
|
-------------------------------------------------------------------
|
|
slack 7.330
|
|
|
|
Slack (MET) : 7.330ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in
|
|
SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.844 18.169
|
|
clock pessimism -0.507 17.663
|
|
clock uncertainty -0.071 17.592
|
|
SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 17.069
|
|
arrival time -9.740
|
|
-------------------------------------------------------------------
|
|
slack 7.330
|
|
|
|
Slack (MET) : 7.330ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in
|
|
SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.844 18.169
|
|
clock pessimism -0.507 17.663
|
|
clock uncertainty -0.071 17.592
|
|
SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 17.069
|
|
arrival time -9.740
|
|
-------------------------------------------------------------------
|
|
slack 7.330
|
|
|
|
Slack (MET) : 7.330ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.150ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in
|
|
SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.844 18.169
|
|
clock pessimism -0.507 17.663
|
|
clock uncertainty -0.071 17.592
|
|
SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 17.069
|
|
arrival time -9.740
|
|
-------------------------------------------------------------------
|
|
slack 7.330
|
|
|
|
Slack (MET) : 7.345ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.206ns (logic 0.606ns (4.965%) route 11.600ns (95.035%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.230ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.751ns = ( 18.249 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.093 9.718 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in
|
|
SLICE_X3Y3 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.924 18.249
|
|
clock pessimism -0.507 17.743
|
|
clock uncertainty -0.071 17.672
|
|
SLICE_X3Y3 FDCE (Recov_fdce_C_CLR) -0.609 17.063 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 17.063
|
|
arrival time -9.718
|
|
-------------------------------------------------------------------
|
|
slack 7.345
|
|
|
|
Slack (MET) : 7.388ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/bf1_count_reg[0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.160ns (logic 0.606ns (4.983%) route 11.554ns (95.017%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.227ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.754ns = ( 18.246 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.047 9.673 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in
|
|
SLICE_X5Y8 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/bf1_count_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.921 18.246
|
|
clock pessimism -0.507 17.740
|
|
clock uncertainty -0.071 17.669
|
|
SLICE_X5Y8 FDCE (Recov_fdce_C_CLR) -0.609 17.060 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/bf1_count_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 17.060
|
|
arrival time -9.673
|
|
-------------------------------------------------------------------
|
|
slack 7.388
|
|
|
|
Slack (MET) : 7.401ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[24]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.139ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[24]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.554 17.880
|
|
clock pessimism -0.507 17.373
|
|
clock uncertainty -0.071 17.302
|
|
SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 16.693
|
|
arrival time -9.293
|
|
-------------------------------------------------------------------
|
|
slack 7.401
|
|
|
|
Slack (MET) : 7.401ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[25]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.139ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[25]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.554 17.880
|
|
clock pessimism -0.507 17.373
|
|
clock uncertainty -0.071 17.302
|
|
SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[25]
|
|
-------------------------------------------------------------------
|
|
required time 16.693
|
|
arrival time -9.293
|
|
-------------------------------------------------------------------
|
|
slack 7.401
|
|
|
|
Slack (MET) : 7.401ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[26]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.139ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[26]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.554 17.880
|
|
clock pessimism -0.507 17.373
|
|
clock uncertainty -0.071 17.302
|
|
SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[26]
|
|
-------------------------------------------------------------------
|
|
required time 16.693
|
|
arrival time -9.293
|
|
-------------------------------------------------------------------
|
|
slack 7.401
|
|
|
|
Slack (MET) : 7.401ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[27]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.139ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[27]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.554 17.880
|
|
clock pessimism -0.507 17.373
|
|
clock uncertainty -0.071 17.302
|
|
SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[27]
|
|
-------------------------------------------------------------------
|
|
required time 16.693
|
|
arrival time -9.293
|
|
-------------------------------------------------------------------
|
|
slack 7.401
|
|
|
|
Slack (MET) : 7.407ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[20]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.137ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[20]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.556 17.882
|
|
clock pessimism -0.507 17.375
|
|
clock uncertainty -0.071 17.304
|
|
SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 16.695
|
|
arrival time -9.289
|
|
-------------------------------------------------------------------
|
|
slack 7.407
|
|
|
|
Slack (MET) : 7.407ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[21]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.137ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[21]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.556 17.882
|
|
clock pessimism -0.507 17.375
|
|
clock uncertainty -0.071 17.304
|
|
SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time 16.695
|
|
arrival time -9.289
|
|
-------------------------------------------------------------------
|
|
slack 7.407
|
|
|
|
Slack (MET) : 7.407ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[22]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.137ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[22]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.556 17.882
|
|
clock pessimism -0.507 17.375
|
|
clock uncertainty -0.071 17.304
|
|
SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 16.695
|
|
arrival time -9.289
|
|
-------------------------------------------------------------------
|
|
slack 7.407
|
|
|
|
Slack (MET) : 7.407ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[23]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.137ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[23]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.556 17.882
|
|
clock pessimism -0.507 17.375
|
|
clock uncertainty -0.071 17.304
|
|
SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[23]
|
|
-------------------------------------------------------------------
|
|
required time 16.695
|
|
arrival time -9.289
|
|
-------------------------------------------------------------------
|
|
slack 7.407
|
|
|
|
Slack (MET) : 7.431ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.206ns (logic 0.606ns (4.965%) route 11.600ns (95.035%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.230ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.751ns = ( 18.249 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 8.093 9.718 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in
|
|
SLICE_X2Y3 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.924 18.249
|
|
clock pessimism -0.507 17.743
|
|
clock uncertainty -0.071 17.672
|
|
SLICE_X2Y3 FDCE (Recov_fdce_C_CLR) -0.523 17.149 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 17.149
|
|
arrival time -9.718
|
|
-------------------------------------------------------------------
|
|
slack 7.431
|
|
|
|
Slack (MET) : 7.510ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/mu_do_en_reg/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.038ns (logic 0.606ns (5.034%) route 11.432ns (94.966%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.228ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.925 9.551 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in
|
|
SLICE_X5Y3 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/mu_do_en_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.922 18.247
|
|
clock pessimism -0.507 17.741
|
|
clock uncertainty -0.071 17.670
|
|
SLICE_X5Y3 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/mu_do_en_reg
|
|
-------------------------------------------------------------------
|
|
required time 17.061
|
|
arrival time -9.551
|
|
-------------------------------------------------------------------
|
|
slack 7.510
|
|
|
|
Slack (MET) : 7.574ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[16]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[16]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.122
|
|
-------------------------------------------------------------------
|
|
slack 7.574
|
|
|
|
Slack (MET) : 7.574ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[17]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[17]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[17]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.122
|
|
-------------------------------------------------------------------
|
|
slack 7.574
|
|
|
|
Slack (MET) : 7.574ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[18]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[18]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.122
|
|
-------------------------------------------------------------------
|
|
slack 7.574
|
|
|
|
Slack (MET) : 7.574ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[19]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.136ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in
|
|
SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[19]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.557 17.883
|
|
clock pessimism -0.507 17.376
|
|
clock uncertainty -0.071 17.305
|
|
SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time 16.696
|
|
arrival time -9.122
|
|
-------------------------------------------------------------------
|
|
slack 7.574
|
|
|
|
Slack (MET) : 7.609ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in
|
|
SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.925 18.250
|
|
clock pessimism -0.507 17.744
|
|
clock uncertainty -0.071 17.673
|
|
SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 17.064
|
|
arrival time -9.455
|
|
-------------------------------------------------------------------
|
|
slack 7.609
|
|
|
|
Slack (MET) : 7.609ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in
|
|
SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.925 18.250
|
|
clock pessimism -0.507 17.744
|
|
clock uncertainty -0.071 17.673
|
|
SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 17.064
|
|
arrival time -9.455
|
|
-------------------------------------------------------------------
|
|
slack 7.609
|
|
|
|
Slack (MET) : 7.609ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in
|
|
SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.925 18.250
|
|
clock pessimism -0.507 17.744
|
|
clock uncertainty -0.071 17.673
|
|
SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 17.064
|
|
arrival time -9.455
|
|
-------------------------------------------------------------------
|
|
slack 7.609
|
|
|
|
Slack (MET) : 7.609ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in
|
|
SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.925 18.250
|
|
clock pessimism -0.507 17.744
|
|
clock uncertainty -0.071 17.673
|
|
SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 17.064
|
|
arrival time -9.455
|
|
-------------------------------------------------------------------
|
|
slack 7.609
|
|
|
|
Slack (MET) : 7.637ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in
|
|
SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.925 18.250
|
|
clock pessimism -0.507 17.744
|
|
clock uncertainty -0.071 17.673
|
|
SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 17.064
|
|
arrival time -9.428
|
|
-------------------------------------------------------------------
|
|
slack 7.637
|
|
|
|
Slack (MET) : 7.637ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[6]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in
|
|
SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.925 18.250
|
|
clock pessimism -0.507 17.744
|
|
clock uncertainty -0.071 17.673
|
|
SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 17.064
|
|
arrival time -9.428
|
|
-------------------------------------------------------------------
|
|
slack 7.637
|
|
|
|
Slack (MET) : 7.637ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[7]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in
|
|
SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.925 18.250
|
|
clock pessimism -0.507 17.744
|
|
clock uncertainty -0.071 17.673
|
|
SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 17.064
|
|
arrival time -9.428
|
|
-------------------------------------------------------------------
|
|
slack 7.637
|
|
|
|
Slack (MET) : 7.637ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[8]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in
|
|
SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.925 18.250
|
|
clock pessimism -0.507 17.744
|
|
clock uncertainty -0.071 17.673
|
|
SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 17.064
|
|
arrival time -9.428
|
|
-------------------------------------------------------------------
|
|
slack 7.637
|
|
|
|
Slack (MET) : 7.637ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in
|
|
SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.925 18.250
|
|
clock pessimism -0.507 17.744
|
|
clock uncertainty -0.071 17.673
|
|
SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 17.064
|
|
arrival time -9.428
|
|
-------------------------------------------------------------------
|
|
slack 7.637
|
|
|
|
Slack (MET) : 7.638ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.958ns (logic 0.606ns (5.068%) route 11.352ns (94.932%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.845 9.470 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in
|
|
SLICE_X2Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.925 18.250
|
|
clock pessimism -0.507 17.744
|
|
clock uncertainty -0.071 17.673
|
|
SLICE_X2Y1 FDCE (Recov_fdce_C_CLR) -0.565 17.108 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg
|
|
-------------------------------------------------------------------
|
|
required time 17.108
|
|
arrival time -9.470
|
|
-------------------------------------------------------------------
|
|
slack 7.638
|
|
|
|
Slack (MET) : 7.638ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[3]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.958ns (logic 0.606ns (5.068%) route 11.352ns (94.932%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.845 9.470 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in
|
|
SLICE_X2Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.925 18.250
|
|
clock pessimism -0.507 17.744
|
|
clock uncertainty -0.071 17.673
|
|
SLICE_X2Y1 FDCE (Recov_fdce_C_CLR) -0.565 17.108 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 17.108
|
|
arrival time -9.470
|
|
-------------------------------------------------------------------
|
|
slack 7.638
|
|
|
|
Slack (MET) : 7.641ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.911ns (logic 0.606ns (5.088%) route 11.305ns (94.912%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.798 9.423 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in
|
|
SLICE_X1Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.925 18.250
|
|
clock pessimism -0.507 17.744
|
|
clock uncertainty -0.071 17.673
|
|
SLICE_X1Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 17.064
|
|
arrival time -9.423
|
|
-------------------------------------------------------------------
|
|
slack 7.641
|
|
|
|
Slack (MET) : 7.668ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.881ns (logic 0.606ns (5.101%) route 11.275ns (94.899%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.228ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.768 9.393 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in
|
|
SLICE_X5Y6 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.922 18.247
|
|
clock pessimism -0.507 17.741
|
|
clock uncertainty -0.071 17.670
|
|
SLICE_X5Y6 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 17.061
|
|
arrival time -9.393
|
|
-------------------------------------------------------------------
|
|
slack 7.668
|
|
|
|
Slack (MET) : 7.668ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[1]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.881ns (logic 0.606ns (5.101%) route 11.275ns (94.899%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.228ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.768 9.393 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in
|
|
SLICE_X5Y6 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.922 18.247
|
|
clock pessimism -0.507 17.741
|
|
clock uncertainty -0.071 17.670
|
|
SLICE_X5Y6 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 17.061
|
|
arrival time -9.393
|
|
-------------------------------------------------------------------
|
|
slack 7.668
|
|
|
|
Slack (MET) : 7.668ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 11.881ns (logic 0.606ns (5.101%) route 11.275ns (94.899%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.228ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 7.768 9.393 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in
|
|
SLICE_X5Y6 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.922 18.247
|
|
clock pessimism -0.507 17.741
|
|
clock uncertainty -0.071 17.670
|
|
SLICE_X5Y6 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 17.061
|
|
arrival time -9.393
|
|
-------------------------------------------------------------------
|
|
slack 7.668
|
|
|
|
Slack (MET) : 10.807ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.360
|
|
-------------------------------------------------------------------
|
|
slack 10.807
|
|
|
|
Slack (MET) : 10.807ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.360
|
|
-------------------------------------------------------------------
|
|
slack 10.807
|
|
|
|
Slack (MET) : 10.807ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.360
|
|
-------------------------------------------------------------------
|
|
slack 10.807
|
|
|
|
Slack (MET) : 10.807ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.360
|
|
-------------------------------------------------------------------
|
|
slack 10.807
|
|
|
|
Slack (MET) : 10.904ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.315
|
|
-------------------------------------------------------------------
|
|
slack 10.904
|
|
|
|
Slack (MET) : 10.904ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.315
|
|
-------------------------------------------------------------------
|
|
slack 10.904
|
|
|
|
Slack (MET) : 10.904ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.315
|
|
-------------------------------------------------------------------
|
|
slack 10.904
|
|
|
|
Slack (MET) : 10.904ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.315
|
|
-------------------------------------------------------------------
|
|
slack 10.904
|
|
|
|
Slack (MET) : 10.918ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.297
|
|
-------------------------------------------------------------------
|
|
slack 10.918
|
|
|
|
Slack (MET) : 10.918ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.297
|
|
-------------------------------------------------------------------
|
|
slack 10.918
|
|
|
|
Slack (MET) : 10.918ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.297
|
|
-------------------------------------------------------------------
|
|
slack 10.918
|
|
|
|
Slack (MET) : 10.918ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.297
|
|
-------------------------------------------------------------------
|
|
slack 10.918
|
|
|
|
Slack (MET) : 11.034ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -26.135
|
|
-------------------------------------------------------------------
|
|
slack 11.034
|
|
|
|
Slack (MET) : 11.034ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -26.135
|
|
-------------------------------------------------------------------
|
|
slack 11.034
|
|
|
|
Slack (MET) : 11.034ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -26.135
|
|
-------------------------------------------------------------------
|
|
slack 11.034
|
|
|
|
Slack (MET) : 11.034ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -26.135
|
|
-------------------------------------------------------------------
|
|
slack 11.034
|
|
|
|
Slack (MET) : 11.059ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.156
|
|
-------------------------------------------------------------------
|
|
slack 11.059
|
|
|
|
Slack (MET) : 11.059ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.156
|
|
-------------------------------------------------------------------
|
|
slack 11.059
|
|
|
|
Slack (MET) : 11.059ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.156
|
|
-------------------------------------------------------------------
|
|
slack 11.059
|
|
|
|
Slack (MET) : 11.059ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.156
|
|
-------------------------------------------------------------------
|
|
slack 11.059
|
|
|
|
Slack (MET) : 11.066ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.153
|
|
-------------------------------------------------------------------
|
|
slack 11.066
|
|
|
|
Slack (MET) : 11.066ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.153
|
|
-------------------------------------------------------------------
|
|
slack 11.066
|
|
|
|
Slack (MET) : 11.066ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.153
|
|
-------------------------------------------------------------------
|
|
slack 11.066
|
|
|
|
Slack (MET) : 11.066ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.153
|
|
-------------------------------------------------------------------
|
|
slack 11.066
|
|
|
|
Slack (MET) : 11.144ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.023
|
|
-------------------------------------------------------------------
|
|
slack 11.144
|
|
|
|
Slack (MET) : 11.144ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.023
|
|
-------------------------------------------------------------------
|
|
slack 11.144
|
|
|
|
Slack (MET) : 11.144ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.023
|
|
-------------------------------------------------------------------
|
|
slack 11.144
|
|
|
|
Slack (MET) : 11.144ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.023
|
|
-------------------------------------------------------------------
|
|
slack 11.144
|
|
|
|
Slack (MET) : 11.144ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.023
|
|
-------------------------------------------------------------------
|
|
slack 11.144
|
|
|
|
Slack (MET) : 11.144ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.023
|
|
-------------------------------------------------------------------
|
|
slack 11.144
|
|
|
|
Slack (MET) : 11.162ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -26.003
|
|
-------------------------------------------------------------------
|
|
slack 11.162
|
|
|
|
Slack (MET) : 11.162ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -26.003
|
|
-------------------------------------------------------------------
|
|
slack 11.162
|
|
|
|
Slack (MET) : 11.162ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -26.003
|
|
-------------------------------------------------------------------
|
|
slack 11.162
|
|
|
|
Slack (MET) : 11.162ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -26.003
|
|
-------------------------------------------------------------------
|
|
slack 11.162
|
|
|
|
Slack (MET) : 11.217ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O
|
|
net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917
|
|
SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.949
|
|
-------------------------------------------------------------------
|
|
slack 11.217
|
|
|
|
Slack (MET) : 11.217ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O
|
|
net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917
|
|
SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.949
|
|
-------------------------------------------------------------------
|
|
slack 11.217
|
|
|
|
Slack (MET) : 11.217ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O
|
|
net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917
|
|
SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.949
|
|
-------------------------------------------------------------------
|
|
slack 11.217
|
|
|
|
Slack (MET) : 11.217ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O
|
|
net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917
|
|
SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.949
|
|
-------------------------------------------------------------------
|
|
slack 11.217
|
|
|
|
Slack (MET) : 11.241ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.978
|
|
-------------------------------------------------------------------
|
|
slack 11.241
|
|
|
|
Slack (MET) : 11.241ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.978
|
|
-------------------------------------------------------------------
|
|
slack 11.241
|
|
|
|
Slack (MET) : 11.241ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.978
|
|
-------------------------------------------------------------------
|
|
slack 11.241
|
|
|
|
Slack (MET) : 11.241ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.978
|
|
-------------------------------------------------------------------
|
|
slack 11.241
|
|
|
|
Slack (MET) : 11.241ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.978
|
|
-------------------------------------------------------------------
|
|
slack 11.241
|
|
|
|
Slack (MET) : 11.241ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.978
|
|
-------------------------------------------------------------------
|
|
slack 11.241
|
|
|
|
Slack (MET) : 11.246ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1
|
|
SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O
|
|
net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473
|
|
SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]
|
|
-------------------------------------------------------------------
|
|
required time 37.214
|
|
arrival time -25.968
|
|
-------------------------------------------------------------------
|
|
slack 11.246
|
|
|
|
Slack (MET) : 11.246ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1
|
|
SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O
|
|
net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473
|
|
SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]
|
|
-------------------------------------------------------------------
|
|
required time 37.214
|
|
arrival time -25.968
|
|
-------------------------------------------------------------------
|
|
slack 11.246
|
|
|
|
Slack (MET) : 11.246ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1
|
|
SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O
|
|
net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473
|
|
SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]
|
|
-------------------------------------------------------------------
|
|
required time 37.214
|
|
arrival time -25.968
|
|
-------------------------------------------------------------------
|
|
slack 11.246
|
|
|
|
Slack (MET) : 11.246ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1
|
|
SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O
|
|
net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473
|
|
SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]
|
|
-------------------------------------------------------------------
|
|
required time 37.214
|
|
arrival time -25.968
|
|
-------------------------------------------------------------------
|
|
slack 11.246
|
|
|
|
Slack (MET) : 11.255ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.960
|
|
-------------------------------------------------------------------
|
|
slack 11.255
|
|
|
|
Slack (MET) : 11.255ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.960
|
|
-------------------------------------------------------------------
|
|
slack 11.255
|
|
|
|
Slack (MET) : 11.255ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.960
|
|
-------------------------------------------------------------------
|
|
slack 11.255
|
|
|
|
Slack (MET) : 11.255ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.960
|
|
-------------------------------------------------------------------
|
|
slack 11.255
|
|
|
|
Slack (MET) : 11.255ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.960
|
|
-------------------------------------------------------------------
|
|
slack 11.255
|
|
|
|
Slack (MET) : 11.255ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.960
|
|
-------------------------------------------------------------------
|
|
slack 11.255
|
|
|
|
Slack (MET) : 11.322ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.099ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1
|
|
SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O
|
|
net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475
|
|
SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.393 37.718
|
|
clock pessimism -0.507 37.211
|
|
clock uncertainty -0.077 37.135
|
|
SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.844
|
|
-------------------------------------------------------------------
|
|
slack 11.322
|
|
|
|
Slack (MET) : 11.322ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.099ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1
|
|
SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O
|
|
net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475
|
|
SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.393 37.718
|
|
clock pessimism -0.507 37.211
|
|
clock uncertainty -0.077 37.135
|
|
SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.844
|
|
-------------------------------------------------------------------
|
|
slack 11.322
|
|
|
|
Slack (MET) : 11.322ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.099ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1
|
|
SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O
|
|
net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475
|
|
SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.393 37.718
|
|
clock pessimism -0.507 37.211
|
|
clock uncertainty -0.077 37.135
|
|
SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.844
|
|
-------------------------------------------------------------------
|
|
slack 11.322
|
|
|
|
Slack (MET) : 11.322ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.099ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1
|
|
SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O
|
|
net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475
|
|
SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.393 37.718
|
|
clock pessimism -0.507 37.211
|
|
clock uncertainty -0.077 37.135
|
|
SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.844
|
|
-------------------------------------------------------------------
|
|
slack 11.322
|
|
|
|
Slack (MET) : 11.371ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -25.798
|
|
-------------------------------------------------------------------
|
|
slack 11.371
|
|
|
|
Slack (MET) : 11.371ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -25.798
|
|
-------------------------------------------------------------------
|
|
slack 11.371
|
|
|
|
Slack (MET) : 11.371ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -25.798
|
|
-------------------------------------------------------------------
|
|
slack 11.371
|
|
|
|
Slack (MET) : 11.371ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -25.798
|
|
-------------------------------------------------------------------
|
|
slack 11.371
|
|
|
|
Slack (MET) : 11.371ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -25.798
|
|
-------------------------------------------------------------------
|
|
slack 11.371
|
|
|
|
Slack (MET) : 11.371ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -25.798
|
|
-------------------------------------------------------------------
|
|
slack 11.371
|
|
|
|
Slack (MET) : 11.396ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.819
|
|
-------------------------------------------------------------------
|
|
slack 11.396
|
|
|
|
Slack (MET) : 11.396ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.819
|
|
-------------------------------------------------------------------
|
|
slack 11.396
|
|
|
|
Slack (MET) : 11.396ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.819
|
|
-------------------------------------------------------------------
|
|
slack 11.396
|
|
|
|
Slack (MET) : 11.396ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.819
|
|
-------------------------------------------------------------------
|
|
slack 11.396
|
|
|
|
Slack (MET) : 11.396ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.819
|
|
-------------------------------------------------------------------
|
|
slack 11.396
|
|
|
|
Slack (MET) : 11.396ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.819
|
|
-------------------------------------------------------------------
|
|
slack 11.396
|
|
|
|
Slack (MET) : 11.403ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.816
|
|
-------------------------------------------------------------------
|
|
slack 11.403
|
|
|
|
Slack (MET) : 11.403ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.816
|
|
-------------------------------------------------------------------
|
|
slack 11.403
|
|
|
|
Slack (MET) : 11.403ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.816
|
|
-------------------------------------------------------------------
|
|
slack 11.403
|
|
|
|
Slack (MET) : 11.403ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.816
|
|
-------------------------------------------------------------------
|
|
slack 11.403
|
|
|
|
Slack (MET) : 11.403ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.816
|
|
-------------------------------------------------------------------
|
|
slack 11.403
|
|
|
|
Slack (MET) : 11.403ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.816
|
|
-------------------------------------------------------------------
|
|
slack 11.403
|
|
|
|
Slack (MET) : 11.414ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O
|
|
net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910
|
|
SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]
|
|
-------------------------------------------------------------------
|
|
required time 37.213
|
|
arrival time -25.799
|
|
-------------------------------------------------------------------
|
|
slack 11.414
|
|
|
|
Slack (MET) : 11.414ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O
|
|
net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910
|
|
SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]
|
|
-------------------------------------------------------------------
|
|
required time 37.213
|
|
arrival time -25.799
|
|
-------------------------------------------------------------------
|
|
slack 11.414
|
|
|
|
Slack (MET) : 11.414ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O
|
|
net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910
|
|
SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]
|
|
-------------------------------------------------------------------
|
|
required time 37.213
|
|
arrival time -25.799
|
|
-------------------------------------------------------------------
|
|
slack 11.414
|
|
|
|
Slack (MET) : 11.414ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O
|
|
net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910
|
|
SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]
|
|
-------------------------------------------------------------------
|
|
required time 37.213
|
|
arrival time -25.799
|
|
-------------------------------------------------------------------
|
|
slack 11.414
|
|
|
|
Slack (MET) : 11.421ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O
|
|
net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469
|
|
SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]
|
|
-------------------------------------------------------------------
|
|
required time 37.217
|
|
arrival time -25.796
|
|
-------------------------------------------------------------------
|
|
slack 11.421
|
|
|
|
Slack (MET) : 11.421ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O
|
|
net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469
|
|
SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]
|
|
-------------------------------------------------------------------
|
|
required time 37.217
|
|
arrival time -25.796
|
|
-------------------------------------------------------------------
|
|
slack 11.421
|
|
|
|
Slack (MET) : 11.421ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O
|
|
net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469
|
|
SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]
|
|
-------------------------------------------------------------------
|
|
required time 37.217
|
|
arrival time -25.796
|
|
-------------------------------------------------------------------
|
|
slack 11.421
|
|
|
|
Slack (MET) : 11.421ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O
|
|
net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469
|
|
SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]
|
|
-------------------------------------------------------------------
|
|
required time 37.217
|
|
arrival time -25.796
|
|
-------------------------------------------------------------------
|
|
slack 11.421
|
|
|
|
Slack (MET) : 11.499ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -25.666
|
|
-------------------------------------------------------------------
|
|
slack 11.499
|
|
|
|
Slack (MET) : 11.499ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -25.666
|
|
-------------------------------------------------------------------
|
|
slack 11.499
|
|
|
|
Slack (MET) : 11.499ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -25.666
|
|
-------------------------------------------------------------------
|
|
slack 11.499
|
|
|
|
Slack (MET) : 11.499ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -25.666
|
|
-------------------------------------------------------------------
|
|
slack 11.499
|
|
|
|
Slack (MET) : 11.499ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -25.666
|
|
-------------------------------------------------------------------
|
|
slack 11.499
|
|
|
|
Slack (MET) : 11.499ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -25.666
|
|
-------------------------------------------------------------------
|
|
slack 11.499
|
|
|
|
Slack (MET) : 11.503ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O
|
|
net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919
|
|
SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]
|
|
-------------------------------------------------------------------
|
|
required time 37.168
|
|
arrival time -25.665
|
|
-------------------------------------------------------------------
|
|
slack 11.503
|
|
|
|
Slack (MET) : 11.503ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O
|
|
net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919
|
|
SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]
|
|
-------------------------------------------------------------------
|
|
required time 37.168
|
|
arrival time -25.665
|
|
-------------------------------------------------------------------
|
|
slack 11.503
|
|
|
|
Slack (MET) : 11.503ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O
|
|
net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919
|
|
SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]
|
|
-------------------------------------------------------------------
|
|
required time 37.168
|
|
arrival time -25.665
|
|
-------------------------------------------------------------------
|
|
slack 11.503
|
|
|
|
Slack (MET) : 11.503ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O
|
|
net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919
|
|
SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]
|
|
-------------------------------------------------------------------
|
|
required time 37.168
|
|
arrival time -25.665
|
|
-------------------------------------------------------------------
|
|
slack 11.503
|
|
|
|
Slack (MET) : 11.505ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.101ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1
|
|
SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O
|
|
net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920
|
|
SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.391 37.716
|
|
clock pessimism -0.507 37.209
|
|
clock uncertainty -0.077 37.133
|
|
SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]
|
|
-------------------------------------------------------------------
|
|
required time 37.162
|
|
arrival time -25.657
|
|
-------------------------------------------------------------------
|
|
slack 11.505
|
|
|
|
Slack (MET) : 11.505ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.101ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1
|
|
SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O
|
|
net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920
|
|
SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.391 37.716
|
|
clock pessimism -0.507 37.209
|
|
clock uncertainty -0.077 37.133
|
|
SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]
|
|
-------------------------------------------------------------------
|
|
required time 37.162
|
|
arrival time -25.657
|
|
-------------------------------------------------------------------
|
|
slack 11.505
|
|
|
|
Slack (MET) : 11.505ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.101ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1
|
|
SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O
|
|
net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920
|
|
SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.391 37.716
|
|
clock pessimism -0.507 37.209
|
|
clock uncertainty -0.077 37.133
|
|
SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]
|
|
-------------------------------------------------------------------
|
|
required time 37.162
|
|
arrival time -25.657
|
|
-------------------------------------------------------------------
|
|
slack 11.505
|
|
|
|
Slack (MET) : 11.505ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.101ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1
|
|
SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O
|
|
net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920
|
|
SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.391 37.716
|
|
clock pessimism -0.507 37.209
|
|
clock uncertainty -0.077 37.133
|
|
SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]
|
|
-------------------------------------------------------------------
|
|
required time 37.162
|
|
arrival time -25.657
|
|
-------------------------------------------------------------------
|
|
slack 11.505
|
|
|
|
Slack (MET) : 11.519ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.099ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1
|
|
SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O
|
|
net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478
|
|
SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.393 37.718
|
|
clock pessimism -0.507 37.211
|
|
clock uncertainty -0.077 37.135
|
|
SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]
|
|
-------------------------------------------------------------------
|
|
required time 37.216
|
|
arrival time -25.697
|
|
-------------------------------------------------------------------
|
|
slack 11.519
|
|
|
|
Slack (MET) : 11.519ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.099ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1
|
|
SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O
|
|
net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478
|
|
SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.393 37.718
|
|
clock pessimism -0.507 37.211
|
|
clock uncertainty -0.077 37.135
|
|
SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]
|
|
-------------------------------------------------------------------
|
|
required time 37.216
|
|
arrival time -25.697
|
|
-------------------------------------------------------------------
|
|
slack 11.519
|
|
|
|
|
|
|
|
|