204 lines
8.0 KiB
Plaintext
204 lines
8.0 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Sun Jul 5 23:34:12 2026
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| Host : fedora running 64-bit unknown
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| Command : report_utilization -file ./vivado_reports/synth_utilization.rpt
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| Design : soc_top
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| Device : 7a200tfbg676-1
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| Design State : Synthesized
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------------------------------------------------------------------------------------
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Utilization Design Information
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Table of Contents
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-----------------
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1. Slice Logic
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1.1 Summary of Registers by Type
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2. Memory
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3. DSP
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4. IO and GT Specific
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5. Clocking
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6. Specific Feature
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7. Primitives
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8. Black Boxes
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9. Instantiated Netlists
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1. Slice Logic
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--------------
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+----------------------------+-------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------------+-------+-------+-----------+-------+
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| Slice LUTs* | 74980 | 0 | 134600 | 55.71 |
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| LUT as Logic | 73234 | 0 | 134600 | 54.41 |
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| LUT as Memory | 1746 | 0 | 46200 | 3.78 |
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| LUT as Distributed RAM | 652 | 0 | | |
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| LUT as Shift Register | 1094 | 0 | | |
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| Slice Registers | 38603 | 0 | 269200 | 14.34 |
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| Register as Flip Flop | 38603 | 0 | 269200 | 14.34 |
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| Register as Latch | 0 | 0 | 269200 | 0.00 |
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| F7 Muxes | 4263 | 0 | 67300 | 6.33 |
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| F8 Muxes | 1403 | 0 | 33650 | 4.17 |
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+----------------------------+-------+-------+-----------+-------+
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* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
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1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0 | _ | - | - |
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| 0 | _ | - | Set |
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| 0 | _ | - | Reset |
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| 0 | _ | Set | - |
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| 0 | _ | Reset | - |
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| 0 | Yes | - | - |
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| 101 | Yes | - | Set |
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| 25523 | Yes | - | Reset |
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| 134 | Yes | Set | - |
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| 12845 | Yes | Reset | - |
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+-------+--------------+-------------+--------------+
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2. Memory
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---------
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+-------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------------+------+-------+-----------+-------+
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| Block RAM Tile | 25.5 | 0 | 365 | 6.99 |
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| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
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| RAMB36E1 only | 10 | | | |
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| RAMB18 | 31 | 0 | 730 | 4.25 |
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| RAMB18E1 only | 31 | | | |
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+-------------------+------+-------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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3. DSP
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------
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+-----------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------+------+-------+-----------+-------+
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| DSPs | 0 | 0 | 740 | 0.00 |
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+-----------+------+-------+-----------+-------+
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4. IO and GT Specific
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---------------------
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+-----------------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------------------------+------+-------+-----------+-------+
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| Bonded IOB | 202 | 202 | 400 | 50.50 |
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| IOB Master Pads | 97 | | | |
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| IOB Slave Pads | 102 | | | |
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| Bonded IPADs | 0 | 0 | 26 | 0.00 |
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| Bonded OPADs | 0 | 0 | 16 | 0.00 |
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| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
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| PHASER_REF | 0 | 0 | 10 | 0.00 |
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| OUT_FIFO | 0 | 0 | 40 | 0.00 |
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| IN_FIFO | 0 | 0 | 40 | 0.00 |
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| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
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| IBUFDS | 0 | 0 | 384 | 0.00 |
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| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 |
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| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
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| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
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| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
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| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
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| ILOGIC | 0 | 0 | 400 | 0.00 |
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| OLOGIC | 0 | 0 | 400 | 0.00 |
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+-----------------------------+------+-------+-----------+-------+
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5. Clocking
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-----------
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+------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+------------+------+-------+-----------+-------+
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| BUFGCTRL | 4 | 0 | 32 | 12.50 |
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| BUFIO | 0 | 0 | 40 | 0.00 |
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| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
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| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
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| BUFMRCE | 0 | 0 | 20 | 0.00 |
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| BUFHCE | 0 | 0 | 120 | 0.00 |
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| BUFR | 0 | 0 | 40 | 0.00 |
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+------------+------+-------+-----------+-------+
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6. Specific Feature
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-------------------
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+-------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------+------+-------+-----------+-------+
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| BSCANE2 | 0 | 0 | 4 | 0.00 |
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| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
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| DNA_PORT | 0 | 0 | 1 | 0.00 |
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| EFUSE_USR | 0 | 0 | 1 | 0.00 |
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| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
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| ICAPE2 | 0 | 0 | 2 | 0.00 |
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| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
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| STARTUPE2 | 0 | 0 | 1 | 0.00 |
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| XADC | 0 | 0 | 1 | 0.00 |
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+-------------+------+-------+-----------+-------+
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7. Primitives
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-------------
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+-----------+-------+---------------------+
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| Ref Name | Used | Functional Category |
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+-----------+-------+---------------------+
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| LUT6 | 36042 | LUT |
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| FDCE | 25523 | Flop & Latch |
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| LUT5 | 16007 | LUT |
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| LUT3 | 13060 | LUT |
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| FDRE | 12845 | Flop & Latch |
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| LUT4 | 11977 | LUT |
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| LUT2 | 9006 | LUT |
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| MUXF7 | 4263 | MuxFx |
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| CARRY4 | 3590 | CarryLogic |
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| MUXF8 | 1403 | MuxFx |
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| SRLC32E | 992 | Distributed Memory |
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| RAMD32 | 892 | Distributed Memory |
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| LUT1 | 816 | LUT |
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| RAMS32 | 272 | Distributed Memory |
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| FDSE | 134 | Flop & Latch |
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| IBUF | 104 | IO |
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| SRL16E | 102 | Distributed Memory |
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| FDPE | 101 | Flop & Latch |
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| OBUF | 98 | IO |
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| OBUFT | 66 | IO |
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| RAMD64E | 32 | Distributed Memory |
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| RAMB18E1 | 31 | Block Memory |
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| RAMB36E1 | 10 | Block Memory |
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| BUFG | 4 | Clock |
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| PLLE2_ADV | 1 | Clock |
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+-----------+-------+---------------------+
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8. Black Boxes
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--------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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9. Instantiated Netlists
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------------------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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| clk_pll | 1 |
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+----------+------+
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