230 lines
18 KiB
Plaintext
230 lines
18 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Sun Jul 5 23:35:50 2026
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| Host : fedora running 64-bit unknown
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| Command : report_clock_utilization -file ./vivado_reports/impl_clock_utilization.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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| Design State : Synthesized
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Clock Utilization Report
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Table of Contents
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-----------------
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1. Clock Primitive Utilization
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2. Global Clock Resources
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3. Global Clock Source Details
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4. Clock Regions: Key Resource Utilization
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5. Clock Regions : Global Clock Summary
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6. Device Cell Placement Summary for Global Clock g0
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7. Device Cell Placement Summary for Global Clock g1
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8. Device Cell Placement Summary for Global Clock g2
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9. Device Cell Placement Summary for Global Clock g3
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10. Clock Region Cell Placement per Global Clock: Region X0Y3
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1. Clock Primitive Utilization
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------------------------------
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+----------+------+-----------+-----+--------------+--------+
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| Type | Used | Available | LOC | Clock Region | Pblock |
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+----------+------+-----------+-----+--------------+--------+
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| BUFGCTRL | 4 | 32 | 0 | 0 | 0 |
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| BUFH | 0 | 120 | 0 | 0 | 0 |
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| BUFIO | 0 | 40 | 0 | 0 | 0 |
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| BUFMR | 0 | 20 | 0 | 0 | 0 |
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| BUFR | 0 | 40 | 0 | 0 | 0 |
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| MMCM | 0 | 10 | 0 | 0 | 0 |
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| PLL | 1 | 10 | 0 | 0 | 0 |
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+----------+------+-----------+-----+--------------+--------+
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2. Global Clock Resources
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-------------------------
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+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
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| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
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+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
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| g0 | src0 | BUFG/O | None | | n/a | 0 | 23490 | 0 | | | r_wb_reg[7]_i_3/O | u_mlkem_axi_slave/mlkem_clk |
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| g1 | src1 | BUFG/O | None | | n/a | 1 | 10604 | 1 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/clkout2_buf/O | pll_clk.u_clk_pll/inst/sys_clk |
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| g2 | src1 | BUFG/O | None | | n/a | 0 | 5859 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/clkout1_buf/O | pll_clk.u_clk_pll/inst/cpu_clk |
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| g3 | src1 | BUFG/O | None | | n/a | 0 | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkf_buf/O | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
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+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
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* Clock Loads column represents the clock pin loads (pin count)
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** Non-Clock Loads column represents the non-clock pin loads (pin count)
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3. Global Clock Source Details
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------------------------------
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+-----------+-----------+--------------------+------------+------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
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| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
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+-----------+-----------+--------------------+------------+------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
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| src0 | g0 | FDCE/Q | None | | n/a | 1 | 1 | | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg/Q | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg_0 |
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| src1 | g3 | PLLE2_ADV/CLKFBOUT | None | | n/a | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT | pll_clk.u_clk_pll/inst/clkfbout_clk_pll |
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| src1 | g2 | PLLE2_ADV/CLKOUT0 | None | | n/a | 1 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll |
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| src1 | g1 | PLLE2_ADV/CLKOUT1 | None | | n/a | 1 | 0 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 | pll_clk.u_clk_pll/inst/sys_clk_clk_pll |
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+-----------+-----------+--------------------+------------+------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
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* Clock Loads column represents the clock pin loads (pin count)
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** Non-Clock Loads column represents the non-clock pin loads (pin count)
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4. Clock Regions: Key Resource Utilization
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------------------------------------------
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+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
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| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 800 | 0 | 60 | 0 | 30 | 0 | 60 |
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| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
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| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4200 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
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| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
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| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
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| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
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| X0Y3 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
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| X1Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
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| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 1 | 0 | 50 | 0 | 50 | 0 | 2550 | 0 | 750 | 0 | 50 | 0 | 25 | 0 | 60 |
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| X1Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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* Global Clock column represents track count; while other columns represents cell counts
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5. Clock Regions : Global Clock Summary
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---------------------------------------
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All Modules
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+----+----+----+
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| | X0 | X1 |
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+----+----+----+
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| Y4 | 0 | 0 |
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| Y3 | 1 | 0 |
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| Y2 | 0 | 0 |
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| Y1 | 0 | 0 |
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| Y0 | 0 | 0 |
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+----+----+----+
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6. Device Cell Placement Summary for Global Clock g0
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----------------------------------------------------
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
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| g0 | BUFG/O | n/a | | | | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+----+----+
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| | X0 | X1 |
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+----+----+----+
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| Y4 | 0 | 0 |
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| Y3 | 0 | 0 |
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| Y2 | 0 | 0 |
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| Y1 | 0 | 0 |
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| Y0 | 0 | 0 |
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+----+----+----+
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7. Device Cell Placement Summary for Global Clock g1
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----------------------------------------------------
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+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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| g1 | BUFG/O | n/a | sys_clk | 20.000 | {0.000 10.000} | 0 | 1 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
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+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+----+----+
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| | X0 | X1 |
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+----+----+----+
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| Y4 | 0 | 0 |
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| Y3 | 1 | 0 |
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| Y2 | 0 | 0 |
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| Y1 | 0 | 0 |
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| Y0 | 0 | 0 |
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+----+----+----+
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8. Device Cell Placement Summary for Global Clock g2
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----------------------------------------------------
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+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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| g2 | BUFG/O | n/a | cpu_clk | 30.323 | {0.000 15.161} | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
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+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+----+----+
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| | X0 | X1 |
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+----+----+----+
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| Y4 | 0 | 0 |
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| Y3 | 0 | 0 |
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| Y2 | 0 | 0 |
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| Y1 | 0 | 0 |
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| Y0 | 0 | 0 |
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+----+----+----+
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9. Device Cell Placement Summary for Global Clock g3
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----------------------------------------------------
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+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
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| g3 | BUFG/O | n/a | clkfbout_clk_pll | 20.000 | {0.000 10.000} | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
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+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+----+----+
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| | X0 | X1 |
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+----+----+----+
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| Y4 | 0 | 0 |
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| Y3 | 0 | 0 |
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| Y2 | 0 | 0 |
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| Y1 | 0 | 0 |
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| Y0 | 0 | 0 |
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+----+----+----+
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10. Clock Region Cell Placement per Global Clock: Region X0Y3
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-------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
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| g1 | n/a | BUFG/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
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+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
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* Clock Loads column represents the clock pin loads (pin count)
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** Non-Clock Loads column represents the non-clock pin loads (pin count)
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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# Location of IO Primitives which is load of clock spine
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set_property LOC IOB_X0Y173 [get_cells video_clk_OBUF_inst]
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# Location of clock ports
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set_property LOC IOB_X0Y176 [get_ports clk]
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