This repository has been archived on 2026-08-21. You can view files and clone it. You cannot open issues or pull requests or push a commit.

FallenSigh 95fe94063c fix: revert UART FIFO batching — caused FIFO overflow + syserr on board ...

uart_puts(13B) + uart_puthex(8B) = 21 bytes without polling → FIFO overflow.
Board UART IP asserts AXI error → CPU syserr exception.
Simulation UART model is lenient, so sim passed but board failed.

Back to per-byte polling (safe).

2026-06-26 23:53:15 +08:00

..

bsp

Restore timing + switch to polling + disable CPU interrupts (IE=0)

2026-06-26 01:01:48 +08:00

examples

fix: revert UART FIFO batching — caused FIFO overflow + syserr on board

2026-06-26 23:53:15 +08:00