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FallenSigh 3f7c9b7a37 feat: optimize sram write channel

2026-07-04 18:54:05 +08:00

..

APB_UART

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

axi_axil_adapter

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

bram0

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

Bus_interconnects

feat: optimize sram write channel

2026-07-04 18:54:05 +08:00

cdma

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

confreg

Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

2026-06-25 20:03:53 +08:00

DVI

Fix linter: remove placeholder, fix DVI reg declarations

2026-06-24 21:41:05 +08:00

matmul

Fix pipe_cnt range: issue 0-15 (16 rounds), acc 4-19, done at 20

2026-06-25 22:26:07 +08:00

mlkem

chore: typo

2026-07-04 18:53:23 +08:00

open-la500

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

PLL_2018_3

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

PLL_2019_2

chore: untrack auto-generated PLL files, add .gitignore

2026-06-30 02:10:29 +08:00

PLL_2023_2

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

ram_wrap

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

rst_sync

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00