25 lines
733 B
Tcl
25 lines
733 B
Tcl
# SET PROJECT NAME
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set project_name Loongson_Soc
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set project_path ./project
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set project_part xc7a200tfbg676-1
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# CLEAR
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file delete -force $project_path
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create_project -force $project_name $project_path -part $project_part
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# Add conventional sources
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add_files -scan_for_includes ../rtl
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# Add IPs
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add_files -norecurse -scan_for_includes ../rtl/ip/PLL_2019_2/clk_pll.xci
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# Add simulation files
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add_files -fileset sim_1 ../sim/
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# Add constraints
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add_files -fileset constrs_1 -quiet ./constraints
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set_property top soc_top [current_fileset]
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set_property -name "top" -value "tb_top" -objects [get_filesets sim_1]
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set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]
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