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FallenSigh 2e4817fea6 set sysclk to 60Mhz

2026-07-14 22:50:44 +08:00

..

APB_UART

fix: typo

2026-07-14 22:50:34 +08:00

axi_axil_adapter

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

bram0

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

Bus_interconnects

Optimize matmul DMA with chained 256-beat bursts

2026-07-14 20:40:43 +08:00

cdma

Pipeline matmul bank chaining

2026-07-01 22:41:31 +08:00

confreg

Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

2026-06-25 20:03:53 +08:00

DVI

Fix linter: remove placeholder, fix DVI reg declarations

2026-06-24 21:41:05 +08:00

matmul

Optimize matmul DMA with chained 256-beat bursts

2026-07-14 20:40:43 +08:00

mlkem

fix: typo

2026-07-01 21:03:46 +08:00

open-la500

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

PLL_2018_3

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

PLL_2019_2

set sysclk to 60Mhz

2026-07-14 22:50:44 +08:00

PLL_2023_2

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

ram_wrap

fix: typo

2026-07-14 22:50:34 +08:00

rst_sync

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00