42 lines
1.4 KiB
Tcl
42 lines
1.4 KiB
Tcl
# Runs the currently built sdk/axi_ram.mif with the generic SoC testbench.
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# The caller is responsible for building the desired software example first.
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set script_dir [file dirname [file normalize [info script]]]
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set repo_root [file normalize [file join $script_dir ../../../..]]
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set xpr [file join $repo_root fpga project Loongson_Soc.xpr]
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# xelab inherits this when compiling generated C files with the host gcc.
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set ::env(CCACHE_DISABLE) 1
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# Vivado 2019.2's bundled clang needs the matching 64-bit ncurses/tinfo pair.
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# On hosts that also carry /lib/libtinfo.so.5, the loader may otherwise mix it
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# with /lib64/libncurses.so.5 and fail with an unresolved _nc_tiparm symbol.
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if {[info exists ::env(LD_LIBRARY_PATH)] && $::env(LD_LIBRARY_PATH) ne ""} {
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append ::env(LD_LIBRARY_PATH) ":/lib64"
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} else {
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set ::env(LD_LIBRARY_PATH) "/lib64"
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}
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if {![file exists $xpr]} {
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puts stderr "ERROR: project not found: $xpr"
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exit 2
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}
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if {![file exists [file join $repo_root sdk axi_ram.mif]]} {
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puts stderr "ERROR: sdk/axi_ram.mif not found; build a software example first"
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exit 3
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}
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open_project $xpr
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set simset [get_filesets sim_1]
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set_property top tb_top $simset
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set_property incremental false $simset
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set_property xsim.elaborate.mt_level off $simset
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set_property xsim.elaborate.debug_level off $simset
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set_property xsim.simulate.log_all_signals false $simset
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update_compile_order -fileset sim_1
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launch_simulation
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run all
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close_sim
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close_project
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exit 0
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