# Runs the currently built sdk/axi_ram.mif with the generic SoC testbench.
# The caller is responsible for building the desired software example first.

set script_dir [file dirname [file normalize [info script]]]
set repo_root [file normalize [file join $script_dir ../../../..]]
set xpr [file join $repo_root fpga project Loongson_Soc.xpr]

# xelab inherits this when compiling generated C files with the host gcc.
set ::env(CCACHE_DISABLE) 1

# Vivado 2019.2's bundled clang needs the matching 64-bit ncurses/tinfo pair.
# On hosts that also carry /lib/libtinfo.so.5, the loader may otherwise mix it
# with /lib64/libncurses.so.5 and fail with an unresolved _nc_tiparm symbol.
if {[info exists ::env(LD_LIBRARY_PATH)] && $::env(LD_LIBRARY_PATH) ne ""} {
    append ::env(LD_LIBRARY_PATH) ":/lib64"
} else {
    set ::env(LD_LIBRARY_PATH) "/lib64"
}

if {![file exists $xpr]} {
    puts stderr "ERROR: project not found: $xpr"
    exit 2
}
if {![file exists [file join $repo_root sdk axi_ram.mif]]} {
    puts stderr "ERROR: sdk/axi_ram.mif not found; build a software example first"
    exit 3
}

open_project $xpr
set simset [get_filesets sim_1]
set_property top tb_top $simset
set_property incremental false $simset
set_property xsim.elaborate.mt_level off $simset
set_property xsim.elaborate.debug_level off $simset
set_property xsim.simulate.log_all_signals false $simset
update_compile_order -fileset sim_1
launch_simulation
run all
close_sim
close_project
exit 0