182 lines
6.8 KiB
C
182 lines
6.8 KiB
C
/**
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* user-sample - CIC-IEC 2026 Stage 3 Evaluation Program
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*
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* (ULTIMATE PERFORMANCE DMA + PING-PONG BUFFER ARCHITECTURE)
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*
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* Utilizes true DMA transfers (Channel 0 for memory->IP, Channel 1 for IP->memory)
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* perfectly overlapped with Hardware IP computation to achieve Zero-Wait execution.
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*/
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#include <stdio.h>
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#include <string.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <common_func.h>
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#include <dma.h>
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/* ─── Configurable group count (default 10 for fast local testing) ─── */
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#ifndef MATMUL_GROUP_NUM
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#define MATMUL_GROUP_NUM 5000
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#endif
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/* ─── BSP globals ─────────────────────────────────────────────────── */
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unsigned long UART_BASE = 0xbf000000;
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unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
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/* ─── Memory layout ────────────────────────────────────────────────── */
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#define EXTRAM_BASE_PHYS 0x1c400000
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#define EXTRAM_BASE_UNCACHED (0xA0000000 | (EXTRAM_BASE_PHYS & 0x1FFFFFFF))
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#define SRC_BASE_WORDS 0
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#define DST_BASE_WORDS (SRC_BASE_WORDS + MATMUL_GROUP_NUM * 32)
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#define RESULT_WORDS (MATMUL_GROUP_NUM * 48)
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/* ExtRAM Physical Addresses for DMA */
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#define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4) + (g) * 128)
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#define EXTRAM_PHYS_C(g) (EXTRAM_BASE_PHYS + (DST_BASE_WORDS * 4) + (g) * 192)
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/* ─── MATMUL IP registers (Ping-Pong Memory Map) ──────────────────── */
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#define MATMUL_BASE_PHYS 0x1f500000
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#define MATMUL_BASE_UNCACHED 0xbf500000
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// CPU Control & Status Registers
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#define MATMUL_CTRL (MATMUL_BASE_UNCACHED + 0x000)
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#define MATMUL_STATUS (MATMUL_BASE_UNCACHED + 0x004)
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// DMA Physical Addresses for IP Space
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// (A and B are contiguous: A is 0x100~0x13F, B is 0x140~0x17F. Total 128 bytes)
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#define MATMUL_PHYS_B0_AB (MATMUL_BASE_PHYS + 0x100)
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#define MATMUL_PHYS_B0_C (MATMUL_BASE_PHYS + 0x180) // 192 bytes
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#define MATMUL_PHYS_B1_AB (MATMUL_BASE_PHYS + 0x300)
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#define MATMUL_PHYS_B1_C (MATMUL_BASE_PHYS + 0x380)
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#define CTRL_START_B0 0x1
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#define CTRL_START_B1 0x2
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#define STATUS_DONE 0x2
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#define STATUS_ERROR 0x4
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// Hardware CRC register (offset 0x010 in matmul IP)
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#define MATMUL_CRC (MATMUL_BASE_UNCACHED + 0x010)
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/* ─── Convenience macros ──────────────────────────────────────────── */
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#define REG_WR(addr, val) (*(volatile uint32_t *)(addr) = (uint32_t)(val))
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#define REG_RD(addr) (*(volatile uint32_t *)(addr))
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static volatile int matmul_done_flag = 0;
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static volatile int dma0_done_flag = 0;
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static volatile int dma1_done_flag = 0;
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void MATMUL_IntrHandler(void)
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{
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matmul_done_flag = 1;
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REG_WR(MATMUL_STATUS, STATUS_DONE); // W1C: deassert intr
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}
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void DMA_IntrHandler(void)
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{
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if (DMA_CH(0)->STATUS & STATUS_DONE_BIT) {
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dma0_done_flag = 1;
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DMA_CH(0)->STATUS = STATUS_DONE_BIT;
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}
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if (DMA_CH(1)->STATUS & STATUS_DONE_BIT) {
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dma1_done_flag = 1;
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DMA_CH(1)->STATUS = STATUS_DONE_BIT;
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}
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}
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static void wait_matmul_done_intr(void)
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{
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while (!matmul_done_flag) { }
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matmul_done_flag = 0;
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}
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static void wait_dma_done_intr(int ch)
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{
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if (ch == 0) {
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while (!dma0_done_flag) { }
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dma0_done_flag = 0;
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} else {
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while (!dma1_done_flag) { }
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dma1_done_flag = 0;
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}
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}
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/* ═══════════════════════════════════════════════════════════════════ */
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int main(void)
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{
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if (MATMUL_GROUP_NUM <= 0) return 0;
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volatile uint32_t *extram = (volatile uint32_t *)EXTRAM_BASE_UNCACHED;
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uint32_t crc;
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int g;
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// Ping-Pong Register Address Arrays (Physical for DMA)
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uint32_t phys_bank_AB[2] = {MATMUL_PHYS_B0_AB, MATMUL_PHYS_B1_AB};
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uint32_t phys_bank_C[2] = {MATMUL_PHYS_B0_C, MATMUL_PHYS_B1_C};
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// IP Control Command Arrays
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uint32_t ctrl_start[2] = {CTRL_START_B0, CTRL_START_B1};
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/* ── Start marker (must be first output) ──────────────────── */
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printf("MATMUL_START\n");
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// 清理寄存器状态
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REG_WR(MATMUL_STATUS, STATUS_DONE | STATUS_ERROR);
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REG_WR(MATMUL_CRC, 0); // 复位硬件 CRC32 为 0xFFFFFFFF
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/* ── Prologue: 第0组数据初始化 ────────────────────────── */
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// DMA Ch0: 从 ExtRAM 将 Group 0 的 A、B (128 bytes) 搬入 IP 的 Bank 0
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dma_start_transfer(0, EXTRAM_PHYS_AB(0), phys_bank_AB[0], 128, 10);
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wait_dma_done_intr(0);
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// 启动 IP Bank 0 计算
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REG_WR(MATMUL_CTRL, ctrl_start[0]);
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/* ── Main Loop: 硬件完全流水线 (Overlapped Execution) ──── */
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// 在 g 循环中:
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// IP 正在计算 prev_bank (g-1)
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// DMA_CH0 正在加载 cur_bank (g)
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// DMA_CH1 正在写回 prev_prev_bank (g-2)
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for (g = 1; g < MATMUL_GROUP_NUM; g++) {
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int cur_bank = g % 2;
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int prev_bank = (g - 1) % 2;
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// 1. 发起加载下一组数据的 DMA 传输 (Channel 0: Memory -> IP)
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dma_start_transfer(0, EXTRAM_PHYS_AB(g), phys_bank_AB[cur_bank], 128, 10);
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// 2. 等待上一组在 IP 中的计算完成
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wait_matmul_done_intr();
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// 3. 确保上一次的结果写回 (Channel 1) 已经空闲
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if (g > 1) {
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wait_dma_done_intr(1);
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}
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// 4. 发起写回刚才计算完成的结果 (Channel 1: IP -> Memory)
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dma_start_transfer(1, phys_bank_C[prev_bank], EXTRAM_PHYS_C(g - 1), 192, 20);
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// 5. 确保当前要计算的输入数据 (Channel 0) 已经加载完毕
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wait_dma_done_intr(0);
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// 6. 立即启动当前组在 IP 中的计算
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REG_WR(MATMUL_CTRL, ctrl_start[cur_bank]);
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}
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/* ── Epilogue: 收尾最后一组 ───────────────────────────── */
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wait_matmul_done_intr(); // 等待最后一次计算完成
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wait_dma_done_intr(1); // 确保之前的 DMA CH1 空闲
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// DMA CH1 将最后一组结果写回
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dma_start_transfer(1, phys_bank_C[(MATMUL_GROUP_NUM - 1) % 2], EXTRAM_PHYS_C(MATMUL_GROUP_NUM - 1), 192, 20);
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wait_dma_done_intr(1);
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/* ── Read hardware CRC32 result ──────────────────────────── */
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crc = REG_RD(MATMUL_CRC);
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/* ── Final markers ────────────────────────────────────────── */
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printf("MATMUL_CRC32=%08lx\n", (unsigned long)crc);
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printf("MATMUL_DONE\n");
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return 0;
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} |