FallenSigh
c5072d7170
Wrap mlkem_top in an AXI4 burst slave (mlkem_axi_slave) mapped to the freed FFT slot 6 at 0x1f400000 (virtual 0xbf400000). The core runs on sys_clk/2 (25 MHz); the wrapper handles the clock-domain crossing: start toggle->pulse, wait-stated byte-preload handshake, busy/done sync, and direct readback taps (ek/dk/ct/ss). CPU drives it via a register map (CTRL/STATUS/CONFIG, d/z/msg, preload + readback windows). Wire into soc_top on the existing axiOut_6 nets (no crossbar change), add mlkem_intr on intrpt[3]. Add sdk mlkem_test example running a KeyGen->Encaps->Decaps self-consistency round trip.
20 lines
523 B
Verilog
20 lines
523 B
Verilog
module ntt_sync (
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input clk, rst_n,
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input [11:0] coeff_in,
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input valid_i,
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output ready_o,
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output [11:0] coeff_out,
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output valid_o,
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input ready_i,
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input mode,
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output done_o
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);
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ntt_core u_ntt_core (
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.clk(clk), .rst_n(rst_n),
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.coeff_in(coeff_in), .valid_i(valid_i), .ready_o(ready_o),
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.mode(mode),
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.coeff_out(coeff_out), .valid_o(valid_o), .ready_i(ready_i),
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.done_o(done_o)
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);
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endmodule
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