189 lines
10 KiB
Plaintext
189 lines
10 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
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| Date : Wed Jul 15 05:09:34 2026
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| Host : Roc_Wang running 64-bit major release (build 9200)
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| Command : report_power -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/power.rpt
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| Design : soc_top
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| Device : xc7a200tfbg676-1
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| Design State : routed
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| Grade : commercial
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| Process : typical
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| Characterization : Production
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Power Report
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Table of Contents
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-----------------
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1. Summary
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1.1 On-Chip Components
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1.2 Power Supply Summary
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1.3 Confidence Level
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2. Settings
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2.1 Environment
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2.2 Clock Constraints
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3. Detailed Reports
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3.1 By Hierarchy
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1. Summary
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----------
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+--------------------------+--------------+
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| Total On-Chip Power (W) | 0.779 |
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| Design Power Budget (W) | Unspecified* |
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| Power Budget Margin (W) | NA |
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| Dynamic (W) | 0.637 |
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| Device Static (W) | 0.142 |
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| Effective TJA (C/W) | 1.9 |
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| Max Ambient (C) | 83.5 |
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| Junction Temperature (C) | 26.5 |
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| Confidence Level | Low |
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| Setting File | --- |
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| Simulation Activity File | --- |
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| Design Nets Matched | NA |
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+--------------------------+--------------+
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* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
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1.1 On-Chip Components
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----------------------
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+--------------------------+-----------+----------+-----------+-----------------+
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| On-Chip | Power (W) | Used | Available | Utilization (%) |
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+--------------------------+-----------+----------+-----------+-----------------+
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| Clocks | 0.060 | 7 | --- | --- |
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| Slice Logic | 0.137 | 103629 | --- | --- |
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| LUT as Logic | 0.128 | 53158 | 133800 | 39.73 |
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| CARRY4 | 0.005 | 3669 | 33450 | 10.97 |
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| Register | 0.002 | 31000 | 267600 | 11.58 |
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| LUT as Distributed RAM | 0.001 | 740 | 46200 | 1.60 |
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| LUT as Shift Register | <0.001 | 1168 | 46200 | 2.53 |
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| F7/F8 Muxes | <0.001 | 2449 | 133800 | 1.83 |
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| Others | 0.000 | 333 | --- | --- |
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| Signals | 0.284 | 78815 | --- | --- |
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| Block RAM | 0.027 | 29.5 | 365 | 8.08 |
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| PLL | 0.102 | 1 | 10 | 10.00 |
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| I/O | 0.027 | 202 | 400 | 50.50 |
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| Static Power | 0.142 | | | |
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| Total | 0.779 | | | |
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+--------------------------+-----------+----------+-----------+-----------------+
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1.2 Power Supply Summary
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------------------------
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+-----------+-------------+-----------+-------------+------------+
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| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
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+-----------+-------------+-----------+-------------+------------+
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| Vccint | 1.000 | 0.545 | 0.512 | 0.033 |
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| Vccaux | 1.800 | 0.085 | 0.054 | 0.031 |
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| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 |
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| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
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| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
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| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
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| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
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| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
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| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
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| Vccbram | 1.000 | 0.003 | 0.002 | 0.001 |
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| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
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| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
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| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
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+-----------+-------------+-----------+-------------+------------+
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1.3 Confidence Level
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--------------------
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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| User Input Data | Confidence | Details | Action |
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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| Design implementation state | High | Design is routed | |
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| Clock nodes activity | High | User specified more than 95% of clocks | |
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| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
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| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
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| Device models | High | Device models are Production | |
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| Overall confidence level | Low | | |
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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2. Settings
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-----------
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2.1 Environment
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---------------
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+-----------------------+--------------------------+
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| Ambient Temp (C) | 25.0 |
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| ThetaJA (C/W) | 1.9 |
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| Airflow (LFM) | 250 |
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| Heat Sink | medium (Medium Profile) |
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| ThetaSA (C/W) | 3.4 |
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| Board Selection | medium (10"x10") |
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| # of Board Layers | 12to15 (12 to 15 Layers) |
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| Board Temperature (C) | 25.0 |
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+-----------------------+--------------------------+
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2.2 Clock Constraints
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---------------------
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+------------------+------------------------------------------+-----------------+
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| Clock | Domain | Constraint (ns) |
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+------------------+------------------------------------------+-----------------+
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| clk | clk | 20.0 |
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| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
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| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.0 |
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| mlkem_clk | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 13.0 |
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| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
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+------------------+------------------------------------------+-----------------+
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3. Detailed Reports
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-------------------
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3.1 By Hierarchy
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----------------
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+----------------------------+-----------+
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| Name | Power (W) |
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+----------------------------+-----------+
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| soc_top | 0.637 |
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| pll_clk.u_clk_pll | 0.103 |
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| inst | 0.103 |
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| u_Axi_CDC | 0.002 |
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| u_axi_uart_controller | 0.002 |
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| uart0 | 0.001 |
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| regs | 0.001 |
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| u_cdma_matmul_bridge | 0.001 |
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| u_confreg | 0.001 |
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| u_cpu | 0.027 |
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| addr_trans | 0.002 |
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| tlb_entry | 0.002 |
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| btb | 0.003 |
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| dcache | 0.004 |
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| icache | 0.005 |
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| u_csr | 0.001 |
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| u_mul | 0.008 |
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| u_fft_mlkem_axi_slave | 0.373 |
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| u_fft_controller | 0.031 |
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| u_FFT | 0.028 |
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| u_out0 | 0.001 |
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| u_out1 | 0.001 |
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| u_mlkem_axi_cdc | 0.003 |
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| wFifo | 0.001 |
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| u_mlkem_axi_slave | 0.339 |
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| u_mlkem | 0.332 |
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| u_matmul_axi_slave | 0.077 |
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| mult_inst[0].u_mult | 0.003 |
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| mult_inst[1].u_mult | 0.002 |
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| mult_inst[2].u_mult | 0.002 |
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| mult_inst[3].u_mult | 0.002 |
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| u_snix_axil_cdma_mux_8ch | 0.008 |
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| u_core_engine | 0.004 |
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| axis_fifo_u0 | 0.002 |
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+----------------------------+-----------+
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