update system design report
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doc/reports/system/evidence/vivado/utilization.rpt
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doc/reports/system/evidence/vivado/utilization.rpt
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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-------------------------------------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
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| Date : Wed Jul 15 05:09:26 2026
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| Host : Roc_Wang running 64-bit major release (build 9200)
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| Command : report_utilization -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/utilization.rpt
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| Design : soc_top
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| Device : 7a200tfbg676-1
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| Design State : Routed
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-------------------------------------------------------------------------------------------------------------------------------
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Utilization Design Information
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Table of Contents
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-----------------
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1. Slice Logic
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1.1 Summary of Registers by Type
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2. Slice Logic Distribution
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3. Memory
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4. DSP
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5. IO and GT Specific
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6. Clocking
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7. Specific Feature
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8. Primitives
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9. Black Boxes
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10. Instantiated Netlists
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1. Slice Logic
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--------------
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+----------------------------+-------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------------+-------+-------+-----------+-------+
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| Slice LUTs | 55066 | 0 | 133800 | 41.16 |
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| LUT as Logic | 53158 | 0 | 133800 | 39.73 |
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| LUT as Memory | 1908 | 0 | 46200 | 4.13 |
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| LUT as Distributed RAM | 740 | 0 | | |
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| LUT as Shift Register | 1168 | 0 | | |
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| Slice Registers | 31000 | 0 | 267600 | 11.58 |
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| Register as Flip Flop | 31000 | 0 | 267600 | 11.58 |
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| Register as Latch | 0 | 0 | 267600 | 0.00 |
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| F7 Muxes | 2130 | 0 | 66900 | 3.18 |
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| F8 Muxes | 319 | 0 | 33450 | 0.95 |
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+----------------------------+-------+-------+-----------+-------+
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1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0 | _ | - | - |
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| 0 | _ | - | Set |
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| 0 | _ | - | Reset |
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| 0 | _ | Set | - |
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| 0 | _ | Reset | - |
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| 0 | Yes | - | - |
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| 24 | Yes | - | Set |
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| 17683 | Yes | - | Reset |
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| 126 | Yes | Set | - |
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| 13167 | Yes | Reset | - |
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+-------+--------------+-------------+--------------+
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2. Slice Logic Distribution
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---------------------------
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+--------------------------------------------+-------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+--------------------------------------------+-------+-------+-----------+-------+
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| Slice | 17126 | 0 | 33450 | 51.20 |
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| SLICEL | 11119 | 0 | | |
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| SLICEM | 6007 | 0 | | |
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| LUT as Logic | 53158 | 0 | 133800 | 39.73 |
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| using O5 output only | 5 | | | |
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| using O6 output only | 42769 | | | |
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| using O5 and O6 | 10384 | | | |
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| LUT as Memory | 1908 | 0 | 46200 | 4.13 |
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| LUT as Distributed RAM | 740 | 0 | | |
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| using O5 output only | 0 | | | |
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| using O6 output only | 60 | | | |
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| using O5 and O6 | 680 | | | |
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| LUT as Shift Register | 1168 | 0 | | |
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| using O5 output only | 123 | | | |
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| using O6 output only | 997 | | | |
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| using O5 and O6 | 48 | | | |
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| Slice Registers | 31000 | 0 | 267600 | 11.58 |
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| Register driven from within the Slice | 16668 | | | |
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| Register driven from outside the Slice | 14332 | | | |
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| LUT in front of the register is unused | 5924 | | | |
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| LUT in front of the register is used | 8408 | | | |
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| Unique Control Sets | 930 | | 33450 | 2.78 |
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+--------------------------------------------+-------+-------+-----------+-------+
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* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
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3. Memory
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---------
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+-------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------------+------+-------+-----------+-------+
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| Block RAM Tile | 29.5 | 0 | 365 | 8.08 |
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| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
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| RAMB36E1 only | 10 | | | |
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| RAMB18 | 39 | 0 | 730 | 5.34 |
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| RAMB18E1 only | 39 | | | |
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+-------------------+------+-------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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4. DSP
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------
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+-----------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------+------+-------+-----------+-------+
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| DSPs | 0 | 0 | 740 | 0.00 |
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+-----------+------+-------+-----------+-------+
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5. IO and GT Specific
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---------------------
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+-----------------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------------------------+------+-------+-----------+-------+
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| Bonded IOB | 202 | 202 | 400 | 50.50 |
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| IOB Master Pads | 97 | | | |
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| IOB Slave Pads | 102 | | | |
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| Bonded IPADs | 0 | 0 | 26 | 0.00 |
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| Bonded OPADs | 0 | 0 | 16 | 0.00 |
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| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
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| PHASER_REF | 0 | 0 | 10 | 0.00 |
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| OUT_FIFO | 0 | 0 | 40 | 0.00 |
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| IN_FIFO | 0 | 0 | 40 | 0.00 |
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| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
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| IBUFDS | 0 | 0 | 384 | 0.00 |
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| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 |
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| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
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| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
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| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
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| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
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| ILOGIC | 0 | 0 | 400 | 0.00 |
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| OLOGIC | 0 | 0 | 400 | 0.00 |
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+-----------------------------+------+-------+-----------+-------+
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6. Clocking
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-----------
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+------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+------------+------+-------+-----------+-------+
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| BUFGCTRL | 4 | 0 | 32 | 12.50 |
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| BUFIO | 0 | 0 | 40 | 0.00 |
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| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
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| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
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| BUFMRCE | 0 | 0 | 20 | 0.00 |
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| BUFHCE | 0 | 0 | 120 | 0.00 |
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| BUFR | 0 | 0 | 40 | 0.00 |
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+------------+------+-------+-----------+-------+
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7. Specific Feature
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-------------------
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+-------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------+------+-------+-----------+-------+
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| BSCANE2 | 0 | 0 | 4 | 0.00 |
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| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
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| DNA_PORT | 0 | 0 | 1 | 0.00 |
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| EFUSE_USR | 0 | 0 | 1 | 0.00 |
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| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
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| ICAPE2 | 0 | 0 | 2 | 0.00 |
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| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
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| STARTUPE2 | 0 | 0 | 1 | 0.00 |
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| XADC | 0 | 0 | 1 | 0.00 |
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+-------------+------+-------+-----------+-------+
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8. Primitives
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-------------
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+-----------+-------+---------------------+
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| Ref Name | Used | Functional Category |
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+-----------+-------+---------------------+
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| LUT6 | 26800 | LUT |
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| FDCE | 17683 | Flop & Latch |
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| FDRE | 13167 | Flop & Latch |
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| LUT3 | 10370 | LUT |
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| LUT4 | 8684 | LUT |
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| LUT2 | 8543 | LUT |
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| LUT5 | 8274 | LUT |
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| CARRY4 | 3669 | CarryLogic |
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| MUXF7 | 2130 | MuxFx |
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| RAMD32 | 1060 | Distributed Memory |
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| SRLC32E | 992 | Distributed Memory |
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| LUT1 | 871 | LUT |
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| RAMS32 | 328 | Distributed Memory |
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| MUXF8 | 319 | MuxFx |
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| SRL16E | 224 | Distributed Memory |
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| FDSE | 126 | Flop & Latch |
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| IBUF | 104 | IO |
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| OBUF | 98 | IO |
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| OBUFT | 66 | IO |
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| RAMB18E1 | 39 | Block Memory |
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| RAMD64E | 32 | Distributed Memory |
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| FDPE | 24 | Flop & Latch |
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| RAMB36E1 | 10 | Block Memory |
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| BUFG | 4 | Clock |
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| PLLE2_ADV | 1 | Clock |
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+-----------+-------+---------------------+
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9. Black Boxes
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--------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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10. Instantiated Netlists
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-------------------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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| clk_pll | 1 |
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+----------+------+
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