diff --git a/doc/reports/system/.gitignore b/doc/reports/system/.gitignore deleted file mode 100644 index afc54af..0000000 --- a/doc/reports/system/.gitignore +++ /dev/null @@ -1,10 +0,0 @@ -system_design_report.aux -system_design_report.fdb_latexmk -system_design_report.fls -system_design_report.log -system_design_report.out -system_design_report.synctex.gz -system_design_report.toc -system_design_report.xdv -tools/__pycache__/ -evidence/**/*.vcd diff --git a/doc/reports/system/Makefile b/doc/reports/system/Makefile deleted file mode 100644 index 859c81f..0000000 --- a/doc/reports/system/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -.PHONY: all figures metrics pdf check clean - -DOT_SOURCES := $(wildcard figures/*.dot) -FIGURE_PDFS := $(DOT_SOURCES:.dot=.pdf) - -all: pdf check - -figures: $(FIGURE_PDFS) - -figures/%.pdf: figures/%.dot - dot -Tpdf -Gfontnames=svg $< -o $@ - -metrics: - python3 tools/update_report_metrics.py - -pdf: figures - latexmk -xelatex -interaction=nonstopmode -halt-on-error system_design_report.tex - -check: pdf - @! rg -n 'undefined references|Citation .* undefined|Reference .* undefined|There were undefined references' system_design_report.log - @pdfinfo system_design_report.pdf | rg '^Pages:|^File size:' - -clean: - latexmk -C system_design_report.tex - rm -f $(FIGURE_PDFS) diff --git a/doc/reports/system/REPORT_RERUN_CHECKLIST.md b/doc/reports/system/REPORT_RERUN_CHECKLIST.md deleted file mode 100644 index 2c40503..0000000 --- a/doc/reports/system/REPORT_RERUN_CHECKLIST.md +++ /dev/null @@ -1,233 +0,0 @@ -# 系统报告复测清单 - -本清单用于为 `system_design_report.tex` 生成同一提交、可追溯的证据。不要把旧的 -`fpga/vivado_reports_nodsp/` 与新板级日志混合后宣称为同一版本结果。 - -## 0. 固化版本与环境 - -在仓库根目录执行并保存输出： - -```bash -git status --short -git rev-parse HEAD -vivado -version | head -n 3 -verilator --version -``` - -建议先提交当前 RTL/约束/软件变更。若工作树不干净，最终报告的证据版本无法唯一复现。 - -## 1. 必跑：RTL 静态检查 - -```bash -cd doc/reports/system -./tools/run_report_tests.sh lint -``` - -通过标准：命令退出码为 0，`evidence/lint.log` 中无 `%Error`。此项只证明静态可分析， -不证明 AXI、CDC 或算法功能正确。 - -## 2. 必跑：SoC 功能回归 - -仅编译指定软件、不运行仿真： - -```bash -cd doc/reports/system -./tools/run_report_tests.sh build -``` - -需要同时运行 SoC 仿真时： - -```bash -cd doc/reports/system -./tools/run_report_tests.sh soc -``` - -需要保存 VCD 时使用可选开关。默认只记录 `tb_top` 的时钟、复位、UART 和提交 PC， -文件写入 `evidence/soc/<用例>.vcd`。记录内部模块时用 `VCD_SCOPE` 指定层次；长时间 -软件测试若递归记录整个 SoC，可能产生数 GB 文件： - -```bash -SAVE_VCD=1 \ -VCD_SCOPE='/tb_top/u_soc_top/u_fft_mlkem_axi_slave/u_mlkem_axi_slave/*' \ -./tools/run_report_tests.sh soc -``` - -启用 VCD 后 elaboration 使用 `debug_level=typical`，并从 0 ns 开始记录，因此包含 -上电复位和复位释放过程。只需要短窗口诊断时可额外设置 `SIM_RUN_TIME=20us`；该选项 -会在软件完成前退出，不能作为功能回归通过证据。VCD 属于大体积临时证据，默认被 -Git 忽略。 - -软件集合固定为 `asm`、`fft`、`fft_dma`、`mlkem_test` 和 `mlkem_hello`。默认 `soc` -会编译全部五项，但只对 `mlkem_test` 和 `mlkem_hello` 运行通用 `tb_top` 仿真。 -`asm` 需要官方 ExtRAM 数据和专用 matmul 流程；`fft` 和 `fft_dma` 包含耗时很长的 -软件 FFT 参考计算，因此默认只做编译检查。每次构建都会覆盖 `sdk/axi_ram.mif`，不要 -并行执行这些用例。构建日志位于 `evidence/build/`。 - -需要更新 FFT 当前提交的功能或性能证据时，再单独执行长仿真： - -```bash -./tools/run_report_tests.sh soc-fft -``` - -没有执行 `soc-fft` 且没有生成当前提交的板级日志时，报告中的 FFT 数值只能标记为 -历史基线，不能声明为当前提交的功能回归结果。 -脚本会设置 `CCACHE_DISABLE=1`，避免 Vivado 2019.2 在编译 XSIM 自动生成的 C 文件时 -因 ccache 目录不可写而只报告不透明的 `XSIM 43-3409`。 -同时会将 `/lib64` 加入 XSIM 子进程库路径，避免旧版 Vivado clang 混用不匹配的 -`libncurses.so.5` 与 `libtinfo.so.5`。 - -逐项检查： - -| 日志 | 必须出现 | 不得出现 | -|---|---|---| -| `evidence/build/{asm,fft,fft_dma,mlkem_test,mlkem_hello}.log` | 编译、链接和 objcopy 成功 | `Error` | -| `evidence/soc/mlkem_test.log` | `MLKEM_RESULT=PASS`、`MLKEM_DONE` | 任一 `FAILS` 非 0 | -| `evidence/soc/mlkem_hello.log` | `MLKEM_HELLO_RESULT=PASS`、`MLKEM_HELLO_DONE` | `RESULT=FAIL` | - -若执行了可选的 `soc-fft`，再检查： - -| 日志 | 必须出现 | 不得出现 | -|---|---|---| -| `evidence/soc/fft.log` | Hardware/Software FFT Time；更新后的程序应输出 `Max Abs Error` | 仿真超时、X/Z 扩散 | -| `evidence/soc/fft_dma.log` | Hardware/Software FFT Time、`Max Abs Error` | DMA 死锁、仿真超时 | - -### FFT 板级验证（推荐） - -FFT 的软件浮点参考在 RTL 仿真中耗时很长，默认使用板级测试作为当前提交的功能与性能 -证据。使用同一提交生成的 bitstream，分别下载 `fft` 和 `fft_dma` 的程序镜像，在 -115200 baud 下保存完整 UART 输出： - -```text -doc/reports/system/evidence/board/fft.log -doc/reports/system/evidence/board/fft_dma.log -``` - -`fft.log` 必须出现： - -```text -FFT_MAX_ABS_ERROR_RE=<不大于8> -FFT_MAX_ABS_ERROR_IM=<不大于8> -FFT_ERROR_LIMIT=8 -FFT_RESULT=PASS -FFT_DONE -``` - -`fft_dma.log` 必须出现： - -```text -FFT_DMA_MAX_ABS_ERROR_RE=<不大于8> -FFT_DMA_MAX_ABS_ERROR_IM=<不大于8> -FFT_DMA_ERROR_LIMIT=8 -FFT_DMA_RESULT=PASS -FFT_DMA_DONE -``` - -两项日志还必须保留 Hardware/Software FFT Time 和 Speedup Ratio。每项至少冷启动运行 -3 次，确认结果和最大误差稳定；DMA 用例还要确认没有轮询死锁。板级日志存在时， -`update_report_metrics.py` 会优先于 XSIM 日志读取它们。 - -ML-KEM 的正确计数是 3 个固定 KAT 向量、900 次执行，不是 360 个不同 KAT。若要在 -报告中声称覆盖隐式拒绝，必须另外增加“篡改 ciphertext 后共享密钥不等且流程按规范 -完成”的负向测试；当前脚本不提供该证据。 - -## 3. 必跑：重新布局布线与实现取证 - -完整实现耗时较长，单独执行： - -```bash -cd doc/reports/system -./tools/run_report_tests.sh implement -``` - -该命令先从 `synth_1` 开始强制重跑，重新综合/布局布线并生成 bitstream，随后生成以下文件： - -- `evidence/vivado/timing_summary_full.rpt` -- `evidence/vivado/utilization.rpt` -- `evidence/vivado/utilization_hierarchical.rpt` -- `evidence/vivado/power.rpt` -- `evidence/vivado/clock_interaction.rpt` -- `evidence/vivado/cdc.rpt` -- `evidence/vivado/drc.rpt` -- `evidence/vivado/methodology.rpt` -- `evidence/vivado/route_status.rpt` -- `evidence/vivado/dsp_check.log` - -通过标准： - -- Setup WNS 和 Hold WNS 均不小于 0； -- failing endpoints 为 0，unconstrained paths 为 0； -- CPU、SYS、ML-KEM 三个预期时钟均存在且频率正确； -- `dsp_check.log` 显示 DSP used 为 0； -- route status 为 fully routed； -- DRC/methodology 无 Critical Warning 被忽略； -- CDC 报告中的跨域均能对应到设计文档里的握手、同步器或异步 FIFO。`report_cdc` - 退出码为 0 不等于 CDC 自动通过，仍需人工查看不安全类别和时钟约束。 - -功耗报告若仍显示 `Confidence Level: Low`，报告中只能称为 vectorless estimate。需要 -正式功耗结论时，应对代表性 ML-KEM 和 matmul 负载回标 SAIF/VCD，再重新运行 -`report_power`；这不是当前满分评测的前置条件。 - -## 4. 必跑：官方 5000 组 matmul 板级评测 - -使用最终 bitstream 和最终 `user-sample.bin`，保持： - -```text -MATMUL_GROUP_NUM=5000 -MATMUL_FAST_START=1 -MATMUL_WRITEBACK_RESULTS=0 -``` - -运行官方评测工具，将完整控制台输出保存为： - -```text -doc/reports/system/evidence/board/matmul_official.log -``` - -必须保留这些行：随机种子、Expected CRC32、`MATMUL_START`、`MATMUL_DONE`、Elapsed -time、Reported/Expected CRC32、Score percent。通过标准为 CRC 匹配、22 s 内收到 -DONE。性能目标是小于等于 4.9 ms；同时记录硬件 `DMA_CYCLES`，用于区分内部批处理 -周期与串口/软件尾部开销。 - -至少连续运行 5 个不同随机种子。报告主表填写中位数，附录写 min/median/max；不要只 -选择最好一次。 - -## 5. 必跑：复位前零操作 - -竞赛约束要求复位前无任何操作。至少覆盖以下信号：UART 写使能、AXI AW/AR/W valid、 -DMA request、matmul start、ML-KEM start。观察窗口从上电开始到每个时钟域同步复位释放。 - -推荐二选一： - -1. 在 Vivado 仿真 testbench 中加入断言，任一信号在 reset 有效时拉高即 `$fatal`； -2. 板上 ILA 同时采集外部 reset、PLL locked、各域 resetn 和上述事务信号。 - -保存断言日志或 ILA 截图，并在文件名中包含提交短哈希。仅观察“串口没有字符”不足以 -证明 DMA 和 AXI 没有操作。 - -## 6. 建议补跑：matmul 仿真与稳健性 - -- 组数：1、2、3、5000，覆盖 Bank 翻转和最后一组； -- DMA endpoint：对 valid/ready 随机插入 backpressure； -- 边界数据：全 0、全 `0xffffffff`、单位矩阵、随机矩阵； -- 控制：done W1C 后立即启动下一批，检查 CRC 清零与 group counter； -- XSIM 与 Verilator 都运行。两者结果不一致时按 RTL 竞态/未初始化问题处理，不能只保留 - 通过的仿真器结果。 - -## 7. 回填指标并生成 PDF - -所有日志就位后执行： - -```bash -cd doc/reports/system -./tools/run_report_tests.sh refresh -``` - -该命令会： - -1. 从 `evidence/` 提取 PPA、ML-KEM、FFT 和 matmul 指标； -2. 更新 `report_metrics.tex`； -3. 从 `figures/*.dot` 生成 PDF 矢量图； -4. 用 XeLaTeX 多轮编译报告并检查未解析引用。 - -最终人工检查：目录非空、没有“图??/表??”、所有图中文字可读、报告中的 commit 与 -bitstream/日志一致、所有“待复测”结论已经按真实证据更新。 diff --git a/doc/reports/system/evidence/README.md b/doc/reports/system/evidence/README.md index e02e416..3f58581 100644 --- a/doc/reports/system/evidence/README.md +++ b/doc/reports/system/evidence/README.md @@ -2,12 +2,23 @@ Generated logs and Vivado reports used by `system_design_report.tex` live here: -- `soc/`: UART output from SoC simulations +- `soc/`: short SoC simulation evidence; `reset_window.vcd` records reset and pre-reset transaction signals - `build/`: software build logs for the five selected examples -- `vivado/`: timing, utilization, CDC, DRC, route and power reports -- `board/`: official matmul evaluation plus FFT/FFT-DMA board UART logs +- `vivado/`: timing, utilization, DRC, route and power reports +- `board/`: official matmul evaluation plus FFT and ML-KEM board UART logs + +The report currently consumes these board filenames: + +- `fft_1.log`, `fft_2.log`, `fft_3.log` +- `fft_dma_1.log`, `fft_dma_2.log`, `fft_dma_3.log` +- `mlkem_test_512.log`, `mlkem_test_768.log`, `mlkem_test_1024.log` +- `mlkem_hello.log` +- `matmul_official.log` (three complete official runs in one file) + +Reset screenshots derived from `soc/reset_window.vcd` belong in `../figures/` as +`reset_release.png` and `reset_no_transaction.png`. Run `../tools/run_report_tests.sh refresh` after replacing evidence. Large generated -artifacts such as `.vcd`, `.wdb`, `.jou`, `.str`, implementation checkpoints and -bitstreams do not belong in Git. SoC VCD files may be generated here temporarily with -`SAVE_VCD=1`; archive them separately when they are needed as report evidence. +artifacts such as `.wdb`, `.jou`, `.str`, implementation checkpoints and bitstreams do +not belong in Git. The short reset VCD may be retained as report evidence; avoid tracing +the complete SoC for long software runs because the result can grow to several GB. diff --git a/doc/reports/system/evidence/vivado/cdc.rpt b/doc/reports/system/evidence/vivado/cdc.rpt new file mode 100644 index 0000000..f814ef9 --- /dev/null +++ b/doc/reports/system/evidence/vivado/cdc.rpt @@ -0,0 +1,390 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Wed Jul 15 05:09:36 2026 +| Host : Roc_Wang running 64-bit major release (build 9200) +| Command : report_cdc -details -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/cdc.rpt +| Design : soc_top +| Device : 7a200t-fbg676 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +------------------------------------------------------------------------------------------------------------------------ + +CDC Report + +ID Severity Count Description +------ -------- ----- ------------------------------------------------------- +CDC-3 Info 1 1-bit synchronized with ASYNC_REG property +CDC-6 Warning 20 Multi-bit synchronized with ASYNC_REG property +CDC-7 Critical 1 Asynchronous reset unknown CDC circuitry +CDC-9 Info 3 Asynchronous reset synchronized with ASYNC_REG property +CDC-11 Critical 2 Fan-out from launch flop to destination clock +CDC-15 Warning 313 Clock enable controlled CDC structure detected + +Source Clock: sys_clk +Destination Clock: cpu_clk +CDC Type: User Ignored + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ------ -------- ---------------------------------------------- ----- ------------------- ---------------------------------------------- ------------------------------------------------------------ + 1 CDC-11 Critical Fan-out from launch flop to destination clock 2 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C pll_clk.u_rst_cpu/delay_reg[0]/CLR + 2 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2:0]/C u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D + 3 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2:0]/C u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D + 4 CDC-11 Critical Fan-out from launch flop to destination clock 2 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR + 5 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2:0]/C u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D + 6 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D + 7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D + 8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D + 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D + 10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + 11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D + 12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D + 13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D + 14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D + 15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D + 16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D + 17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D + 18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D + 19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + 20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + 21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D + 22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D + 23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D + 24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D + 25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D + 26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D + 27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D + 28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D + 29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D + 30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D + 31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D + 32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D + 33 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D + 34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D + 35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D + 36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D + 37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D + 38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D + 39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D + 40 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3:0]/C u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D + 41 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3:0]/C u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D + 42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_confreg/int_out_or_q2_reg/C u_cpu/u_csr/csr_estat_reg[2]/D + 43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_cdma_matmul_bridge/seq_done_flag_reg/C u_cpu/u_csr/csr_estat_reg[3]/D + 44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_matmul_axi_slave/done_reg/C u_cpu/u_csr/csr_estat_reg[4]/D + 45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C u_cpu/u_csr/csr_estat_reg[5]/D + +Source Clock: sys_clk +Destination Clock: mlkem_clk +CDC Type: User Ignored + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ------ -------- ------------------------------------------------------- ----- ------------------- -------------------------------------------------------------------------- ---------------------------------------------------------------------------------------- + 1 CDC-7 Critical Asynchronous reset unknown CDC circuitry 0 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C pll_clk.u_rst_mlkem/delay_reg[0]/CLR + 2 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D + 3 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D + 4 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D + 5 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D + 6 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D + 7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D + 8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D + 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D + 10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D + 11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D + 12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D + 13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11]/D + 14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D + 15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D + 16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D + 17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D + 18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D + 19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D + 20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D + 21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D + 22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D + 23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D + 24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D + 25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D + 26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D + 27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D + 28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D + 29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D + 30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D + 31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D + 32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D + 33 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D + 34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D + 35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D + 36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D + 37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D + 38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D + 39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[5]/D + 40 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D + 41 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D + 42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D + 43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D + 44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D + 45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D + 46 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12]/D + 47 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D + 48 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D + 49 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D + 50 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D + 51 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D + 52 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D + 53 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D + 54 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D + 55 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D + 56 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D + 57 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR + 58 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D + 59 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D + 60 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D + 61 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D + 62 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D + 63 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D + 64 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/D + 65 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D + 66 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D + 67 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D + 68 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D + 69 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/D + 70 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D + 71 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10]/D + 72 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D + 73 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D + 74 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D + 75 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D + 76 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D + 77 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D + 78 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/D + 79 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D + 80 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D + 81 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D + 82 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D + 83 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D + 84 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D + 85 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D + 86 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D + 87 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D + 88 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D + 89 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D + 90 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D + 91 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D + 92 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D + 93 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32]/D + 94 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D + 95 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D + 96 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D + 97 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D + 98 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D + +Source Clock: cpu_clk +Destination Clock: sys_clk +CDC Type: User Ignored + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ------ -------- ------------------------------------------------------- ----- ------------------- ---------------------------------------------- ------------------------------------------------------------ + 1 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D + 2 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[1]/D + 3 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D + 4 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D + 5 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D + 6 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D + 7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D + 8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D + 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D + 10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D + 11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D + 12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/D + 13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D + 14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D + 15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[14]/D + 16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D + 17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[16]/D + 18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[17]/D + 19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D + 20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D + 21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[20]/D + 22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D + 23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D + 24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D + 25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D + 26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D + 27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/D + 28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[27]/D + 29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[28]/D + 30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D + 31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D + 32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D + 33 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D + 34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/D + 35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/D + 36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D + 37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D + 38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[38]/D + 39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[39]/D + 40 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[40]/D + 41 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D + 42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D + 43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[43]/D + 44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D + 45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D + 46 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D + 47 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[47]/D + 48 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D + 49 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D + 50 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[50]/D + 51 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/D + 52 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[52]/D + 53 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/D + 54 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2:0]/C u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D + 55 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D + 56 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D + 57 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D + 58 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D + 59 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[4]/D + 60 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D + 61 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D + 62 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D + 63 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D + 64 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[9]/D + 65 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[10]/D + 66 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[11]/D + 67 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D + 68 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D + 69 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[14]/D + 70 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[15]/D + 71 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[16]/D + 72 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/D + 73 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D + 74 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D + 75 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[20]/D + 76 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D + 77 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D + 78 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[23]/D + 79 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D + 80 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D + 81 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[26]/D + 82 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[27]/D + 83 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[28]/D + 84 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[29]/D + 85 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D + 86 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D + 87 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D + 88 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D + 89 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[34]/D + 90 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D + 91 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D + 92 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[38]/D + 93 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D + 94 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/D + 95 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D + 96 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D + 97 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D + 98 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D + 99 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D +100 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/D +101 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D +102 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D +103 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D +104 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/D +105 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D +106 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/D +107 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D +108 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 Asynch Clock Groups pll_clk.u_rst_cpu/delay_reg[1]/C u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR +109 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2:0]/C u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D +110 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2:0]/C u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D +111 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3:0]/C u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D +112 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D +113 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D +114 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D +115 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[3]/D +116 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[4]/D +117 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/D +118 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D +119 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D +120 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D +121 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/D +122 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D +123 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[11]/D +124 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D +125 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D +126 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D +127 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[15]/D +128 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D +129 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/D +130 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D +131 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D +132 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[20]/D +133 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/D +134 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D +135 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D +136 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D +137 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D +138 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[26]/D +139 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/D +140 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D +141 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D +142 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D +143 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D +144 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[32]/D +145 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[33]/D +146 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D +147 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/D +148 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D +149 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3:0]/C u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D + +Source Clock: mlkem_clk +Destination Clock: sys_clk +CDC Type: User Ignored + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ------ -------- ------------------------------------------------------- ----- ------------------- ------------------------------------------------------------------------- ---------------------------------------------------------------------------------------- + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D + 2 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D + 3 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D + 4 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D + 5 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 Asynch Clock Groups pll_clk.u_rst_mlkem/delay_reg[1]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR + 6 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D + 7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D + 8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D + 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D + 10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D + 11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D + 12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D + 13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D + 14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D + 15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D + 16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D + 17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D + 18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D + 19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D + 20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D + 21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D + 22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D + 23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D + 24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D + 25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D + 26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D + 27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D + 28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D + 29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D + 30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D + 31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D + 32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D + 33 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D + 34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D + 35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D + 36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D + 37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D + 38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D + 39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D + 40 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D + 41 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D + 42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D + 43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D + 44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D + 45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D + 46 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D + 47 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D + 48 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D + diff --git a/doc/reports/system/evidence/vivado/clock_interaction.rpt b/doc/reports/system/evidence/vivado/clock_interaction.rpt new file mode 100644 index 0000000..02fe739 --- /dev/null +++ b/doc/reports/system/evidence/vivado/clock_interaction.rpt @@ -0,0 +1,28 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Wed Jul 15 05:09:35 2026 +| Host : Roc_Wang running 64-bit major release (build 9200) +| Command : report_clock_interaction -delay_type min_max -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/clock_interaction.rpt +| Design : soc_top +| Device : 7a200t-fbg676 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +--------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Clock Interaction Report + +Clock Interaction Table +----------------------- + + WNS TNS Failing TNS Total WNS Path WHS THS Failing THS Total WHS Path Clock-Pair Inter-Clock +From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Clock Edges WHS(ns) THS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints +---------------- ---------------- ----------- ------- ------- ----------- ----------- --------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- ------------------- +cpu_clk cpu_clk rise - rise 0.74 0.00 0 17264 30.00 rise - rise 0.04 0.00 0 17264 0.00 Clean Timed +cpu_clk sys_clk 0 162 0 162 Ignored Asynchronous Groups +mlkem_clk mlkem_clk rise - rise 0.07 0.00 0 48386 13.00 rise - rise 0.06 0.00 0 48386 0.00 Clean Timed +mlkem_clk sys_clk 0 61 0 61 Ignored Asynchronous Groups +sys_clk cpu_clk 0 59 0 59 Ignored Asynchronous Groups +sys_clk mlkem_clk 0 112 0 112 Ignored Asynchronous Groups +sys_clk sys_clk rise - rise 0.12 0.00 0 23193 20.00 rise - rise 0.02 0.00 0 23193 0.00 Clean Timed + + diff --git a/doc/reports/system/evidence/vivado/clocks.rpt b/doc/reports/system/evidence/vivado/clocks.rpt new file mode 100644 index 0000000..2bb29db --- /dev/null +++ b/doc/reports/system/evidence/vivado/clocks.rpt @@ -0,0 +1,76 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Wed Jul 15 05:09:25 2026 +| Host : Roc_Wang running 64-bit major release (build 9200) +| Command : report_clocks -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/clocks.rpt +| Design : soc_top +| Device : 7a200t-fbg676 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +--------------------------------------------------------------------------------------------------------------------- + +Clock Report + + +Attributes + P: Propagated + G: Generated + A: Auto-derived + R: Renamed + V: Virtual + I: Inverted + S: Pin phase-shifted with Latency mode + +Clock Period(ns) Waveform(ns) Attributes Sources +clk 20.000 {0.000 10.000} P {clk} +clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT} +cpu_clk 30.000 {0.000 15.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0} +mlkem_clk 13.000 {0.000 6.500} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2} +sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1} + + +==================================================== +Generated Clocks +==================================================== + +Generated Clock : clkfbout_clk_pll +Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 +Master Clock : clk +Multiply By : 1 +Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT} + +Generated Clock : cpu_clk +Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 +Master Clock : clk +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 5.000 10.000} +Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0} + +Generated Clock : mlkem_clk +Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 +Master Clock : clk +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 -3.500 -7.000} +Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2} + +Generated Clock : sys_clk +Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 +Master Clock : clk +Multiply By : 1 +Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1} + + + +==================================================== +User Uncertainty +==================================================== + + + +==================================================== +User Jitter +==================================================== + +Clock Jitter(ns) +clk 0.200 + diff --git a/doc/reports/system/evidence/vivado/drc.rpt b/doc/reports/system/evidence/vivado/drc.rpt new file mode 100644 index 0000000..8097d57 --- /dev/null +++ b/doc/reports/system/evidence/vivado/drc.rpt @@ -0,0 +1,248 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Wed Jul 15 05:09:39 2026 +| Host : Roc_Wang running 64-bit major release (build 9200) +| Command : report_drc -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/drc.rpt +| Design : soc_top +| Device : xc7a200tfbg676-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: impl_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 42 ++-----------+----------+----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+----------------------------+------------+ +| CHECK-3 | Warning | Report rule limit reached | 2 | +| REQP-1839 | Warning | RAMB36 async control check | 20 | +| REQP-1840 | Warning | RAMB18 async control check | 20 | ++-----------+----------+----------------------------+------------+ + +2. REPORT DETAILS +----------------- +CHECK-3#1 Warning +Report rule limit reached +REQP-1839 rule limit reached: 20 violations have been found. +Related violations: + +CHECK-3#2 Warning +Report rule limit reached +REQP-1840 rule limit reached: 20 violations have been found. +Related violations: + +REQP-1839#1 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#2 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#3 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#4 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#5 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#6 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#7 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#8 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#9 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#10 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#11 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#12 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#13 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#14 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#15 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#16 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#17 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#18 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#19 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1839#20 Warning +RAMB36 async control check +The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#1 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#2 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#3 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#4 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#5 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#6 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#7 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#8 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#9 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#10 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#11 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#12 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#13 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#14 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#15 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#16 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#17 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#18 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#19 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + +REQP-1840#20 Warning +RAMB18 async control check +The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +Related violations: + + diff --git a/doc/reports/system/evidence/vivado/methodology.rpt b/doc/reports/system/evidence/vivado/methodology.rpt new file mode 100644 index 0000000..f9cb812 --- /dev/null +++ b/doc/reports/system/evidence/vivado/methodology.rpt @@ -0,0 +1,623 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Wed Jul 15 05:09:49 2026 +| Host : Roc_Wang running 64-bit major release (build 9200) +| Command : report_methodology -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/methodology.rpt +| Design : soc_top +| Device : xc7a200tfbg676-1 +| Speed File : -1 +| Design State : Fully Routed +------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: impl_1 + Design limits: + Max violations: + Violations found: 115 ++-----------+----------+-------------------------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-------------------------------------------------------------------+------------+ +| LUTAR-1 | Warning | LUT drives async reset alert | 1 | +| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 8 | +| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 6 | +| SYNTH-16 | Warning | Address collision | 16 | +| TIMING-9 | Warning | Unknown CDC Logic | 1 | +| TIMING-10 | Warning | Missing property on synchronizer | 1 | +| TIMING-18 | Warning | Missing input or output delay | 76 | +| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 4 | +| XDCC-1 | Warning | Scoped Clock constraint overwritten with the same name | 1 | +| XDCC-7 | Warning | Scoped Clock constraint overwritten on the same source | 1 | ++-----------+----------+-------------------------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +LUTAR-1#1 Warning +LUT drives async reset alert +LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 15633 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +SYNTH-5#1 Warning +Mapped onto distributed RAM because of timing constraints +The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#2 Warning +Mapped onto distributed RAM because of timing constraints +The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#3 Warning +Mapped onto distributed RAM because of timing constraints +The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#4 Warning +Mapped onto distributed RAM because of timing constraints +The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#5 Warning +Mapped onto distributed RAM because of timing constraints +The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#6 Warning +Mapped onto distributed RAM because of timing constraints +The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#7 Warning +Mapped onto distributed RAM because of timing constraints +The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#8 Warning +Mapped onto distributed RAM because of timing constraints +The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-6#1 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#2 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#3 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#4 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#5 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#6 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-16#1 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#2 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#3 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#4 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#5 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#6 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#7 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#8 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#9 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#10 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#11 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#12 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#13 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#14 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#15 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#16 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +TIMING-9#1 Warning +Unknown CDC Logic +One or more asynchronous Clock Domain Crossing has been detected between 2 clock domains through a set_false_path or a set_clock_groups or set_max_delay -datapath_only constraint but no double-registers logic synchronizer has been found on the side of the capture clock. It is recommended to run report_cdc for a complete and detailed CDC coverage. Please consider using XPM_CDC to avoid Critical severities +Related violations: + +TIMING-10#1 Warning +Missing property on synchronizer +One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage +Related violations: + +TIMING-18#1 Warning +Missing input or output delay +An input delay is missing on UART_RX relative to clock(s) clk +Related violations: + +TIMING-18#2 Warning +Missing input or output delay +An input delay is missing on UART_TX relative to clock(s) clk +Related violations: + +TIMING-18#3 Warning +Missing input or output delay +An input delay is missing on dip_sw[0] relative to clock(s) clk +Related violations: + +TIMING-18#4 Warning +Missing input or output delay +An input delay is missing on dip_sw[10] relative to clock(s) clk +Related violations: + +TIMING-18#5 Warning +Missing input or output delay +An input delay is missing on dip_sw[11] relative to clock(s) clk +Related violations: + +TIMING-18#6 Warning +Missing input or output delay +An input delay is missing on dip_sw[12] relative to clock(s) clk +Related violations: + +TIMING-18#7 Warning +Missing input or output delay +An input delay is missing on dip_sw[13] relative to clock(s) clk +Related violations: + +TIMING-18#8 Warning +Missing input or output delay +An input delay is missing on dip_sw[14] relative to clock(s) clk +Related violations: + +TIMING-18#9 Warning +Missing input or output delay +An input delay is missing on dip_sw[15] relative to clock(s) clk +Related violations: + +TIMING-18#10 Warning +Missing input or output delay +An input delay is missing on dip_sw[16] relative to clock(s) clk +Related violations: + +TIMING-18#11 Warning +Missing input or output delay +An input delay is missing on dip_sw[17] relative to clock(s) clk +Related violations: + +TIMING-18#12 Warning +Missing input or output delay +An input delay is missing on dip_sw[18] relative to clock(s) clk +Related violations: + +TIMING-18#13 Warning +Missing input or output delay +An input delay is missing on dip_sw[19] relative to clock(s) clk +Related violations: + +TIMING-18#14 Warning +Missing input or output delay +An input delay is missing on dip_sw[1] relative to clock(s) clk +Related violations: + +TIMING-18#15 Warning +Missing input or output delay +An input delay is missing on dip_sw[20] relative to clock(s) clk +Related violations: + +TIMING-18#16 Warning +Missing input or output delay +An input delay is missing on dip_sw[21] relative to clock(s) clk +Related violations: + +TIMING-18#17 Warning +Missing input or output delay +An input delay is missing on dip_sw[22] relative to clock(s) clk +Related violations: + +TIMING-18#18 Warning +Missing input or output delay +An input delay is missing on dip_sw[23] relative to clock(s) clk +Related violations: + +TIMING-18#19 Warning +Missing input or output delay +An input delay is missing on dip_sw[24] relative to clock(s) clk +Related violations: + +TIMING-18#20 Warning +Missing input or output delay +An input delay is missing on dip_sw[25] relative to clock(s) clk +Related violations: + +TIMING-18#21 Warning +Missing input or output delay +An input delay is missing on dip_sw[26] relative to clock(s) clk +Related violations: + +TIMING-18#22 Warning +Missing input or output delay +An input delay is missing on dip_sw[27] relative to clock(s) clk +Related violations: + +TIMING-18#23 Warning +Missing input or output delay +An input delay is missing on dip_sw[28] relative to clock(s) clk +Related violations: + +TIMING-18#24 Warning +Missing input or output delay +An input delay is missing on dip_sw[29] relative to clock(s) clk +Related violations: + +TIMING-18#25 Warning +Missing input or output delay +An input delay is missing on dip_sw[2] relative to clock(s) clk +Related violations: + +TIMING-18#26 Warning +Missing input or output delay +An input delay is missing on dip_sw[30] relative to clock(s) clk +Related violations: + +TIMING-18#27 Warning +Missing input or output delay +An input delay is missing on dip_sw[31] relative to clock(s) clk +Related violations: + +TIMING-18#28 Warning +Missing input or output delay +An input delay is missing on dip_sw[3] relative to clock(s) clk +Related violations: + +TIMING-18#29 Warning +Missing input or output delay +An input delay is missing on dip_sw[4] relative to clock(s) clk +Related violations: + +TIMING-18#30 Warning +Missing input or output delay +An input delay is missing on dip_sw[5] relative to clock(s) clk +Related violations: + +TIMING-18#31 Warning +Missing input or output delay +An input delay is missing on dip_sw[6] relative to clock(s) clk +Related violations: + +TIMING-18#32 Warning +Missing input or output delay +An input delay is missing on dip_sw[7] relative to clock(s) clk +Related violations: + +TIMING-18#33 Warning +Missing input or output delay +An input delay is missing on dip_sw[8] relative to clock(s) clk +Related violations: + +TIMING-18#34 Warning +Missing input or output delay +An input delay is missing on dip_sw[9] relative to clock(s) clk +Related violations: + +TIMING-18#35 Warning +Missing input or output delay +An input delay is missing on touch_btn[0] relative to clock(s) clk +Related violations: + +TIMING-18#36 Warning +Missing input or output delay +An input delay is missing on touch_btn[1] relative to clock(s) clk +Related violations: + +TIMING-18#37 Warning +Missing input or output delay +An input delay is missing on touch_btn[2] relative to clock(s) clk +Related violations: + +TIMING-18#38 Warning +Missing input or output delay +An input delay is missing on touch_btn[3] relative to clock(s) clk +Related violations: + +TIMING-18#39 Warning +Missing input or output delay +An output delay is missing on dpy0[0] relative to clock(s) clk +Related violations: + +TIMING-18#40 Warning +Missing input or output delay +An output delay is missing on dpy0[1] relative to clock(s) clk +Related violations: + +TIMING-18#41 Warning +Missing input or output delay +An output delay is missing on dpy0[2] relative to clock(s) clk +Related violations: + +TIMING-18#42 Warning +Missing input or output delay +An output delay is missing on dpy0[3] relative to clock(s) clk +Related violations: + +TIMING-18#43 Warning +Missing input or output delay +An output delay is missing on dpy0[4] relative to clock(s) clk +Related violations: + +TIMING-18#44 Warning +Missing input or output delay +An output delay is missing on dpy0[5] relative to clock(s) clk +Related violations: + +TIMING-18#45 Warning +Missing input or output delay +An output delay is missing on dpy0[6] relative to clock(s) clk +Related violations: + +TIMING-18#46 Warning +Missing input or output delay +An output delay is missing on dpy0[7] relative to clock(s) clk +Related violations: + +TIMING-18#47 Warning +Missing input or output delay +An output delay is missing on dpy1[0] relative to clock(s) clk +Related violations: + +TIMING-18#48 Warning +Missing input or output delay +An output delay is missing on dpy1[1] relative to clock(s) clk +Related violations: + +TIMING-18#49 Warning +Missing input or output delay +An output delay is missing on dpy1[2] relative to clock(s) clk +Related violations: + +TIMING-18#50 Warning +Missing input or output delay +An output delay is missing on dpy1[3] relative to clock(s) clk +Related violations: + +TIMING-18#51 Warning +Missing input or output delay +An output delay is missing on dpy1[4] relative to clock(s) clk +Related violations: + +TIMING-18#52 Warning +Missing input or output delay +An output delay is missing on dpy1[5] relative to clock(s) clk +Related violations: + +TIMING-18#53 Warning +Missing input or output delay +An output delay is missing on dpy1[6] relative to clock(s) clk +Related violations: + +TIMING-18#54 Warning +Missing input or output delay +An output delay is missing on dpy1[7] relative to clock(s) clk +Related violations: + +TIMING-18#55 Warning +Missing input or output delay +An output delay is missing on leds[0] relative to clock(s) clk +Related violations: + +TIMING-18#56 Warning +Missing input or output delay +An output delay is missing on leds[10] relative to clock(s) clk +Related violations: + +TIMING-18#57 Warning +Missing input or output delay +An output delay is missing on leds[11] relative to clock(s) clk +Related violations: + +TIMING-18#58 Warning +Missing input or output delay +An output delay is missing on leds[12] relative to clock(s) clk +Related violations: + +TIMING-18#59 Warning +Missing input or output delay +An output delay is missing on leds[13] relative to clock(s) clk +Related violations: + +TIMING-18#60 Warning +Missing input or output delay +An output delay is missing on leds[14] relative to clock(s) clk +Related violations: + +TIMING-18#61 Warning +Missing input or output delay +An output delay is missing on leds[15] relative to clock(s) clk +Related violations: + +TIMING-18#62 Warning +Missing input or output delay +An output delay is missing on leds[1] relative to clock(s) clk +Related violations: + +TIMING-18#63 Warning +Missing input or output delay +An output delay is missing on leds[2] relative to clock(s) clk +Related violations: + +TIMING-18#64 Warning +Missing input or output delay +An output delay is missing on leds[3] relative to clock(s) clk +Related violations: + +TIMING-18#65 Warning +Missing input or output delay +An output delay is missing on leds[4] relative to clock(s) clk +Related violations: + +TIMING-18#66 Warning +Missing input or output delay +An output delay is missing on leds[5] relative to clock(s) clk +Related violations: + +TIMING-18#67 Warning +Missing input or output delay +An output delay is missing on leds[6] relative to clock(s) clk +Related violations: + +TIMING-18#68 Warning +Missing input or output delay +An output delay is missing on leds[7] relative to clock(s) clk +Related violations: + +TIMING-18#69 Warning +Missing input or output delay +An output delay is missing on leds[8] relative to clock(s) clk +Related violations: + +TIMING-18#70 Warning +Missing input or output delay +An output delay is missing on leds[9] relative to clock(s) clk +Related violations: + +TIMING-18#71 Warning +Missing input or output delay +An output delay is missing on video_de relative to clock(s) clk +Related violations: + +TIMING-18#72 Warning +Missing input or output delay +An output delay is missing on video_hsync relative to clock(s) clk +Related violations: + +TIMING-18#73 Warning +Missing input or output delay +An output delay is missing on video_red[0] relative to clock(s) clk +Related violations: + +TIMING-18#74 Warning +Missing input or output delay +An output delay is missing on video_red[1] relative to clock(s) clk +Related violations: + +TIMING-18#75 Warning +Missing input or output delay +An output delay is missing on video_red[2] relative to clock(s) clk +Related violations: + +TIMING-18#76 Warning +Missing input or output delay +An output delay is missing on video_vsync relative to clock(s) clk +Related violations: + +TIMING-47#1 Warning +False path or asynchronous clock group between synchronous clocks +A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. +Related violations: + +TIMING-47#2 Warning +False path or asynchronous clock group between synchronous clocks +A Clock Group timing constraint is set between synchronous clocks mlkem_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. +Related violations: + +TIMING-47#3 Warning +False path or asynchronous clock group between synchronous clocks +A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. +Related violations: + +TIMING-47#4 Warning +False path or asynchronous clock group between synchronous clocks +A Clock Group timing constraint is set between synchronous clocks sys_clk and mlkem_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. +Related violations: + +XDCC-1#1 Warning +Scoped Clock constraint overwritten with the same name +A new clock constraint create_clock overrides a previous scoped clock constraint with the same name. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors. +New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: c:/Users/11747/Desktop/ciciec2026/fpga/constraints/soc.xdc (Line: 4)) +Previous: create_clock -period 20.000 [get_ports clk] (Source: c:/Users/11747/Desktop/ciciec2026/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56)) +Related violations: + +XDCC-7#1 Warning +Scoped Clock constraint overwritten on the same source +A new clock constraint create_clock overrides a previous scoped clock constraint defined on the same source. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors. +New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: c:/Users/11747/Desktop/ciciec2026/fpga/constraints/soc.xdc (Line: 4)) +Previous: create_clock -period 20.000 [get_ports clk] (Source: c:/Users/11747/Desktop/ciciec2026/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56)) +Related violations: + + diff --git a/doc/reports/system/evidence/vivado/power.rpt b/doc/reports/system/evidence/vivado/power.rpt new file mode 100644 index 0000000..94b058d --- /dev/null +++ b/doc/reports/system/evidence/vivado/power.rpt @@ -0,0 +1,188 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Wed Jul 15 05:09:34 2026 +| Host : Roc_Wang running 64-bit major release (build 9200) +| Command : report_power -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/power.rpt +| Design : soc_top +| Device : xc7a200tfbg676-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.779 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.637 | +| Device Static (W) | 0.142 | +| Effective TJA (C/W) | 1.9 | +| Max Ambient (C) | 83.5 | +| Junction Temperature (C) | 26.5 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++--------------------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++--------------------------+-----------+----------+-----------+-----------------+ +| Clocks | 0.060 | 7 | --- | --- | +| Slice Logic | 0.137 | 103629 | --- | --- | +| LUT as Logic | 0.128 | 53158 | 133800 | 39.73 | +| CARRY4 | 0.005 | 3669 | 33450 | 10.97 | +| Register | 0.002 | 31000 | 267600 | 11.58 | +| LUT as Distributed RAM | 0.001 | 740 | 46200 | 1.60 | +| LUT as Shift Register | <0.001 | 1168 | 46200 | 2.53 | +| F7/F8 Muxes | <0.001 | 2449 | 133800 | 1.83 | +| Others | 0.000 | 333 | --- | --- | +| Signals | 0.284 | 78815 | --- | --- | +| Block RAM | 0.027 | 29.5 | 365 | 8.08 | +| PLL | 0.102 | 1 | 10 | 10.00 | +| I/O | 0.027 | 202 | 400 | 50.50 | +| Static Power | 0.142 | | | | +| Total | 0.779 | | | | ++--------------------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.545 | 0.512 | 0.033 | +| Vccaux | 1.800 | 0.085 | 0.054 | 0.031 | +| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.003 | 0.002 | 0.001 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 1.9 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 3.4 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++------------------+------------------------------------------+-----------------+ +| Clock | Domain | Constraint (ns) | ++------------------+------------------------------------------+-----------------+ +| clk | clk | 20.0 | +| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 | +| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.0 | +| mlkem_clk | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 13.0 | +| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 | ++------------------+------------------------------------------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++----------------------------+-----------+ +| Name | Power (W) | ++----------------------------+-----------+ +| soc_top | 0.637 | +| pll_clk.u_clk_pll | 0.103 | +| inst | 0.103 | +| u_Axi_CDC | 0.002 | +| u_axi_uart_controller | 0.002 | +| uart0 | 0.001 | +| regs | 0.001 | +| u_cdma_matmul_bridge | 0.001 | +| u_confreg | 0.001 | +| u_cpu | 0.027 | +| addr_trans | 0.002 | +| tlb_entry | 0.002 | +| btb | 0.003 | +| dcache | 0.004 | +| icache | 0.005 | +| u_csr | 0.001 | +| u_mul | 0.008 | +| u_fft_mlkem_axi_slave | 0.373 | +| u_fft_controller | 0.031 | +| u_FFT | 0.028 | +| u_out0 | 0.001 | +| u_out1 | 0.001 | +| u_mlkem_axi_cdc | 0.003 | +| wFifo | 0.001 | +| u_mlkem_axi_slave | 0.339 | +| u_mlkem | 0.332 | +| u_matmul_axi_slave | 0.077 | +| mult_inst[0].u_mult | 0.003 | +| mult_inst[1].u_mult | 0.002 | +| mult_inst[2].u_mult | 0.002 | +| mult_inst[3].u_mult | 0.002 | +| u_snix_axil_cdma_mux_8ch | 0.008 | +| u_core_engine | 0.004 | +| axis_fifo_u0 | 0.002 | ++----------------------------+-----------+ + + diff --git a/doc/reports/system/evidence/vivado/revision.txt b/doc/reports/system/evidence/vivado/revision.txt new file mode 100644 index 0000000..78a25e1 --- /dev/null +++ b/doc/reports/system/evidence/vivado/revision.txt @@ -0,0 +1,5 @@ +Evidence generated from implemented design. +Vivado version: 2019.2 +Project: C:/Users/11747/Desktop/ciciec2026/fpga/project/Loongson_Soc.xpr +Git revision: d45646342b79cefbc30775b5045e34c1f0d26ad6 +Generated at: 2026-07-15 05:09:50 +0800 diff --git a/doc/reports/system/evidence/vivado/route_status.rpt b/doc/reports/system/evidence/vivado/route_status.rpt new file mode 100644 index 0000000..e466ae1 --- /dev/null +++ b/doc/reports/system/evidence/vivado/route_status.rpt @@ -0,0 +1,12 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 114880 : + # of nets not needing routing.......... : 36054 : + # of internally routed nets........ : 35589 : + # of nets with no loads............ : 465 : + # of routable nets..................... : 78826 : + # of fully routed nets............. : 78826 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/doc/reports/system/evidence/vivado/timing_summary_full.rpt b/doc/reports/system/evidence/vivado/timing_summary_full.rpt new file mode 100644 index 0000000..faadc11 --- /dev/null +++ b/doc/reports/system/evidence/vivado/timing_summary_full.rpt @@ -0,0 +1,32030 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Wed Jul 15 05:09:25 2026 +| Host : Roc_Wang running 64-bit major release (build 9200) +| Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 20 -input_pins -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/timing_summary_full.rpt +| Design : soc_top +| Device : 7a200t-fbg676 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 38 input ports with no input delay specified. (HIGH) + +UART_RX +UART_TX +dip_sw[0] +dip_sw[10] +dip_sw[11] +dip_sw[12] +dip_sw[13] +dip_sw[14] +dip_sw[15] +dip_sw[16] +dip_sw[17] +dip_sw[18] +dip_sw[19] +dip_sw[1] +dip_sw[20] +dip_sw[21] +dip_sw[22] +dip_sw[23] +dip_sw[24] +dip_sw[25] +dip_sw[26] +dip_sw[27] +dip_sw[28] +dip_sw[29] +dip_sw[2] +dip_sw[30] +dip_sw[31] +dip_sw[3] +dip_sw[4] +dip_sw[5] +dip_sw[6] +dip_sw[7] +dip_sw[8] +dip_sw[9] +touch_btn[0] +touch_btn[1] +touch_btn[2] +touch_btn[3] + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 40 ports with no output delay specified. (HIGH) + +UART_RX +UART_TX +dpy0[0] +dpy0[1] +dpy0[2] +dpy0[3] +dpy0[4] +dpy0[5] +dpy0[6] +dpy0[7] +dpy1[0] +dpy1[1] +dpy1[2] +dpy1[3] +dpy1[4] +dpy1[5] +dpy1[6] +dpy1[7] +leds[0] +leds[10] +leds[11] +leds[12] +leds[13] +leds[14] +leds[15] +leds[1] +leds[2] +leds[3] +leds[4] +leds[5] +leds[6] +leds[7] +leds[8] +leds[9] +video_de +video_hsync +video_red[0] +video_red[1] +video_red[2] +video_vsync + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.070 0.000 0 88843 0.024 0.000 0 88843 5.250 0.000 0 33736 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 10.000} 20.000 50.000 + clkfbout_clk_pll {0.000 10.000} 20.000 50.000 + cpu_clk {0.000 15.000} 30.000 33.333 + mlkem_clk {0.000 6.500} 13.000 76.923 + sys_clk {0.000 10.000} 20.000 50.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 7.000 0.000 0 1 + clkfbout_clk_pll 17.845 0.000 0 3 + cpu_clk 0.737 0.000 0 17197 0.040 0.000 0 17197 13.750 0.000 0 6486 + mlkem_clk 0.070 0.000 0 31646 0.057 0.000 0 31646 5.250 0.000 0 17274 + sys_clk 0.125 0.000 0 22307 0.024 0.000 0 22307 8.750 0.000 0 9972 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +**async_default** cpu_clk cpu_clk 26.018 0.000 0 67 0.681 0.000 0 67 +**async_default** mlkem_clk mlkem_clk 3.826 0.000 0 16740 0.658 0.000 0 16740 +**async_default** sys_clk sys_clk 6.335 0.000 0 886 0.573 0.000 0 886 + + +------------------------------------------------------------------------------------------------ +| User Ignored Path Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) sys_clk cpu_clk +(none) sys_clk mlkem_clk +(none) cpu_clk sys_clk +(none) mlkem_clk sys_clk + + +------------------------------------------------------------------------------------------------ +| Unconstrained Path Table +| ------------------------ +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) clkfbout_clk_pll +(none) sys_clk +(none) sys_clk + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk + To Clock: clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk +Waveform(ns): { 0.000 10.000 } +Period(ns): 20.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 +Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 +Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 +Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 +High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 +High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clkfbout_clk_pll + To Clock: clkfbout_clk_pll + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clkfbout_clk_pll +Waveform(ns): { 0.000 10.000 } +Period(ns): 20.000 +Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y19 pll_clk.u_clk_pll/inst/clkf_buf/I +Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT +Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN +Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN +Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT + + + +--------------------------------------------------------------------------------------------------- +From Clock: cpu_clk + To Clock: cpu_clk + +Setup : 0 Failing Endpoints, Worst Slack 0.737ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.040ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 13.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.737ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2 + SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O + net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 + SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3 + SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O + net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4 + SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O + net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] + ------------------------------------------------------------------- + required time 27.175 + arrival time -26.438 + ------------------------------------------------------------------- + slack 0.737 + +Slack (MET) : 0.754ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0 + SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O + net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 + SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3 + SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O + net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1 + SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O + net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/C + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.370 + ------------------------------------------------------------------- + slack 0.754 + +Slack (MET) : 0.793ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2 + SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O + net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 + SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3 + SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O + net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3 + SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O + net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] + ------------------------------------------------------------------- + required time 27.177 + arrival time -26.384 + ------------------------------------------------------------------- + slack 0.793 + +Slack (MET) : 0.803ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2 + SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O + net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 + SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1 + SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O + net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.322 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.804ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 + SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0 + SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O + net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 + SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0 + SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O + net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 + SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 + SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O + net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] + ------------------------------------------------------------------- + required time 27.172 + arrival time -26.369 + ------------------------------------------------------------------- + slack 0.804 + +Slack (MET) : 0.863ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2 + SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O + net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 + SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2 + SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O + net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2 + SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O + net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.311 + ------------------------------------------------------------------- + slack 0.863 + +Slack (MET) : 0.865ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 + SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 + SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O + net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 + SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 + SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O + net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 + SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 + SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O + net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] + ------------------------------------------------------------------- + required time 27.126 + arrival time -26.261 + ------------------------------------------------------------------- + slack 0.865 + +Slack (MET) : 0.867ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5 + SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O + net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 + SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O + net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/C + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] + ------------------------------------------------------------------- + required time 27.122 + arrival time -26.255 + ------------------------------------------------------------------- + slack 0.867 + +Slack (MET) : 0.894ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 + SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1 + SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O + net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] + SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2 + SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O + net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] + ------------------------------------------------------------------- + required time 27.127 + arrival time -26.233 + ------------------------------------------------------------------- + slack 0.894 + +Slack (MET) : 0.921ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0 + SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O + net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] + SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1 + SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O + net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] + SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2 + SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O + net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/C + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.204 + ------------------------------------------------------------------- + slack 0.921 + +Slack (MET) : 0.943ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.831ns (logic 8.005ns (27.765%) route 20.826ns (72.235%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=9 LUT6=12 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.866 24.418 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y152 f u_cpu/u_csr/ds_to_es_bus_r[192]_i_9/I0 + SLICE_X115Y152 LUT5 (Prop_lut5_I0_O) 0.326 24.744 r u_cpu/u_csr/ds_to_es_bus_r[192]_i_9/O + net (fo=1, routed) 0.415 25.158 u_cpu/id_stage/ds_to_es_bus_r_reg[192] + SLICE_X111Y152 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_3/I3 + SLICE_X111Y152 LUT4 (Prop_lut4_I3_O) 0.124 25.282 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_3/O + net (fo=1, routed) 0.775 26.057 u_cpu/id_stage/ds_to_es_bus_r[192]_i_3_n_0 + SLICE_X110Y159 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_1/I2 + SLICE_X110Y159 LUT6 (Prop_lut6_I2_O) 0.124 26.181 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_1/O + net (fo=1, routed) 0.000 26.181 u_cpu/exe_stage/ds_to_es_bus[142] + SLICE_X110Y159 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk + SLICE_X110Y159 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/C + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y159 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[192] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.181 + ------------------------------------------------------------------- + slack 0.943 + +Slack (MET) : 0.964ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.862ns (logic 7.809ns (27.057%) route 21.053ns (72.943%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.138ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.275ns = ( 27.725 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_4 + SLICE_X103Y151 f u_cpu/id_stage/ds_to_es_bus_r[163]_i_7/I2 + SLICE_X103Y151 LUT4 (Prop_lut4_I2_O) 0.124 24.312 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_7/O + net (fo=1, routed) 0.590 24.902 u_cpu/id_stage/ds_to_es_bus_r[163]_i_7_n_0 + SLICE_X102Y150 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_3/I4 + SLICE_X102Y150 LUT5 (Prop_lut5_I4_O) 0.124 25.026 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_3/O + net (fo=1, routed) 1.061 26.087 u_cpu/id_stage/ds_to_es_bus_r[163]_i_3_n_0 + SLICE_X112Y150 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_1/I2 + SLICE_X112Y150 LUT6 (Prop_lut6_I2_O) 0.124 26.211 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_1/O + net (fo=1, routed) 0.000 26.211 u_cpu/exe_stage/ds_to_es_bus[113] + SLICE_X112Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.554 27.725 u_cpu/exe_stage/cpu_clk + SLICE_X112Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/C + clock pessimism -0.514 27.212 + clock uncertainty -0.113 27.098 + SLICE_X112Y150 FDRE (Setup_fdre_C_D) 0.077 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[163] + ------------------------------------------------------------------- + required time 27.175 + arrival time -26.211 + ------------------------------------------------------------------- + slack 0.964 + +Slack (MET) : 0.965ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.812ns (logic 8.005ns (27.784%) route 20.807ns (72.216%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 + SLICE_X114Y154 f u_cpu/id_stage/ds_to_es_bus_r[175]_i_7/I0 + SLICE_X114Y154 LUT4 (Prop_lut4_I0_O) 0.326 24.579 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_7/O + net (fo=1, routed) 0.772 25.352 u_cpu/id_stage/ds_to_es_bus_r[175]_i_7_n_0 + SLICE_X112Y154 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_3/I2 + SLICE_X112Y154 LUT4 (Prop_lut4_I2_O) 0.124 25.476 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_3/O + net (fo=1, routed) 0.561 26.037 u_cpu/id_stage/ds_to_es_bus_r[175]_i_3_n_0 + SLICE_X111Y153 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/I2 + SLICE_X111Y153 LUT6 (Prop_lut6_I2_O) 0.124 26.161 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O + net (fo=1, routed) 0.000 26.161 u_cpu/exe_stage/ds_to_es_bus[125] + SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X111Y153 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] + ------------------------------------------------------------------- + required time 27.126 + arrival time -26.161 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 1.001ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.774ns (logic 7.809ns (27.139%) route 20.965ns (72.861%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.935 25.244 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X117Y151 f u_cpu/id_stage/ds_to_es_bus_r[178]_i_2/I0 + SLICE_X117Y151 LUT6 (Prop_lut6_I0_O) 0.124 25.368 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_2/O + net (fo=1, routed) 0.631 26.000 u_cpu/id_stage/ds_to_es_bus_r[178]_i_2_n_0 + SLICE_X110Y156 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/I1 + SLICE_X110Y156 LUT6 (Prop_lut6_I1_O) 0.124 26.124 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O + net (fo=1, routed) 0.000 26.124 u_cpu/exe_stage/ds_to_es_bus[128] + SLICE_X110Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X110Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X110Y156 FDRE (Setup_fdre_C_D) 0.029 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.124 + ------------------------------------------------------------------- + slack 1.001 + +Slack (MET) : 1.021ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.754ns (logic 7.809ns (27.158%) route 20.945ns (72.842%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X112Y150 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_2/I2 + SLICE_X112Y150 LUT4 (Prop_lut4_I2_O) 0.124 25.241 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_2/O + net (fo=1, routed) 0.738 25.979 u_cpu/id_stage/ds_to_es_bus_r[170]_i_2_n_0 + SLICE_X111Y153 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I1 + SLICE_X111Y153 LUT6 (Prop_lut6_I1_O) 0.124 26.103 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O + net (fo=1, routed) 0.000 26.103 u_cpu/exe_stage/ds_to_es_bus[120] + SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X111Y153 FDRE (Setup_fdre_C_D) 0.029 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.103 + ------------------------------------------------------------------- + slack 1.021 + +Slack (MET) : 1.037ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.784ns (logic 8.012ns (27.834%) route 20.772ns (72.165%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.761 24.317 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X112Y155 f u_cpu/u_csr/ds_to_es_bus_r[182]_i_8/I0 + SLICE_X112Y155 LUT5 (Prop_lut5_I0_O) 0.332 24.649 r u_cpu/u_csr/ds_to_es_bus_r[182]_i_8/O + net (fo=1, routed) 0.667 25.316 u_cpu/id_stage/ds_to_es_bus_r_reg[182] + SLICE_X112Y154 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_2/I1 + SLICE_X112Y154 LUT6 (Prop_lut6_I1_O) 0.124 25.440 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_2/O + net (fo=1, routed) 0.569 26.010 u_cpu/id_stage/ds_to_es_bus_r[182]_i_2_n_0 + SLICE_X108Y157 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_1/I1 + SLICE_X108Y157 LUT6 (Prop_lut6_I1_O) 0.124 26.134 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_1/O + net (fo=1, routed) 0.000 26.134 u_cpu/exe_stage/ds_to_es_bus[132] + SLICE_X108Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk + SLICE_X108Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/C + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X108Y157 FDRE (Setup_fdre_C_D) 0.077 27.171 u_cpu/exe_stage/ds_to_es_bus_r_reg[182] + ------------------------------------------------------------------- + required time 27.171 + arrival time -26.134 + ------------------------------------------------------------------- + slack 1.037 + +Slack (MET) : 1.065ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.709ns (logic 7.809ns (27.200%) route 20.900ns (72.800%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.884 25.193 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[187]_i_3/I3 + SLICE_X117Y153 LUT6 (Prop_lut6_I3_O) 0.124 25.317 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_3/O + net (fo=1, routed) 0.617 25.935 u_cpu/id_stage/ds_to_es_bus_r[187]_i_3_n_0 + SLICE_X111Y158 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/I2 + SLICE_X111Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.059 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O + net (fo=1, routed) 0.000 26.059 u_cpu/exe_stage/ds_to_es_bus[137] + SLICE_X111Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk + SLICE_X111Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/C + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X111Y158 FDRE (Setup_fdre_C_D) 0.029 27.123 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] + ------------------------------------------------------------------- + required time 27.123 + arrival time -26.059 + ------------------------------------------------------------------- + slack 1.065 + +Slack (MET) : 1.081ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.695ns (logic 8.005ns (27.897%) route 20.690ns (72.103%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.124 23.557 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O + net (fo=12, routed) 0.657 24.214 u_cpu/u_csr/ds_to_es_bus_r[166]_i_4_0 + SLICE_X112Y151 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_8/I1 + SLICE_X112Y151 LUT2 (Prop_lut2_I1_O) 0.116 24.330 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_8/O + net (fo=1, routed) 0.808 25.138 u_cpu/u_csr/ds_to_es_bus_r[165]_i_8_n_0 + SLICE_X111Y151 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/I0 + SLICE_X111Y151 LUT6 (Prop_lut6_I0_O) 0.328 25.466 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O + net (fo=1, routed) 0.455 25.920 u_cpu/id_stage/ds_to_es_bus_r_reg[165] + SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/I3 + SLICE_X109Y151 LUT6 (Prop_lut6_I3_O) 0.124 26.044 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O + net (fo=1, routed) 0.000 26.044 u_cpu/exe_stage/ds_to_es_bus[115] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.044 + ------------------------------------------------------------------- + slack 1.081 + +Slack (MET) : 1.086ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.690ns (logic 8.012ns (27.926%) route 20.678ns (72.074%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.950 24.506 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X115Y152 f u_cpu/u_csr/ds_to_es_bus_r[180]_i_8/I1 + SLICE_X115Y152 LUT5 (Prop_lut5_I1_O) 0.332 24.838 r u_cpu/u_csr/ds_to_es_bus_r[180]_i_8/O + net (fo=1, routed) 0.451 25.289 u_cpu/id_stage/ds_to_es_bus_r_reg[180] + SLICE_X113Y152 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_2/I1 + SLICE_X113Y152 LUT6 (Prop_lut6_I1_O) 0.124 25.413 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_2/O + net (fo=1, routed) 0.502 25.916 u_cpu/id_stage/ds_to_es_bus_r[180]_i_2_n_0 + SLICE_X110Y158 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/I1 + SLICE_X110Y158 LUT6 (Prop_lut6_I1_O) 0.124 26.040 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/O + net (fo=1, routed) 0.000 26.040 u_cpu/exe_stage/ds_to_es_bus[130] + SLICE_X110Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk + SLICE_X110Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/C + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X110Y158 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[180] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.040 + ------------------------------------------------------------------- + slack 1.086 + +Slack (MET) : 1.129ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.694ns (logic 8.012ns (27.922%) route 20.682ns (72.078%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.922 24.333 u_cpu/u_csr/ds_to_es_bus_r_reg[166]_0 + SLICE_X111Y151 f u_cpu/u_csr/ds_to_es_bus_r[167]_i_9/I1 + SLICE_X111Y151 LUT2 (Prop_lut2_I1_O) 0.119 24.452 r u_cpu/u_csr/ds_to_es_bus_r[167]_i_9/O + net (fo=1, routed) 0.505 24.957 u_cpu/id_stage/ds_to_es_bus_r_reg[167] + SLICE_X110Y151 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_3/I5 + SLICE_X110Y151 LUT6 (Prop_lut6_I5_O) 0.332 25.289 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_3/O + net (fo=1, routed) 0.631 25.920 u_cpu/id_stage/ds_to_es_bus_r[167]_i_3_n_0 + SLICE_X108Y152 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/I2 + SLICE_X108Y152 LUT6 (Prop_lut6_I2_O) 0.124 26.044 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O + net (fo=1, routed) 0.000 26.044 u_cpu/exe_stage/ds_to_es_bus[117] + SLICE_X108Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X108Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X108Y152 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.044 + ------------------------------------------------------------------- + slack 1.129 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.040ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_csr/csr_badv_reg[0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.405ns (logic 0.186ns (45.911%) route 0.219ns (54.089%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.274ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk + SLICE_X113Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X113Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/Q + net (fo=3, routed) 0.219 -0.314 u_cpu/wb_stage/ms_to_ws_bus_r_reg_n_0_[0] + SLICE_X107Y149 r u_cpu/wb_stage/csr_badv[0]_i_1/I2 + SLICE_X107Y149 LUT6 (Prop_lut6_I2_O) 0.045 -0.269 r u_cpu/wb_stage/csr_badv[0]_i_1/O + net (fo=1, routed) 0.000 -0.269 u_cpu/u_csr/csr_badv_reg[31]_4[0] + SLICE_X107Y149 FDRE r u_cpu/u_csr/csr_badv_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.863 -0.445 u_cpu/u_csr/cpu_clk + SLICE_X107Y149 FDRE r u_cpu/u_csr/csr_badv_reg[0]/C + clock pessimism 0.045 -0.400 + SLICE_X107Y149 FDRE (Hold_fdre_C_D) 0.091 -0.309 u_cpu/u_csr/csr_badv_reg[0] + ------------------------------------------------------------------- + required time 0.309 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.040 + +Slack (MET) : 0.049ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk + SLICE_X117Y149 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[20]/C + ------------------------------------------------------------------- ------------------- + SLICE_X117Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q + net (fo=4, routed) 0.068 -0.458 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 + SLICE_X116Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK + SLICE_X116Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/CLK + clock pessimism -0.213 -0.654 + SLICE_X116Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.458 + ------------------------------------------------------------------- + slack 0.049 + +Slack (MET) : 0.058ns (arrival time - required time) + Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.400ns (logic 0.164ns (40.951%) route 0.236ns (59.049%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.453ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_cpu/mem_stage/cpu_clk + SLICE_X98Y152 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C + ------------------------------------------------------------------- ------------------- + SLICE_X98Y152 FDRE (Prop_fdre_C_Q) 0.164 -0.521 r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/Q + net (fo=2, routed) 0.236 -0.284 u_cpu/wb_stage/ms_to_ws_bus[78] + SLICE_X99Y148 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.855 -0.453 u_cpu/wb_stage/cpu_clk + SLICE_X99Y148 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/C + clock pessimism 0.045 -0.408 + SLICE_X99Y148 FDRE (Hold_fdre_C_D) 0.066 -0.342 u_cpu/wb_stage/ms_to_ws_bus_r_reg[114] + ------------------------------------------------------------------- + required time 0.342 + arrival time -0.284 + ------------------------------------------------------------------- + slack 0.058 + +Slack (MET) : 0.061ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.683ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.580 -0.683 u_cpu/wb_stage/cpu_clk + SLICE_X103Y161 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y161 FDRE (Prop_fdre_C_Q) 0.141 -0.542 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/Q + net (fo=6, routed) 0.080 -0.462 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/DIA0 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/CLK + clock pessimism -0.212 -0.670 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.523 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA + ------------------------------------------------------------------- + required time 0.523 + arrival time -0.462 + ------------------------------------------------------------------- + slack 0.061 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.355ns (logic 0.128ns (36.084%) route 0.227ns (63.916%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.586 -0.677 u_cpu/exe_stage/cpu_clk + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C + ------------------------------------------------------------------- ------------------- + SLICE_X105Y150 FDRE (Prop_fdre_C_Q) 0.128 -0.549 r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/Q + net (fo=1, routed) 0.227 -0.322 u_cpu/mem_stage/D[126] + SLICE_X106Y149 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.863 -0.445 u_cpu/mem_stage/cpu_clk + SLICE_X106Y149 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/C + clock pessimism 0.045 -0.400 + SLICE_X106Y149 FDRE (Hold_fdre_C_D) 0.016 -0.384 u_cpu/mem_stage/es_to_ms_bus_r_reg[126] + ------------------------------------------------------------------- + required time 0.384 + arrival time -0.322 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.063ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.223ns (logic 0.141ns (63.098%) route 0.082ns (36.902%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk + SLICE_X121Y148 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[26]/C + ------------------------------------------------------------------- ------------------- + SLICE_X121Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo0_reg[26]/Q + net (fo=4, routed) 0.082 -0.444 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/DIA0 + SLICE_X120Y148 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/WCLK + SLICE_X120Y148 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/CLK + clock pessimism -0.213 -0.654 + SLICE_X120Y148 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.444 + ------------------------------------------------------------------- + slack 0.063 + +Slack (MET) : 0.064ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.443ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.594 -0.669 u_cpu/u_csr/cpu_clk + SLICE_X109Y149 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 r u_cpu/u_csr/csr_tlbelo0_reg[5]/Q + net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D + SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.865 -0.443 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/WCLK + SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/CLK + clock pessimism -0.213 -0.656 + SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.512 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP + ------------------------------------------------------------------- + required time 0.512 + arrival time -0.448 + ------------------------------------------------------------------- + slack 0.064 + +Slack (MET) : 0.066ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.226ns (logic 0.141ns (62.492%) route 0.085ns (37.508%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk + SLICE_X117Y147 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X117Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[14]/Q + net (fo=4, routed) 0.085 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIA0 + SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/WCLK + SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/CLK + clock pessimism -0.213 -0.654 + SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.441 + ------------------------------------------------------------------- + slack 0.066 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.403ns (logic 0.164ns (40.684%) route 0.239ns (59.316%)) + Logic Levels: 0 + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.457ns + Source Clock Delay (SCD): -0.679ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.584 -0.679 u_cpu/mem_stage/cpu_clk + SLICE_X98Y148 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C + ------------------------------------------------------------------- ------------------- + SLICE_X98Y148 FDRE (Prop_fdre_C_Q) 0.164 -0.515 r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/Q + net (fo=2, routed) 0.239 -0.276 u_cpu/wb_stage/ms_to_ws_bus[69] + SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.851 -0.457 u_cpu/wb_stage/cpu_clk + SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/C + clock pessimism 0.045 -0.412 + SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.052 -0.360 u_cpu/wb_stage/ms_to_ws_bus_r_reg[105] + ------------------------------------------------------------------- + required time 0.360 + arrival time -0.276 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.085ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.479ns (logic 0.141ns (29.406%) route 0.338ns (70.594%)) + Logic Levels: 0 + Clock Path Skew: 0.275ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.444ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.589 -0.674 u_cpu/u_csr/cpu_clk + SLICE_X115Y150 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[27]/C + ------------------------------------------------------------------- ------------------- + SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q + net (fo=4, routed) 0.338 -0.194 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 + SLICE_X112Y141 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.864 -0.444 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/WCLK + SLICE_X112Y141 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/CLK + clock pessimism 0.045 -0.399 + SLICE_X112Y141 RAMD32 (Hold_ramd32_CLK_I) + 0.120 -0.279 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 + ------------------------------------------------------------------- + required time 0.279 + arrival time -0.194 + ------------------------------------------------------------------- + slack 0.085 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.415ns (logic 0.141ns (33.953%) route 0.274ns (66.047%)) + Logic Levels: 0 + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.457ns + Source Clock Delay (SCD): -0.679ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.584 -0.679 u_cpu/mem_stage/cpu_clk + SLICE_X97Y148 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.538 r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/Q + net (fo=2, routed) 0.274 -0.264 u_cpu/wb_stage/ms_to_ws_bus[68] + SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.851 -0.457 u_cpu/wb_stage/cpu_clk + SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/C + clock pessimism 0.045 -0.412 + SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.059 -0.353 u_cpu/wb_stage/ms_to_ws_bus_r_reg[104] + ------------------------------------------------------------------- + required time 0.353 + arrival time -0.264 + ------------------------------------------------------------------- + slack 0.089 + +Slack (MET) : 0.091ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.443ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.594 -0.669 u_cpu/u_csr/cpu_clk + SLICE_X109Y149 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 r u_cpu/u_csr/csr_tlbelo0_reg[5]/Q + net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D + SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.865 -0.443 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/WCLK + SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/CLK + clock pessimism -0.213 -0.656 + SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.117 -0.539 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP + ------------------------------------------------------------------- + required time 0.539 + arrival time -0.448 + ------------------------------------------------------------------- + slack 0.091 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: cpu_clk +Waveform(ns): { 0.000 15.000 } +Period(ns): 30.000 +Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y47 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y47 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y46 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y46 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y48 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y48 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y49 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y49 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y50 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y50 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y51 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y51 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y48 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y48 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y49 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y49 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y52 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y52 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.000 130.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: mlkem_clk + To Clock: mlkem_clk + +Setup : 0 Failing Endpoints, Worst Slack 0.070ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.057ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 5.250ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.070ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O + net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732] + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/C + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.555 + ------------------------------------------------------------------- + slack 0.070 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.080 + ------------------------------------------------------------------- + slack 0.088 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.077 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.128ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948] + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/C + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948] + ------------------------------------------------------------------- + required time 10.701 + arrival time -10.573 + ------------------------------------------------------------------- + slack 0.128 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.135ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O + net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731] + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/C + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.491 + ------------------------------------------------------------------- + slack 0.135 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.159ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S + SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O + net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943] + SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/C + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943] + ------------------------------------------------------------------- + required time 10.750 + arrival time -10.591 + ------------------------------------------------------------------- + slack 0.159 + +Slack (MET) : 0.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2 + SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O + net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0 + SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0 + SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O + net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975] + SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.987 11.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/C + clock pessimism -0.498 10.660 + clock uncertainty -0.093 10.567 + SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975] + ------------------------------------------------------------------- + required time 10.631 + arrival time -10.455 + ------------------------------------------------------------------- + slack 0.175 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.214ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2 + SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O + net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0 + SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0 + SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888] + SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.061 11.232 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/C + clock pessimism -0.498 10.734 + clock uncertainty -0.093 10.641 + SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888] + ------------------------------------------------------------------- + required time 10.754 + arrival time -10.573 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.185ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y33 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S + SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O + net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812] + SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.056 11.227 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/C + clock pessimism -0.498 10.729 + clock uncertainty -0.093 10.636 + SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] + ------------------------------------------------------------------- + required time 10.700 + arrival time -10.515 + ------------------------------------------------------------------- + slack 0.185 + +Slack (MET) : 0.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.992ns (logic 0.732ns (5.634%) route 12.260ns (94.366%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.513 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/O + net (fo=1, routed) 0.000 10.513 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[946] + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/C + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946] + ------------------------------------------------------------------- + required time 10.701 + arrival time -10.513 + ------------------------------------------------------------------- + slack 0.188 + +Slack (MET) : 0.208ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.969ns (logic 0.732ns (5.644%) route 12.237ns (94.356%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.207ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.775ns = ( 11.225 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.237 10.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X159Y32 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[921]_i_1/S + SLICE_X159Y32 MUXF7 (Prop_muxf7_S_O) 0.276 10.490 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[921]_i_1/O + net (fo=1, routed) 0.000 10.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[921] + SLICE_X159Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.054 11.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X159Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921]/C + clock pessimism -0.498 10.727 + clock uncertainty -0.093 10.634 + SLICE_X159Y32 FDCE (Setup_fdce_C_D) 0.064 10.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921] + ------------------------------------------------------------------- + required time 10.698 + arrival time -10.490 + ------------------------------------------------------------------- + slack 0.208 + +Slack (MET) : 0.216ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.516ns (logic 4.831ns (38.597%) route 7.685ns (61.403%)) + Logic Levels: 16 (CARRY4=5 LUT2=2 LUT5=2 LUT6=3 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.651 6.519 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_182/I0 + SLICE_X139Y85 LUT2 (Prop_lut2_I0_O) 0.150 6.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_182/O + net (fo=1, routed) 0.617 7.286 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub1[0] + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100/CYINIT + SLICE_X139Y86 CARRY4 (Prop_carry4_CYINIT_CO[3]) + 0.788 8.074 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100/CO[3] + net (fo=1, routed) 0.000 8.074 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100_n_0 + SLICE_X139Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_87/CI + SLICE_X139Y87 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 8.408 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_87/O[1] + net (fo=1, routed) 1.013 9.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[5] + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_27/I0 + SLICE_X140Y88 LUT6 (Prop_lut6_I0_O) 0.303 9.723 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_27/O + net (fo=1, routed) 0.313 10.036 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[6] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[6]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.036 + ------------------------------------------------------------------- + slack 0.216 + +Slack (MET) : 0.221ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.008ns (logic 0.748ns (5.750%) route 12.260ns (94.250%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[936]_i_1/S + SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.292 10.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[936]_i_1/O + net (fo=1, routed) 0.000 10.529 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[936] + SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936]/C + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936] + ------------------------------------------------------------------- + required time 10.750 + arrival time -10.529 + ------------------------------------------------------------------- + slack 0.221 + +Slack (MET) : 0.223ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.960ns (logic 0.752ns (5.803%) route 12.208ns (94.197%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.212ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.770ns = ( 11.230 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.208 10.184 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[817]_i_1/S + SLICE_X160Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[817]_i_1/O + net (fo=1, routed) 0.000 10.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[817] + SLICE_X160Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.059 11.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X160Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817]/C + clock pessimism -0.498 10.732 + clock uncertainty -0.093 10.639 + SLICE_X160Y37 FDCE (Setup_fdce_C_D) 0.064 10.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817] + ------------------------------------------------------------------- + required time 10.703 + arrival time -10.480 + ------------------------------------------------------------------- + slack 0.223 + +Slack (MET) : 0.230ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.947ns (logic 0.732ns (5.654%) route 12.215ns (94.346%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.207ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.775ns = ( 11.225 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.215 10.192 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X156Y32 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[874]_i_1/S + SLICE_X156Y32 MUXF7 (Prop_muxf7_S_O) 0.276 10.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[874]_i_1/O + net (fo=1, routed) 0.000 10.468 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[874] + SLICE_X156Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.054 11.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X156Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874]/C + clock pessimism -0.498 10.727 + clock uncertainty -0.093 10.634 + SLICE_X156Y32 FDCE (Setup_fdce_C_D) 0.064 10.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874] + ------------------------------------------------------------------- + required time 10.698 + arrival time -10.468 + ------------------------------------------------------------------- + slack 0.230 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.057ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.276ns (logic 0.141ns (51.000%) route 0.135ns (49.000%)) + Logic Levels: 0 + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X135Y114 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X135Y114 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/Q + net (fo=7, routed) 0.135 -0.394 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[6] + SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.863 -0.445 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK + clock pessimism -0.189 -0.634 + SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) + 0.183 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.451 + arrival time -0.394 + ------------------------------------------------------------------- + slack 0.057 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.455ns (logic 0.164ns (36.015%) route 0.291ns (63.985%)) + Logic Levels: 0 + Clock Path Skew: 0.334ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.375ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.594 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X108Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C + ------------------------------------------------------------------- ------------------- + SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/Q + net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[16] + SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.933 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/C + clock pessimism 0.040 -0.335 + SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.059 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16] + ------------------------------------------------------------------- + required time 0.276 + arrival time -0.214 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.069ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.455ns (logic 0.164ns (36.017%) route 0.291ns (63.983%)) + Logic Levels: 0 + Clock Path Skew: 0.334ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.375ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.594 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X108Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C + ------------------------------------------------------------------- ------------------- + SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/Q + net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[17] + SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.933 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/C + clock pessimism 0.040 -0.335 + SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.052 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17] + ------------------------------------------------------------------- + required time 0.283 + arrival time -0.214 + ------------------------------------------------------------------- + slack 0.069 + +Slack (MET) : 0.085ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.281ns (logic 0.141ns (50.089%) route 0.140ns (49.911%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.211ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X133Y115 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/Q + net (fo=6, routed) 0.140 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[7] + SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.862 -0.446 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK + clock pessimism -0.211 -0.657 + SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) + 0.183 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.474 + arrival time -0.388 + ------------------------------------------------------------------- + slack 0.085 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q + net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[5] + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mlkem_clk + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK + clock pessimism 0.040 -0.333 + RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.061 + ------------------------------------------------------------------- + slack 0.089 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q + net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[5] + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mlkem_clk + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK + clock pessimism 0.040 -0.333 + RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.061 + ------------------------------------------------------------------- + slack 0.089 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.233ns (logic 0.141ns (60.420%) route 0.092ns (39.580%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.211ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X133Y115 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/Q + net (fo=7, routed) 0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[2] + SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.862 -0.446 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK + clock pessimism -0.211 -0.657 + SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) + 0.117 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.540 + arrival time -0.437 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[7] + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mlkem_clk + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK + clock pessimism 0.040 -0.333 + RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.040 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[7] + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mlkem_clk + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK + clock pessimism 0.040 -0.333 + RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.040 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) + Logic Levels: 0 + Clock Path Skew: 0.058ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.303ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): 0.214ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/Q[6] + RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.005 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mlkem_clk + RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKARDCLK + clock pessimism -0.214 -0.517 + RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg + ------------------------------------------------------------------- + required time 0.334 + arrival time -0.223 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) + Logic Levels: 0 + Clock Path Skew: 0.058ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.303ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): 0.214ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/Q[6] + RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.005 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mlkem_clk + RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKARDCLK + clock pessimism -0.214 -0.517 + RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg + ------------------------------------------------------------------- + required time 0.334 + arrival time -0.223 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[19] + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.935 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/C + clock pessimism -0.229 -0.602 + SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.078 -0.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19] + ------------------------------------------------------------------- + required time 0.524 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.119 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.301ns (logic 0.141ns (46.859%) route 0.160ns (53.141%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X57Y91 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/Q + net (fo=1, routed) 0.160 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIC0 + SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK + SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK + clock pessimism -0.192 -0.573 + SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.429 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC + ------------------------------------------------------------------- + required time 0.429 + arrival time -0.309 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.410ns (logic 0.186ns (45.405%) route 0.224ns (54.595%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.198ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.442ns + Source Clock Delay (SCD): -0.600ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.662 -0.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X118Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X118Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.459 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/Q + net (fo=29, routed) 0.224 -0.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0[0] + SLICE_X114Y100 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/I1 + SLICE_X114Y100 LUT6 (Prop_lut6_I1_O) 0.045 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/O + net (fo=1, routed) 0.000 -0.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_next0[5] + SLICE_X114Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.866 -0.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X114Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/C + clock pessimism 0.040 -0.402 + SLICE_X114Y100 FDCE (Hold_fdce_C_D) 0.091 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5] + ------------------------------------------------------------------- + required time 0.311 + arrival time -0.191 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.598 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X138Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q + net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[4] + RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.004 -0.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mlkem_clk + RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKBWRCLK + clock pessimism 0.040 -0.263 + RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.040 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.598 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X138Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q + net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[4] + RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.004 -0.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mlkem_clk + RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKBWRCLK + clock pessimism 0.040 -0.263 + RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.040 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.121ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C + ------------------------------------------------------------------- ------------------- + SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[18] + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.935 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/C + clock pessimism -0.229 -0.602 + SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.076 -0.526 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18] + ------------------------------------------------------------------- + required time 0.526 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.121 + +Slack (MET) : 0.121ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q + net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[1] + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mlkem_clk + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK + clock pessimism 0.040 -0.333 + RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.029 + ------------------------------------------------------------------- + slack 0.121 + +Slack (MET) : 0.121ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q + net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[1] + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mlkem_clk + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK + clock pessimism 0.040 -0.333 + RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.029 + ------------------------------------------------------------------- + slack 0.121 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: mlkem_clk +Waveform(ns): { 0.000 6.500 } +Period(ns): 13.000 +Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y39 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y38 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y40 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y41 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB36_X7Y14 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y37 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X8Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X6Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y44 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y43 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y42 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y45 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y39 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y38 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y40 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y41 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKBWRCLK +Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 13.000 147.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_clk + To Clock: sys_clk + +Setup : 0 Failing Endpoints, Worst Slack 0.125ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.024ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.125ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[18] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 + SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I + AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I + AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 r ext_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.197 ext_ram_data[18] + AB17 r ext_ram_data[18] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.197 + ------------------------------------------------------------------- + slack 0.125 + +Slack (MET) : 0.253ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.069 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.069 + ------------------------------------------------------------------- + slack 0.253 + +Slack (MET) : 0.342ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[22] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T + Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T + Y15 OBUFT (TriStatE_obuft_T_O) + 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.980 ext_ram_data[22] + Y15 r ext_ram_data[22] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.980 + ------------------------------------------------------------------- + slack 0.342 + +Slack (MET) : 0.395ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[20] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 + SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O + net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] + SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0 + SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O + net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 + SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4 + SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O + net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] + SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5 + SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O + net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] + SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 + SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O + net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I + AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I + AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 r ext_ram_data_IOBUF[20]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.927 ext_ram_data[20] + AD18 r ext_ram_data[20] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.927 + ------------------------------------------------------------------- + slack 0.395 + +Slack (MET) : 0.403ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.919 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.919 + ------------------------------------------------------------------- + slack 0.403 + +Slack (MET) : 0.416ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[6] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%)) + Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 + SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1 + SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.820 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O + net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38] + SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3 + SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 r u_matmul_axi_slave/ram_reg_i_46/O + net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] + SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5 + SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O + net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 + SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0 + SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O + net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I + AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I + AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 r ext_ram_data_IOBUF[6]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.906 ext_ram_data[6] + AE20 r ext_ram_data[6] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.906 + ------------------------------------------------------------------- + slack 0.416 + +Slack (MET) : 0.422ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[31] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I + AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I + AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.900 ext_ram_data[31] + AC23 r ext_ram_data[31] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.900 + ------------------------------------------------------------------- + slack 0.422 + +Slack (MET) : 0.475ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.847 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.847 + ------------------------------------------------------------------- + slack 0.475 + +Slack (MET) : 0.483ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[31] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I + M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I + M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.839 base_ram_data[31] + M22 r base_ram_data[31] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.839 + ------------------------------------------------------------------- + slack 0.483 + +Slack (MET) : 0.489ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[19] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T + AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T + AC18 OBUFT (TriStatE_obuft_T_O) + 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.833 ext_ram_data[19] + AC18 r ext_ram_data[19] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.833 + ------------------------------------------------------------------- + slack 0.489 + +Slack (MET) : 0.508ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.143ns (logic 6.882ns (45.449%) route 8.261ns (54.551%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.595 9.272 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 12.815 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.815 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.815 + ------------------------------------------------------------------- + slack 0.508 + +Slack (MET) : 0.518ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.133ns (logic 6.891ns (45.538%) route 8.241ns (54.462%)) + Logic Levels: 13 (CARRY4=6 LUT5=1 LUT6=5 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 2.371 7.266 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y129 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y129 LUT6 (Prop_lut6_I5_O) 0.124 7.390 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 1.863 9.253 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 12.804 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 12.804 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.804 + ------------------------------------------------------------------- + slack 0.518 + +Slack (MET) : 0.535ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[25] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.116ns (logic 6.893ns (45.603%) route 8.223ns (54.397%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.557 9.234 ext_ram_data_IOBUF[25]_inst/T + AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T + AC17 OBUFT (TriStatE_obuft_T_O) + 3.553 12.788 r ext_ram_data_IOBUF[25]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.788 ext_ram_data[25] + AC17 r ext_ram_data[25] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.788 + ------------------------------------------------------------------- + slack 0.535 + +Slack (MET) : 0.557ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.173ns (logic 5.026ns (33.126%) route 10.147ns (66.874%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 0.971 1.949 u_snix_axil_cdma_mux_8ch/ep_rd_elem[1] + SLICE_X21Y79 r u_snix_axil_cdma_mux_8ch/ram_reg_i_77/I3 + SLICE_X21Y79 LUT6 (Prop_lut6_I3_O) 0.124 2.073 r u_snix_axil_cdma_mux_8ch/ram_reg_i_77/O + net (fo=32, routed) 1.329 3.402 u_matmul_axi_slave/ram_reg_i_51_1 + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_i_67/I3 + SLICE_X24Y84 LUT4 (Prop_lut4_I3_O) 0.124 3.526 r u_matmul_axi_slave/ram_reg_i_67/O + net (fo=1, routed) 0.500 4.026 u_matmul_axi_slave/ram_reg_i_67_n_0 + SLICE_X25Y84 r u_matmul_axi_slave/ram_reg_i_49/I4 + SLICE_X25Y84 LUT5 (Prop_lut5_I4_O) 0.124 4.150 r u_matmul_axi_slave/ram_reg_i_49/O + net (fo=1, routed) 0.645 4.795 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[3] + SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_33/I5 + SLICE_X29Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.919 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_33/O + net (fo=3, routed) 0.413 5.332 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[3] + SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[3]_inst_i_1/I0 + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.456 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[3]_inst_i_1/O + net (fo=2, routed) 3.731 9.187 ext_ram_data_IOBUF[3]_inst/I + AE22 r ext_ram_data_IOBUF[3]_inst/OBUFT/I + AE22 OBUFT (Prop_obuft_I_O) 3.578 12.765 r ext_ram_data_IOBUF[3]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.765 ext_ram_data[3] + AE22 r ext_ram_data[3] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.765 + ------------------------------------------------------------------- + slack 0.557 + +Slack (MET) : 0.561ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.169ns (logic 5.223ns (34.430%) route 9.946ns (65.570%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT6=4 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.303 2.393 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA0 + SLICE_X22Y84 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/RADR0 + SLICE_X22Y84 RAMD32 (Prop_ramd32_RADR0_O) + 0.150 2.543 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/O + net (fo=1, routed) 0.961 3.504 u_matmul_axi_slave/ep_rd_c0[0] + SLICE_X24Y82 r u_matmul_axi_slave/ram_reg_i_73/I2 + SLICE_X24Y82 LUT4 (Prop_lut4_I2_O) 0.328 3.832 r u_matmul_axi_slave/ram_reg_i_73/O + net (fo=1, routed) 0.667 4.499 u_matmul_axi_slave/ram_reg_i_73_n_0 + SLICE_X24Y82 r u_matmul_axi_slave/ram_reg_i_52/I0 + SLICE_X24Y82 LUT6 (Prop_lut6_I0_O) 0.124 4.623 r u_matmul_axi_slave/ram_reg_i_52/O + net (fo=1, routed) 0.414 5.036 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[0] + SLICE_X26Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_36/I5 + SLICE_X26Y82 LUT6 (Prop_lut6_I5_O) 0.124 5.160 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_36/O + net (fo=3, routed) 0.309 5.470 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/I0 + SLICE_X27Y83 LUT3 (Prop_lut3_I0_O) 0.124 5.594 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O + net (fo=2, routed) 3.623 9.217 base_ram_data_IOBUF[0]_inst/I + L24 r base_ram_data_IOBUF[0]_inst/OBUFT/I + L24 OBUFT (Prop_obuft_I_O) 3.545 12.761 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.761 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.761 + ------------------------------------------------------------------- + slack 0.561 + +Slack (MET) : 0.585ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.145ns (logic 5.222ns (34.482%) route 9.923ns (65.518%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.356 2.446 u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y85 r u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/RAMA/RADR0 + SLICE_X22Y85 RAMD32 (Prop_ramd32_RADR0_O) + 0.150 2.596 r u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/RAMA/O + net (fo=1, routed) 0.805 3.401 u_matmul_axi_slave/ep_rd_c0[30] + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0/I2 + SLICE_X24Y83 LUT4 (Prop_lut4_I2_O) 0.328 3.729 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0/O + net (fo=1, routed) 0.428 4.157 u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0_n_0 + SLICE_X26Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I4 + SLICE_X26Y82 LUT5 (Prop_lut5_I4_O) 0.124 4.281 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O + net (fo=1, routed) 0.462 4.742 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[30] + SLICE_X28Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_8__1/I5 + SLICE_X28Y82 LUT6 (Prop_lut6_I5_O) 0.124 4.866 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_8__1/O + net (fo=3, routed) 0.482 5.348 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[30] + SLICE_X28Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I0 + SLICE_X28Y82 LUT3 (Prop_lut3_I0_O) 0.124 5.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O + net (fo=2, routed) 3.721 9.193 base_ram_data_IOBUF[30]_inst/I + M24 r base_ram_data_IOBUF[30]_inst/OBUFT/I + M24 OBUFT (Prop_obuft_I_O) 3.544 12.737 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.737 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.737 + ------------------------------------------------------------------- + slack 0.585 + +Slack (MET) : 0.587ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.143ns (logic 5.221ns (34.475%) route 9.923ns (65.525%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.328 2.418 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/ADDRA0 + SLICE_X22Y82 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA/RADR0 + SLICE_X22Y82 RAMD32 (Prop_ramd32_RADR0_O) + 0.150 2.568 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA/O + net (fo=1, routed) 0.801 3.369 u_matmul_axi_slave/ep_rd_c0[24] + SLICE_X19Y77 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_20__0/I2 + SLICE_X19Y77 LUT4 (Prop_lut4_I2_O) 0.328 3.697 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_20__0/O + net (fo=1, routed) 0.151 3.848 u_matmul_axi_slave/ram_reg_0_7_24_29_i_20__0_n_0 + SLICE_X19Y77 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_14__0/I4 + SLICE_X19Y77 LUT5 (Prop_lut5_I4_O) 0.124 3.972 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_14__0/O + net (fo=1, routed) 0.433 4.405 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[24] + SLICE_X19Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_8__1/I5 + SLICE_X19Y77 LUT6 (Prop_lut6_I5_O) 0.124 4.529 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_8__1/O + net (fo=3, routed) 0.840 5.368 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[24] + SLICE_X11Y71 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[24]_inst_i_1/I0 + SLICE_X11Y71 LUT3 (Prop_lut3_I0_O) 0.124 5.492 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[24]_inst_i_1/O + net (fo=2, routed) 3.701 9.193 ext_ram_data_IOBUF[24]_inst/I + AD17 r ext_ram_data_IOBUF[24]_inst/OBUFT/I + AD17 OBUFT (Prop_obuft_I_O) 3.543 12.736 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.736 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.736 + ------------------------------------------------------------------- + slack 0.587 + +Slack (MET) : 0.616ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.035ns (logic 6.884ns (45.785%) route 8.151ns (54.215%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.367 9.162 base_ram_data_IOBUF[21]_inst/T + M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T + M20 OBUFT (TriStatE_obuft_T_O) + 3.544 12.706 r base_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.706 base_ram_data[21] + M20 r base_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.706 + ------------------------------------------------------------------- + slack 0.616 + +Slack (MET) : 0.622ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.029ns (logic 6.910ns (45.974%) route 8.120ns (54.026%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.335 9.131 base_ram_data_IOBUF[3]_inst/T + M25 f base_ram_data_IOBUF[3]_inst/OBUFT/T + M25 OBUFT (TriStatE_obuft_T_O) + 3.570 12.701 r base_ram_data_IOBUF[3]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.701 base_ram_data[3] + M25 r base_ram_data[3] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.701 + ------------------------------------------------------------------- + slack 0.622 + +Slack (MET) : 0.628ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[18] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.102ns (logic 5.207ns (34.482%) route 9.895ns (65.518%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 + SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 3.505 9.161 base_ram_data_IOBUF[18]_inst/I + P23 r base_ram_data_IOBUF[18]_inst/OBUFT/I + P23 OBUFT (Prop_obuft_I_O) 3.533 12.694 r base_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.694 base_ram_data[18] + P23 r base_ram_data[18] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.694 + ------------------------------------------------------------------- + slack 0.628 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.024ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X57Y90 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.927 -0.381 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 0.287 + arrival time -0.263 + ------------------------------------------------------------------- + slack 0.024 + +Slack (MET) : 0.024ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X57Y90 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.927 -0.381 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 0.287 + arrival time -0.263 + ------------------------------------------------------------------- + slack 0.024 + +Slack (MET) : 0.067ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.559 -0.704 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X82Y130 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[19]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[3] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.063 -0.269 r u_axi_uart_controller/uart0/regs/M_next_carry/O[3] + net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/C + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.067 + +Slack (MET) : 0.071ns (arrival time - required time) + Source: u_matmul_axi_slave/req_1_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/busy_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.362ns (logic 0.186ns (51.410%) route 0.176ns (48.590%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.199ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.448ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.655 -0.607 u_matmul_axi_slave/sys_clk + SLICE_X45Y99 FDRE r u_matmul_axi_slave/req_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 r u_matmul_axi_slave/req_1_reg/Q + net (fo=19, routed) 0.176 -0.291 u_matmul_axi_slave/p_5_in[1] + SLICE_X45Y100 r u_matmul_axi_slave/busy_i_1/I2 + SLICE_X45Y100 LUT6 (Prop_lut6_I2_O) 0.045 -0.246 r u_matmul_axi_slave/busy_i_1/O + net (fo=1, routed) 0.000 -0.246 u_matmul_axi_slave/busy_i_1_n_0 + SLICE_X45Y100 FDRE r u_matmul_axi_slave/busy_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.860 -0.448 u_matmul_axi_slave/sys_clk + SLICE_X45Y100 FDRE r u_matmul_axi_slave/busy_reg/C + clock pessimism 0.040 -0.408 + SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.091 -0.317 u_matmul_axi_slave/busy_reg + ------------------------------------------------------------------- + required time 0.317 + arrival time -0.246 + ------------------------------------------------------------------- + slack 0.071 + +Slack (MET) : 0.073ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.393ns (logic 0.227ns (57.716%) route 0.166ns (42.284%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.199ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.453ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.650 -0.612 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/sys_clk + SLICE_X63Y98 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X63Y98 FDRE (Prop_fdre_C_Q) 0.128 -0.484 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/Q + net (fo=7, routed) 0.166 -0.318 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[1] + SLICE_X62Y100 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/I1 + SLICE_X62Y100 LUT6 (Prop_lut6_I1_O) 0.099 -0.219 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/O + net (fo=1, routed) 0.000 -0.219 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/p_1_in[2] + SLICE_X62Y100 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.855 -0.453 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/sys_clk + SLICE_X62Y100 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/C + clock pessimism 0.040 -0.413 + SLICE_X62Y100 FDRE (Hold_fdre_C_D) 0.121 -0.292 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2] + ------------------------------------------------------------------- + required time 0.292 + arrival time -0.219 + ------------------------------------------------------------------- + slack 0.073 + +Slack (MET) : 0.073ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.437ns (logic 0.189ns (43.230%) route 0.248ns (56.770%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.257ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.486ns + Source Clock Delay (SCD): -0.703ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk + SLICE_X87Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q + net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] + SLICE_X82Y126 r u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/I2 + SLICE_X82Y126 LUT4 (Prop_lut4_I2_O) 0.048 -0.266 r u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/O + net (fo=1, routed) 0.000 -0.266 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[19] + SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.822 -0.486 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk + SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/C + clock pessimism 0.040 -0.446 + SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.107 -0.339 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19] + ------------------------------------------------------------------- + required time 0.339 + arrival time -0.266 + ------------------------------------------------------------------- + slack 0.073 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.559 -0.704 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X82Y130 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[16]/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[0] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) + 0.070 -0.262 r u_axi_uart_controller/uart0/regs/M_next_carry/O[0] + net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/C + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.262 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.425ns (logic 0.209ns (49.172%) route 0.216ns (50.828%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.259ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.486ns + Source Clock Delay (SCD): -0.705ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk + SLICE_X84Y128 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X84Y128 FDRE (Prop_fdre_C_Q) 0.164 -0.541 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/Q + net (fo=23, routed) 0.216 -0.325 u_Axi_CDC/wFifo/Q[19] + SLICE_X82Y126 r u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/I3 + SLICE_X82Y126 LUT6 (Prop_lut6_I3_O) 0.045 -0.280 r u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/O + net (fo=1, routed) 0.000 -0.280 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[3] + SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.822 -0.486 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk + SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/C + clock pessimism 0.040 -0.446 + SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.092 -0.354 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3] + ------------------------------------------------------------------- + required time 0.354 + arrival time -0.280 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.080ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/ier_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.436ns (logic 0.209ns (47.943%) route 0.227ns (52.057%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.476ns + Source Clock Delay (SCD): -0.700ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.563 -0.700 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X84Y133 FDRE r u_axi_uart_controller/uart0/regs/ier_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/ier_reg[3]/Q + net (fo=3, routed) 0.227 -0.309 u_axi_uart_controller/uart0/regs/transmitter/Q[0] + SLICE_X83Y135 r u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/I1 + SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.264 r u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/O + net (fo=1, routed) 0.000 -0.264 u_axi_uart_controller/uart0/regs/transmitter_n_1 + SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.832 -0.476 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/C + clock pessimism 0.040 -0.436 + SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ms_int_pnd_reg + ------------------------------------------------------------------- + required time 0.344 + arrival time -0.264 + ------------------------------------------------------------------- + slack 0.080 + +Slack (MET) : 0.081ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.465ns (logic 0.186ns (40.004%) route 0.279ns (59.996%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.705ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk + SLICE_X85Y128 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X85Y128 FDRE (Prop_fdre_C_Q) 0.141 -0.564 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/Q + net (fo=20, routed) 0.279 -0.285 u_Axi_CDC/wFifo/Q[14] + SLICE_X80Y128 r u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/I4 + SLICE_X80Y128 LUT5 (Prop_lut5_I4_O) 0.045 -0.240 r u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/O + net (fo=1, routed) 0.000 -0.240 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[14] + SLICE_X80Y128 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk + SLICE_X80Y128 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/C + clock pessimism 0.040 -0.441 + SLICE_X80Y128 FDRE (Hold_fdre_C_D) 0.120 -0.321 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14] + ------------------------------------------------------------------- + required time 0.321 + arrival time -0.240 + ------------------------------------------------------------------- + slack 0.081 + +Slack (MET) : 0.083ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/ier_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.439ns (logic 0.209ns (47.634%) route 0.230ns (52.366%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.476ns + Source Clock Delay (SCD): -0.700ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.563 -0.700 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X84Y133 FDRE r u_axi_uart_controller/uart0/regs/ier_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/ier_reg[0]/Q + net (fo=6, routed) 0.230 -0.306 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/Q[0] + SLICE_X83Y135 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/I1 + SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.261 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/O + net (fo=1, routed) 0.000 -0.261 u_axi_uart_controller/uart0/regs/receiver_n_1 + SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.832 -0.476 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/C + clock pessimism 0.040 -0.436 + SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ti_int_pnd_reg + ------------------------------------------------------------------- + required time 0.344 + arrival time -0.261 + ------------------------------------------------------------------- + slack 0.083 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk + SLICE_X43Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q + net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/Q[7] + RAMB18_X2Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.962 -0.346 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/sys_clk + RAMB18_X2Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK + clock pessimism -0.213 -0.559 + RAMB18_X2Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.292 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk + SLICE_X43Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q + net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/Q[7] + RAMB18_X2Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.962 -0.346 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/sys_clk + RAMB18_X2Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK + clock pessimism -0.213 -0.559 + RAMB18_X2Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.292 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_clk +Waveform(ns): { 0.000 10.000 } +Period(ns): 20.000 +Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X2Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X2Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X2Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X2Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y6 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK +Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I +Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 +Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: cpu_clk + To Clock: cpu_clk + +Setup : 0 Failing Endpoints, Worst Slack 26.018ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.681ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 26.018ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 26.696 + arrival time -0.678 + ------------------------------------------------------------------- + slack 26.018 + +Slack (MET) : 26.018ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 26.696 + arrival time -0.678 + ------------------------------------------------------------------- + slack 26.018 + +Slack (MET) : 26.018ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 26.696 + arrival time -0.678 + ------------------------------------------------------------------- + slack 26.018 + +Slack (MET) : 26.018ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 26.696 + arrival time -0.678 + ------------------------------------------------------------------- + slack 26.018 + +Slack (MET) : 26.062ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.361 26.740 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 26.740 + arrival time -0.678 + ------------------------------------------------------------------- + slack 26.062 + +Slack (MET) : 26.062ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.361 26.740 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 26.740 + arrival time -0.678 + ------------------------------------------------------------------- + slack 26.062 + +Slack (MET) : 26.104ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.782 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 26.782 + arrival time -0.678 + ------------------------------------------------------------------- + slack 26.104 + +Slack (MET) : 26.104ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.782 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 26.782 + arrival time -0.678 + ------------------------------------------------------------------- + slack 26.104 + +Slack (MET) : 26.156ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.270ns (logic 0.642ns (19.635%) route 2.628ns (80.365%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.056ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.299ns = ( 27.701 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.986 0.592 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y127 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.529 27.701 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y127 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.435 27.266 + clock uncertainty -0.113 27.153 + SLICE_X89Y127 FDCE (Recov_fdce_C_CLR) -0.405 26.748 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] + ------------------------------------------------------------------- + required time 26.748 + arrival time -0.592 + ------------------------------------------------------------------- + slack 26.156 + +Slack (MET) : 26.156ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.270ns (logic 0.642ns (19.635%) route 2.628ns (80.365%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.056ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.299ns = ( 27.701 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.986 0.592 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y127 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.529 27.701 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y127 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C + clock pessimism -0.435 27.266 + clock uncertainty -0.113 27.153 + SLICE_X89Y127 FDCE (Recov_fdce_C_CLR) -0.405 26.748 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] + ------------------------------------------------------------------- + required time 26.748 + arrival time -0.592 + ------------------------------------------------------------------- + slack 26.156 + +Slack (MET) : 26.290ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.110ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.507 27.212 + clock uncertainty -0.113 27.099 + SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.361 26.738 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 26.738 + arrival time -0.448 + ------------------------------------------------------------------- + slack 26.290 + +Slack (MET) : 26.332ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.110ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.507 27.212 + clock uncertainty -0.113 27.099 + SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.319 26.780 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 26.780 + arrival time -0.448 + ------------------------------------------------------------------- + slack 26.332 + +Slack (MET) : 26.332ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.110ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.507 27.212 + clock uncertainty -0.113 27.099 + SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.319 26.780 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 26.780 + arrival time -0.448 + ------------------------------------------------------------------- + slack 26.332 + +Slack (MET) : 26.332ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.110ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C + clock pessimism -0.507 27.212 + clock uncertainty -0.113 27.099 + SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.319 26.780 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] + ------------------------------------------------------------------- + required time 26.780 + arrival time -0.448 + ------------------------------------------------------------------- + slack 26.332 + +Slack (MET) : 26.351ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.109ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C + clock pessimism -0.507 27.213 + clock uncertainty -0.113 27.100 + SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.361 26.739 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 26.739 + arrival time -0.388 + ------------------------------------------------------------------- + slack 26.351 + +Slack (MET) : 26.393ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.109ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.507 27.213 + clock uncertainty -0.113 27.100 + SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.781 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 26.781 + arrival time -0.388 + ------------------------------------------------------------------- + slack 26.393 + +Slack (MET) : 26.393ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.109ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.507 27.213 + clock uncertainty -0.113 27.100 + SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.781 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 26.781 + arrival time -0.388 + ------------------------------------------------------------------- + slack 26.393 + +Slack (MET) : 26.393ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.109ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C + clock pessimism -0.507 27.213 + clock uncertainty -0.113 27.100 + SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.781 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] + ------------------------------------------------------------------- + required time 26.781 + arrival time -0.388 + ------------------------------------------------------------------- + slack 26.393 + +Slack (MET) : 26.825ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.435 27.267 + clock uncertainty -0.113 27.154 + SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 26.749 + arrival time 0.077 + ------------------------------------------------------------------- + slack 26.825 + +Slack (MET) : 26.825ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.435 27.267 + clock uncertainty -0.113 27.154 + SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 26.749 + arrival time 0.077 + ------------------------------------------------------------------- + slack 26.825 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.681ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.596ns (logic 0.246ns (41.259%) route 0.350ns (58.741%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.293 -0.089 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X93Y122 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y122 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C + clock pessimism -0.209 -0.678 + SLICE_X93Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.770 + arrival time -0.089 + ------------------------------------------------------------------- + slack 0.681 + +Slack (MET) : 0.692ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk + SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C + clock pessimism -0.189 -0.656 + SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.723 + arrival time -0.031 + ------------------------------------------------------------------- + slack 0.692 + +Slack (MET) : 0.692ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk + SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.189 -0.656 + SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.723 + arrival time -0.031 + ------------------------------------------------------------------- + slack 0.692 + +Slack (MET) : 0.692ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk + SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.189 -0.656 + SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.723 + arrival time -0.031 + ------------------------------------------------------------------- + slack 0.692 + +Slack (MET) : 0.692ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk + SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.189 -0.656 + SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.723 + arrival time -0.031 + ------------------------------------------------------------------- + slack 0.692 + +Slack (MET) : 0.750ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/bFifo/cpu_clk + SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/C + clock pessimism -0.209 -0.678 + SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 0.770 + arrival time -0.020 + ------------------------------------------------------------------- + slack 0.750 + +Slack (MET) : 0.750ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/bFifo/cpu_clk + SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.209 -0.678 + SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.770 + arrival time -0.020 + ------------------------------------------------------------------- + slack 0.750 + +Slack (MET) : 0.750ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/bFifo/cpu_clk + SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.209 -0.678 + SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.770 + arrival time -0.020 + ------------------------------------------------------------------- + slack 0.750 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.209 -0.667 + SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.074 + ------------------------------------------------------------------- + slack 0.808 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: mlkem_clk + To Clock: mlkem_clk + +Setup : 0 Failing Endpoints, Worst Slack 3.826ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.658ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 3.826ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.817ns (logic 0.642ns (7.282%) route 8.175ns (92.718%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.745 6.147 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X96Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.720 10.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X96Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/C + clock pessimism -0.507 10.385 + clock uncertainty -0.093 10.292 + SLICE_X96Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.973 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22] + ------------------------------------------------------------------- + required time 9.973 + arrival time -6.147 + ------------------------------------------------------------------- + slack 3.826 + +Slack (MET) : 3.860ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.747ns (logic 0.642ns (7.340%) route 8.105ns (92.660%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.061ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.102ns = ( 10.898 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.675 6.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X104Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.726 10.898 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X104Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/C + clock pessimism -0.507 10.391 + clock uncertainty -0.093 10.298 + SLICE_X104Y85 FDCE (Recov_fdce_C_CLR) -0.361 9.937 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5] + ------------------------------------------------------------------- + required time 9.937 + arrival time -6.077 + ------------------------------------------------------------------- + slack 3.860 + +Slack (MET) : 3.902ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.747ns (logic 0.642ns (7.340%) route 8.105ns (92.660%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.061ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.102ns = ( 10.898 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.675 6.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X104Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.726 10.898 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X104Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/C + clock pessimism -0.507 10.391 + clock uncertainty -0.093 10.298 + SLICE_X104Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26] + ------------------------------------------------------------------- + required time 9.979 + arrival time -6.077 + ------------------------------------------------------------------- + slack 3.902 + +Slack (MET) : 4.068ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22] + ------------------------------------------------------------------- + required time 9.883 + arrival time -5.815 + ------------------------------------------------------------------- + slack 4.068 + +Slack (MET) : 4.068ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8] + ------------------------------------------------------------------- + required time 9.883 + arrival time -5.815 + ------------------------------------------------------------------- + slack 4.068 + +Slack (MET) : 4.068ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9] + ------------------------------------------------------------------- + required time 9.883 + arrival time -5.815 + ------------------------------------------------------------------- + slack 4.068 + +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12] + ------------------------------------------------------------------- + required time 9.884 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.115 + +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31] + ------------------------------------------------------------------- + required time 9.884 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.115 + +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3] + ------------------------------------------------------------------- + required time 9.884 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.115 + +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4] + ------------------------------------------------------------------- + required time 9.884 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.115 + +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5] + ------------------------------------------------------------------- + required time 9.884 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.115 + +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6] + ------------------------------------------------------------------- + required time 9.884 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.115 + +Slack (MET) : 4.154ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X94Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X94Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X94Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6] + ------------------------------------------------------------------- + required time 9.969 + arrival time -5.815 + ------------------------------------------------------------------- + slack 4.154 + +Slack (MET) : 4.154ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X94Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X94Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X94Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8] + ------------------------------------------------------------------- + required time 9.969 + arrival time -5.815 + ------------------------------------------------------------------- + slack 4.154 + +Slack (MET) : 4.159ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X100Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X100Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X100Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.928 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26] + ------------------------------------------------------------------- + required time 9.928 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.159 + +Slack (MET) : 4.201ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X100Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X100Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X100Y86 FDCE (Recov_fdce_C_CLR) -0.319 9.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25] + ------------------------------------------------------------------- + required time 9.970 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.201 + +Slack (MET) : 4.223ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/C + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24] + ------------------------------------------------------------------- + required time 9.886 + arrival time -5.662 + ------------------------------------------------------------------- + slack 4.223 + +Slack (MET) : 4.223ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/C + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27] + ------------------------------------------------------------------- + required time 9.886 + arrival time -5.662 + ------------------------------------------------------------------- + slack 4.223 + +Slack (MET) : 4.223ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/C + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4] + ------------------------------------------------------------------- + required time 9.886 + arrival time -5.662 + ------------------------------------------------------------------- + slack 4.223 + +Slack (MET) : 4.223ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/C + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7] + ------------------------------------------------------------------- + required time 9.886 + arrival time -5.662 + ------------------------------------------------------------------- + slack 4.223 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.658ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.923ns (logic 0.227ns (24.583%) route 0.696ns (75.417%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.332ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.414 0.243 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X72Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C + clock pessimism 0.040 -0.348 + SLICE_X72Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.415 + arrival time 0.243 + ------------------------------------------------------------------- + slack 0.658 + +Slack (MET) : 0.796ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism 0.040 -0.350 + SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.417 + arrival time 0.379 + ------------------------------------------------------------------- + slack 0.796 + +Slack (MET) : 0.796ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism 0.040 -0.350 + SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.417 + arrival time 0.379 + ------------------------------------------------------------------- + slack 0.796 + +Slack (MET) : 0.796ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism 0.040 -0.350 + SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.417 + arrival time 0.379 + ------------------------------------------------------------------- + slack 0.796 + +Slack (MET) : 0.796ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism 0.040 -0.350 + SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.417 + arrival time 0.379 + ------------------------------------------------------------------- + slack 0.796 + +Slack (MET) : 0.807ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C + clock pessimism 0.040 -0.351 + SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.418 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.807 + +Slack (MET) : 0.807ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C + clock pessimism 0.040 -0.351 + SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.418 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.807 + +Slack (MET) : 0.807ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism 0.040 -0.351 + SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.418 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.807 + +Slack (MET) : 0.807ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism 0.040 -0.351 + SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.418 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.807 + +Slack (MET) : 0.832ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/C + clock pessimism 0.040 -0.351 + SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.443 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.832 + +Slack (MET) : 0.832ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/C + clock pessimism 0.040 -0.351 + SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.443 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.832 + +Slack (MET) : 0.832ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/C + clock pessimism 0.040 -0.351 + SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 0.443 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.832 + +Slack (MET) : 0.832ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/C + clock pessimism 0.040 -0.351 + SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.443 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.832 + +Slack (MET) : 0.884ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg + SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/C + clock pessimism 0.040 -0.345 + SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.437 + arrival time 0.447 + ------------------------------------------------------------------- + slack 0.884 + +Slack (MET) : 0.884ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg + SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/C + clock pessimism 0.040 -0.345 + SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.437 + arrival time 0.447 + ------------------------------------------------------------------- + slack 0.884 + +Slack (MET) : 0.884ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg + SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/C + clock pessimism 0.040 -0.345 + SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 0.437 + arrival time 0.447 + ------------------------------------------------------------------- + slack 0.884 + +Slack (MET) : 0.884ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg + SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/C + clock pessimism 0.040 -0.345 + SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.437 + arrival time 0.447 + ------------------------------------------------------------------- + slack 0.884 + +Slack (MET) : 0.906ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.080ns (logic 0.226ns (20.934%) route 0.854ns (79.066%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.683 0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X93Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/C + clock pessimism 0.040 -0.347 + SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15] + ------------------------------------------------------------------- + required time 0.506 + arrival time 0.400 + ------------------------------------------------------------------- + slack 0.906 + +Slack (MET) : 0.906ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.080ns (logic 0.226ns (20.934%) route 0.854ns (79.066%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.683 0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X93Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/C + clock pessimism 0.040 -0.347 + SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53] + ------------------------------------------------------------------- + required time 0.506 + arrival time 0.400 + ------------------------------------------------------------------- + slack 0.906 + +Slack (MET) : 0.927ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X100Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/C + clock pessimism 0.040 -0.341 + SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.452 + ------------------------------------------------------------------- + slack 0.927 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: sys_clk + To Clock: sys_clk + +Setup : 0 Failing Endpoints, Worst Slack 6.335ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.573ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 6.335ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.243ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C + clock pessimism -0.514 17.184 + clock uncertainty -0.102 17.081 + SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[1] + ------------------------------------------------------------------- + required time 16.558 + arrival time -10.223 + ------------------------------------------------------------------- + slack 6.335 + +Slack (MET) : 6.335ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.243ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C + clock pessimism -0.514 17.184 + clock uncertainty -0.102 17.081 + SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[2] + ------------------------------------------------------------------- + required time 16.558 + arrival time -10.223 + ------------------------------------------------------------------- + slack 6.335 + +Slack (MET) : 6.335ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.243ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + clock pessimism -0.514 17.184 + clock uncertainty -0.102 17.081 + SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[5] + ------------------------------------------------------------------- + required time 16.558 + arrival time -10.223 + ------------------------------------------------------------------- + slack 6.335 + +Slack (MET) : 6.335ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.243ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + clock pessimism -0.514 17.184 + clock uncertainty -0.102 17.081 + SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[6] + ------------------------------------------------------------------- + required time 16.558 + arrival time -10.223 + ------------------------------------------------------------------- + slack 6.335 + +Slack (MET) : 6.478ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.242ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + clock pessimism -0.514 17.185 + clock uncertainty -0.102 17.082 + SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[0] + ------------------------------------------------------------------- + required time 16.559 + arrival time -10.081 + ------------------------------------------------------------------- + slack 6.478 + +Slack (MET) : 6.478ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.242ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C + clock pessimism -0.514 17.185 + clock uncertainty -0.102 17.082 + SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[3] + ------------------------------------------------------------------- + required time 16.559 + arrival time -10.081 + ------------------------------------------------------------------- + slack 6.478 + +Slack (MET) : 6.478ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.242ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C + clock pessimism -0.514 17.185 + clock uncertainty -0.102 17.082 + SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[4] + ------------------------------------------------------------------- + required time 16.559 + arrival time -10.081 + ------------------------------------------------------------------- + slack 6.478 + +Slack (MET) : 6.478ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.242ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C + clock pessimism -0.514 17.185 + clock uncertainty -0.102 17.082 + SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[7] + ------------------------------------------------------------------- + required time 16.559 + arrival time -10.081 + ------------------------------------------------------------------- + slack 6.478 + +Slack (MET) : 6.900ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 12.246ns (logic 0.668ns (5.455%) route 11.578ns (94.545%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 17.719 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.466 9.673 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X63Y141 FDCE f u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.547 17.719 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X63Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C + clock pessimism -0.435 17.284 + clock uncertainty -0.102 17.182 + SLICE_X63Y141 FDCE (Recov_fdce_C_CLR) -0.609 16.573 u_confreg/u_digitaltube_controller/dpy0_reg_reg[0] + ------------------------------------------------------------------- + required time 16.573 + arrival time -9.673 + ------------------------------------------------------------------- + slack 6.900 + +Slack (MET) : 6.930ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 12.290ns (logic 0.668ns (5.435%) route 11.622ns (94.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.155ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.509 9.716 u_confreg/u_int_ctrl/p_0_in + SLICE_X70Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.534 17.706 u_confreg/u_int_ctrl/sys_clk + SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C + clock pessimism -0.435 17.271 + clock uncertainty -0.102 17.169 + SLICE_X70Y133 FDCE (Recov_fdce_C_CLR) -0.523 16.646 u_confreg/u_int_ctrl/int_in_sync_d1_reg[1] + ------------------------------------------------------------------- + required time 16.646 + arrival time -9.716 + ------------------------------------------------------------------- + slack 6.930 + +Slack (MET) : 6.930ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/int_in_sync_d2_reg[1]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 12.290ns (logic 0.668ns (5.435%) route 11.622ns (94.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.155ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.509 9.716 u_confreg/u_int_ctrl/p_0_in + SLICE_X70Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d2_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.534 17.706 u_confreg/u_int_ctrl/sys_clk + SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[1]/C + clock pessimism -0.435 17.271 + clock uncertainty -0.102 17.169 + SLICE_X70Y133 FDCE (Recov_fdce_C_CLR) -0.523 16.646 u_confreg/u_int_ctrl/int_in_sync_d2_reg[1] + ------------------------------------------------------------------- + required time 16.646 + arrival time -9.716 + ------------------------------------------------------------------- + slack 6.930 + +Slack (MET) : 7.490ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 11.649ns (logic 0.668ns (5.734%) route 10.981ns (94.266%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.149ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.288ns = ( 17.712 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.868 9.076 u_confreg/u_int_ctrl/p_0_in + SLICE_X65Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.540 17.712 u_confreg/u_int_ctrl/sys_clk + SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C + clock pessimism -0.435 17.277 + clock uncertainty -0.102 17.175 + SLICE_X65Y133 FDCE (Recov_fdce_C_CLR) -0.609 16.566 u_confreg/u_int_ctrl/int_in_sync_d1_reg[2] + ------------------------------------------------------------------- + required time 16.566 + arrival time -9.076 + ------------------------------------------------------------------- + slack 7.490 + +Slack (MET) : 7.490ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/int_in_sync_d2_reg[2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 11.649ns (logic 0.668ns (5.734%) route 10.981ns (94.266%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.149ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.288ns = ( 17.712 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.868 9.076 u_confreg/u_int_ctrl/p_0_in + SLICE_X65Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d2_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.540 17.712 u_confreg/u_int_ctrl/sys_clk + SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[2]/C + clock pessimism -0.435 17.277 + clock uncertainty -0.102 17.175 + SLICE_X65Y133 FDCE (Recov_fdce_C_CLR) -0.609 16.566 u_confreg/u_int_ctrl/int_in_sync_d2_reg[2] + ------------------------------------------------------------------- + required time 16.566 + arrival time -9.076 + ------------------------------------------------------------------- + slack 7.490 + +Slack (MET) : 7.742ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[23]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 11.496ns (logic 0.668ns (5.811%) route 10.828ns (94.189%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.137ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.715 8.922 u_confreg/u_int_ctrl/p_0_in + SLICE_X46Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[23]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk + SLICE_X46Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[23]/C + clock pessimism -0.435 17.289 + clock uncertainty -0.102 17.187 + SLICE_X46Y140 FDCE (Recov_fdce_C_CLR) -0.523 16.664 u_confreg/u_int_ctrl/edge_int_state_reg[23] + ------------------------------------------------------------------- + required time 16.664 + arrival time -8.922 + ------------------------------------------------------------------- + slack 7.742 + +Slack (MET) : 7.801ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[21]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 11.350ns (logic 0.668ns (5.885%) route 10.682ns (94.115%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.137ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.569 8.777 u_confreg/u_int_ctrl/p_0_in + SLICE_X47Y139 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[21]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk + SLICE_X47Y139 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[21]/C + clock pessimism -0.435 17.289 + clock uncertainty -0.102 17.187 + SLICE_X47Y139 FDCE (Recov_fdce_C_CLR) -0.609 16.578 u_confreg/u_int_ctrl/edge_int_state_reg[21] + ------------------------------------------------------------------- + required time 16.578 + arrival time -8.777 + ------------------------------------------------------------------- + slack 7.801 + +Slack (MET) : 7.821ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[29]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 11.414ns (logic 0.668ns (5.852%) route 10.746ns (94.148%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.139ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.634 8.841 u_confreg/u_int_ctrl/p_0_in + SLICE_X56Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[29]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk + SLICE_X56Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[29]/C + clock pessimism -0.435 17.287 + clock uncertainty -0.102 17.185 + SLICE_X56Y140 FDCE (Recov_fdce_C_CLR) -0.523 16.662 u_confreg/u_int_ctrl/edge_int_state_reg[29] + ------------------------------------------------------------------- + required time 16.662 + arrival time -8.841 + ------------------------------------------------------------------- + slack 7.821 + +Slack (MET) : 7.851ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[30]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 11.298ns (logic 0.668ns (5.912%) route 10.630ns (94.088%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.139ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.517 8.725 u_confreg/u_int_ctrl/p_0_in + SLICE_X55Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[30]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk + SLICE_X55Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[30]/C + clock pessimism -0.435 17.287 + clock uncertainty -0.102 17.185 + SLICE_X55Y140 FDCE (Recov_fdce_C_CLR) -0.609 16.576 u_confreg/u_int_ctrl/edge_int_state_reg[30] + ------------------------------------------------------------------- + required time 16.576 + arrival time -8.725 + ------------------------------------------------------------------- + slack 7.851 + +Slack (MET) : 7.963ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[20]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 11.189ns (logic 0.668ns (5.970%) route 10.521ns (94.030%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.137ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.408 8.616 u_confreg/u_int_ctrl/p_0_in + SLICE_X49Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[20]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk + SLICE_X49Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[20]/C + clock pessimism -0.435 17.289 + clock uncertainty -0.102 17.187 + SLICE_X49Y140 FDCE (Recov_fdce_C_CLR) -0.609 16.578 u_confreg/u_int_ctrl/edge_int_state_reg[20] + ------------------------------------------------------------------- + required time 16.578 + arrival time -8.616 + ------------------------------------------------------------------- + slack 7.963 + +Slack (MET) : 8.025ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[5]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 11.122ns (logic 0.668ns (6.006%) route 10.454ns (93.994%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.342 8.549 u_confreg/u_int_ctrl/p_0_in + SLICE_X58Y137 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk + SLICE_X58Y137 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[5]/C + clock pessimism -0.435 17.285 + clock uncertainty -0.102 17.183 + SLICE_X58Y137 FDCE (Recov_fdce_C_CLR) -0.609 16.574 u_confreg/u_int_ctrl/edge_int_state_reg[5] + ------------------------------------------------------------------- + required time 16.574 + arrival time -8.549 + ------------------------------------------------------------------- + slack 8.025 + +Slack (MET) : 8.025ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 11.122ns (logic 0.668ns (6.006%) route 10.454ns (93.994%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.342 8.549 u_confreg/u_int_ctrl/p_0_in + SLICE_X58Y137 FDCE f u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk + SLICE_X58Y137 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/C + clock pessimism -0.435 17.285 + clock uncertainty -0.102 17.183 + SLICE_X58Y137 FDCE (Recov_fdce_C_CLR) -0.609 16.574 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5] + ------------------------------------------------------------------- + required time 16.574 + arrival time -8.549 + ------------------------------------------------------------------- + slack 8.025 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.573ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.019ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.213 -0.600 + SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.667 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.573 + +Slack (MET) : 0.573ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.019ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.213 -0.600 + SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.667 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.573 + +Slack (MET) : 0.573ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.019ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.213 -0.600 + SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.667 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.573 + +Slack (MET) : 0.837ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.812ns (logic 0.227ns (27.961%) route 0.585ns (72.039%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.445 0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X64Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X64Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/C + clock pessimism -0.192 -0.577 + SLICE_X64Y95 FDCE (Remov_fdce_C_CLR) -0.067 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.644 + arrival time 0.192 + ------------------------------------------------------------------- + slack 0.837 + +Slack (MET) : 0.871ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.822ns (logic 0.227ns (27.605%) route 0.595ns (72.395%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.043ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.384ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.456 0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X65Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X65Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.192 -0.576 + SLICE_X65Y99 FDCE (Remov_fdce_C_CLR) -0.092 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.203 + ------------------------------------------------------------------- + slack 0.871 + +Slack (MET) : 0.871ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.822ns (logic 0.227ns (27.605%) route 0.595ns (72.395%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.043ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.384ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.456 0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X65Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X65Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.192 -0.576 + SLICE_X65Y99 FDCE (Remov_fdce_C_CLR) -0.092 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.203 + ------------------------------------------------------------------- + slack 0.871 + +Slack (MET) : 0.912ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.189 -0.666 + SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.912 + +Slack (MET) : 0.912ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.189 -0.666 + SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.912 + +Slack (MET) : 0.912ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.189 -0.666 + SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.912 + +Slack (MET) : 0.912ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C + clock pessimism -0.189 -0.666 + SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.912 + +Slack (MET) : 0.919ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.023ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.209 -0.670 + SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.737 + arrival time 0.182 + ------------------------------------------------------------------- + slack 0.919 + +Slack (MET) : 0.919ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.023ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.209 -0.670 + SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.737 + arrival time 0.182 + ------------------------------------------------------------------- + slack 0.919 + +Slack (MET) : 0.919ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.023ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.209 -0.670 + SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.737 + arrival time 0.182 + ------------------------------------------------------------------- + slack 0.919 + +Slack (MET) : 0.919ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.023ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.209 -0.670 + SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.737 + arrival time 0.182 + ------------------------------------------------------------------- + slack 0.919 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: sys_clk + To Clock: cpu_clk + +Max Delay 59 Endpoints +Min Delay 59 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: pll_clk.u_rst_cpu/delay_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.290ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.617 7.824 pll_clk.u_rst_cpu/p_0_in_0 + SLICE_X92Y115 FDCE f pll_clk.u_rst_cpu/delay_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.544 -2.284 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[0]/C + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: pll_clk.u_rst_cpu/delay_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.290ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.617 7.824 pll_clk.u_rst_cpu/p_0_in_0 + SLICE_X92Y115 FDCE f pll_clk.u_rst_cpu/delay_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.544 -2.284 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.290ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.617 7.824 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 + SLICE_X92Y115 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.544 -2.284 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.290ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.617 7.824 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 + SLICE_X92Y115 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.544 -2.284 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.208ns (logic 1.344ns (25.806%) route 3.864ns (74.194%)) + Logic Levels: 0 + Clock Path Skew: 0.107ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns + Source Clock Delay (SCD): -2.397ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 1.344 -1.053 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 3.864 2.811 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.118ns (logic 1.336ns (26.105%) route 3.782ns (73.895%)) + Logic Levels: 0 + Clock Path Skew: 0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.336 -1.062 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O + net (fo=1, routed) 3.782 2.720 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.096ns (logic 1.317ns (25.844%) route 3.779ns (74.156%)) + Logic Levels: 0 + Clock Path Skew: 0.104ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.397ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 1.317 -1.080 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O + net (fo=1, routed) 3.779 2.699 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.064ns (logic 1.314ns (25.947%) route 3.750ns (74.053%)) + Logic Levels: 0 + Clock Path Skew: 0.106ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.314 -1.084 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O + net (fo=1, routed) 3.750 2.667 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.040ns (logic 1.309ns (25.973%) route 3.731ns (74.027%)) + Logic Levels: 0 + Clock Path Skew: 0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.309 -1.089 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 3.731 2.642 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.035ns (logic 1.314ns (26.100%) route 3.721ns (73.900%)) + Logic Levels: 0 + Clock Path Skew: 0.107ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns + Source Clock Delay (SCD): -2.397ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 1.314 -1.083 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O + net (fo=1, routed) 3.721 2.638 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.971ns (logic 1.344ns (27.035%) route 3.627ns (72.965%)) + Logic Levels: 0 + Clock Path Skew: 0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.344 -1.054 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O + net (fo=1, routed) 3.627 2.574 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.947ns (logic 1.344ns (27.169%) route 3.603ns (72.831%)) + Logic Levels: 0 + Clock Path Skew: 0.106ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.344 -1.054 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 3.603 2.549 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.937ns (logic 1.317ns (26.677%) route 3.620ns (73.323%)) + Logic Levels: 0 + Clock Path Skew: 0.106ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.317 -1.081 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O + net (fo=1, routed) 3.620 2.539 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.925ns (logic 1.309ns (26.579%) route 3.616ns (73.421%)) + Logic Levels: 0 + Clock Path Skew: 0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.309 -1.089 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 3.616 2.527 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.852ns (logic 1.317ns (27.146%) route 3.535ns (72.854%)) + Logic Levels: 0 + Clock Path Skew: 0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.317 -1.081 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O + net (fo=1, routed) 3.535 2.454 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] + SLICE_X93Y111 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y111 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.709ns (logic 1.336ns (28.372%) route 3.373ns (71.628%)) + Logic Levels: 0 + Clock Path Skew: 0.119ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.336 -1.076 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O + net (fo=1, routed) 3.373 2.297 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.686ns (logic 1.314ns (28.042%) route 3.372ns (71.958%)) + Logic Levels: 0 + Clock Path Skew: 0.119ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.314 -1.098 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O + net (fo=1, routed) 3.372 2.274 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.616ns (logic 1.336ns (28.941%) route 3.280ns (71.059%)) + Logic Levels: 0 + Clock Path Skew: 0.104ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.397ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 1.336 -1.061 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O + net (fo=1, routed) 3.280 2.220 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.560ns (logic 1.343ns (29.450%) route 3.217ns (70.550%)) + Logic Levels: 0 + Clock Path Skew: 0.106ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.343 -1.055 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O + net (fo=1, routed) 3.217 2.163 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.469ns (logic 1.309ns (29.293%) route 3.160ns (70.707%)) + Logic Levels: 0 + Clock Path Skew: 0.105ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns + Source Clock Delay (SCD): -2.397ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 1.309 -1.088 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 3.160 2.072 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cpu/u_csr/csr_estat_reg[3]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.669ns (logic 0.518ns (77.393%) route 0.151ns (22.607%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.396ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.697ns + Source Clock Delay (SCD): -2.301ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.527 -2.301 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X74Y119 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y119 FDRE (Prop_fdre_C_Q) 0.418 -1.883 r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/Q + net (fo=3, routed) 0.151 -1.732 u_snix_axil_cdma_mux_8ch/ch_done_reg[2]_0 + SLICE_X75Y119 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/I1 + SLICE_X75Y119 LUT5 (Prop_lut5_I1_O) 0.100 -1.632 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O + net (fo=1, routed) 0.000 -1.632 u_cpu/u_csr/interrupt[1] + SLICE_X75Y119 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.645 -2.697 u_cpu/u_csr/cpu_clk + SLICE_X75Y119 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.682ns (logic 0.418ns (61.288%) route 0.264ns (38.712%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.694ns + Source Clock Delay (SCD): -2.300ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.418 -1.882 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q + net (fo=1, routed) 0.264 -1.618 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.672ns (logic 0.418ns (62.183%) route 0.254ns (37.817%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.685ns + Source Clock Delay (SCD): -2.290ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.538 -2.290 u_Axi_CDC/bFifo/sys_clk + SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.418 -1.872 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.254 -1.618 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.657 -2.685 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.776ns (logic 0.385ns (49.618%) route 0.391ns (50.382%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.694ns + Source Clock Delay (SCD): -2.300ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.385 -1.915 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.391 -1.524 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] + SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.803ns (logic 0.418ns (52.045%) route 0.385ns (47.955%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.280ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.548 -2.280 u_Axi_CDC/awFifo/sys_clk + SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y110 FDCE (Prop_fdce_C_Q) 0.418 -1.862 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.385 -1.477 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[0] + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.837ns (logic 0.418ns (49.921%) route 0.419ns (50.079%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.694ns + Source Clock Delay (SCD): -2.300ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.418 -1.882 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.419 -1.463 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3] + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.838ns (logic 0.418ns (49.893%) route 0.420ns (50.107%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.280ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.548 -2.280 u_Axi_CDC/awFifo/sys_clk + SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y110 FDCE (Prop_fdce_C_Q) 0.418 -1.862 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.420 -1.442 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.857ns (logic 0.367ns (42.833%) route 0.490ns (57.167%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.280ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.548 -2.280 u_Axi_CDC/awFifo/sys_clk + SLICE_X93Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X93Y110 FDCE (Prop_fdce_C_Q) 0.367 -1.913 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.490 -1.423 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.968ns (logic 0.418ns (43.176%) route 0.550ns (56.824%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.694ns + Source Clock Delay (SCD): -2.300ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.418 -1.882 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q + net (fo=1, routed) 0.550 -1.332 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.007ns (logic 0.385ns (38.250%) route 0.622ns (61.750%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.685ns + Source Clock Delay (SCD): -2.290ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.538 -2.290 u_Axi_CDC/bFifo/sys_clk + SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.385 -1.905 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.622 -1.283 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.657 -2.685 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.033ns (logic 0.418ns (40.449%) route 0.615ns (59.551%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.685ns + Source Clock Delay (SCD): -2.290ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.538 -2.290 u_Axi_CDC/bFifo/sys_clk + SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.418 -1.872 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.615 -1.256 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.657 -2.685 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.901ns (logic 0.337ns (37.384%) route 0.564ns (62.616%)) + Logic Levels: 0 + Clock Path Skew: -0.556ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.692ns + Source Clock Delay (SCD): -2.135ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.693 -2.135 u_Axi_CDC/arFifo/sys_clk + SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.337 -1.798 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.564 -1.234 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.650 -2.692 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_confreg/int_out_or_q2_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cpu/u_csr/csr_estat_reg[2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.082ns (logic 0.367ns (33.922%) route 0.715ns (66.078%)) + Logic Levels: 0 + Clock Path Skew: -0.389ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.691ns + Source Clock Delay (SCD): -2.302ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.526 -2.302 u_confreg/sys_clk + SLICE_X78Y141 FDRE r u_confreg/int_out_or_q2_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y141 FDRE (Prop_fdre_C_Q) 0.367 -1.935 r u_confreg/int_out_or_q2_reg/Q + net (fo=1, routed) 0.715 -1.220 u_cpu/u_csr/interrupt[0] + SLICE_X84Y149 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.651 -2.691 u_cpu/u_csr/cpu_clk + SLICE_X84Y149 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.927ns (logic 0.367ns (39.581%) route 0.560ns (60.419%)) + Logic Levels: 0 + Clock Path Skew: -0.556ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.692ns + Source Clock Delay (SCD): -2.135ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.693 -2.135 u_Axi_CDC/arFifo/sys_clk + SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.367 -1.768 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.560 -1.208 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.650 -2.692 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.999ns (logic 0.418ns (41.855%) route 0.581ns (58.145%)) + Logic Levels: 0 + Clock Path Skew: -0.558ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk + SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.418 -1.697 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=2, routed) 0.581 -1.117 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.010ns (logic 0.418ns (41.371%) route 0.592ns (58.629%)) + Logic Levels: 0 + Clock Path Skew: -0.558ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk + SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.418 -1.697 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.592 -1.105 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.033ns (logic 0.367ns (35.528%) route 0.666ns (64.472%)) + Logic Levels: 0 + Clock Path Skew: -0.556ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.692ns + Source Clock Delay (SCD): -2.135ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.693 -2.135 u_Axi_CDC/arFifo/sys_clk + SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.367 -1.768 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.666 -1.102 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.650 -2.692 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.099ns (logic 0.385ns (35.032%) route 0.714ns (64.968%)) + Logic Levels: 0 + Clock Path Skew: -0.558ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk + SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.385 -1.730 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q + net (fo=4, routed) 0.714 -1.016 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.234ns (logic 0.418ns (33.873%) route 0.816ns (66.127%)) + Logic Levels: 0 + Clock Path Skew: -0.558ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk + SLICE_X62Y94 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y94 FDCE (Prop_fdce_C_Q) 0.418 -1.697 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.816 -0.881 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cpu/u_csr/csr_estat_reg[5]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.609ns (logic 0.385ns (23.934%) route 1.224ns (76.066%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.670ns + Source Clock Delay (SCD): -2.276ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.552 -2.276 u_fft_mlkem_axi_slave/sys_clk + SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X96Y110 FDCE (Prop_fdce_C_Q) 0.385 -1.891 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/Q + net (fo=1, routed) 1.224 -0.667 u_cpu/u_csr/interrupt[3] + SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.672 -2.670 u_cpu/u_csr/cpu_clk + SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: sys_clk + To Clock: mlkem_clk + +Max Delay 112 Endpoints +Min Delay 112 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 10.980ns (logic 0.668ns (6.084%) route 10.312ns (93.916%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.301ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.273ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.199 8.406 pll_clk.u_rst_mlkem/p_0_in + SLICE_X96Y101 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.555 -2.273 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X96Y101 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 10.561ns (logic 0.668ns (6.325%) route 9.893ns (93.675%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.297ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.780 7.987 pll_clk.u_rst_mlkem/p_0_in + SLICE_X92Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.551 -2.277 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.643ns (logic 0.668ns (10.055%) route 5.975ns (89.945%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.294ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 2.863 4.070 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in + SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.548 -2.280 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.643ns (logic 0.668ns (10.055%) route 5.975ns (89.945%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.294ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 2.863 4.070 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in + SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.548 -2.280 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.143ns (logic 0.612ns (53.534%) route 0.531ns (46.466%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/O + net (fo=1, routed) 0.531 0.756 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[36] + SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.059ns (logic 0.612ns (57.810%) route 0.447ns (42.190%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK + SLICE_X44Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.447 0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24] + SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.002ns (logic 0.595ns (59.409%) route 0.407ns (40.591%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.208 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.407 0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[7] + SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.994ns (logic 0.612ns (61.564%) route 0.382ns (38.436%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.617ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y97 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/O + net (fo=1, routed) 0.382 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[48] + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.982ns (logic 0.612ns (62.344%) route 0.370ns (37.656%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.384ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/O + net (fo=1, routed) 0.370 0.597 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[0] + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.966ns (logic 0.612ns (63.335%) route 0.354ns (36.665%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.611ns + Source Clock Delay (SCD): -0.380ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/WCLK + SLICE_X56Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.232 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/O + net (fo=1, routed) 0.354 0.586 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[36] + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.963ns (logic 0.491ns (50.975%) route 0.472ns (49.025%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.384ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.107 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O + net (fo=1, routed) 0.472 0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2] + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.957ns (logic 0.595ns (62.185%) route 0.362ns (37.815%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.617ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/O + net (fo=1, routed) 0.362 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[13] + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.957ns (logic 0.482ns (50.382%) route 0.475ns (49.618%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.617ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O + net (fo=1, routed) 0.475 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15] + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.954ns (logic 0.482ns (50.537%) route 0.472ns (49.463%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.095 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/O + net (fo=1, routed) 0.472 0.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[9] + SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.940ns (logic 0.595ns (63.287%) route 0.345ns (36.713%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK + SLICE_X44Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 0.345 0.551 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[1] + SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.935ns (logic 0.612ns (65.444%) route 0.323ns (34.556%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/O + net (fo=1, routed) 0.323 0.550 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[12] + SLICE_X67Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X67Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.927ns (logic 0.595ns (64.162%) route 0.332ns (35.838%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK + SLICE_X44Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 0.332 0.539 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25] + SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.925ns (logic 0.595ns (64.303%) route 0.330ns (35.697%)) + Logic Levels: 0 + Clock Path Skew: -0.224ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.615ns + Source Clock Delay (SCD): -0.391ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK + SLICE_X46Y79 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.204 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 0.330 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[7] + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.919ns (logic 0.595ns (64.745%) route 0.324ns (35.255%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X64Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.324 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[7] + SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.908ns (logic 0.612ns (67.424%) route 0.296ns (32.576%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X70Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y98 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/O + net (fo=1, routed) 0.296 0.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[42] + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.629ns (logic 0.367ns (58.312%) route 0.262ns (41.688%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.112ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk + SLICE_X54Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y91 FDCE (Prop_fdce_C_Q) 0.367 -1.745 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.262 -1.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[2] + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.660ns (logic 0.337ns (51.055%) route 0.323ns (48.945%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.504ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk + SLICE_X51Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y83 FDCE (Prop_fdce_C_Q) 0.337 -1.780 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.323 -1.457 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.672ns (logic 0.385ns (57.253%) route 0.287ns (42.747%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.511ns + Source Clock Delay (SCD): -2.125ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.703 -2.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X74Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y96 FDCE (Prop_fdce_C_Q) 0.385 -1.740 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.287 -1.453 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.831 -2.511 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.673ns (logic 0.418ns (62.094%) route 0.255ns (37.906%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.506ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X68Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y92 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.255 -1.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[3] + SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.672ns (logic 0.367ns (54.616%) route 0.305ns (45.384%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.504ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk + SLICE_X51Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y83 FDCE (Prop_fdce_C_Q) 0.367 -1.750 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.305 -1.445 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[1] + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.680ns (logic 0.385ns (56.580%) route 0.295ns (43.420%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk + SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.385 -1.735 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/Q + net (fo=4, routed) 0.295 -1.440 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[3] + SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.722ns (logic 0.418ns (57.896%) route 0.304ns (42.104%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk + SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.304 -1.398 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[0] + SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.760ns (logic 0.385ns (50.673%) route 0.375ns (49.327%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.506ns + Source Clock Delay (SCD): -2.119ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X66Y93 FDCE (Prop_fdce_C_Q) 0.385 -1.734 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.375 -1.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[2] + SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.756ns (logic 0.367ns (48.571%) route 0.389ns (51.429%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.500ns + Source Clock Delay (SCD): -2.112ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk + SLICE_X54Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y91 FDCE (Prop_fdce_C_Q) 0.367 -1.745 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.389 -1.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[1] + SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.842 -2.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.784ns (logic 0.418ns (53.295%) route 0.366ns (46.705%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.505ns + Source Clock Delay (SCD): -2.119ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X66Y93 FDCE (Prop_fdce_C_Q) 0.418 -1.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/Q + net (fo=1, routed) 0.366 -1.335 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[1] + SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.837 -2.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.788ns (logic 0.367ns (46.589%) route 0.421ns (53.411%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.504ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk + SLICE_X51Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y83 FDCE (Prop_fdce_C_Q) 0.367 -1.750 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.421 -1.330 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[0] + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.801ns (logic 0.418ns (52.179%) route 0.383ns (47.821%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.511ns + Source Clock Delay (SCD): -2.125ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.703 -2.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X74Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y96 FDCE (Prop_fdce_C_Q) 0.418 -1.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.383 -1.324 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[1] + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.831 -2.511 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.794ns (logic 0.367ns (46.198%) route 0.427ns (53.802%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.112ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk + SLICE_X54Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y91 FDCE (Prop_fdce_C_Q) 0.367 -1.745 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.427 -1.318 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[0] + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.924ns (logic 0.418ns (45.244%) route 0.506ns (54.756%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk + SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=2, routed) 0.506 -1.196 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[2] + SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.948ns (logic 0.418ns (44.102%) route 0.530ns (55.898%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.513ns + Source Clock Delay (SCD): -2.125ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.703 -2.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X74Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y96 FDCE (Prop_fdce_C_Q) 0.418 -1.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.530 -1.177 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[0] + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.829 -2.513 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.961ns (logic 0.418ns (43.489%) route 0.543ns (56.511%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk + SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.543 -1.159 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[1] + SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.504ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK + SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.033 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/O + net (fo=1, routed) 0.162 -0.871 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[30] + SLICE_X49Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.314ns (logic 1.062ns (80.806%) route 0.252ns (19.194%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.119ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK + SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.057 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/O + net (fo=1, routed) 0.252 -0.805 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[21] + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.326ns (logic 0.418ns (31.525%) route 0.908ns (68.475%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.506ns + Source Clock Delay (SCD): -2.119ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X66Y93 FDCE (Prop_fdce_C_Q) 0.418 -1.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/Q + net (fo=1, routed) 0.908 -0.793 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[0] + SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.332ns (logic 1.062ns (79.740%) route 0.270ns (20.260%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.059 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/O + net (fo=1, routed) 0.270 -0.789 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[39] + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: cpu_clk + To Clock: sys_clk + +Max Delay 162 Endpoints +Min Delay 162 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.425ns (logic 0.485ns (34.039%) route 0.940ns (65.961%)) + Logic Levels: 0 + Clock Path Skew: -0.207ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.674ns + Source Clock Delay (SCD): -0.467ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK + SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.018 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/O + net (fo=1, routed) 0.940 0.958 u_Axi_CDC/awFifo/_zz_ram_port10[22] + SLICE_X52Y101 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.589 -0.674 u_Axi_CDC/awFifo/sys_clk + SLICE_X52Y101 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.308ns (logic 0.482ns (36.863%) route 0.826ns (63.137%)) + Logic Levels: 0 + Clock Path Skew: -0.204ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.681ns + Source Clock Delay (SCD): -0.477ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.005 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/O + net (fo=1, routed) 0.826 0.830 u_Axi_CDC/arFifo/_zz_ram_port10__1[9] + SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.582 -0.681 u_Axi_CDC/arFifo/sys_clk + SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.238ns (logic 0.485ns (39.176%) route 0.753ns (60.824%)) + Logic Levels: 0 + Clock Path Skew: -0.204ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.681ns + Source Clock Delay (SCD): -0.477ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.008 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/O + net (fo=1, routed) 0.753 0.761 u_Axi_CDC/arFifo/_zz_ram_port10__1[10] + SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.582 -0.681 u_Axi_CDC/arFifo/sys_clk + SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.212ns (logic 0.485ns (40.001%) route 0.727ns (59.999%)) + Logic Levels: 0 + Clock Path Skew: -0.150ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.608ns + Source Clock Delay (SCD): -0.458ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK + SLICE_X70Y105 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y105 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.027 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/O + net (fo=1, routed) 0.727 0.754 u_Axi_CDC/arFifo/_zz_ram_port10__1[22] + SLICE_X47Y95 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.654 -0.608 u_Axi_CDC/arFifo/sys_clk + SLICE_X47Y95 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.193ns (logic 0.612ns (51.321%) route 0.581ns (48.679%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.702ns + Source Clock Delay (SCD): -0.474ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK + SLICE_X88Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y128 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.138 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/O + net (fo=1, routed) 0.581 0.718 u_Axi_CDC/wFifo/_zz_ram_port10__0[18] + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.185ns (logic 0.612ns (51.630%) route 0.573ns (48.370%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.702ns + Source Clock Delay (SCD): -0.475ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.833 -0.475 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/WCLK + SLICE_X90Y125 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X90Y125 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.137 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/O + net (fo=1, routed) 0.573 0.710 u_Axi_CDC/wFifo/_zz_ram_port10__0[36] + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.173ns (logic 0.612ns (52.170%) route 0.561ns (47.830%)) + Logic Levels: 0 + Clock Path Skew: -0.233ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.700ns + Source Clock Delay (SCD): -0.467ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK + SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.145 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/O + net (fo=1, routed) 0.561 0.706 u_Axi_CDC/awFifo/_zz_ram_port10[18] + SLICE_X82Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.563 -0.700 u_Axi_CDC/awFifo/sys_clk + SLICE_X82Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.116ns (logic 0.482ns (43.203%) route 0.634ns (56.797%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.695ns + Source Clock Delay (SCD): -0.467ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK + SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.015 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/O + net (fo=1, routed) 0.634 0.648 u_Axi_CDC/awFifo/_zz_ram_port10[21] + SLICE_X81Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.568 -0.695 u_Axi_CDC/awFifo/sys_clk + SLICE_X81Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.100ns (logic 0.612ns (55.644%) route 0.488ns (44.356%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.698ns + Source Clock Delay (SCD): -0.467ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.145 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/O + net (fo=1, routed) 0.488 0.633 u_Axi_CDC/awFifo/_zz_ram_port10[6] + SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk + SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.080ns (logic 0.612ns (56.690%) route 0.468ns (43.310%)) + Logic Levels: 0 + Clock Path Skew: -0.233ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.698ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.843 -0.465 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK + SLICE_X90Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X90Y115 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.147 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/O + net (fo=1, routed) 0.468 0.614 u_Axi_CDC/awFifo/_zz_ram_port10[0] + SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk + SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.075ns (logic 0.485ns (45.122%) route 0.590ns (54.878%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.702ns + Source Clock Delay (SCD): -0.471ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK + SLICE_X90Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X90Y128 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.014 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/O + net (fo=1, routed) 0.590 0.604 u_Axi_CDC/wFifo/_zz_ram_port10__0[16] + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.070ns (logic 0.612ns (57.190%) route 0.458ns (42.810%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.696ns + Source Clock Delay (SCD): -0.471ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK + SLICE_X84Y109 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y109 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.141 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/O + net (fo=1, routed) 0.458 0.599 u_Axi_CDC/arFifo/_zz_ram_port10__1[24] + SLICE_X80Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.567 -0.696 u_Axi_CDC/arFifo/sys_clk + SLICE_X80Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.061ns (logic 0.491ns (46.270%) route 0.570ns (53.730%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.698ns + Source Clock Delay (SCD): -0.467ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.024 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/O + net (fo=1, routed) 0.570 0.594 u_Axi_CDC/awFifo/_zz_ram_port10[8] + SLICE_X82Y111 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk + SLICE_X82Y111 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.048ns (logic 0.595ns (56.753%) route 0.453ns (43.247%)) + Logic Levels: 0 + Clock Path Skew: -0.222ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.699ns + Source Clock Delay (SCD): -0.477ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.118 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.453 0.571 u_Axi_CDC/arFifo/_zz_ram_port10__1[7] + SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/arFifo/sys_clk + SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.024ns (logic 0.612ns (59.777%) route 0.412ns (40.223%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.680ns + Source Clock Delay (SCD): -0.455ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.853 -0.455 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.157 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/O + net (fo=1, routed) 0.412 0.569 u_Axi_CDC/awFifo/_zz_ram_port10[42] + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.583 -0.680 u_Axi_CDC/awFifo/sys_clk + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.025ns (logic 0.595ns (58.034%) route 0.430ns (41.966%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.703ns + Source Clock Delay (SCD): -0.472ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.836 -0.472 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK + SLICE_X88Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y130 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.123 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 0.430 0.553 u_Axi_CDC/wFifo/_zz_ram_port10__0[1] + SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk + SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.009ns (logic 0.612ns (60.640%) route 0.397ns (39.360%)) + Logic Levels: 0 + Clock Path Skew: -0.157ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.615ns + Source Clock Delay (SCD): -0.458ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK + SLICE_X70Y105 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y105 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.154 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/O + net (fo=1, routed) 0.397 0.551 u_Axi_CDC/arFifo/_zz_ram_port10__1[18] + SLICE_X66Y97 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.647 -0.615 u_Axi_CDC/arFifo/sys_clk + SLICE_X66Y97 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.006ns (logic 0.491ns (48.819%) route 0.515ns (51.181%)) + Logic Levels: 0 + Clock Path Skew: -0.222ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.699ns + Source Clock Delay (SCD): -0.477ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.014 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/O + net (fo=1, routed) 0.515 0.529 u_Axi_CDC/arFifo/_zz_ram_port10__1[8] + SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/arFifo/sys_clk + SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.992ns (logic 0.612ns (61.686%) route 0.380ns (38.314%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.703ns + Source Clock Delay (SCD): -0.472ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.836 -0.472 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK + SLICE_X88Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y130 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.140 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/O + net (fo=1, routed) 0.380 0.520 u_Axi_CDC/wFifo/_zz_ram_port10__0[0] + SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk + SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.990ns (logic 0.595ns (60.095%) route 0.395ns (39.905%)) + Logic Levels: 0 + Clock Path Skew: -0.234ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.705ns + Source Clock Delay (SCD): -0.471ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK + SLICE_X88Y131 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y131 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.124 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 0.395 0.519 u_Axi_CDC/wFifo/_zz_ram_port10__0[7] + SLICE_X82Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk + SLICE_X82Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.514ns (logic 0.367ns (71.372%) route 0.147ns (28.628%)) + Logic Levels: 0 + Clock Path Skew: -0.396ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.688ns + Source Clock Delay (SCD): -2.292ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/bFifo/cpu_clk + SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y122 FDCE (Prop_fdce_C_Q) 0.367 -1.925 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.147 -1.778 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[1] + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.654 -2.688 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.611ns (logic 0.337ns (55.112%) route 0.274ns (44.888%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.697ns + Source Clock Delay (SCD): -2.302ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y125 FDCE (Prop_fdce_C_Q) 0.337 -1.965 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/Q + net (fo=5, routed) 0.274 -1.690 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[3] + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.665ns (logic 0.385ns (57.882%) route 0.280ns (42.118%)) + Logic Levels: 0 + Clock Path Skew: -0.400ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.688ns + Source Clock Delay (SCD): -2.288ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.540 -2.288 u_Axi_CDC/bFifo/cpu_clk + SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X96Y122 FDCE (Prop_fdce_C_Q) 0.385 -1.903 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.280 -1.623 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[2] + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.654 -2.688 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.672ns (logic 0.418ns (62.186%) route 0.254ns (37.814%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.675ns + Source Clock Delay (SCD): -2.281ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.418 -1.863 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.254 -1.609 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[3] + SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.738ns (logic 0.337ns (45.657%) route 0.401ns (54.343%)) + Logic Levels: 0 + Clock Path Skew: -0.402ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.700ns + Source Clock Delay (SCD): -2.298ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 -2.298 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y105 FDCE (Prop_fdce_C_Q) 0.337 -1.961 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.401 -1.560 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.642 -2.700 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk + SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.779ns (logic 0.367ns (47.087%) route 0.412ns (52.913%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.697ns + Source Clock Delay (SCD): -2.302ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y125 FDCE (Prop_fdce_C_Q) 0.367 -1.935 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=3, routed) 0.412 -1.522 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[2] + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.781ns (logic 0.367ns (46.998%) route 0.414ns (53.002%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.697ns + Source Clock Delay (SCD): -2.302ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y125 FDCE (Prop_fdce_C_Q) 0.367 -1.935 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.414 -1.521 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[0] + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.792ns (logic 0.367ns (46.340%) route 0.425ns (53.660%)) + Logic Levels: 0 + Clock Path Skew: -0.396ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.688ns + Source Clock Delay (SCD): -2.292ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/bFifo/cpu_clk + SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y122 FDCE (Prop_fdce_C_Q) 0.367 -1.925 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.425 -1.500 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[0] + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.654 -2.688 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.791ns (logic 0.367ns (46.425%) route 0.424ns (53.575%)) + Logic Levels: 0 + Clock Path Skew: -0.393ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.676ns + Source Clock Delay (SCD): -2.283ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.545 -2.283 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X93Y113 FDCE (Prop_fdce_C_Q) 0.367 -1.916 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.424 -1.492 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[1] + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.790ns (logic 0.418ns (52.908%) route 0.372ns (47.092%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.676ns + Source Clock Delay (SCD): -2.281ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.418 -1.863 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/Q + net (fo=1, routed) 0.372 -1.491 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[1] + SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.793ns (logic 0.367ns (46.304%) route 0.426ns (53.696%)) + Logic Levels: 0 + Clock Path Skew: -0.392ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.675ns + Source Clock Delay (SCD): -2.283ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.545 -2.283 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X93Y113 FDCE (Prop_fdce_C_Q) 0.367 -1.916 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.426 -1.490 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[0] + SLICE_X92Y112 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y112 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.829ns (logic 0.418ns (50.441%) route 0.411ns (49.559%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.676ns + Source Clock Delay (SCD): -2.281ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.418 -1.863 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/Q + net (fo=1, routed) 0.411 -1.452 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[0] + SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.847ns (logic 0.367ns (43.340%) route 0.480ns (56.660%)) + Logic Levels: 0 + Clock Path Skew: -0.398ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.697ns + Source Clock Delay (SCD): -2.299ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.529 -2.299 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y127 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y127 FDCE (Prop_fdce_C_Q) 0.367 -1.932 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.480 -1.452 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[1] + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.870ns (logic 0.367ns (42.168%) route 0.503ns (57.832%)) + Logic Levels: 0 + Clock Path Skew: -0.402ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.700ns + Source Clock Delay (SCD): -2.298ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 -2.298 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y105 FDCE (Prop_fdce_C_Q) 0.367 -1.931 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.503 -1.428 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[1] + SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.642 -2.700 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk + SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.892ns (logic 0.367ns (41.125%) route 0.525ns (58.875%)) + Logic Levels: 0 + Clock Path Skew: -0.402ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.700ns + Source Clock Delay (SCD): -2.298ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 -2.298 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y105 FDCE (Prop_fdce_C_Q) 0.367 -1.931 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.525 -1.405 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[0] + SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.642 -2.700 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk + SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.974ns (logic 0.337ns (34.595%) route 0.637ns (65.405%)) + Logic Levels: 0 + Clock Path Skew: -0.393ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.676ns + Source Clock Delay (SCD): -2.283ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.545 -2.283 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X93Y113 FDCE (Prop_fdce_C_Q) 0.337 -1.946 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.637 -1.309 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.171ns (logic 0.385ns (32.864%) route 0.786ns (67.136%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.675ns + Source Clock Delay (SCD): -2.281ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.385 -1.896 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.786 -1.109 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[2] + SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.215ns (logic 1.056ns (86.901%) route 0.159ns (13.099%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.684ns + Source Clock Delay (SCD): -2.290ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.234 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.159 -1.075 u_Axi_CDC/awFifo/_zz_ram_port10[7] + SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.658 -2.684 u_Axi_CDC/awFifo/sys_clk + SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.221ns (logic 1.062ns (86.996%) route 0.159ns (13.004%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.669ns + Source Clock Delay (SCD): -2.275ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.553 -2.275 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X60Y100 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X60Y100 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.213 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/O + net (fo=1, routed) 0.159 -1.054 u_Axi_CDC/awFifo/_zz_ram_port10[33] + SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.673 -2.669 u_Axi_CDC/awFifo/sys_clk + SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.312ns (logic 1.062ns (80.930%) route 0.250ns (19.070%)) + Logic Levels: 0 + Clock Path Skew: -0.393ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.699ns + Source Clock Delay (SCD): -2.306ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.522 -2.306 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X84Y117 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y117 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.244 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/O + net (fo=1, routed) 0.250 -0.994 u_Axi_CDC/arFifo/_zz_ram_port10__1[15] + SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.643 -2.699 u_Axi_CDC/arFifo/sys_clk + SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: mlkem_clk + To Clock: sys_clk + +Max Delay 61 Endpoints +Min Delay 61 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 5.746ns (logic 0.642ns (11.174%) route 5.104ns (88.826%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.546ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.123ns + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 2.674 3.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1 + SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.705 -2.123 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C + +Slack: inf + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 5.746ns (logic 0.642ns (11.174%) route 5.104ns (88.826%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.546ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.123ns + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 2.674 3.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1 + SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.705 -2.123 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.364ns (logic 0.612ns (44.884%) route 0.752ns (55.116%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O + net (fo=1, routed) 0.752 0.977 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.284ns (logic 0.612ns (47.657%) route 0.672ns (52.343%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/O + net (fo=1, routed) 0.672 0.895 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[0] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.195ns (logic 0.595ns (49.811%) route 0.600ns (50.189%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 0.600 0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.183ns (logic 0.595ns (50.304%) route 0.588ns (49.696%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O + net (fo=1, routed) 0.588 0.797 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.169ns (logic 0.612ns (52.356%) route 0.557ns (47.644%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.612ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O + net (fo=1, routed) 0.557 0.780 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.167ns (logic 0.612ns (52.454%) route 0.555ns (47.546%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 0.555 0.779 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.166ns (logic 0.480ns (41.172%) route 0.686ns (58.828%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.092 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O + net (fo=1, routed) 0.686 0.778 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.160ns (logic 0.612ns (52.737%) route 0.548ns (47.263%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.548 0.771 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.139ns (logic 0.612ns (53.734%) route 0.527ns (46.266%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O + net (fo=1, routed) 0.527 0.750 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.128ns (logic 0.595ns (52.742%) route 0.533ns (47.258%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 0.533 0.739 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.122ns (logic 0.595ns (53.042%) route 0.527ns (46.958%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O + net (fo=1, routed) 0.527 0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.103ns (logic 0.482ns (43.685%) route 0.621ns (56.315%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O + net (fo=1, routed) 0.621 0.714 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.093ns (logic 0.485ns (44.377%) route 0.608ns (55.623%)) + Logic Levels: 0 + Clock Path Skew: -0.222ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O + net (fo=1, routed) 0.608 0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10] + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.073ns (logic 0.595ns (55.460%) route 0.478ns (44.540%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 0.478 0.684 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.071ns (logic 0.595ns (55.545%) route 0.476ns (44.455%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 0.476 0.682 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.064ns (logic 0.485ns (45.566%) route 0.579ns (54.434%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O + net (fo=1, routed) 0.579 0.675 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.051ns (logic 0.485ns (46.153%) route 0.566ns (53.847%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O + net (fo=1, routed) 0.566 0.662 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.028ns (logic 0.485ns (47.163%) route 0.543ns (52.837%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O + net (fo=1, routed) 0.543 0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.636ns (logic 0.367ns (57.746%) route 0.269ns (42.254%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.367 -1.755 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.269 -1.487 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0] + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.633ns (logic 0.367ns (57.963%) route 0.266ns (42.037%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.499ns + Source Clock Delay (SCD): -2.113ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.715 -2.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk + SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.266 -1.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[1] + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.637ns (logic 0.367ns (57.593%) route 0.270ns (42.407%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.367 -1.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.270 -1.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0] + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.682ns (logic 0.418ns (61.266%) route 0.264ns (38.734%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.514ns + Source Clock Delay (SCD): -2.127ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.701 -2.127 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y97 FDCE (Prop_fdce_C_Q) 0.418 -1.709 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.264 -1.445 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2] + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.828 -2.514 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.684ns (logic 0.418ns (61.086%) route 0.266ns (38.914%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.514ns + Source Clock Delay (SCD): -2.127ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.701 -2.127 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y97 FDCE (Prop_fdce_C_Q) 0.418 -1.709 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.266 -1.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[1] + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.828 -2.514 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.730ns (logic 0.337ns (46.159%) route 0.393ns (53.841%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.499ns + Source Clock Delay (SCD): -2.113ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.715 -2.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk + SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.337 -1.776 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.393 -1.383 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.750ns (logic 0.367ns (48.935%) route 0.383ns (51.065%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.367 -1.755 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=3, routed) 0.383 -1.372 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[2] + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.770ns (logic 0.367ns (47.632%) route 0.403ns (52.368%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.367 -1.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/Q + net (fo=1, routed) 0.403 -1.350 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[1] + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.776ns (logic 0.337ns (43.419%) route 0.439ns (56.581%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.337 -1.785 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q + net (fo=5, routed) 0.439 -1.346 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3] + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.792ns (logic 0.367ns (46.358%) route 0.425ns (53.642%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.367 -1.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.425 -1.324 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2] + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.837ns (logic 0.418ns (49.937%) route 0.419ns (50.063%)) + Logic Levels: 0 + Clock Path Skew: -0.391ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.514ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X72Y96 FDCE (Prop_fdce_C_Q) 0.418 -1.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.419 -1.285 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.828 -2.514 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.844ns (logic 0.367ns (43.474%) route 0.477ns (56.526%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.367 -1.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/Q + net (fo=1, routed) 0.477 -1.276 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[0] + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.848ns (logic 0.337ns (39.750%) route 0.511ns (60.250%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.337 -1.783 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.511 -1.272 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.044ns (logic 0.367ns (35.163%) route 0.677ns (64.837%)) + Logic Levels: 0 + Clock Path Skew: -0.393ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.670ns + Source Clock Delay (SCD): -2.277ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.551 -2.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X93Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X93Y102 FDCE (Prop_fdce_C_Q) 0.367 -1.910 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q + net (fo=2, routed) 0.677 -1.233 u_fft_mlkem_axi_slave/mlkem_intr_m + SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.672 -2.670 u_fft_mlkem_axi_slave/sys_clk + SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.902ns (logic 0.367ns (40.694%) route 0.535ns (59.306%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.367 -1.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.535 -1.218 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[3] + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.908ns (logic 0.367ns (40.413%) route 0.541ns (59.587%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.367 -1.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.541 -1.207 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[1] + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.925ns (logic 0.367ns (39.693%) route 0.558ns (60.307%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.499ns + Source Clock Delay (SCD): -2.113ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.715 -2.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk + SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.558 -1.189 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.985ns (logic 0.367ns (37.277%) route 0.618ns (62.723%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.367 -1.755 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.618 -1.138 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.240ns (logic 1.078ns (86.936%) route 0.162ns (13.064%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.112ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK + SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y90 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.034 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O + net (fo=1, routed) 0.162 -0.872 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] + SLICE_X53Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk + SLICE_X53Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.467ns (logic 1.062ns (72.369%) route 0.405ns (27.631%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.502ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.055 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O + net (fo=1, routed) 0.405 -0.650 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clkfbout_clk_pll + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT + (clock source 'clkfbout_clk_pll' {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN + Path Group: (none) + Path Type: Max at Fast Process Corner + Data Path Delay: 1.519ns (logic 0.029ns (1.909%) route 1.490ns (98.091%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.225ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.110ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkfbout_clk_pll fall edge) + 10.000 10.000 f + K21 0.000 10.000 f clk (IN) + net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 f pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 10.419 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 10.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + -2.847 8.053 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT + net (fo=1, routed) 0.611 8.663 pll_clk.u_clk_pll/inst/clkfbout_clk_pll + BUFGCTRL_X0Y19 f pll_clk.u_clk_pll/inst/clkf_buf/I + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.029 8.692 f pll_clk.u_clk_pll/inst/clkf_buf/O + net (fo=1, routed) 0.880 9.572 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT + (clock source 'clkfbout_clk_pll' {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 3.498ns (logic 0.091ns (2.602%) route 3.407ns (97.398%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.225ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.110ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkfbout_clk_pll rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/clkfbout_clk_pll + BUFGCTRL_X0Y19 r pll_clk.u_clk_pll/inst/clkf_buf/I + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkf_buf/O + net (fo=1, routed) 1.652 -2.177 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: sys_clk + To Clock: + +Max Delay 41 Endpoints +Min Delay 41 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: u_axi_dvi/DVI_SQU_DIR_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[0] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 15.825ns (logic 6.208ns (39.226%) route 9.618ns (60.774%)) + Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_axi_dvi/sys_clk + SLICE_X42Y81 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.989 r u_axi_dvi/DVI_SQU_DIR_reg[0]/Q + net (fo=5, routed) 1.348 -0.641 u_axi_dvi/DVI_SQU_DIR_reg_n_0_[0] + SLICE_X42Y84 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/I0 + SLICE_X42Y84 LUT2 (Prop_lut2_I0_O) 0.124 -0.517 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/O + net (fo=1, routed) 0.000 -0.517 u_axi_dvi/video_red_OBUF[2]_inst_i_264_n_0 + SLICE_X42Y84 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/S[0] + SLICE_X42Y84 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 -0.004 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/CO[3] + net (fo=1, routed) 0.000 -0.004 u_axi_dvi/video_red_OBUF[2]_inst_i_225_n_0 + SLICE_X42Y85 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CI + SLICE_X42Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 0.113 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CO[3] + net (fo=1, routed) 0.000 0.113 u_axi_dvi/video_red_OBUF[2]_inst_i_165_n_0 + SLICE_X42Y86 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/CI + SLICE_X42Y86 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 0.436 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/O[1] + net (fo=1, routed) 1.222 1.658 u_axi_dvi/video_red_OBUF[2]_inst_i_96_n_6 + SLICE_X42Y82 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/I1 + SLICE_X42Y82 LUT2 (Prop_lut2_I1_O) 0.306 1.964 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/O + net (fo=1, routed) 0.000 1.964 u_axi_dvi/video_red_OBUF[2]_inst_i_38_n_0 + SLICE_X42Y82 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/S[1] + SLICE_X42Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 2.497 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/CO[3] + net (fo=1, routed) 0.000 2.497 u_axi_dvi/video_red_OBUF[2]_inst_i_7_n_0 + SLICE_X42Y83 r u_axi_dvi/video_red_OBUF[2]_inst_i_2/CI + SLICE_X42Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 2.614 f u_axi_dvi/video_red_OBUF[2]_inst_i_2/CO[3] + net (fo=1, routed) 1.354 3.969 u_axi_dvi/video_red_OBUF[2]_inst_i_2_n_0 + SLICE_X41Y85 f u_axi_dvi/video_red_OBUF[2]_inst_i_1/I0 + SLICE_X41Y85 LUT5 (Prop_lut5_I0_O) 0.124 4.093 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 5.693 9.786 video_red_OBUF[0] + K23 r video_red_OBUF[0]_inst/I + K23 OBUF (Prop_obuf_I_O) 3.533 13.319 r video_red_OBUF[0]_inst/O + net (fo=0) 0.000 13.319 video_red[0] + K23 r video_red[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/DVI_SQU_DIR_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[1] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 15.712ns (logic 6.235ns (39.686%) route 9.476ns (60.314%)) + Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_axi_dvi/sys_clk + SLICE_X42Y81 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.989 r u_axi_dvi/DVI_SQU_DIR_reg[0]/Q + net (fo=5, routed) 1.348 -0.641 u_axi_dvi/DVI_SQU_DIR_reg_n_0_[0] + SLICE_X42Y84 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/I0 + SLICE_X42Y84 LUT2 (Prop_lut2_I0_O) 0.124 -0.517 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/O + net (fo=1, routed) 0.000 -0.517 u_axi_dvi/video_red_OBUF[2]_inst_i_264_n_0 + SLICE_X42Y84 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/S[0] + SLICE_X42Y84 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 -0.004 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/CO[3] + net (fo=1, routed) 0.000 -0.004 u_axi_dvi/video_red_OBUF[2]_inst_i_225_n_0 + SLICE_X42Y85 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CI + SLICE_X42Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 0.113 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CO[3] + net (fo=1, routed) 0.000 0.113 u_axi_dvi/video_red_OBUF[2]_inst_i_165_n_0 + SLICE_X42Y86 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/CI + SLICE_X42Y86 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 0.436 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/O[1] + net (fo=1, routed) 1.222 1.658 u_axi_dvi/video_red_OBUF[2]_inst_i_96_n_6 + SLICE_X42Y82 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/I1 + SLICE_X42Y82 LUT2 (Prop_lut2_I1_O) 0.306 1.964 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/O + net (fo=1, routed) 0.000 1.964 u_axi_dvi/video_red_OBUF[2]_inst_i_38_n_0 + SLICE_X42Y82 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/S[1] + SLICE_X42Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 2.497 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/CO[3] + net (fo=1, routed) 0.000 2.497 u_axi_dvi/video_red_OBUF[2]_inst_i_7_n_0 + SLICE_X42Y83 r u_axi_dvi/video_red_OBUF[2]_inst_i_2/CI + SLICE_X42Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 2.614 f u_axi_dvi/video_red_OBUF[2]_inst_i_2/CO[3] + net (fo=1, routed) 1.354 3.969 u_axi_dvi/video_red_OBUF[2]_inst_i_2_n_0 + SLICE_X41Y85 f u_axi_dvi/video_red_OBUF[2]_inst_i_1/I0 + SLICE_X41Y85 LUT5 (Prop_lut5_I0_O) 0.124 4.093 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 5.552 9.645 video_red_OBUF[0] + F24 r video_red_OBUF[1]_inst/I + F24 OBUF (Prop_obuf_I_O) 3.560 13.205 r video_red_OBUF[1]_inst/O + net (fo=0) 0.000 13.205 video_red[1] + F24 r video_red[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/DVI_SQU_DIR_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 15.445ns (logic 6.262ns (40.541%) route 9.183ns (59.459%)) + Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_axi_dvi/sys_clk + SLICE_X42Y81 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.989 r u_axi_dvi/DVI_SQU_DIR_reg[0]/Q + net (fo=5, routed) 1.348 -0.641 u_axi_dvi/DVI_SQU_DIR_reg_n_0_[0] + SLICE_X42Y84 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/I0 + SLICE_X42Y84 LUT2 (Prop_lut2_I0_O) 0.124 -0.517 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/O + net (fo=1, routed) 0.000 -0.517 u_axi_dvi/video_red_OBUF[2]_inst_i_264_n_0 + SLICE_X42Y84 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/S[0] + SLICE_X42Y84 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 -0.004 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/CO[3] + net (fo=1, routed) 0.000 -0.004 u_axi_dvi/video_red_OBUF[2]_inst_i_225_n_0 + SLICE_X42Y85 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CI + SLICE_X42Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 0.113 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CO[3] + net (fo=1, routed) 0.000 0.113 u_axi_dvi/video_red_OBUF[2]_inst_i_165_n_0 + SLICE_X42Y86 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/CI + SLICE_X42Y86 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 0.436 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/O[1] + net (fo=1, routed) 1.222 1.658 u_axi_dvi/video_red_OBUF[2]_inst_i_96_n_6 + SLICE_X42Y82 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/I1 + SLICE_X42Y82 LUT2 (Prop_lut2_I1_O) 0.306 1.964 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/O + net (fo=1, routed) 0.000 1.964 u_axi_dvi/video_red_OBUF[2]_inst_i_38_n_0 + SLICE_X42Y82 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/S[1] + SLICE_X42Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 2.497 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/CO[3] + net (fo=1, routed) 0.000 2.497 u_axi_dvi/video_red_OBUF[2]_inst_i_7_n_0 + SLICE_X42Y83 r u_axi_dvi/video_red_OBUF[2]_inst_i_2/CI + SLICE_X42Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 2.614 f u_axi_dvi/video_red_OBUF[2]_inst_i_2/CO[3] + net (fo=1, routed) 1.354 3.969 u_axi_dvi/video_red_OBUF[2]_inst_i_2_n_0 + SLICE_X41Y85 f u_axi_dvi/video_red_OBUF[2]_inst_i_1/I0 + SLICE_X41Y85 LUT5 (Prop_lut5_I0_O) 0.124 4.093 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 5.259 9.352 video_red_OBUF[0] + E26 r video_red_OBUF[2]_inst/I + E26 OBUF (Prop_obuf_I_O) 3.587 12.938 r video_red_OBUF[2]_inst/O + net (fo=0) 0.000 12.938 video_red[2] + E26 r video_red[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_clk + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.589ns (logic 3.629ns (42.252%) route 4.960ns (57.748%)) + Logic Levels: 2 (BUFG=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk fall edge) 10.000 10.000 f + K21 0.000 10.000 f clk (IN) + net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 f pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 11.463 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 12.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 3.725 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 5.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 f pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 5.658 f pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 3.123 8.781 video_clk_OBUF + H22 f video_clk_OBUF_inst/I + H22 OBUF (Prop_obuf_I_O) 3.533 12.314 f video_clk_OBUF_inst/O + net (fo=0) 0.000 12.314 video_clk + H22 f video_clk (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/vdata_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_vsync + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 12.805ns (logic 4.379ns (34.194%) route 8.427ns (65.806%)) + Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.838 -2.504 u_axi_dvi/sys_clk + SLICE_X47Y82 FDRE r u_axi_dvi/vdata_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y82 FDRE (Prop_fdre_C_Q) 0.456 -2.048 f u_axi_dvi/vdata_reg[6]/Q + net (fo=13, routed) 1.558 -0.490 u_axi_dvi/vdata_reg_n_0_[6] + SLICE_X49Y83 f u_axi_dvi/video_vsync_OBUF_inst_i_5/I1 + SLICE_X49Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.366 f u_axi_dvi/video_vsync_OBUF_inst_i_5/O + net (fo=1, routed) 0.667 0.301 u_axi_dvi/video_vsync_OBUF_inst_i_5_n_0 + SLICE_X49Y83 f u_axi_dvi/video_vsync_OBUF_inst_i_3/I5 + SLICE_X49Y83 LUT6 (Prop_lut6_I5_O) 0.124 0.425 r u_axi_dvi/video_vsync_OBUF_inst_i_3/O + net (fo=1, routed) 0.298 0.723 u_axi_dvi/video_vsync_OBUF_inst_i_3_n_0 + SLICE_X49Y81 r u_axi_dvi/video_vsync_OBUF_inst_i_1/I2 + SLICE_X49Y81 LUT4 (Prop_lut4_I2_O) 0.124 0.847 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O + net (fo=1, routed) 5.904 6.751 video_vsync_OBUF + H24 r video_vsync_OBUF_inst/I + H24 OBUF (Prop_obuf_I_O) 3.551 10.302 r video_vsync_OBUF_inst/O + net (fo=0) 0.000 10.302 video_vsync + H24 r video_vsync (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/vdata_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_de + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 12.756ns (logic 4.389ns (34.405%) route 8.367ns (65.595%)) + Logic Levels: 4 (LUT2=1 LUT6=2 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.836 -2.506 u_axi_dvi/sys_clk + SLICE_X47Y81 FDRE r u_axi_dvi/vdata_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y81 FDRE (Prop_fdre_C_Q) 0.456 -2.050 f u_axi_dvi/vdata_reg[3]/Q + net (fo=11, routed) 1.027 -1.023 u_axi_dvi/vdata_reg_n_0_[3] + SLICE_X48Y83 f u_axi_dvi/vdata[11]_i_4/I0 + SLICE_X48Y83 LUT2 (Prop_lut2_I0_O) 0.124 -0.899 r u_axi_dvi/vdata[11]_i_4/O + net (fo=3, routed) 0.717 -0.182 u_axi_dvi/vdata[11]_i_4_n_0 + SLICE_X49Y83 r u_axi_dvi/video_de_OBUF_inst_i_2/I2 + SLICE_X49Y83 LUT6 (Prop_lut6_I2_O) 0.124 -0.058 r u_axi_dvi/video_de_OBUF_inst_i_2/O + net (fo=1, routed) 0.863 0.805 u_axi_dvi/video_de_OBUF_inst_i_2_n_0 + SLICE_X46Y83 r u_axi_dvi/video_de_OBUF_inst_i_1/I0 + SLICE_X46Y83 LUT6 (Prop_lut6_I0_O) 0.124 0.929 r u_axi_dvi/video_de_OBUF_inst_i_1/O + net (fo=1, routed) 5.761 6.690 video_de_OBUF + G24 r video_de_OBUF_inst/I + G24 OBUF (Prop_obuf_I_O) 3.561 10.251 r video_de_OBUF_inst/O + net (fo=0) 0.000 10.251 video_de + G24 r video_de (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/hdata_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_hsync + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 11.845ns (logic 4.311ns (36.394%) route 7.534ns (63.606%)) + Logic Levels: 3 (LUT5=2 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.840 -2.502 u_axi_dvi/sys_clk + SLICE_X46Y84 FDRE r u_axi_dvi/hdata_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X46Y84 FDRE (Prop_fdre_C_Q) 0.518 -1.984 r u_axi_dvi/hdata_reg[4]/Q + net (fo=11, routed) 1.550 -0.433 u_axi_dvi/hdata_reg_n_0_[4] + SLICE_X41Y85 r u_axi_dvi/video_hsync_OBUF_inst_i_2/I4 + SLICE_X41Y85 LUT5 (Prop_lut5_I4_O) 0.124 -0.309 f u_axi_dvi/video_hsync_OBUF_inst_i_2/O + net (fo=1, routed) 0.291 -0.018 u_axi_dvi/video_hsync_OBUF_inst_i_2_n_0 + SLICE_X41Y86 f u_axi_dvi/video_hsync_OBUF_inst_i_1/I4 + SLICE_X41Y86 LUT5 (Prop_lut5_I4_O) 0.124 0.106 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O + net (fo=1, routed) 5.693 5.799 video_hsync_OBUF + J24 r video_hsync_OBUF_inst/I + J24 OBUF (Prop_obuf_I_O) 3.545 9.343 r video_hsync_OBUF_inst/O + net (fo=0) 0.000 9.343 video_hsync + J24 r video_hsync (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[6] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.827ns (logic 4.074ns (37.631%) route 6.753ns (62.369%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q + net (fo=1, routed) 6.753 4.594 dpy0_OBUF[6] + B17 r dpy0_OBUF[6]_inst/I + B17 OBUF (Prop_obuf_I_O) 3.556 8.151 r dpy0_OBUF[6]_inst/O + net (fo=0) 0.000 8.151 dpy0[6] + B17 r dpy0[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: UART_TX + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.830ns (logic 4.317ns (39.866%) route 6.513ns (60.134%)) + Logic Levels: 2 (LUT3=1 OBUFT=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.638 -2.704 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X80Y133 FDRE r u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y133 FDRE (Prop_fdre_C_Q) 0.478 -2.226 f u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/Q + net (fo=13, routed) 1.393 -0.832 u_axi_uart_controller/uart0/regs/transmitter/tf_pop_reg_0[1] + SLICE_X77Y137 f u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/I1 + SLICE_X77Y137 LUT3 (Prop_lut3_I1_O) 0.295 -0.537 f u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O + net (fo=1, routed) 5.119 4.582 UART_TX_IOBUF_inst/T + H18 f UART_TX_IOBUF_inst/OBUFT/T + H18 OBUFT (TriStatE_obuft_T_O) + 3.544 8.126 r UART_TX_IOBUF_inst/OBUFT/O + net (fo=1, unset) 0.000 8.126 UART_TX + H18 r UART_TX (INOUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[7] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.564ns (logic 4.063ns (38.456%) route 6.502ns (61.544%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q + net (fo=1, routed) 6.502 4.343 dpy0_OBUF[7] + C17 r dpy0_OBUF[7]_inst/I + C17 OBUF (Prop_obuf_I_O) 3.545 7.888 r dpy0_OBUF[7]_inst/O + net (fo=0) 0.000 7.888 dpy0[7] + C17 r dpy0[7] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[4] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.495ns (logic 4.057ns (38.657%) route 6.438ns (61.343%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q + net (fo=1, routed) 6.438 4.280 dpy0_OBUF[4] + E18 r dpy0_OBUF[4]_inst/I + E18 OBUF (Prop_obuf_I_O) 3.539 7.819 r dpy0_OBUF[4]_inst/O + net (fo=0) 0.000 7.819 dpy0[4] + E18 r dpy0[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: UART_RX + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.517ns (logic 4.100ns (38.989%) route 6.416ns (61.011%)) + Logic Levels: 2 (LUT2=1 OBUFT=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.643 -2.699 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X85Y134 FDRE r u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X85Y134 FDRE (Prop_fdre_C_Q) 0.456 -2.243 r u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/Q + net (fo=2, routed) 0.810 -1.433 u_axi_uart_controller/uart0/regs/sclk_por + SLICE_X86Y135 r u_axi_uart_controller/uart0/regs/UART_RX_IOBUF_inst_i_1/I1 + SLICE_X86Y135 LUT2 (Prop_lut2_I1_O) 0.124 -1.309 r u_axi_uart_controller/uart0/regs/UART_RX_IOBUF_inst_i_1/O + net (fo=1, routed) 5.607 4.298 UART_RX_IOBUF_inst/I + J20 r UART_RX_IOBUF_inst/OBUFT/I + J20 OBUFT (Prop_obuft_I_O) 3.520 7.818 r UART_RX_IOBUF_inst/OBUFT/O + net (fo=1, unset) 0.000 7.818 UART_RX + J20 r UART_RX (INOUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[0] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.196ns (logic 4.016ns (39.389%) route 6.180ns (60.611%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.666 -2.676 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X63Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X63Y141 FDCE (Prop_fdce_C_Q) 0.456 -2.220 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q + net (fo=1, routed) 6.180 3.960 dpy0_OBUF[0] + B19 r dpy0_OBUF[0]_inst/I + B19 OBUF (Prop_obuf_I_O) 3.560 7.520 r dpy0_OBUF[0]_inst/O + net (fo=0) 0.000 7.520 dpy0[0] + B19 r dpy0[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[7] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.115ns (logic 4.038ns (39.923%) route 6.077ns (60.077%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q + net (fo=1, routed) 6.077 3.899 dpy1_OBUF[7] + G17 r dpy1_OBUF[7]_inst/I + G17 OBUF (Prop_obuf_I_O) 3.520 7.419 r dpy1_OBUF[7]_inst/O + net (fo=0) 0.000 7.419 dpy1[7] + G17 r dpy1[7] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[5] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.022ns (logic 4.002ns (39.929%) route 6.021ns (60.071%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q + net (fo=1, routed) 6.021 3.800 dpy0_OBUF[5] + C19 r dpy0_OBUF[5]_inst/I + C19 OBUF (Prop_obuf_I_O) 3.546 7.346 r dpy0_OBUF[5]_inst/O + net (fo=0) 0.000 7.346 dpy0[5] + C19 r dpy0[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[3] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.920ns (logic 4.091ns (41.241%) route 5.829ns (58.759%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q + net (fo=1, routed) 5.829 3.670 dpy0_OBUF[3] + A19 r dpy0_OBUF[3]_inst/I + A19 OBUF (Prop_obuf_I_O) 3.573 7.243 r dpy0_OBUF[3]_inst/O + net (fo=0) 0.000 7.243 dpy0[3] + A19 r dpy0[3] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[3] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.911ns (logic 4.032ns (40.684%) route 5.879ns (59.316%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q + net (fo=1, routed) 5.879 3.701 dpy1_OBUF[3] + F17 r dpy1_OBUF[3]_inst/I + F17 OBUF (Prop_obuf_I_O) 3.514 7.215 r dpy1_OBUF[3]_inst/O + net (fo=0) 0.000 7.215 dpy1[3] + F17 r dpy1[3] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[6] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.858ns (logic 4.055ns (41.135%) route 5.803ns (58.865%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.644 -2.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.518 -2.180 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q + net (fo=1, routed) 5.803 3.623 dpy1_OBUF[6] + F15 r dpy1_OBUF[6]_inst/I + F15 OBUF (Prop_obuf_I_O) 3.537 7.160 r dpy1_OBUF[6]_inst/O + net (fo=0) 0.000 7.160 dpy1[6] + F15 r dpy1[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[5] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.779ns (logic 4.052ns (41.435%) route 5.727ns (58.565%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.644 -2.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.518 -2.180 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q + net (fo=1, routed) 5.727 3.547 dpy1_OBUF[5] + G16 r dpy1_OBUF[5]_inst/I + G16 OBUF (Prop_obuf_I_O) 3.534 7.081 r dpy1_OBUF[5]_inst/O + net (fo=0) 0.000 7.081 dpy1[5] + G16 r dpy1[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[4] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.775ns (logic 4.060ns (41.529%) route 5.716ns (58.471%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q + net (fo=1, routed) 5.716 3.538 dpy1_OBUF[4] + E16 r dpy1_OBUF[4]_inst/I + E16 OBUF (Prop_obuf_I_O) 3.542 7.079 r dpy1_OBUF[4]_inst/O + net (fo=0) 0.000 7.079 dpy1[4] + E16 r dpy1[4] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_clk + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.614ns (logic 1.260ns (48.196%) route 1.354ns (51.804%)) + Logic Levels: 2 (BUFG=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.794 -0.468 video_clk_OBUF + H22 r video_clk_OBUF_inst/I + H22 OBUF (Prop_obuf_I_O) 1.234 0.766 r video_clk_OBUF_inst/O + net (fo=0) 0.000 0.766 video_clk + H22 r video_clk (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[9]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[9] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.581ns (logic 1.447ns (56.055%) route 1.134ns (43.945%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X14Y141 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X14Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[9]_lopt_replica/Q + net (fo=1, routed) 1.134 0.663 lopt_15 + A23 r leds_OBUF[9]_inst/I + A23 OBUF (Prop_obuf_I_O) 1.283 1.946 r leds_OBUF[9]_inst/O + net (fo=0) 0.000 1.946 leds[9] + A23 r leds[9] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[15]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[15] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.597ns (logic 1.427ns (54.964%) route 1.170ns (45.036%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X12Y142 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[15]_lopt_replica/Q + net (fo=1, routed) 1.170 0.699 lopt_6 + B20 r leds_OBUF[15]_inst/I + B20 OBUF (Prop_obuf_I_O) 1.263 1.962 r leds_OBUF[15]_inst/O + net (fo=0) 0.000 1.962 leds[15] + B20 r leds[15] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[10]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[10] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.666ns (logic 1.412ns (52.947%) route 1.255ns (47.053%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk + SLICE_X20Y141 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X20Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[10]_lopt_replica/Q + net (fo=1, routed) 1.255 0.781 lopt_1 + D21 r leds_OBUF[10]_inst/I + D21 OBUF (Prop_obuf_I_O) 1.248 2.028 r leds_OBUF[10]_inst/O + net (fo=0) 0.000 2.028 leds[10] + D21 r leds[10] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[12]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[12] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.709ns (logic 1.384ns (51.091%) route 1.325ns (48.909%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X13Y142 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y142 FDRE (Prop_fdre_C_Q) 0.141 -0.494 r u_confreg/led_data_reg[12]_lopt_replica/Q + net (fo=1, routed) 1.325 0.831 lopt_3 + D20 r leds_OBUF[12]_inst/I + D20 OBUF (Prop_obuf_I_O) 1.243 2.074 r leds_OBUF[12]_inst/O + net (fo=0) 0.000 2.074 leds[12] + D20 r leds[12] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[0]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[0] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.736ns (logic 1.439ns (52.603%) route 1.297ns (47.397%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk + SLICE_X22Y141 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[0]_lopt_replica/Q + net (fo=1, routed) 1.297 0.823 lopt + B24 r leds_OBUF[0]_inst/I + B24 OBUF (Prop_obuf_I_O) 1.275 2.098 r leds_OBUF[0]_inst/O + net (fo=0) 0.000 2.098 leds[0] + B24 r leds[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[11]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[11] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.765ns (logic 1.431ns (51.772%) route 1.333ns (48.228%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X12Y141 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[11]_lopt_replica/Q + net (fo=1, routed) 1.333 0.862 lopt_2 + A18 r leds_OBUF[11]_inst/I + A18 OBUF (Prop_obuf_I_O) 1.267 2.130 r leds_OBUF[11]_inst/O + net (fo=0) 0.000 2.130 leds[11] + A18 r leds[11] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[1]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.956ns (logic 1.406ns (47.555%) route 1.550ns (52.445%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X12Y142 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[1]_lopt_replica/Q + net (fo=1, routed) 1.550 1.079 lopt_7 + E21 r leds_OBUF[1]_inst/I + E21 OBUF (Prop_obuf_I_O) 1.242 2.321 r leds_OBUF[1]_inst/O + net (fo=0) 0.000 2.321 leds[1] + E21 r leds[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[13]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[13] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.031ns (logic 1.412ns (46.583%) route 1.619ns (53.417%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X13Y142 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y142 FDRE (Prop_fdre_C_Q) 0.141 -0.494 r u_confreg/led_data_reg[13]_lopt_replica/Q + net (fo=1, routed) 1.619 1.125 lopt_4 + A22 r leds_OBUF[13]_inst/I + A22 OBUF (Prop_obuf_I_O) 1.271 2.396 r leds_OBUF[13]_inst/O + net (fo=0) 0.000 2.396 leds[13] + A22 r leds[13] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[5]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[5] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.069ns (logic 1.418ns (46.208%) route 1.651ns (53.792%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk + SLICE_X20Y141 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X20Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[5]_lopt_replica/Q + net (fo=1, routed) 1.651 1.177 lopt_11 + C21 r leds_OBUF[5]_inst/I + C21 OBUF (Prop_obuf_I_O) 1.254 2.431 r leds_OBUF[5]_inst/O + net (fo=0) 0.000 2.431 leds[5] + C21 r leds[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[3]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[3] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.092ns (logic 1.427ns (46.147%) route 1.665ns (53.853%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.617 -0.646 u_confreg/sys_clk + SLICE_X36Y141 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X36Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.482 r u_confreg/led_data_reg[3]_lopt_replica/Q + net (fo=1, routed) 1.665 1.183 lopt_9 + D23 r leds_OBUF[3]_inst/I + D23 OBUF (Prop_obuf_I_O) 1.263 2.446 r leds_OBUF[3]_inst/O + net (fo=0) 0.000 2.446 leds[3] + D23 r leds[3] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[8]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[8] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.086ns (logic 1.426ns (46.198%) route 1.660ns (53.802%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk + SLICE_X22Y141 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[8]_lopt_replica/Q + net (fo=1, routed) 1.660 1.186 lopt_14 + C23 r leds_OBUF[8]_inst/I + C23 OBUF (Prop_obuf_I_O) 1.262 2.448 r leds_OBUF[8]_inst/O + net (fo=0) 0.000 2.448 leds[8] + C23 r leds[8] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[4]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[4] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.088ns (logic 1.427ns (46.209%) route 1.661ns (53.791%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk + SLICE_X22Y141 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[4]_lopt_replica/Q + net (fo=1, routed) 1.661 1.187 lopt_10 + C22 r leds_OBUF[4]_inst/I + C22 OBUF (Prop_obuf_I_O) 1.263 2.450 r leds_OBUF[4]_inst/O + net (fo=0) 0.000 2.450 leds[4] + C22 r leds[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[7]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[7] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.095ns (logic 1.437ns (46.407%) route 1.659ns (53.593%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X12Y142 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[7]_lopt_replica/Q + net (fo=1, routed) 1.659 1.188 lopt_13 + B22 r leds_OBUF[7]_inst/I + B22 OBUF (Prop_obuf_I_O) 1.273 2.461 r leds_OBUF[7]_inst/O + net (fo=0) 0.000 2.461 leds[7] + B22 r leds[7] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[6]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[6] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.132ns (logic 1.406ns (44.897%) route 1.726ns (55.103%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X12Y142 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[6]_lopt_replica/Q + net (fo=1, routed) 1.726 1.255 lopt_12 + E20 r leds_OBUF[6]_inst/I + E20 OBUF (Prop_obuf_I_O) 1.242 2.497 r leds_OBUF[6]_inst/O + net (fo=0) 0.000 2.497 leds[6] + E20 r leds[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[14]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[14] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.179ns (logic 1.427ns (44.902%) route 1.752ns (55.098%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk + SLICE_X22Y141 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[14]_lopt_replica/Q + net (fo=1, routed) 1.752 1.278 lopt_5 + A20 r leds_OBUF[14]_inst/I + A20 OBUF (Prop_obuf_I_O) 1.263 2.541 r leds_OBUF[14]_inst/O + net (fo=0) 0.000 2.541 leds[14] + A20 r leds[14] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[2]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[2] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.213ns (logic 1.451ns (45.157%) route 1.762ns (54.843%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.617 -0.646 u_confreg/sys_clk + SLICE_X36Y140 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X36Y140 FDRE (Prop_fdre_C_Q) 0.164 -0.482 r u_confreg/led_data_reg[2]_lopt_replica/Q + net (fo=1, routed) 1.762 1.280 lopt_8 + A24 r leds_OBUF[2]_inst/I + A24 OBUF (Prop_obuf_I_O) 1.287 2.567 r leds_OBUF[2]_inst/O + net (fo=0) 0.000 2.567 leds[2] + A24 r leds[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: UART_TX + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.463ns (logic 1.033ns (29.825%) route 2.430ns (70.175%)) + Logic Levels: 2 (LUT3=1 OBUFT=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.572 -0.691 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X76Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y137 FDRE (Prop_fdre_C_Q) 0.164 -0.527 r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/Q + net (fo=2, routed) 0.147 -0.380 u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en + SLICE_X77Y137 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/I0 + SLICE_X77Y137 LUT3 (Prop_lut3_I0_O) 0.045 -0.335 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O + net (fo=1, routed) 2.283 1.949 UART_TX_IOBUF_inst/T + H18 r UART_TX_IOBUF_inst/OBUFT/T + H18 OBUFT (TriStatD_obuft_T_O) + 0.824 2.773 r UART_TX_IOBUF_inst/OBUFT/O + net (fo=1, unset) 0.000 2.773 UART_TX + H18 r UART_TX (INOUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[2] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.498ns (logic 1.406ns (40.207%) route 2.091ns (59.793%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q + net (fo=1, routed) 2.091 1.566 dpy1_OBUF[2] + E17 r dpy1_OBUF[2]_inst/I + E17 OBUF (Prop_obuf_I_O) 1.242 2.808 r dpy1_OBUF[2]_inst/O + net (fo=0) 0.000 2.808 dpy1[2] + E17 r dpy1[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.553ns (logic 1.387ns (39.035%) route 2.166ns (60.965%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q + net (fo=1, routed) 2.166 1.625 dpy0_OBUF[1] + D19 r dpy0_OBUF[1]_inst/I + D19 OBUF (Prop_obuf_I_O) 1.246 2.871 r dpy0_OBUF[1]_inst/O + net (fo=0) 0.000 2.871 dpy0[1] + D19 r dpy0[1] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: sys_clk + +Max Delay 43 Endpoints +Min Delay 43 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: dip_sw[22] + (input port) + Destination: u_confreg/s_rdata_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.330ns (logic 1.710ns (20.531%) route 6.620ns (79.469%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.277ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P6 0.000 0.000 r dip_sw[22] (IN) + net (fo=0) 0.000 0.000 dip_sw[22] + P6 r dip_sw_IBUF[22]_inst/I + P6 IBUF (Prop_ibuf_I_O) 1.462 1.462 r dip_sw_IBUF[22]_inst/O + net (fo=1, routed) 5.658 7.120 u_confreg/dip_sw_IBUF[22] + SLICE_X58Y140 r u_confreg/s_rdata[22]_i_4/I4 + SLICE_X58Y140 LUT5 (Prop_lut5_I4_O) 0.124 7.244 r u_confreg/s_rdata[22]_i_4/O + net (fo=1, routed) 0.963 8.206 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 + SLICE_X52Y140 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/I4 + SLICE_X52Y140 LUT6 (Prop_lut6_I4_O) 0.124 8.330 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O + net (fo=1, routed) 0.000 8.330 u_confreg/u_int_ctrl_n_9 + SLICE_X52Y140 FDRE r u_confreg/s_rdata_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.551 -2.277 u_confreg/sys_clk + SLICE_X52Y140 FDRE r u_confreg/s_rdata_reg[22]/C + +Slack: inf + Source: dip_sw[29] + (input port) + Destination: u_confreg/s_rdata_reg[29]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.156ns (logic 1.726ns (21.164%) route 6.430ns (78.836%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.278ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T5 0.000 0.000 r dip_sw[29] (IN) + net (fo=0) 0.000 0.000 dip_sw[29] + T5 r dip_sw_IBUF[29]_inst/I + T5 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[29]_inst/O + net (fo=1, routed) 5.466 6.944 u_confreg/dip_sw_IBUF[29] + SLICE_X60Y139 r u_confreg/s_rdata[29]_i_4/I4 + SLICE_X60Y139 LUT5 (Prop_lut5_I4_O) 0.124 7.068 r u_confreg/s_rdata[29]_i_4/O + net (fo=1, routed) 0.963 8.032 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 + SLICE_X57Y140 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/I4 + SLICE_X57Y140 LUT6 (Prop_lut6_I4_O) 0.124 8.156 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O + net (fo=1, routed) 0.000 8.156 u_confreg/u_int_ctrl_n_2 + SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[29]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk + SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[29]/C + +Slack: inf + Source: dip_sw[19] + (input port) + Destination: u_confreg/s_rdata_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.100ns (logic 1.726ns (21.311%) route 6.374ns (78.689%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L4 0.000 0.000 r dip_sw[19] (IN) + net (fo=0) 0.000 0.000 dip_sw[19] + L4 r dip_sw_IBUF[19]_inst/I + L4 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[19]_inst/O + net (fo=1, routed) 5.423 6.901 u_confreg/dip_sw_IBUF[19] + SLICE_X54Y136 r u_confreg/s_rdata[19]_i_4/I4 + SLICE_X54Y136 LUT5 (Prop_lut5_I4_O) 0.124 7.025 r u_confreg/s_rdata[19]_i_4/O + net (fo=1, routed) 0.951 7.976 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 + SLICE_X48Y135 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/I4 + SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.124 8.100 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O + net (fo=1, routed) 0.000 8.100 u_confreg/u_int_ctrl_n_12 + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[19]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.928ns (logic 1.980ns (24.979%) route 5.948ns (75.021%)) + Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) + Clock Path Skew: -2.306ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.306ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 f UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 f UART_TX_IOBUF_inst/IBUF/I + H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 5.067 6.541 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X79Y136 f u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/I1 + SLICE_X79Y136 LUT2 (Prop_lut2_I1_O) 0.152 6.693 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O + net (fo=2, routed) 0.881 7.574 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 + SLICE_X78Y136 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/I1 + SLICE_X78Y136 LUT5 (Prop_lut5_I1_O) 0.354 7.928 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O + net (fo=1, routed) 0.000 7.928 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 + SLICE_X78Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.522 -2.306 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X78Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C + +Slack: inf + Source: dip_sw[14] + (input port) + Destination: u_confreg/s_rdata_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.857ns (logic 1.763ns (22.438%) route 6.094ns (77.562%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + J1 0.000 0.000 r dip_sw[14] (IN) + net (fo=0) 0.000 0.000 dip_sw[14] + J1 r dip_sw_IBUF[14]_inst/I + J1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r dip_sw_IBUF[14]_inst/O + net (fo=1, routed) 4.730 6.245 u_confreg/dip_sw_IBUF[14] + SLICE_X62Y135 r u_confreg/s_rdata[14]_i_4/I4 + SLICE_X62Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.369 r u_confreg/s_rdata[14]_i_4/O + net (fo=1, routed) 1.365 7.733 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 + SLICE_X49Y135 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/I4 + SLICE_X49Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.857 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O + net (fo=1, routed) 0.000 7.857 u_confreg/u_int_ctrl_n_17 + SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[14]/C + +Slack: inf + Source: dip_sw[27] + (input port) + Destination: u_confreg/s_rdata_reg[27]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.823ns (logic 1.753ns (22.406%) route 6.070ns (77.594%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R1 0.000 0.000 r dip_sw[27] (IN) + net (fo=0) 0.000 0.000 dip_sw[27] + R1 r dip_sw_IBUF[27]_inst/I + R1 IBUF (Prop_ibuf_I_O) 1.505 1.505 r dip_sw_IBUF[27]_inst/O + net (fo=1, routed) 4.956 6.461 u_confreg/dip_sw_IBUF[27] + SLICE_X61Y135 r u_confreg/s_rdata[27]_i_4/I4 + SLICE_X61Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.585 r u_confreg/s_rdata[27]_i_4/O + net (fo=1, routed) 1.114 7.699 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 + SLICE_X50Y137 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/I4 + SLICE_X50Y137 LUT6 (Prop_lut6_I4_O) 0.124 7.823 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O + net (fo=1, routed) 0.000 7.823 u_confreg/u_int_ctrl_n_4 + SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[27]/C + +Slack: inf + Source: dip_sw[15] + (input port) + Destination: u_confreg/s_rdata_reg[15]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.701ns (logic 1.742ns (22.623%) route 5.959ns (77.377%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L2 0.000 0.000 r dip_sw[15] (IN) + net (fo=0) 0.000 0.000 dip_sw[15] + L2 r dip_sw_IBUF[15]_inst/I + L2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[15]_inst/O + net (fo=1, routed) 5.004 6.498 u_confreg/dip_sw_IBUF[15] + SLICE_X58Y135 r u_confreg/s_rdata[15]_i_4/I4 + SLICE_X58Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.622 r u_confreg/s_rdata[15]_i_4/O + net (fo=1, routed) 0.955 7.577 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 + SLICE_X49Y135 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/I4 + SLICE_X49Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.701 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O + net (fo=1, routed) 0.000 7.701 u_confreg/u_int_ctrl_n_16 + SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[15]/C + +Slack: inf + Source: dip_sw[7] + (input port) + Destination: u_confreg/s_rdata_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.567ns (logic 1.719ns (22.721%) route 5.848ns (77.279%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.286ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.286ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N6 0.000 0.000 r dip_sw[7] (IN) + net (fo=0) 0.000 0.000 dip_sw[7] + N6 r dip_sw_IBUF[7]_inst/I + N6 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[7]_inst/O + net (fo=1, routed) 4.586 6.058 u_confreg/dip_sw_IBUF[7] + SLICE_X66Y139 r u_confreg/s_rdata[7]_i_4/I4 + SLICE_X66Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.182 r u_confreg/s_rdata[7]_i_4/O + net (fo=1, routed) 1.261 7.443 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 + SLICE_X56Y131 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/I4 + SLICE_X56Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.567 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O + net (fo=1, routed) 0.000 7.567 u_confreg/u_int_ctrl_n_24 + SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk + SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[7]/C + +Slack: inf + Source: dip_sw[12] + (input port) + Destination: u_confreg/s_rdata_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.550ns (logic 1.717ns (22.743%) route 5.833ns (77.257%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M5 0.000 0.000 r dip_sw[12] (IN) + net (fo=0) 0.000 0.000 dip_sw[12] + M5 r dip_sw_IBUF[12]_inst/I + M5 IBUF (Prop_ibuf_I_O) 1.469 1.469 r dip_sw_IBUF[12]_inst/O + net (fo=1, routed) 4.809 6.278 u_confreg/dip_sw_IBUF[12] + SLICE_X59Y137 r u_confreg/s_rdata[12]_i_4/I4 + SLICE_X59Y137 LUT5 (Prop_lut5_I4_O) 0.124 6.402 r u_confreg/s_rdata[12]_i_4/O + net (fo=1, routed) 1.024 7.426 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 + SLICE_X48Y135 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/I4 + SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.550 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O + net (fo=1, routed) 0.000 7.550 u_confreg/u_int_ctrl_n_19 + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[12]/C + +Slack: inf + Source: dip_sw[16] + (input port) + Destination: u_confreg/s_rdata_reg[16]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.532ns (logic 1.748ns (23.209%) route 5.784ns (76.791%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K2 0.000 0.000 r dip_sw[16] (IN) + net (fo=0) 0.000 0.000 dip_sw[16] + K2 r dip_sw_IBUF[16]_inst/I + K2 IBUF (Prop_ibuf_I_O) 1.500 1.500 r dip_sw_IBUF[16]_inst/O + net (fo=1, routed) 4.874 6.374 u_confreg/dip_sw_IBUF[16] + SLICE_X62Y135 r u_confreg/s_rdata[16]_i_4/I4 + SLICE_X62Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.498 r u_confreg/s_rdata[16]_i_4/O + net (fo=1, routed) 0.910 7.408 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 + SLICE_X48Y135 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/I4 + SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.532 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O + net (fo=1, routed) 0.000 7.532 u_confreg/u_int_ctrl_n_15 + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[16]/C + +Slack: inf + Source: dip_sw[25] + (input port) + Destination: u_confreg/s_rdata_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.498ns (logic 1.737ns (23.169%) route 5.761ns (76.831%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.278ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R3 0.000 0.000 r dip_sw[25] (IN) + net (fo=0) 0.000 0.000 dip_sw[25] + R3 r dip_sw_IBUF[25]_inst/I + R3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[25]_inst/O + net (fo=1, routed) 5.036 6.525 u_confreg/dip_sw_IBUF[25] + SLICE_X55Y138 r u_confreg/s_rdata[25]_i_4/I4 + SLICE_X55Y138 LUT5 (Prop_lut5_I4_O) 0.124 6.649 r u_confreg/s_rdata[25]_i_4/O + net (fo=1, routed) 0.725 7.374 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 + SLICE_X51Y138 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/I4 + SLICE_X51Y138 LUT6 (Prop_lut6_I4_O) 0.124 7.498 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O + net (fo=1, routed) 0.000 7.498 u_confreg/u_int_ctrl_n_6 + SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk + SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[25]/C + +Slack: inf + Source: dip_sw[24] + (input port) + Destination: u_confreg/s_rdata_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.497ns (logic 1.714ns (22.868%) route 5.783ns (77.132%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.277ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P5 0.000 0.000 r dip_sw[24] (IN) + net (fo=0) 0.000 0.000 dip_sw[24] + P5 r dip_sw_IBUF[24]_inst/I + P5 IBUF (Prop_ibuf_I_O) 1.466 1.466 r dip_sw_IBUF[24]_inst/O + net (fo=1, routed) 5.182 6.648 u_confreg/dip_sw_IBUF[24] + SLICE_X55Y139 r u_confreg/s_rdata[24]_i_4/I4 + SLICE_X55Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.772 r u_confreg/s_rdata[24]_i_4/O + net (fo=1, routed) 0.601 7.373 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 + SLICE_X52Y139 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/I4 + SLICE_X52Y139 LUT6 (Prop_lut6_I4_O) 0.124 7.497 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O + net (fo=1, routed) 0.000 7.497 u_confreg/u_int_ctrl_n_7 + SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.551 -2.277 u_confreg/sys_clk + SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[24]/C + +Slack: inf + Source: dip_sw[4] + (input port) + Destination: u_confreg/s_rdata_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.485ns (logic 1.736ns (23.197%) route 5.748ns (76.803%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.281ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P4 0.000 0.000 r dip_sw[4] (IN) + net (fo=0) 0.000 0.000 dip_sw[4] + P4 r dip_sw_IBUF[4]_inst/I + P4 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[4]_inst/O + net (fo=1, routed) 4.844 6.332 u_confreg/dip_sw_IBUF[4] + SLICE_X63Y134 r u_confreg/s_rdata[4]_i_4/I4 + SLICE_X63Y134 LUT5 (Prop_lut5_I4_O) 0.124 6.456 r u_confreg/s_rdata[4]_i_4/O + net (fo=1, routed) 0.904 7.361 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 + SLICE_X55Y135 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/I4 + SLICE_X55Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.485 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O + net (fo=1, routed) 0.000 7.485 u_confreg/u_int_ctrl_n_27 + SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.547 -2.281 u_confreg/sys_clk + SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[4]/C + +Slack: inf + Source: dip_sw[8] + (input port) + Destination: u_confreg/s_rdata_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.481ns (logic 1.724ns (23.040%) route 5.758ns (76.960%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.286ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.286ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M6 0.000 0.000 r dip_sw[8] (IN) + net (fo=0) 0.000 0.000 dip_sw[8] + M6 r dip_sw_IBUF[8]_inst/I + M6 IBUF (Prop_ibuf_I_O) 1.476 1.476 r dip_sw_IBUF[8]_inst/O + net (fo=1, routed) 4.998 6.474 u_confreg/dip_sw_IBUF[8] + SLICE_X61Y135 r u_confreg/s_rdata[8]_i_4/I4 + SLICE_X61Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.598 r u_confreg/s_rdata[8]_i_4/O + net (fo=1, routed) 0.760 7.357 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 + SLICE_X59Y131 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/I4 + SLICE_X59Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.481 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O + net (fo=1, routed) 0.000 7.481 u_confreg/u_int_ctrl_n_23 + SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk + SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[8]/C + +Slack: inf + Source: dip_sw[20] + (input port) + Destination: u_confreg/s_rdata_reg[20]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.437ns (logic 1.723ns (23.170%) route 5.714ns (76.830%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.278ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M4 0.000 0.000 r dip_sw[20] (IN) + net (fo=0) 0.000 0.000 dip_sw[20] + M4 r dip_sw_IBUF[20]_inst/I + M4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r dip_sw_IBUF[20]_inst/O + net (fo=1, routed) 4.743 6.219 u_confreg/dip_sw_IBUF[20] + SLICE_X54Y140 r u_confreg/s_rdata[20]_i_4/I4 + SLICE_X54Y140 LUT5 (Prop_lut5_I4_O) 0.124 6.343 r u_confreg/s_rdata[20]_i_4/O + net (fo=1, routed) 0.970 7.313 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 + SLICE_X50Y138 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/I4 + SLICE_X50Y138 LUT6 (Prop_lut6_I4_O) 0.124 7.437 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O + net (fo=1, routed) 0.000 7.437 u_confreg/u_int_ctrl_n_11 + SLICE_X50Y138 FDRE r u_confreg/s_rdata_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk + SLICE_X50Y138 FDRE r u_confreg/s_rdata_reg[20]/C + +Slack: inf + Source: dip_sw[6] + (input port) + Destination: u_confreg/s_rdata_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.429ns (logic 1.736ns (23.368%) route 5.693ns (76.632%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.284ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L3 0.000 0.000 r dip_sw[6] (IN) + net (fo=0) 0.000 0.000 dip_sw[6] + L3 r dip_sw_IBUF[6]_inst/I + L3 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[6]_inst/O + net (fo=1, routed) 4.696 6.184 u_confreg/dip_sw_IBUF[6] + SLICE_X65Y134 r u_confreg/s_rdata[6]_i_4/I4 + SLICE_X65Y134 LUT5 (Prop_lut5_I4_O) 0.124 6.308 r u_confreg/s_rdata[6]_i_4/O + net (fo=1, routed) 0.997 7.305 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 + SLICE_X57Y132 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/I4 + SLICE_X57Y132 LUT6 (Prop_lut6_I4_O) 0.124 7.429 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O + net (fo=1, routed) 0.000 7.429 u_confreg/u_int_ctrl_n_25 + SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.544 -2.284 u_confreg/sys_clk + SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[6]/C + +Slack: inf + Source: dip_sw[13] + (input port) + Destination: u_confreg/s_rdata_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.400ns (logic 1.734ns (23.431%) route 5.666ns (76.569%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.283ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.283ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K3 0.000 0.000 r dip_sw[13] (IN) + net (fo=0) 0.000 0.000 dip_sw[13] + K3 r dip_sw_IBUF[13]_inst/I + K3 IBUF (Prop_ibuf_I_O) 1.486 1.486 r dip_sw_IBUF[13]_inst/O + net (fo=1, routed) 5.048 6.534 u_confreg/dip_sw_IBUF[13] + SLICE_X58Y139 r u_confreg/s_rdata[13]_i_4/I4 + SLICE_X58Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.658 r u_confreg/s_rdata[13]_i_4/O + net (fo=1, routed) 0.618 7.276 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 + SLICE_X57Y133 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/I4 + SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.124 7.400 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O + net (fo=1, routed) 0.000 7.400 u_confreg/u_int_ctrl_n_18 + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.545 -2.283 u_confreg/sys_clk + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[13]/C + +Slack: inf + Source: dip_sw[21] + (input port) + Destination: u_confreg/s_rdata_reg[21]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.324ns (logic 1.736ns (23.706%) route 5.588ns (76.294%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.278ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N2 0.000 0.000 r dip_sw[21] (IN) + net (fo=0) 0.000 0.000 dip_sw[21] + N2 r dip_sw_IBUF[21]_inst/I + N2 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[21]_inst/O + net (fo=1, routed) 5.103 6.592 u_confreg/dip_sw_IBUF[21] + SLICE_X57Y138 r u_confreg/s_rdata[21]_i_4/I4 + SLICE_X57Y138 LUT5 (Prop_lut5_I4_O) 0.124 6.716 r u_confreg/s_rdata[21]_i_4/O + net (fo=1, routed) 0.484 7.200 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 + SLICE_X51Y138 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/I4 + SLICE_X51Y138 LUT6 (Prop_lut6_I4_O) 0.124 7.324 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O + net (fo=1, routed) 0.000 7.324 u_confreg/u_int_ctrl_n_10 + SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk + SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[21]/C + +Slack: inf + Source: dip_sw[2] + (input port) + Destination: u_confreg/s_rdata_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.267ns (logic 1.743ns (23.989%) route 5.524ns (76.011%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.286ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.286ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M2 0.000 0.000 r dip_sw[2] (IN) + net (fo=0) 0.000 0.000 dip_sw[2] + M2 r dip_sw_IBUF[2]_inst/I + M2 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[2]_inst/O + net (fo=1, routed) 4.493 5.988 u_confreg/dip_sw_IBUF[2] + SLICE_X66Y131 r u_confreg/s_rdata[2]_i_4/I4 + SLICE_X66Y131 LUT5 (Prop_lut5_I4_O) 0.124 6.112 r u_confreg/s_rdata[2]_i_4/O + net (fo=1, routed) 1.030 7.143 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 + SLICE_X56Y131 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/I4 + SLICE_X56Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.267 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O + net (fo=1, routed) 0.000 7.267 u_confreg/u_int_ctrl_n_29 + SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk + SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[2]/C + +Slack: inf + Source: dip_sw[0] + (input port) + Destination: u_confreg/s_rdata_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.201ns (logic 1.743ns (24.206%) route 5.458ns (75.794%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.283ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.283ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T3 0.000 0.000 r dip_sw[0] (IN) + net (fo=0) 0.000 0.000 dip_sw[0] + T3 r dip_sw_IBUF[0]_inst/I + T3 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[0]_inst/O + net (fo=1, routed) 4.700 6.196 u_confreg/dip_sw_IBUF[0] + SLICE_X62Y133 r u_confreg/s_rdata[0]_i_4/I4 + SLICE_X62Y133 LUT5 (Prop_lut5_I4_O) 0.124 6.320 r u_confreg/s_rdata[0]_i_4/O + net (fo=1, routed) 0.758 7.077 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 + SLICE_X60Y133 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/I4 + SLICE_X60Y133 LUT6 (Prop_lut6_I4_O) 0.124 7.201 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O + net (fo=1, routed) 0.000 7.201 u_confreg/u_int_ctrl_n_31 + SLICE_X60Y133 FDRE r u_confreg/s_rdata_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.545 -2.283 u_confreg/sys_clk + SLICE_X60Y133 FDRE r u_confreg/s_rdata_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED + (internal pin) + Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.811ns (logic 0.045ns (2.485%) route 1.766ns (97.515%)) + Logic Levels: 1 (LUT1=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED + net (fo=1, routed) 1.592 1.592 pll_clk.u_rst_sys/locked + SLICE_X22Y139 r pll_clk.u_rst_sys/delay[1]_i_1/I0 + SLICE_X22Y139 LUT1 (Prop_lut1_I0_O) 0.045 1.637 f pll_clk.u_rst_sys/delay[1]_i_1/O + net (fo=2, routed) 0.174 1.811 pll_clk.u_rst_sys/delay[1]_i_1_n_0 + SLICE_X22Y139 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.896 -0.412 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C + +Slack: inf + Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED + (internal pin) + Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.811ns (logic 0.045ns (2.485%) route 1.766ns (97.515%)) + Logic Levels: 1 (LUT1=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED + net (fo=1, routed) 1.592 1.592 pll_clk.u_rst_sys/locked + SLICE_X22Y139 r pll_clk.u_rst_sys/delay[1]_i_1/I0 + SLICE_X22Y139 LUT1 (Prop_lut1_I0_O) 0.045 1.637 f pll_clk.u_rst_sys/delay[1]_i_1/O + net (fo=2, routed) 0.174 1.811 pll_clk.u_rst_sys/delay[1]_i_1_n_0 + SLICE_X22Y139 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.896 -0.412 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + +Slack: inf + Source: dip_sw[31] + (input port) + Destination: u_confreg/s_rdata_reg[31]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.161ns (logic 0.351ns (16.258%) route 1.810ns (83.742%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.454ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.454ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R2 0.000 0.000 r dip_sw[31] (IN) + net (fo=0) 0.000 0.000 dip_sw[31] + R2 r dip_sw_IBUF[31]_inst/I + R2 IBUF (Prop_ibuf_I_O) 0.261 0.261 r dip_sw_IBUF[31]_inst/O + net (fo=1, routed) 1.699 1.960 u_confreg/dip_sw_IBUF[31] + SLICE_X59Y137 r u_confreg/s_rdata[31]_i_6/I4 + SLICE_X59Y137 LUT5 (Prop_lut5_I4_O) 0.045 2.005 r u_confreg/s_rdata[31]_i_6/O + net (fo=1, routed) 0.111 2.116 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 + SLICE_X57Y137 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/I4 + SLICE_X57Y137 LUT6 (Prop_lut6_I4_O) 0.045 2.161 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O + net (fo=1, routed) 0.000 2.161 u_confreg/u_int_ctrl_n_0 + SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk + SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[31]/C + +Slack: inf + Source: dip_sw[23] + (input port) + Destination: u_confreg/s_rdata_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.220ns (logic 0.376ns (16.930%) route 1.845ns (83.070%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.452ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N1 0.000 0.000 r dip_sw[23] (IN) + net (fo=0) 0.000 0.000 dip_sw[23] + N1 r dip_sw_IBUF[23]_inst/I + N1 IBUF (Prop_ibuf_I_O) 0.286 0.286 r dip_sw_IBUF[23]_inst/O + net (fo=1, routed) 1.603 1.889 u_confreg/dip_sw_IBUF[23] + SLICE_X51Y139 r u_confreg/s_rdata[23]_i_4/I4 + SLICE_X51Y139 LUT5 (Prop_lut5_I4_O) 0.045 1.934 r u_confreg/s_rdata[23]_i_4/O + net (fo=1, routed) 0.241 2.175 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 + SLICE_X50Y139 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/I4 + SLICE_X50Y139 LUT6 (Prop_lut6_I4_O) 0.045 2.220 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O + net (fo=1, routed) 0.000 2.220 u_confreg/u_int_ctrl_n_8 + SLICE_X50Y139 FDRE r u_confreg/s_rdata_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk + SLICE_X50Y139 FDRE r u_confreg/s_rdata_reg[23]/C + +Slack: inf + Source: touch_btn[1] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.242ns (logic 0.283ns (12.603%) route 1.959ns (87.397%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.465ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.465ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M1 0.000 0.000 r touch_btn[1] (IN) + net (fo=0) 0.000 0.000 touch_btn[1] + M1 r touch_btn_IBUF[1]_inst/I + M1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r touch_btn_IBUF[1]_inst/O + net (fo=1, routed) 1.959 2.242 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] + SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.843 -0.465 u_confreg/u_int_ctrl/sys_clk + SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.295ns (logic 0.287ns (12.514%) route 2.008ns (87.486%)) + Logic Levels: 2 (IBUF=1 LUT5=1) + Clock Path Skew: -0.466ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.466ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 f UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 f UART_TX_IOBUF_inst/IBUF/I + H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 2.008 2.250 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF + SLICE_X77Y137 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/I2 + SLICE_X77Y137 LUT5 (Prop_lut5_I2_O) 0.045 2.295 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O + net (fo=1, routed) 0.000 2.295 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 + SLICE_X77Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.842 -0.466 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X77Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C + +Slack: inf + Source: dip_sw[28] + (input port) + Destination: u_confreg/s_rdata_reg[28]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.315ns (logic 0.326ns (14.065%) route 1.989ns (85.935%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.452ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R5 0.000 0.000 r dip_sw[28] (IN) + net (fo=0) 0.000 0.000 dip_sw[28] + R5 r dip_sw_IBUF[28]_inst/I + R5 IBUF (Prop_ibuf_I_O) 0.236 0.236 r dip_sw_IBUF[28]_inst/O + net (fo=1, routed) 1.643 1.878 u_confreg/dip_sw_IBUF[28] + SLICE_X59Y139 r u_confreg/s_rdata[28]_i_4/I4 + SLICE_X59Y139 LUT5 (Prop_lut5_I4_O) 0.045 1.923 r u_confreg/s_rdata[28]_i_4/O + net (fo=1, routed) 0.346 2.270 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 + SLICE_X52Y139 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/I4 + SLICE_X52Y139 LUT6 (Prop_lut6_I4_O) 0.045 2.315 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O + net (fo=1, routed) 0.000 2.315 u_confreg/u_int_ctrl_n_3 + SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk + SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[28]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D + (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.347ns (logic 0.287ns (12.237%) route 2.060ns (87.763%)) + Logic Levels: 2 (IBUF=1 LUT4=1) + Clock Path Skew: -0.466ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.466ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 r UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 r UART_TX_IOBUF_inst/IBUF/I + H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 2.060 2.302 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_TX_IBUF + SLICE_X77Y137 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/I2 + SLICE_X77Y137 LUT4 (Prop_lut4_I2_O) 0.045 2.347 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O + net (fo=1, routed) 0.000 2.347 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i + SLICE_X77Y137 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.842 -0.466 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk + SLICE_X77Y137 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C + +Slack: inf + Source: dip_sw[17] + (input port) + Destination: u_confreg/s_rdata_reg[17]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.367ns (logic 0.362ns (15.281%) route 2.005ns (84.719%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.455ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.455ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K1 0.000 0.000 r dip_sw[17] (IN) + net (fo=0) 0.000 0.000 dip_sw[17] + K1 r dip_sw_IBUF[17]_inst/I + K1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[17]_inst/O + net (fo=1, routed) 1.744 2.015 u_confreg/dip_sw_IBUF[17] + SLICE_X56Y136 r u_confreg/s_rdata[17]_i_4/I4 + SLICE_X56Y136 LUT5 (Prop_lut5_I4_O) 0.045 2.060 r u_confreg/s_rdata[17]_i_4/O + net (fo=1, routed) 0.262 2.322 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 + SLICE_X49Y136 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/I4 + SLICE_X49Y136 LUT6 (Prop_lut6_I4_O) 0.045 2.367 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O + net (fo=1, routed) 0.000 2.367 u_confreg/u_int_ctrl_n_14 + SLICE_X49Y136 FDRE r u_confreg/s_rdata_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk + SLICE_X49Y136 FDRE r u_confreg/s_rdata_reg[17]/C + +Slack: inf + Source: touch_btn[2] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.371ns (logic 0.255ns (10.737%) route 2.117ns (89.263%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.462ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.462ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P3 0.000 0.000 r touch_btn[2] (IN) + net (fo=0) 0.000 0.000 touch_btn[2] + P3 r touch_btn_IBUF[2]_inst/I + P3 IBUF (Prop_ibuf_I_O) 0.255 0.255 r touch_btn_IBUF[2]_inst/O + net (fo=1, routed) 2.117 2.371 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] + SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.846 -0.462 u_confreg/u_int_ctrl/sys_clk + SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C + +Slack: inf + Source: dip_sw[11] + (input port) + Destination: u_confreg/s_rdata_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.379ns (logic 0.329ns (13.836%) route 2.050ns (86.164%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.457ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.457ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L7 0.000 0.000 r dip_sw[11] (IN) + net (fo=0) 0.000 0.000 dip_sw[11] + L7 r dip_sw_IBUF[11]_inst/I + L7 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[11]_inst/O + net (fo=1, routed) 1.819 2.059 u_confreg/dip_sw_IBUF[11] + SLICE_X60Y139 r u_confreg/s_rdata[11]_i_4/I4 + SLICE_X60Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.104 r u_confreg/s_rdata[11]_i_4/O + net (fo=1, routed) 0.230 2.334 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 + SLICE_X57Y133 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/I4 + SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.045 2.379 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O + net (fo=1, routed) 0.000 2.379 u_confreg/u_int_ctrl_n_20 + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.851 -0.457 u_confreg/sys_clk + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[11]/C + +Slack: inf + Source: dip_sw[9] + (input port) + Destination: u_confreg/s_rdata_reg[9]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.511ns (logic 0.328ns (13.048%) route 2.184ns (86.952%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.458ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N7 0.000 0.000 r dip_sw[9] (IN) + net (fo=0) 0.000 0.000 dip_sw[9] + N7 r dip_sw_IBUF[9]_inst/I + N7 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[9]_inst/O + net (fo=1, routed) 1.929 2.167 u_confreg/dip_sw_IBUF[9] + SLICE_X58Y135 r u_confreg/s_rdata[9]_i_4/I4 + SLICE_X58Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.212 r u_confreg/s_rdata[9]_i_4/O + net (fo=1, routed) 0.254 2.466 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 + SLICE_X57Y132 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/I4 + SLICE_X57Y132 LUT6 (Prop_lut6_I4_O) 0.045 2.511 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O + net (fo=1, routed) 0.000 2.511 u_confreg/u_int_ctrl_n_22 + SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.850 -0.458 u_confreg/sys_clk + SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[9]/C + +Slack: inf + Source: dip_sw[30] + (input port) + Destination: u_confreg/s_rdata_reg[30]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.573ns (logic 0.317ns (12.327%) route 2.256ns (87.673%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.451ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R6 0.000 0.000 r dip_sw[30] (IN) + net (fo=0) 0.000 0.000 dip_sw[30] + R6 r dip_sw_IBUF[30]_inst/I + R6 IBUF (Prop_ibuf_I_O) 0.227 0.227 r dip_sw_IBUF[30]_inst/O + net (fo=1, routed) 2.205 2.432 u_confreg/dip_sw_IBUF[30] + SLICE_X57Y140 r u_confreg/s_rdata[30]_i_4/I4 + SLICE_X57Y140 LUT5 (Prop_lut5_I4_O) 0.045 2.477 r u_confreg/s_rdata[30]_i_4/O + net (fo=1, routed) 0.050 2.528 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 + SLICE_X57Y140 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/I4 + SLICE_X57Y140 LUT6 (Prop_lut6_I4_O) 0.045 2.573 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O + net (fo=1, routed) 0.000 2.573 u_confreg/u_int_ctrl_n_1 + SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.857 -0.451 u_confreg/sys_clk + SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[30]/C + +Slack: inf + Source: dip_sw[26] + (input port) + Destination: u_confreg/s_rdata_reg[26]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.588ns (logic 0.367ns (14.175%) route 2.221ns (85.825%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.454ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.454ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T4 0.000 0.000 r dip_sw[26] (IN) + net (fo=0) 0.000 0.000 dip_sw[26] + T4 r dip_sw_IBUF[26]_inst/I + T4 IBUF (Prop_ibuf_I_O) 0.277 0.277 r dip_sw_IBUF[26]_inst/O + net (fo=1, routed) 1.957 2.234 u_confreg/dip_sw_IBUF[26] + SLICE_X52Y137 r u_confreg/s_rdata[26]_i_4/I4 + SLICE_X52Y137 LUT5 (Prop_lut5_I4_O) 0.045 2.279 r u_confreg/s_rdata[26]_i_4/O + net (fo=1, routed) 0.264 2.543 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 + SLICE_X50Y137 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/I4 + SLICE_X50Y137 LUT6 (Prop_lut6_I4_O) 0.045 2.588 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O + net (fo=1, routed) 0.000 2.588 u_confreg/u_int_ctrl_n_5 + SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk + SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[26]/C + +Slack: inf + Source: touch_btn[0] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.605ns (logic 0.267ns (10.235%) route 2.338ns (89.765%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.460ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T2 0.000 0.000 r touch_btn[0] (IN) + net (fo=0) 0.000 0.000 touch_btn[0] + T2 r touch_btn_IBUF[0]_inst/I + T2 IBUF (Prop_ibuf_I_O) 0.267 0.267 r touch_btn_IBUF[0]_inst/O + net (fo=1, routed) 2.338 2.605 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] + SLICE_X60Y132 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.848 -0.460 u_confreg/u_int_ctrl/sys_clk + SLICE_X60Y132 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C + +Slack: inf + Source: dip_sw[10] + (input port) + Destination: u_confreg/s_rdata_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.611ns (logic 0.330ns (12.645%) route 2.281ns (87.355%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.455ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.455ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M7 0.000 0.000 r dip_sw[10] (IN) + net (fo=0) 0.000 0.000 dip_sw[10] + M7 r dip_sw_IBUF[10]_inst/I + M7 IBUF (Prop_ibuf_I_O) 0.240 0.240 r dip_sw_IBUF[10]_inst/O + net (fo=1, routed) 1.737 1.977 u_confreg/dip_sw_IBUF[10] + SLICE_X62Y139 r u_confreg/s_rdata[10]_i_4/I4 + SLICE_X62Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.022 r u_confreg/s_rdata[10]_i_4/O + net (fo=1, routed) 0.543 2.566 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 + SLICE_X55Y135 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/I4 + SLICE_X55Y135 LUT6 (Prop_lut6_I4_O) 0.045 2.611 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O + net (fo=1, routed) 0.000 2.611 u_confreg/u_int_ctrl_n_21 + SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk + SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[10]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.615ns (logic 0.287ns (10.986%) route 2.328ns (89.014%)) + Logic Levels: 2 (IBUF=1 LUT5=1) + Clock Path Skew: -0.474ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.474ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 r UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 r UART_TX_IOBUF_inst/IBUF/I + H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 2.328 2.570 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X79Y136 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/I0 + SLICE_X79Y136 LUT5 (Prop_lut5_I0_O) 0.045 2.615 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O + net (fo=1, routed) 0.000 2.615 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 + SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.834 -0.474 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C + +Slack: inf + Source: touch_btn[3] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.660ns (logic 0.280ns (10.536%) route 2.380ns (89.464%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.461ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + U2 0.000 0.000 r touch_btn[3] (IN) + net (fo=0) 0.000 0.000 touch_btn[3] + U2 r touch_btn_IBUF[3]_inst/I + U2 IBUF (Prop_ibuf_I_O) 0.280 0.280 r touch_btn_IBUF[3]_inst/O + net (fo=1, routed) 2.380 2.660 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] + SLICE_X60Y131 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.847 -0.461 u_confreg/u_int_ctrl/sys_clk + SLICE_X60Y131 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C + +Slack: inf + Source: dip_sw[1] + (input port) + Destination: u_confreg/s_rdata_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.718ns (logic 0.355ns (13.080%) route 2.362ns (86.920%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.457ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.457ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + J3 0.000 0.000 r dip_sw[1] (IN) + net (fo=0) 0.000 0.000 dip_sw[1] + J3 r dip_sw_IBUF[1]_inst/I + J3 IBUF (Prop_ibuf_I_O) 0.265 0.265 r dip_sw_IBUF[1]_inst/O + net (fo=1, routed) 1.935 2.201 u_confreg/dip_sw_IBUF[1] + SLICE_X66Y141 r u_confreg/s_rdata[1]_i_4/I4 + SLICE_X66Y141 LUT5 (Prop_lut5_I4_O) 0.045 2.246 r u_confreg/s_rdata[1]_i_4/O + net (fo=1, routed) 0.427 2.673 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 + SLICE_X57Y133 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/I4 + SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.045 2.718 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O + net (fo=1, routed) 0.000 2.718 u_confreg/u_int_ctrl_n_30 + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.851 -0.457 u_confreg/sys_clk + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[1]/C + +Slack: inf + Source: dip_sw[5] + (input port) + Destination: u_confreg/s_rdata_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.769ns (logic 0.328ns (11.858%) route 2.441ns (88.142%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.454ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.454ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L5 0.000 0.000 r dip_sw[5] (IN) + net (fo=0) 0.000 0.000 dip_sw[5] + L5 r dip_sw_IBUF[5]_inst/I + L5 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[5]_inst/O + net (fo=1, routed) 2.069 2.307 u_confreg/dip_sw_IBUF[5] + SLICE_X66Y139 r u_confreg/s_rdata[5]_i_4/I4 + SLICE_X66Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.352 r u_confreg/s_rdata[5]_i_4/O + net (fo=1, routed) 0.372 2.724 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 + SLICE_X57Y137 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/I4 + SLICE_X57Y137 LUT6 (Prop_lut6_I4_O) 0.045 2.769 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O + net (fo=1, routed) 0.000 2.769 u_confreg/u_int_ctrl_n_26 + SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk + SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[5]/C + + + + + diff --git a/doc/reports/system/evidence/vivado/utilization.rpt b/doc/reports/system/evidence/vivado/utilization.rpt new file mode 100644 index 0000000..b67d28d --- /dev/null +++ b/doc/reports/system/evidence/vivado/utilization.rpt @@ -0,0 +1,235 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Wed Jul 15 05:09:26 2026 +| Host : Roc_Wang running 64-bit major release (build 9200) +| Command : report_utilization -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/utilization.rpt +| Design : soc_top +| Device : 7a200tfbg676-1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+-------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------------------+-------+-------+-----------+-------+ +| Slice LUTs | 55066 | 0 | 133800 | 41.16 | +| LUT as Logic | 53158 | 0 | 133800 | 39.73 | +| LUT as Memory | 1908 | 0 | 46200 | 4.13 | +| LUT as Distributed RAM | 740 | 0 | | | +| LUT as Shift Register | 1168 | 0 | | | +| Slice Registers | 31000 | 0 | 267600 | 11.58 | +| Register as Flip Flop | 31000 | 0 | 267600 | 11.58 | +| Register as Latch | 0 | 0 | 267600 | 0.00 | +| F7 Muxes | 2130 | 0 | 66900 | 3.18 | +| F8 Muxes | 319 | 0 | 33450 | 0.95 | ++----------------------------+-------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 24 | Yes | - | Set | +| 17683 | Yes | - | Reset | +| 126 | Yes | Set | - | +| 13167 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+-------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------------------------+-------+-------+-----------+-------+ +| Slice | 17126 | 0 | 33450 | 51.20 | +| SLICEL | 11119 | 0 | | | +| SLICEM | 6007 | 0 | | | +| LUT as Logic | 53158 | 0 | 133800 | 39.73 | +| using O5 output only | 5 | | | | +| using O6 output only | 42769 | | | | +| using O5 and O6 | 10384 | | | | +| LUT as Memory | 1908 | 0 | 46200 | 4.13 | +| LUT as Distributed RAM | 740 | 0 | | | +| using O5 output only | 0 | | | | +| using O6 output only | 60 | | | | +| using O5 and O6 | 680 | | | | +| LUT as Shift Register | 1168 | 0 | | | +| using O5 output only | 123 | | | | +| using O6 output only | 997 | | | | +| using O5 and O6 | 48 | | | | +| Slice Registers | 31000 | 0 | 267600 | 11.58 | +| Register driven from within the Slice | 16668 | | | | +| Register driven from outside the Slice | 14332 | | | | +| LUT in front of the register is unused | 5924 | | | | +| LUT in front of the register is used | 8408 | | | | +| Unique Control Sets | 930 | | 33450 | 2.78 | ++--------------------------------------------+-------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++-------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------+------+-------+-----------+-------+ +| Block RAM Tile | 29.5 | 0 | 365 | 8.08 | +| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 | +| RAMB36E1 only | 10 | | | | +| RAMB18 | 39 | 0 | 730 | 5.34 | +| RAMB18E1 only | 39 | | | | ++-------------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 740 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 202 | 202 | 400 | 50.50 | +| IOB Master Pads | 97 | | | | +| IOB Slave Pads | 102 | | | | +| Bonded IPADs | 0 | 0 | 26 | 0.00 | +| Bonded OPADs | 0 | 0 | 16 | 0.00 | +| PHY_CONTROL | 0 | 0 | 10 | 0.00 | +| PHASER_REF | 0 | 0 | 10 | 0.00 | +| OUT_FIFO | 0 | 0 | 40 | 0.00 | +| IN_FIFO | 0 | 0 | 40 | 0.00 | +| IDELAYCTRL | 0 | 0 | 10 | 0.00 | +| IBUFDS | 0 | 0 | 384 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 | +| ILOGIC | 0 | 0 | 400 | 0.00 | +| OLOGIC | 0 | 0 | 400 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 4 | 0 | 32 | 12.50 | +| BUFIO | 0 | 0 | 40 | 0.00 | +| MMCME2_ADV | 0 | 0 | 10 | 0.00 | +| PLLE2_ADV | 1 | 0 | 10 | 10.00 | +| BUFMRCE | 0 | 0 | 20 | 0.00 | +| BUFHCE | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 40 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++-----------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++-----------+-------+---------------------+ +| LUT6 | 26800 | LUT | +| FDCE | 17683 | Flop & Latch | +| FDRE | 13167 | Flop & Latch | +| LUT3 | 10370 | LUT | +| LUT4 | 8684 | LUT | +| LUT2 | 8543 | LUT | +| LUT5 | 8274 | LUT | +| CARRY4 | 3669 | CarryLogic | +| MUXF7 | 2130 | MuxFx | +| RAMD32 | 1060 | Distributed Memory | +| SRLC32E | 992 | Distributed Memory | +| LUT1 | 871 | LUT | +| RAMS32 | 328 | Distributed Memory | +| MUXF8 | 319 | MuxFx | +| SRL16E | 224 | Distributed Memory | +| FDSE | 126 | Flop & Latch | +| IBUF | 104 | IO | +| OBUF | 98 | IO | +| OBUFT | 66 | IO | +| RAMB18E1 | 39 | Block Memory | +| RAMD64E | 32 | Distributed Memory | +| FDPE | 24 | Flop & Latch | +| RAMB36E1 | 10 | Block Memory | +| BUFG | 4 | Clock | +| PLLE2_ADV | 1 | Clock | ++-----------+-------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ +| clk_pll | 1 | ++----------+------+ + + diff --git a/doc/reports/system/evidence/vivado/utilization_hierarchical.rpt b/doc/reports/system/evidence/vivado/utilization_hierarchical.rpt new file mode 100644 index 0000000..f11c82a --- /dev/null +++ b/doc/reports/system/evidence/vivado/utilization_hierarchical.rpt @@ -0,0 +1,229 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Wed Jul 15 05:09:25 2026 +| Host : Roc_Wang running 64-bit major release (build 9200) +| Command : report_utilization -hierarchical -hierarchical_depth 4 -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/utilization_hierarchical.rpt +| Design : soc_top +| Device : 7a200tfbg676-1 +| Design State : Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Utilization by Hierarchy + +1. Utilization by Hierarchy +--------------------------- + ++------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ +| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks | ++------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ +| soc_top | (top) | 55066 | 53158 | 740 | 1168 | 31000 | 10 | 39 | 0 | +| (soc_top) | (top) | 927 | 919 | 8 | 0 | 4 | 0 | 0 | 0 | +| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst | clk_pll_clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 368 | 368 | 0 | 0 | 151 | 0 | 0 | 0 | +| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 | +| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_92 | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 | +| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_75 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_91 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_76 | 17 | 17 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_90 | 17 | 17 | 0 | 0 | 3 | 0 | 0 | 0 | +| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_77 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_89 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 | +| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 32 | 32 | 0 | 0 | 11 | 0 | 0 | 0 | +| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_86 | 26 | 26 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_87 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | +| fifo | StreamFifo_3_88 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | +| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_83 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_84 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | +| fifo | StreamFifo_3_85 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | +| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 | +| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_80 | 24 | 24 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_81 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | +| fifo | StreamFifo_3_82 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | +| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 | +| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7 | 21 | 21 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | +| fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | +| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 90 | 90 | 0 | 0 | 25 | 0 | 0 | 0 | +| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 74 | 74 | 0 | 0 | 12 | 0 | 0 | 0 | +| errorSlave | Axi4ReadOnlyErrorSlave_1_79 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 | +| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | +| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | +| errorSlave | Axi4WriteOnlyErrorSlave_1_78 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 | +| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 52 | 52 | 0 | 0 | 17 | 0 | 0 | 0 | +| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 36 | 36 | 0 | 0 | 8 | 0 | 0 | 0 | +| errorSlave | Axi4ReadOnlyErrorSlave_1 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 | +| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 23 | 23 | 0 | 0 | 14 | 0 | 0 | 0 | +| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 15 | 15 | 0 | 0 | 12 | 0 | 0 | 0 | +| errorSlave | Axi4WriteOnlyErrorSlave_1 | 8 | 8 | 0 | 0 | 2 | 0 | 0 | 0 | +| u_Axi_CDC | Axi_CDC | 427 | 299 | 128 | 0 | 317 | 0 | 0 | 0 | +| arFifo | StreamFifoCC_3_58 | 192 | 156 | 36 | 0 | 77 | 0 | 0 | 0 | +| (arFifo) | StreamFifoCC_3_58 | 186 | 150 | 36 | 0 | 65 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_9_73 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_11_74 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | +| awFifo | StreamFifoCC_59 | 110 | 74 | 36 | 0 | 79 | 0 | 0 | 0 | +| (awFifo) | StreamFifoCC_59 | 103 | 67 | 36 | 0 | 65 | 0 | 0 | 0 | +| bufferCC_12 | BufferCC_10_70 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_9_71 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_11_72 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| bFifo | StreamFifoCC_2_60 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 | +| (bFifo) | StreamFifoCC_2_60 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| bufferCC_12 | BufferCC_5_67 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_4_68 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_6_69 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| rFifo | StreamFifoCC_4_61 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 | +| (rFifo) | StreamFifoCC_4_61 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_65 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_1_66 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| wFifo | StreamFifoCC_1_62 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 | +| (wFifo) | StreamFifoCC_1_62 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_7_63 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_8_64 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| u_axi_axil_adapter | axi_axil_adapter | 1245 | 1245 | 0 | 0 | 161 | 0 | 0 | 0 | +| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 640 | 640 | 0 | 0 | 81 | 0 | 0 | 0 | +| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 605 | 605 | 0 | 0 | 80 | 0 | 0 | 0 | +| u_axi_dvi | axi_dvi | 284 | 284 | 0 | 0 | 211 | 0 | 0 | 0 | +| u_axi_ram | axi_wrap_ram_sp_external | 356 | 356 | 0 | 0 | 78 | 0 | 0 | 0 | +| u_axi_sram_sp | axi2sram_sp_external | 356 | 356 | 0 | 0 | 78 | 0 | 0 | 0 | +| u_axi_uart_controller | axi_uart_controller | 684 | 668 | 16 | 0 | 457 | 0 | 0 | 0 | +| AA_axi2apb_bridge_cpu | axi2apb_bridge | 252 | 252 | 0 | 0 | 120 | 0 | 0 | 0 | +| uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 | +| regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 | +| (regs) | uart_regs | 118 | 118 | 0 | 0 | 155 | 0 | 0 | 0 | +| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 | +| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 | +| u_cdma_matmul_bridge | cdma_matmul_bridge | 248 | 248 | 0 | 0 | 578 | 0 | 0 | 0 | +| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 | +| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 | +| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 | +| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 | +| u_cpu | core_top | 8584 | 8284 | 300 | 0 | 5591 | 0 | 20 | 0 | +| (u_cpu) | core_top | 561 | 513 | 48 | 0 | 1 | 0 | 0 | 0 | +| addr_trans | addr_trans | 2240 | 2100 | 140 | 0 | 1244 | 0 | 0 | 0 | +| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 | +| tlb_entry | tlb_entry | 2240 | 2100 | 140 | 0 | 1204 | 0 | 0 | 0 | +| axi_bridge | axi_bridge | 39 | 39 | 0 | 0 | 214 | 0 | 0 | 0 | +| btb | btb | 1041 | 961 | 80 | 0 | 1611 | 0 | 0 | 0 | +| (btb) | btb | 1039 | 959 | 80 | 0 | 1611 | 0 | 0 | 0 | +| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | +| dcache | dcache | 551 | 519 | 32 | 0 | 146 | 0 | 10 | 0 | +| (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 | +| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_46 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_47 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_48 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_49 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_50 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_51 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_52 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_53 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 | +| lfsr | lfsr_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| tagv_ram_way[0].u | tagv_sram_55 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 | +| tagv_ram_way[1].u | tagv_sram_56 | 42 | 42 | 0 | 0 | 0 | 0 | 1 | 0 | +| exe_stage | exe_stage | 666 | 666 | 0 | 0 | 233 | 0 | 0 | 0 | +| (exe_stage) | exe_stage | 635 | 635 | 0 | 0 | 233 | 0 | 0 | 0 | +| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | +| icache | icache | 233 | 233 | 0 | 0 | 55 | 0 | 10 | 0 | +| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 | +| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_38 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_39 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_40 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_41 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_42 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_43 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_44 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 | +| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 | +| tagv_ram_way[1].u | tagv_sram_45 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 | +| id_stage | id_stage | 1054 | 1054 | 0 | 0 | 108 | 0 | 0 | 0 | +| if_stage | if_stage | 134 | 134 | 0 | 0 | 173 | 0 | 0 | 0 | +| mem_stage | mem_stage | 115 | 115 | 0 | 0 | 211 | 0 | 0 | 0 | +| u_csr | csr | 201 | 201 | 0 | 0 | 663 | 0 | 0 | 0 | +| u_div | div | 141 | 141 | 0 | 0 | 107 | 0 | 0 | 0 | +| u_mul | mul | 938 | 938 | 0 | 0 | 592 | 0 | 0 | 0 | +| wb_stage | wb_stage | 682 | 682 | 0 | 0 | 233 | 0 | 0 | 0 | +| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 30142 | 28868 | 112 | 1162 | 18251 | 10 | 18 | 0 | +| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | +| u_fft_controller | fft_controller | 6934 | 5894 | 0 | 1040 | 1083 | 8 | 4 | 0 | +| (u_fft_controller) | fft_controller | 118 | 118 | 0 | 0 | 100 | 0 | 0 | 0 | +| u_FFT | FFT | 6782 | 5742 | 0 | 1040 | 983 | 8 | 0 | 0 | +| SU1 | SdfUnit | 2144 | 1376 | 0 | 768 | 197 | 2 | 0 | 0 | +| SU2 | SdfUnit__parameterized0 | 1567 | 1375 | 0 | 192 | 197 | 2 | 0 | 0 | +| SU3 | SdfUnit__parameterized1 | 1416 | 1368 | 0 | 48 | 197 | 2 | 0 | 0 | +| SU4 | SdfUnit__parameterized2 | 1397 | 1365 | 0 | 32 | 197 | 2 | 0 | 0 | +| SU5 | SdfUnit__parameterized3 | 258 | 258 | 0 | 0 | 195 | 0 | 0 | 0 | +| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_in1 | my_bram0_21 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_out0 | my_bram0_22 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_out1 | my_bram0_23 | 32 | 32 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_mlkem_axi_cdc | Axi_CDC_5 | 336 | 224 | 112 | 0 | 272 | 0 | 0 | 0 | +| arFifo | StreamFifoCC_3 | 50 | 22 | 28 | 0 | 55 | 0 | 0 | 0 | +| (arFifo) | StreamFifoCC_3 | 42 | 14 | 28 | 0 | 43 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_9_19 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_11_20 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| awFifo | StreamFifoCC | 39 | 15 | 24 | 0 | 49 | 0 | 0 | 0 | +| (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 | +| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_9 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 | +| (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 | +| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | +| rFifo | StreamFifoCC_4 | 65 | 37 | 28 | 0 | 72 | 0 | 0 | 0 | +| (rFifo) | StreamFifoCC_4 | 58 | 30 | 28 | 0 | 56 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| wFifo | StreamFifoCC_1 | 164 | 136 | 28 | 0 | 69 | 0 | 0 | 0 | +| (wFifo) | StreamFifoCC_1 | 159 | 131 | 28 | 0 | 53 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | +| u_mlkem_axi_slave | mlkem_axi_slave | 22873 | 22751 | 0 | 122 | 16890 | 2 | 14 | 0 | +| (u_mlkem_axi_slave) | mlkem_axi_slave | 1179 | 1179 | 0 | 0 | 1064 | 0 | 0 | 0 | +| u_mlkem | mlkem_top | 21697 | 21575 | 0 | 122 | 15826 | 2 | 14 | 0 | +| (u_mlkem) | mlkem_top | 2633 | 2633 | 0 | 0 | 5010 | 0 | 0 | 0 | +| u_bank_a | sd_bram__parameterized0 | 61 | 61 | 0 | 0 | 0 | 1 | 1 | 0 | +| u_bank_se | sd_bram__parameterized1 | 77 | 77 | 0 | 0 | 0 | 1 | 0 | 0 | +| u_bank_t | sd_bram__parameterized2 | 632 | 632 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_c_in_bram | sd_bram | 1301 | 1301 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_cbd | sample_cbd_sync_shared | 2739 | 2739 | 0 | 0 | 3186 | 0 | 0 | 0 | +| u_comp | comp_decomp_sync | 620 | 618 | 0 | 2 | 319 | 0 | 0 | 0 | +| u_ct_bram | sd_bram_6 | 10 | 10 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_dkp_bram | sd_bram_7 | 74 | 74 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_ek_bram | sd_bram_8 | 304 | 304 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_keccak | keccak_core | 5258 | 5258 | 0 | 0 | 1618 | 0 | 0 | 0 | +| u_ntt | ntt_core | 1900 | 1817 | 0 | 83 | 1062 | 0 | 4 | 0 | +| u_pmul | poly_mul_sync | 2058 | 2021 | 0 | 37 | 584 | 0 | 4 | 0 | +| u_sha3 | sha3_top_shared | 1955 | 1955 | 0 | 0 | 2378 | 0 | 0 | 0 | +| u_snt | sample_ntt_sync_shared | 2109 | 2109 | 0 | 0 | 1669 | 0 | 0 | 0 | +| u_matmul_axi_slave | matmul_axi_slave | 9879 | 9697 | 176 | 6 | 3243 | 0 | 0 | 0 | +| (u_matmul_axi_slave) | matmul_axi_slave | 5761 | 5579 | 176 | 6 | 2475 | 0 | 0 | 0 | +| mult_inst[0].u_mult | pipelined_mult_32x32 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 | +| mult_inst[1].u_mult | pipelined_mult_32x32_2 | 999 | 999 | 0 | 0 | 192 | 0 | 0 | 0 | +| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 1060 | 1060 | 0 | 0 | 192 | 0 | 0 | 0 | +| mult_inst[3].u_mult | pipelined_mult_32x32_4 | 997 | 997 | 0 | 0 | 192 | 0 | 0 | 0 | +| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1557 | 1557 | 0 | 0 | 1476 | 0 | 1 | 0 | +| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 600 | 600 | 0 | 0 | 1180 | 0 | 0 | 0 | +| u_core_engine | snix_axi_mm2mm | 960 | 960 | 0 | 0 | 296 | 0 | 1 | 0 | +| (u_core_engine) | snix_axi_mm2mm | 750 | 750 | 0 | 0 | 243 | 0 | 0 | 0 | +| axis_fifo_u0 | snix_axis_fifo | 210 | 210 | 0 | 0 | 53 | 0 | 1 | 0 | +| u_fifo | snix_sync_fifo | 210 | 210 | 0 | 0 | 53 | 0 | 1 | 0 | ++------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ +* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining + + diff --git a/doc/reports/system/figures/clock_cdc.dot b/doc/reports/system/figures/clock_cdc.dot deleted file mode 100644 index 6208e38..0000000 --- a/doc/reports/system/figures/clock_cdc.dot +++ /dev/null @@ -1,30 +0,0 @@ -digraph G { - graph [rankdir=TB, bgcolor="transparent", pad=0.15, nodesep=0.30, ranksep=0.42, - fontname="Noto Sans CJK SC"]; - node [shape=box, style="rounded,filled", fontname="Noto Sans CJK SC", fontsize=10, - color="#44546A", fillcolor="#F7F8FA", margin="0.13,0.08"]; - edge [fontname="Noto Sans CJK SC", fontsize=9, color="#596777", arrowsize=0.7]; - - osc [label="50 MHz 外部时钟"]; - pll [label="PLL\nlocked", fillcolor="#D9EAF7"]; - cpu [label="cpu_clk 33.333 MHz\nCPU + AXI CPU 侧", fillcolor="#EAF2F8"]; - sys [label="sys_clk 50 MHz\nCrossbar / DMA / FFT / matmul", fillcolor="#E8F3E8"]; - mlk [label="mlkem_clk 76.923 MHz\nML-KEM 计算域", fillcolor="#F8E6EA"]; - cdc_cpu [label="CPU↔SYS AXI CDC\n异步握手 / FIFO", shape=box, fillcolor="#FFF1D6"]; - cdc_mlk [label="SYS↔ML-KEM CDC\n命令 / 数据 / 状态同步", shape=box, fillcolor="#FFF1D6"]; - rst [label="各域复位同步器\n异步置位、同步释放", fillcolor="#F2F2F2"]; - - { rank=same; osc; pll; } - { rank=same; cpu; cdc_cpu; sys; } - { rank=same; cdc_mlk; mlk; } - osc -> pll; - pll -> cpu; - pll -> sys; - pll -> mlk; - cpu -> cdc_cpu -> sys [dir=both]; - sys -> cdc_mlk -> mlk [dir=both]; - pll -> rst [label="locked"]; - rst -> cpu [style=dashed, label="resetn", constraint=false]; - rst -> sys [style=dashed, label="resetn", constraint=false]; - rst -> mlk [style=dashed, label="resetn", constraint=false]; -} diff --git a/doc/reports/system/figures/clock_cdc.pdf b/doc/reports/system/figures/clock_cdc.pdf deleted file mode 100644 index 7b5b531..0000000 Binary files a/doc/reports/system/figures/clock_cdc.pdf and /dev/null differ diff --git a/doc/reports/system/figures/matmul_pipeline.dot b/doc/reports/system/figures/matmul_pipeline.dot deleted file mode 100644 index 2eb5086..0000000 --- a/doc/reports/system/figures/matmul_pipeline.dot +++ /dev/null @@ -1,22 +0,0 @@ -digraph G { - graph [rankdir=TB, bgcolor="transparent", pad=0.15, nodesep=0.28, ranksep=0.38, - fontname="Noto Sans CJK SC"]; - node [shape=box, style="rounded,filled", fontname="Noto Sans CJK SC", fontsize=10, - color="#44546A", fillcolor="#F7F8FA", margin="0.12,0.08"]; - edge [fontname="Noto Sans CJK SC", fontsize=9, color="#596777", arrowsize=0.7]; - - cfg [label="CPU 一次配置\n基址 / 组数 / stride", fillcolor="#EAF2F8"]; - read [label="DMA 读取 128 B\nA、B → 空闲 Bank", fillcolor="#E8F3E8"]; - calc [label="4 路 32x32 LUT 乘法\n每拍形成一个输出元素的 4 项乘积", fillcolor="#FFF1D6"]; - write [label="DMA 写回 192 B\nC → ExtRAM", fillcolor="#E8F3E8"]; - crc [label="硬件流水 CRC32\n不写回时仍可判定整批结果", fillcolor="#F8E6EA"]; - next [label="Bank 翻转 / group+1", shape=diamond, fillcolor="#F2F2F2"]; - done [label="done + dma_cycles", fillcolor="#D9EAF7"]; - - { rank=same; read; calc; write; } - cfg -> read; - read -> calc -> write; - write -> crc -> next; - next -> read [label="未完成", constraint=false]; - next -> done [label="全部完成"]; -} diff --git a/doc/reports/system/figures/matmul_pipeline.pdf b/doc/reports/system/figures/matmul_pipeline.pdf deleted file mode 100644 index d7a45da..0000000 Binary files a/doc/reports/system/figures/matmul_pipeline.pdf and /dev/null differ diff --git a/doc/reports/system/figures/system_boundary.dot b/doc/reports/system/figures/system_boundary.dot deleted file mode 100644 index 4378a01..0000000 --- a/doc/reports/system/figures/system_boundary.dot +++ /dev/null @@ -1,29 +0,0 @@ -digraph G { - graph [rankdir=LR, bgcolor="transparent", pad=0.15, nodesep=0.35, ranksep=0.65, - fontname="Noto Sans CJK SC", fontsize=10]; - node [shape=box, style="rounded,filled", fontname="Noto Sans CJK SC", fontsize=10, - color="#44546A", fillcolor="#F5F7FA", margin="0.13,0.08"]; - edge [fontname="Noto Sans CJK SC", fontsize=9, color="#596777", arrowsize=0.7]; - - cpu [label="LoongArch32r CPU\n软件调度 / 校验", fillcolor="#EAF2F8"]; - xbar [label="AXI Crossbar\n双主设备 / 统一编址", fillcolor="#D9EAF7"]; - mem [label="BaseRAM / ExtRAM", fillcolor="#F2F2F2"]; - periph [label="UART / DVI / confreg", fillcolor="#F2F2F2"]; - dma [label="4 通道 DMA\nmem2mem / endpoint", fillcolor="#E8F3E8"]; - seq [label="matmul 批处理序列器", fillcolor="#E8F3E8"]; - matmul [label="4x4 矩阵乘法\n双 Bank + CRC", fillcolor="#FFF1D6"]; - fft [label="1024 点 FFT\n5 个 Radix-2² SDF 单元", fillcolor="#FFF1D6"]; - mlkem [label="ML-KEM-512/768/1024\nKeyGen / Encaps / Decaps", fillcolor="#F8E6EA"]; - - cpu -> xbar [label="AXI master 0"]; - dma -> xbar [label="AXI master 1", dir=both]; - xbar -> mem [dir=both]; - xbar -> periph [dir=both]; - xbar -> dma [label="配置"]; - xbar -> matmul [label="Slave 7", dir=both]; - xbar -> fft [label="Slave 6 / 高地址", dir=both]; - xbar -> mlkem [label="Slave 6 / 低地址", dir=both]; - seq -> dma [label="描述符"]; - seq -> matmul [label="start / done"]; - dma -> matmul [label="本地 endpoint", dir=both, color="#2F6B3C", penwidth=1.4]; -} diff --git a/doc/reports/system/figures/system_boundary.pdf b/doc/reports/system/figures/system_boundary.pdf deleted file mode 100644 index a6da6f1..0000000 Binary files a/doc/reports/system/figures/system_boundary.pdf and /dev/null differ diff --git a/doc/reports/system/figures/verification_flow.dot b/doc/reports/system/figures/verification_flow.dot deleted file mode 100644 index d19bd69..0000000 --- a/doc/reports/system/figures/verification_flow.dot +++ /dev/null @@ -1,21 +0,0 @@ -digraph G { - graph [rankdir=LR, bgcolor="transparent", pad=0.15, nodesep=0.28, ranksep=0.55, - fontname="Noto Sans CJK SC"]; - node [shape=box, style="rounded,filled", fontname="Noto Sans CJK SC", fontsize=9.5, - color="#44546A", fillcolor="#F7F8FA", margin="0.12,0.08"]; - edge [fontname="Noto Sans CJK SC", fontsize=9, color="#596777", arrowsize=0.7]; - - rtl [label="RTL 静态检查\nVerilator lint"]; - unit [label="模块级仿真\n协议、边界、反压"]; - soc [label="SoC 仿真\nCPU + AXI + 加速器"]; - impl [label="布局布线\n时序 / DRC / CDC / 资源"]; - board [label="板级回归\n正确性 + 实测耗时"]; - evidence [label="版本化证据\n日志 / rpt / bit / 指标文件", fillcolor="#D9EAF7"]; - - rtl -> unit -> soc -> impl -> board; - rtl -> evidence [style=dashed]; - unit -> evidence [style=dashed]; - soc -> evidence [style=dashed]; - impl -> evidence [style=dashed]; - board -> evidence [style=dashed]; -} diff --git a/doc/reports/system/figures/verification_flow.pdf b/doc/reports/system/figures/verification_flow.pdf deleted file mode 100644 index a38f22f..0000000 Binary files a/doc/reports/system/figures/verification_flow.pdf and /dev/null differ diff --git a/doc/reports/system/matmul_arch.png b/doc/reports/system/matmul_arch.png index 45cebb1..473182c 100644 Binary files a/doc/reports/system/matmul_arch.png and b/doc/reports/system/matmul_arch.png differ diff --git a/doc/reports/system/mlkem_modules.png b/doc/reports/system/mlkem_modules.png index ce96182..dd6985e 100644 Binary files a/doc/reports/system/mlkem_modules.png and b/doc/reports/system/mlkem_modules.png differ diff --git a/doc/reports/system/modules/00_clock_domains.md b/doc/reports/system/modules/00_clock_domains.md new file mode 100644 index 0000000..3664729 --- /dev/null +++ b/doc/reports/system/modules/00_clock_domains.md @@ -0,0 +1,104 @@ +# 时钟域、复位与跨时钟域设计说明 + +## 1. 时钟拓扑 + +板级输入 `clk` 的周期为 20 ns，即 50 MHz。硬件路径由 `clk_pll` 产生 CPU、系统总线和 +ML-KEM 三个时钟。当前实现报告记录的周期和频率如下。 + +| 时钟 | 周期 | 频率 | 主要负载 | +|---|---:|---:|---| +| `cpu_clk` | 30 ns | 33.333 MHz | OpenLA500 CPU、CPU 侧缓存和 AXI 主接口 | +| `sys_clk` | 20 ns | 50 MHz | Crossbar、SRAM、UART、DMA、FFT、matmul 和系统寄存器 | +| `mlkem_clk` | 13 ns | 76.923 MHz | ML-KEM AXI 从端、算法总控、Keccak、NTT 和多项式算子 | + +三个时钟均由同一个 PLL 产生，但 `soc.xdc` 使用 `set_clock_groups -asynchronous` 将三者 +划入独立异步组。工程含义是任何跨域逻辑都不能依赖固定相位关系，静态时序分析也不会把 +普通组合路径当作同步时序路径检查。跨域正确性必须由双时钟 FIFO、同步器、握手协议和 +专门的 CDC 验证保证。 + +## 2. 模块归属 + +CPU 核及其 AXI 主端属于 CPU 域。CPU 发出的 AW、W、AR 通道在进入 Crossbar 前跨到 +SYS 域，B 和 R 响应反向跨回 CPU 域。Crossbar 的两个主端、八个从端、外部 SRAM、 +DMA、FFT、矩阵序列器和矩阵乘法器全部属于 SYS 域，这些模块之间是同步连接。 + +FFT/ML-KEM 共享从端的地址选择和 FFT 分支属于 SYS 域。ML-KEM 分支的完整 AXI 接口 +跨到 ML-KEM 域后，`mlkem_axi_slave`、`mlkem_top` 及其所有叶子算子均在 +`mlkem_clk` 下工作。密码核心内部没有第二个计算时钟。 + +## 3. CPU--SYS AXI 跨域 + +`u_Axi_CDC` 为 AXI 的 AW、W、B、AR 和 R 五个通道分别设置双时钟 FIFO。AW、W 和 AR +在 CPU 域写入 FIFO、在 SYS 域读出；B 和 R 在 SYS 域写入、在 CPU 域读出。FIFO 将 +valid/ready 反压限制在各自时钟域，并连同地址、ID、burst 属性、数据、WSTRB、响应和 +RLAST/WLAST 一起跨域。 + +该结构不对多位 AXI payload 逐位使用两级同步器，而是在写时钟域稳定写入存储，使用同步 +后的读写指针传递所有权，再在读时钟域读取。这是多位总线跨域的必要条件。AW 和 W 仍为 +独立通道，下游从端必须按 AXI 规则处理两者不同拍到达，不能假设跨域 FIFO 会自动配对。 + +CPU--SYS 路径的延迟包含 FIFO 入队、指针同步和出队，不应通过 CPU 与 SYS 周期的简单 +比例估算。端到端软件周期已经包含该延迟。 + +## 4. SYS--ML-KEM AXI 跨域 + +`fft_mlkem_axi_slave` 在 SYS 域锁存目标选择。FFT 请求保持在 SYS 域；ML-KEM 请求进入 +第二个 `Axi_CDC`，再由 ML-KEM 域的 `mlkem_axi_slave` 处理。该跨域同样覆盖 AXI 五个 +通道，而不是只同步 start/done。因此配置寄存器、批量密钥窗口和读回数据都遵循统一的 +AXI CDC 语义。 + +ML-KEM 完成中断在 `mlkem_clk` 域产生，先通过两级 `mlkem_intr_sync` 同步到 SYS 域。 +由于完成状态保持到软件 W1C，接收端观察的是电平而不是单周期脉冲，避免因频率差异丢失 +事件。软件读取 STATUS 获得最终完成语义，中断只负责通知。 + +## 5. 中断到 CPU 的边界 + +当前 `soc_top` 将 `confreg_int`、DMA done、matmul done 和 ML-KEM done 组合后直接连接 +到 CPU 的 `intrpt` 输入。其中 DMA 和 matmul 状态产生于 SYS 域；ML-KEM 状态虽已同步到 +SYS 域，仍需跨入 CPU 域。它们均为保持到清除的电平信号，因此相较单拍脉冲更不易漏采， +但当前顶层没有为项目新增的三路中断显式实例化 CPU 域两级同步器。 + +严谨的前端实现应在 `cpu_clk` 域对每路异步电平增加两级 `ASYNC_REG` 同步，或把中断状态 +放入已有的 CPU--SYS 握手寄存器。同步前的电平必须保持不少于两个 CPU 周期，清除语义也 +应以 CPU 可观察到状态后再执行。该项属于时钟域实现风险，不能仅以板级轮询程序通过替代 +结构验证。 + +## 6. 复位生成与释放顺序 + +`rst_sync` 包含两个串联寄存器。输入复位有效时通过异步低电平立即把两级清零；输入复位 +撤销后，逻辑 1 在本时钟域连续两个上升沿移入，形成异步断言、同步撤销的低有效复位。 + +硬件路径中，外部 reset 先复位 PLL。PLL `locked` 进入 SYS 域复位同步器，产生 +`sys_resetn`；随后 `sys_resetn` 分别作为 CPU 和 ML-KEM 复位同步器输入，产生 +`cpu_resetn` 和 `mlkem_resetn`。因此 SYS 域先释放，CPU 和 ML-KEM 域至少再等待各自两个 +有效时钟边沿。CDC 两侧在各自复位释放前不得发送 valid，也不得保留上一轮 FIFO 所有权。 + +行为仿真 `SIMULATION=1` 不实例化 PLL。testbench 的 50 MHz 时钟直接作为 `sys_clk`， +内部 30 ns 周期时钟作为 `cpu_clk`，`mlkem_clk` 暂等于 `sys_clk`。此模式可验证复位顺序 +和零事务，但不能验证真实 13 ns ML-KEM 时钟的相位、PLL 锁定过程或异步 FIFO 的全部 +频率组合。 + +当前 20 us XSIM VCD 中，外部 reset 在 2.000 us 撤销，`sys_resetn`、`mlkem_resetn` 和 +`cpu_resetn` 分别约在 2.030、2.070 和 2.085 us 释放。第一个 CPU ARVALID 约在 +2.205 us 出现，复位释放前 UART、AXI、DMA 请求和加速器 start 均没有高电平。 + +## 7. 跨域信号设计规则 + +单比特静态状态可以采用两级同步器，但源端必须保持足够长时间。单周期脉冲需要 toggle、 +脉冲展宽或 request/ack 握手，不能直接送入另一个时钟域。多位配置和数据必须通过异步 +FIFO、握手后稳定保持的影子寄存器或双口存储传递，禁止逐位同步后重新组合。 + +复位也是跨域信号。每个时钟域必须使用本地同步释放的 resetn，不能用另一个域同步器的 +输出直接复位本域大量寄存器。所有 CDC 结构的两侧复位关系必须保证复位期间不会把残留 +valid 解释为新事务。 + +## 8. 时序与验证方法 + +单域时序分别在 `cpu_clk`、`sys_clk` 和 `mlkem_clk` 路径组内检查 setup 和 hold。由于 +时钟组被声明为异步，跨域路径不应以普通 WNS 作为正确性依据。验证应包括 CDC 结构审查、 +同步寄存器属性检查、异步 FIFO 满空边界、随机相位/频率仿真、复位任意时刻进入，以及 +valid/ready 双向反压。 + +板级功能测试证明常用任务能够跨域完成，但不能观察亚稳态。报告中的时钟域结论应分别 +引用时钟报告、单域时序报告、复位波形和 CDC 结构说明，避免用单一板级 PASS 替代这些 +不同层次的证据。 diff --git a/doc/reports/system/modules/01_soc_integration.md b/doc/reports/system/modules/01_soc_integration.md new file mode 100644 index 0000000..b1ca0b7 --- /dev/null +++ b/doc/reports/system/modules/01_soc_integration.md @@ -0,0 +1,77 @@ +# SoC 集成与时钟复位技术说明 + +## 1. 模块定位 + +`rtl/soc_top.v` 是项目的系统集成顶层。该文件不重新实现 CPU、UART 或 SRAM 控制器， +而是将 OpenLA500 处理器、存储器、外设、DMA 和三个计算加速器组织为统一的 AXI 系统。 +项目相关的集成工作包括扩展 Crossbar 从端口、增加 DMA 主端口、划分加速器地址窗口、 +建立 CPU--SYS 和 SYS--ML-KEM 时钟边界，以及将完成状态接入中断系统。 + +系统采用 CPU 控制、DMA 搬运、加速器计算的职责划分。CPU 通过寄存器完成参数配置和 +任务启动；DMA 作为第二个 AXI 主机访问存储器与外设；FFT、ML-KEM 和矩阵乘法器作为 +被控计算单元。矩阵批处理序列器位于 DMA 控制窗口内，可脱离 CPU 的逐组调度执行长任务。 + +## 2. 地址空间与互连 + +系统 Crossbar 具有两个主端和八个从端。主端 0 接收经 `Axi_CDC` 转换后的 CPU AXI +事务，主端 1 接收 DMA 发起的 AXI 事务。与本项目直接相关的从端如下。 + +| 物理地址 | 模块 | 作用 | +|---|---|---| +| `0x1f30_0000` | DMA 控制窗口 | 通道寄存器位于 `0x000--0x1ff`，矩阵序列器位于 `0x200--0x21f` | +| `0x1f40_0000` | FFT/ML-KEM 共享窗口 | ML-KEM 使用低 `0x0000--0x3fff`，FFT 使用 `0x8000--0xcfff` | +| `0x1f50_0000` | 矩阵乘法器 | 控制状态、CRC32、双 Bank 输入和结果窗口 | + +CPU 软件使用高位映射访问未缓存地址，例如物理地址 `0x1f40_0000` 对应 +`0xbf40_0000`。DMA 始终使用物理地址，软件在提交描述符前需要去除 CPU 虚拟地址的 +高位映射。该约定避免 DMA 错把虚拟地址送入 Crossbar。 + +DMA 控制从端原始接口为 AXI4，经 `axi_axil_adapter` 转换为 AXI-Lite。地址偏移 +`0x200` 的访问在顶层被路由到 `cdma_matmul_bridge`，其余访问进入通用 DMA 通道寄存器。 +写地址的目标选择在 AW 握手后保持到 B 响应返回，读地址选择保持到 R 响应返回，从而 +避免响应阶段再次依赖变化中的地址信号。 + +## 3. 时钟结构 + +硬件实现使用 50 MHz 外部时钟驱动 PLL，产生三个逻辑时钟域。当前实现报告中的目标 +频率为 CPU 33.333 MHz、系统总线 50 MHz 和 ML-KEM 76.923 MHz。CPU 核及其 AXI 侧 +逻辑工作在 `cpu_clk`；Crossbar、DMA、FFT、矩阵乘法器和外设工作在 `sys_clk`； +ML-KEM 核心工作在 `mlkem_clk`。 + +CPU AXI 五个通道通过 `Axi_CDC` 跨入系统时钟域。ML-KEM 的配置、批量数据窗口和完成 +响应通过第二个完整 AXI CDC 跨越 SYS--ML-KEM 边界；`mlkem_axi_slave` 内部的 +toggle/ack 负责把寄存器动作转换为单次事件。FFT 与矩阵乘法器均位于系统时钟域，不需要 +额外的计算域 CDC。 + +完整的时钟归属、异步时钟组约束、AXI 双时钟 FIFO 和中断边界见 +[时钟域、复位与跨时钟域设计说明](00_clock_domains.md)。本文件只说明顶层集成关系。 + +行为仿真中 `SIMULATION=1`，PLL 被可控仿真时钟替代：`sys_clk` 使用 50 MHz testbench +时钟，`cpu_clk` 使用约 33.333 MHz 时钟，`mlkem_clk` 暂与 `sys_clk` 相同。该模式用于 +功能验证，不用于推导硬件 PLL 的锁定时间或跨域相位关系。 + +## 4. 复位结构 + +硬件路径中，PLL 的 `locked` 信号首先送入系统域 `rst_sync`。`sys_resetn` 释放后，CPU +域和 ML-KEM 域的复位同步器再分别产生 `cpu_resetn` 和 `mlkem_resetn`。各同步器采用 +异步断言、同步撤销原则，使复位可立即进入有效状态，而退出复位只能发生在本时钟域的 +有效边沿。 + +复位约束不仅要求状态机回到初始状态，还要求复位释放前不产生外部可见事务。当前短时 +XSIM 证据记录了 UART 写使能、CPU AXI AW/W/AR valid、DMA 读写请求、矩阵启动和 +ML-KEM 启动。VCD 中 `sys_resetn`、`mlkem_resetn` 和 `cpu_resetn` 分别约在 2.030 us、 +2.070 us 和 2.085 us 释放；第一个 CPU 读请求出现在约 2.205 us，晚于 CPU 复位释放。 + +## 5. 中断与完成状态 + +DMA 的通道完成标志归并为 `cdma_dma_finish`，矩阵序列器另有 `cdma_matmul_seq_irq`。 +矩阵乘法器输出电平型 `matmul_intr`，ML-KEM 前端输出 `mlkem_intr`，FFT 完成状态接入 +原有 `confreg` 中断路径。性能测试程序主要采用轮询，以减少短任务的中断现场开销； +中断信号仍保留给功能软件和后续异步调度使用。 + +## 6. 验证重点 + +顶层验证应覆盖地址译码互斥性、CPU 与 DMA 并发访问、AW/W 分离到达、复位前零事务、 +各域复位释放顺序以及完成状态的置位和清除。板级功能通过 FFT、ML-KEM 和矩阵乘法 +程序分别验证；时钟频率、时序裕量和资源使用以实现后报告为准。行为仿真不能替代 PLL +实现检查，单个应用通过也不能证明所有地址空洞和并发组合均已覆盖。 diff --git a/doc/reports/system/modules/02_dma_subsystem.md b/doc/reports/system/modules/02_dma_subsystem.md new file mode 100644 index 0000000..ef7acf5 --- /dev/null +++ b/doc/reports/system/modules/02_dma_subsystem.md @@ -0,0 +1,83 @@ +# 通用 DMA 子系统技术说明 + +## 1. 功能与组成 + +DMA 子系统位于 `rtl/ip/cdma/`，对软件提供四个逻辑通道，对系统提供一个 32 位 AXI4 +主端，并对矩阵乘法器提供 32 位本地 endpoint。当前顶层实例参数为 `PORTS=4`、 +`DATA_WIDTH=32`、`FIFO_DEPTH=64`。源码中的“8 通道”实例名和注释是历史名称，实际 +综合配置应以参数值四通道为准。 + +子系统由三部分组成。`snix_axil_cdma_mux` 实现通道寄存器、轮询仲裁、传输模式选择和 +AXI 主端复用；`snix_axi_mm2mm` 实现普通内存到内存的 burst 搬运；本地 endpoint 状态机 +实现内存与矩阵双 Bank 之间的数据传递。同步 FIFO 和 AXIS FIFO 用于隔离 AXI 读、写 +通道的反压。 + +## 2. 软件接口 + +每个通道占用 `0x40` 字节，通道 `n` 的偏移基址为 `n*0x40`。 + +| 偏移 | 名称 | 说明 | +|---|---|---| +| `0x00` | SRC_ADDR | 源物理地址 | +| `0x04` | DST_ADDR | 目的物理地址 | +| `0x08` | LENGTH | 传输字节数 | +| `0x0c` | TAG | 软件标记，硬件不解释 | +| `0x10` | CTRL | bit 0 启动，bits 5:3 为 AxSIZE，bits 13:6 为 AxLEN | +| `0x14` | STATUS | bit 0 busy，bit 1 done；done 采用 W1C | +| `0x18` | MODE | 0 为 mem2mem，1 为 mem2ep，2 为 ep2mem | +| `0x1c` | EP_CFG | bits 3:0 Bank，bits 15:8 word offset，bits 19:16 endpoint ID | + +通道处于 busy 时，源地址、目的地址、长度、模式和 endpoint 配置不再接受修改。新启动 +请求会清除旧 done，硬件完成与软件 W1C 同周期发生时以硬件置位优先，避免丢失完成事件。 +所有地址均为物理地址，长度以字节计。 + +## 3. 通道仲裁 + +`snix_axil_cdma_mux` 为四个通道维护独立的请求位和完成位，但共享一个实际搬运引擎。 +仲裁器从 `rr_ptr` 开始循环检查待处理通道，选中后锁存 `cur_ch`，在 START 状态发出单拍 +`engine_start`，在 RUN 状态等待对应引擎完成。完成后设置该通道 done，并将轮询指针 +移动到下一通道。该结构保证长期存在的请求不会固定占用最低编号优先级。 + +共享引擎意味着四个通道可以独立排队，但不能同时占用 AXI 主端。多通道的主要收益是 +减少软件串行配置依赖并提供公平排队，而不是形成四路并行 AXI 数据流。 + +## 4. 内存到内存路径 + +`snix_axi_mm2mm` 的控制状态依次为 IDLE、PREP1、PREP2、AR、READ、AW、WRITE 和 +WAIT_BRESP。引擎先计算本次 burst 的实际长度，发出 INCR 读请求，将 R 通道数据写入 +FIFO，再发出对应写请求并从 FIFO 驱动 W 通道。最后一个写响应返回后，若仍有剩余字节， +引擎更新源地址和目的地址并处理下一 burst。 + +读数据只在 READ 状态接收，写数据只在 WRITE 状态发送。该门控防止非活动状态下的 +AXI beat 被误计数。末尾不足一个数据宽度时由 `WSTRB` 屏蔽无效字节。当前 SoC 数据宽度 +为 32 bit，常用配置为 AxSIZE=2，即每 beat 4 字节。 + +## 5. 本地 endpoint 路径 + +mem2ep 模式从 AXI 地址读取数据，并逐字送往 `ep_wr_valid/ready`；ep2mem 模式通过 +`ep_rd_valid/ready` 读取本地结果，再发出 AXI 写事务。endpoint 接口附带 endpoint ID、 +Bank 号和字地址，因此无需把矩阵双 Bank 映射回 Crossbar，也避免每个 32 位字再次经过 +从端地址译码。 + +矩阵批处理序列器还可通过 `ext_rd_req_*` 和 `ext_wr_req_*` 直接提交一次外部请求。这组 +请求优先占用 AXI 主端，并在通用通道引擎空闲时接收。读请求完成后产生单拍 +`ext_rd_req_done`，写请求在 B 响应返回后产生 `ext_wr_req_done`。该接口用于流水调度， +减少序列器重复写入通道 CSR 的延迟。 + +## 6. 复位与反压 + +当前集成的 DMA 通道寄存器、仲裁器、mem2mem 引擎、endpoint 引擎和 AXI 主端均工作在 +`sys_clk`，内部不存在活动的异步时钟边界。仓库保留的 `snix_async_fifo` 未被当前 +`soc_top` 层次实例化；实际数据 FIFO 为同一 SYS 域内的同步 FIFO。 + +所有控制状态、通道请求和完成位在 `rst_n=0` 时清零。AXI 与 endpoint 均遵循 +valid/ready 规则：发送端在握手前保持数据和控制字段，接收端可通过 ready 插入反压。 +目前 endpoint 只按 32 位数据宽度实现，字节数不是 4 的整数倍时不应使用该路径。 + +## 7. 验证方法与限制 + +DMA 验证至少应覆盖不同 burst 长度、末尾非满 beat、四通道公平性、R/W 反压、 +mem2mem、mem2ep、ep2mem 和 W1C 竞态。当前板级 FFT DMA 和 ML-KEM DMA 测试证明了 +普通外设窗口搬运路径，矩阵评测证明了外部请求与本地 endpoint 路径。当前实现未设置 +总线超时和错误恢复状态，若 AXI 从端永久不响应，通道会保持 busy；因此系统集成时必须 +保证目标地址有效，或在后续版本增加 watchdog 和错误码。 diff --git a/doc/reports/system/modules/03_matmul_batch_sequencer.md b/doc/reports/system/modules/03_matmul_batch_sequencer.md new file mode 100644 index 0000000..9920b48 --- /dev/null +++ b/doc/reports/system/modules/03_matmul_batch_sequencer.md @@ -0,0 +1,70 @@ +# 矩阵批处理序列器技术说明 + +## 1. 模块职责 + +`cdma_matmul_bridge` 将一次软件启动扩展为多组矩阵的完整硬件调度。模块位于 DMA 控制 +窗口偏移 `0x200`，通过通用 DMA 的外部请求接口搬运输入和可选结果，通过本地控制信号 +启动矩阵乘法器。该结构消除了 CPU 对 5000 组任务逐组配置、轮询和切换 Bank 的开销。 + +序列器、通用 DMA 外部请求接口和矩阵本地控制接口全部工作在 `sys_clk`，因此 Bank 状态、 +request/done 和 start 信号之间为同步路径。CPU 对序列器寄存器的访问在到达本模块前已由 +CPU--SYS `Axi_CDC` 完成跨域。 + +每组输入由两个 4x4、32 位无符号矩阵组成，共 32 个字，即 128 字节。每组结果包含 +16 个 66 位元素，以每元素三个 32 位字存储，共 192 字节。序列器使用可配置 stride， +因此数据可以连续排列，也可嵌入更大的记录结构。 + +## 2. 寄存器接口 + +| 绝对偏移 | 名称 | 说明 | +|---|---|---| +| `0x200` | CTRL | bit 0 启动，bit 1 跳过结果写回 | +| `0x204` | STATUS | bit 0 busy，bit 1 done；done 为 W1C | +| `0x208` | SRC_BASE | 第一组 A/B 的物理地址 | +| `0x20c` | DST_BASE | 第一组 C 的物理地址 | +| `0x210` | GROUPS | 任务组数 | +| `0x214` | MAT_BASE | 软件兼容字段，当前直接 endpoint 路径不使用 | +| `0x218` | SRC_STRIDE | 相邻输入组地址间隔，默认 128 字节 | +| `0x21c` | DST_STRIDE | 相邻结果组地址间隔，默认 192 字节 | + +配置寄存器只在序列器空闲时接受写入。启动时模块锁存是否跳过写回，清除旧完成状态， +清零矩阵 CRC，并初始化组计数、地址计数和两个 Bank 的占用状态。`GROUPS=0` 不产生计算。 + +## 3. 双 Bank 调度模型 + +序列器为两个 Bank 分别维护 load active、A/B valid、compute active、store pending 和 +store active 五类状态。一个 Bank 只有在上述状态均为零时才能接收下一组输入。输入组 +按组号奇偶映射到 Bank 0/1，并在 `bank_group_idx` 中记录所属组号。 + +调度过程包含三个可重叠阶段。装载阶段提交 128 字节 mem2ep 请求；计算阶段在 A/B +有效后发出 `mat_start_valid` 和 Bank 号；存储阶段在计算完成后提交 192 字节 ep2mem +请求。只要另一 Bank 可用，下一组装载可以与当前组计算或结果写回交叠。 + +当两个 Bank 均具备计算条件时，序列器选择组号较小者，保持提交顺序。计算 Bank 被放入 +两项深度的 `compute_q`，用于把矩阵乘法器的电平 done 事件对应回具体 Bank。done 通过 +边沿检测转化为单次完成事件，防止电平保持期间重复退休同一任务。 + +## 4. 完成与快速路径 + +正常模式下，一组任务在结果写回的 B 响应完成后退休。快速模式设置 +`skip_result_writeback`，计算完成即退休，不再把 192 字节结果写入 ExtRAM。矩阵乘法器 +在计算结果产生时直接更新整批 CRC32，因此跳过写回不会跳过正确性判定。该模式适用于 +官方评测只检查最终 CRC、无需读取全部结果矩阵的场景。 + +当 `groups_retired` 达到配置组数，且没有活动的装载、计算和存储任务时，序列器清除 +busy、置位 done 并拉高 `seq_done_irq`。软件通过 STATUS 的 W1C 位确认并清除完成状态。 + +## 5. 关键不变量 + +同一 Bank 不得同时被装载和计算，也不得在结果尚未消费时覆盖。组号只在输入请求被接受 +后递增，退休计数只响应写回完成或快速模式下的计算完成。输入和结果地址分别按 stride +递增，不从 Bank 号反推地址。CRC 只在整批启动时清零，不在 Bank 切换时清零。 + +这些不变量是验证的核心。若仅检查最终 done，无法发现 Bank 覆盖、组号乱序或重复退休。 +测试平台应同时观察每个 Bank 的状态向量、DMA 请求握手、矩阵 start/done 和退休计数。 + +## 6. 当前验证范围 + +区域赛证据包含三次 5000 组官方板级运行，三次均收到完成标志并通过 CRC。该结果验证了 +长序列快速模式的主要数据流，但不等价于覆盖所有边界。模块级回归仍应包含组数 1、2、3， +两种写回模式，不同 stride，DMA 读写反压，以及 done W1C 后立即启动下一批等场景。 diff --git a/doc/reports/system/modules/04_matmul_accelerator.md b/doc/reports/system/modules/04_matmul_accelerator.md new file mode 100644 index 0000000..ab352c7 --- /dev/null +++ b/doc/reports/system/modules/04_matmul_accelerator.md @@ -0,0 +1,82 @@ +# 4x4 矩阵乘法加速器技术说明 + +## 1. 计算规格 + +`matmul_axi_slave` 计算两个 4x4 无符号整数矩阵的乘积。输入元素宽度为 32 bit，输出 +元素满足 + +`C[i][j] = sum(A[i][k] * B[k][j]), k=0..3`。 + +单个乘积为 64 bit，四项相加的最坏情况需要 66 bit，因此结果存储宽度固定为 66 bit。 +每个输出元素通过三个 32 位字传输：低 32 位、高 32 位以及最高 2 位。该布局使 AXI 和 +DMA 数据宽度保持 32 bit，同时不截断数学结果。 + +## 2. 接口组成 + +模块同时提供完整 AXI4 从接口、本地 DMA endpoint 和矩阵序列器直连控制接口。AXI +接口支持 INCR burst，可由 CPU 或普通 DMA 访问控制寄存器及双 Bank 数据窗口。本地 +endpoint 直接接收 A/B 字或输出 C 字，不经过 Crossbar 的矩阵从端。序列器通过 +`mat_start_valid`、`mat_start_bank`、`mat_done_clear` 和 `mat_crc_clear` 完成批处理控制。 + +矩阵 AXI 从端、endpoint、乘法流水线和 CRC 均使用 `sys_clk/sys_resetn`。DMA 和序列器也 +位于 SYS 域，三者之间没有 CDC。CPU 发起的矩阵访问在 Crossbar 之前已经跨入 SYS 域。 +`matmul_intr` 产生于 SYS 域，接入 CPU 前的时钟边界见独立时钟域说明。 + +两个 endpoint ready 在当前实现中恒为 1，表示矩阵本地缓冲不施加反压。上游仍必须只在 +目标 Bank 空闲时写入，Bank 所有权由批处理序列器保证，而不是由加速器内部检查。 + +## 3. 寄存器与双 Bank 布局 + +| 偏移 | 内容 | 说明 | +|---|---|---| +| `0x000` | CTRL | bit 0 请求 Bank 0，bit 1 请求 Bank 1 | +| `0x004` | STATUS | busy、done、error；done/error 支持 W1C | +| `0x010` | CRC32 | 返回 `crc_reg XOR 0xffff_ffff`；写入用于清零 CRC | +| `0x100` | Bank 0 A | 16 个 32 位元素 | +| `0x140` | Bank 0 B | 16 个 32 位元素 | +| `0x180` | Bank 0 C | 16 个 66 位元素，共 48 个 32 位字 | +| `0x300` | Bank 1 A | 16 个 32 位元素 | +| `0x340` | Bank 1 B | 16 个 32 位元素 | +| `0x380` | Bank 1 C | 16 个 66 位元素，共 48 个 32 位字 | + +A 和 B 均按行优先方式存储。endpoint 写地址 0--15 对应 A，16--31 对应 B；endpoint +读地址 0--47 对应 C 的三字布局。双 Bank 允许一组数据计算时准备另一组，但计算核心 +本身一次只处理一个 Bank。 + +## 4. 乘法数据通路 + +核心包含四个 `pipelined_mult_32x32` 实例，并使用 `use_dsp="no"` 属性约束综合器将乘法 +映射到 LUT 逻辑。每个乘法器包含输入寄存、乘积寄存和输出寄存三个流水级，吞吐率为 +每周期一个乘积。 + +计算核心每周期选择一个输出元素 `(i,j)`，同时向四个乘法器发出 +`A[i][0..3]` 与 `B[0..3][j]`。流水线对齐后，四个 64 位乘积采用成对加法生成一个 +66 位结果。16 个输出元素连续发射，索引和 Bank 标识经过四级有效流水线与乘积对齐。 +因此稳态吞吐为每周期一个 C 元素，而不是逐项乘加的四周期结构。 + +当 Bank 0 完成且 Bank 1 已有待处理请求时，状态机可直接调用 `start_calc_bank` 切换 +Bank，不必先返回空闲态。最后一个有效结果写回时产生 `calc_done_pulse`，置位 done 并 +驱动电平型中断。 + +## 5. CRC32 数据通路 + +CRC 使用 IEEE 802.3 反射多项式 `0xedb8_8320`，初值为 `0xffff_ffff`，软件读取时执行 +末尾异或。每个 66 位 C 元素按低 32 位、高 32 位、最高 2 位补零三个字依次进入 +`crc32_word_next`。CRC 在计算结果有效时更新，与 CPU 或 DMA 是否读取 C 无关。 + +这一选择使快速评测可以关闭结果写回，只保留硬件计算与 CRC。CRC 顺序严格跟随输出 +元素发射顺序；整批任务开始时由序列器清零，Bank 切换和单组完成不会清零。 + +## 6. AXI 协议处理 + +写通道分别处理 AW、W 和 B 阶段，锁存 ID、burst 类型和起始地址；INCR burst 每次有效 +W 握手后地址增加 4。读通道锁存 AR 参数并连续产生 R beat，最后一拍置位 RLAST。 +无效写地址置位 error，响应码当前始终为 OKAY。输出 C 的组合读选择在当前地址上解析 +元素号和三字片段。 + +## 7. 验证要求 + +功能验证需要逐元素与 128 bit 或更宽的软件参考模型比较，覆盖全零、全 `0xffff_ffff`、 +单位矩阵和随机矩阵。协议验证需覆盖 AW/W 分离、R/B 反压、单 beat 与 burst、两个 Bank +连续请求和非法地址。CRC 应独立比较完整 192 字节输出序列。当前官方板测只读取最终 +CRC，证明了长批处理的端到端一致性，但不能替代逐元素和 AXI 边界测试。 diff --git a/doc/reports/system/modules/05_fft_accelerator.md b/doc/reports/system/modules/05_fft_accelerator.md new file mode 100644 index 0000000..2787ef9 --- /dev/null +++ b/doc/reports/system/modules/05_fft_accelerator.md @@ -0,0 +1,73 @@ +# 1024 点 FFT 加速器技术说明 + +## 1. 模块组成与数值格式 + +FFT 加速器由 `fft_controller`、五级 `SdfUnit` 流水、蝶形、延迟反馈存储、旋转因子 ROM +和复数乘法器构成。当前配置处理 1024 点复数序列，实部和虚部均为 16 位有符号定点数。 +AXI 窗口按 32 位字编址，每个字的低 16 位承载一个输入或输出分量，读取时对 16 位结果 +进行符号扩展。 + +FFT 的 AXI 控制器、输入输出 BRAM、SDF 数据通路和完成状态全部工作在 +`sys_clk/sys_resetn`。DMA 访问 FFT 窗口时不跨域；CPU 请求在到达共享从端前已经通过 +CPU--SYS AXI CDC。FFT 不使用 `mlkem_clk`，即使两者共享同一外部地址从端。 + +顶层 `FFT` 使用 Radix-2^2 单路径延迟反馈架构。五个 `SdfUnit` 的参数 M 依次为 1024、 +256、64、16 和 4，每级完成两层 radix-2 蝶形并处理相应旋转因子。输入要求按自然顺序 +连续提供，核心输出为位反转顺序；AXI 控制器在读输出 BRAM 时反转地址位，使软件观察到 +自然顺序结果。 + +## 2. 地址窗口 + +FFT 位于共享物理基址 `0x1f40_0000` 的高半区。 + +| 偏移 | 内容 | 容量 | +|---|---|---| +| `0x8000` | 输入实部 | 1024 个 32 位字，低 16 位有效 | +| `0x9000` | 输入虚部 | 1024 个 32 位字，低 16 位有效 | +| `0xa000` | 输出实部 | 1024 个符号扩展的 32 位字 | +| `0xb000` | 输出虚部 | 1024 个符号扩展的 32 位字 | +| `0xc000` | CSR | bits 3:0 状态，bits 7:4 控制 | + +CSR 控制 bit 4 为 start，状态 bit 0 为 busy，bit 1 为 done。写 start 同时清除旧 done； +计算完成后 done 保持，`fft_finish` 直接反映该状态。输入和输出窗口均支持 AXI INCR +burst，因此既可由 CPU 逐字访问，也可由 DMA 批量搬运。 + +## 3. 控制状态机 + +控制器包含 IDLE、LOAD、WAIT_OUT 和 DONE 四个状态。IDLE 检测 start；LOAD 在 1024 个 +周期内顺序读取输入实部和虚部 BRAM，并根据 BRAM 读延迟产生对齐的 `di_en`；WAIT_OUT +接收 FFT 流水线输出并写入输出 BRAM；收到第 1024 个有效输出后进入 DONE，再返回 IDLE。 + +busy 在 LOAD 和 WAIT_OUT 期间有效。输入 BRAM 与输出 BRAM均采用独立读写端口，CPU 或 +DMA 的窗口访问与计算侧顺序访问通过双端口结构隔离。软件不得在 busy 期间覆盖输入， +也不应在 done 前读取尚未完成的输出。 + +## 4. SDF 数据通路 + +每个 `SdfUnit` 含两级蝶形和两组延迟反馈缓存。计数器决定当前样本进入反馈存储还是参与 +加减运算。第二级蝶形输出根据当前阶段选择 `1`、`-j` 或 ROM 旋转因子，并通过复数乘法 +进入下一级。单路径结构每周期只传递一个复数样本，减少并行蝶形和存储端口数量。 + +`Butterfly` 对和、差各执行一次算术右移，相邻级使用不同的半舍入偏置以减小累计偏差。 +五个 SDF 单元合计执行十次除 2，因此总缩放因子为 `1/1024`。软件参考结果同样除以 +1024 后再与硬件比较。 + +复数乘法器计算四个有符号乘积并按 `WIDTH-1` 位右移恢复定点尺度。模块带有 +`use_dsp="no"` 属性，所有乘法映射到 LUT/CARRY 资源。该约束满足竞赛资源要求，但会 +增加 LUT 占用和组合路径压力。 + +## 5. 软件访问模式 + +CPU 路径逐字写入两个输入窗口、启动 FFT、轮询 done，再逐字读回两个输出窗口。DMA +路径使用两个 DMA 通道分别搬入实部和虚部，计算完成后再分别搬回输出。CPU 路径测量 +包含大量寄存器访问，DMA 路径测量包含四次批量搬运和一次计算，二者均属于端到端时间， +不能直接解释为纯 FFT 核延迟。 + +## 6. 验证与数值误差 + +板级程序使用相同的 1024 点多音输入和浮点 radix-2 DIT 软件参考。全部 1024 个点逐点 +比较，当前三次 CPU 路径和三次 DMA 路径的最大绝对误差均为实部 1、虚部 2，低于阈值 +8。CPU 路径端到端时间为 1,724,940 ns，DMA 路径为 296,730 ns；三次运行结果一致。 + +这些结果证明当前测试向量上的定点误差和数据搬运正确性。进一步验证应增加冲激、单频、 +满幅随机、接近溢出和复数输入，并检查连续 start、busy 期间非法写入以及 AXI 反压。 diff --git a/doc/reports/system/modules/06_mlkem_core.md b/doc/reports/system/modules/06_mlkem_core.md new file mode 100644 index 0000000..fd0d464 --- /dev/null +++ b/doc/reports/system/modules/06_mlkem_core.md @@ -0,0 +1,78 @@ +# ML-KEM 总控与算法数据通路技术说明 + +## 1. 功能范围 + +`mlkem_top` 实现 FIPS 203 ML-KEM 的 KeyGen、Encaps 和 Decaps 主数据通路。安全等级由 +运行时参数 `k_i` 选择：2、3、4 分别对应 ML-KEM-512、768、1024。模数固定为 3329， +多项式次数固定为 256，共享密钥长度为 32 字节。模块在 `start_i` 有效时锁存安全等级和 +操作码，运行期间不再读取外部配置。 + +三个等级共享同一比特流。片上存储按最大等级静态分配，循环边界、槽位基址、密钥长度和 +压缩参数由锁存的 K 动态计算。对应公钥长度为 800、1184、1568 字节，私钥长度为 1632、 +2400、3168 字节，密文长度为 768、1088、1568 字节。 + +## 2. 顶层接口 + +配置端口包括 3 位安全等级、2 位操作码和单拍 start。KeyGen 输入 256 位随机种子 d 和 z； +Encaps 输入消息 m，并在启动前通过字节端口装载公钥；Decaps 在启动前通过字节端口装载 +私钥和密文。`busy_o` 在非 IDLE 状态有效，`done_o` 在 ST_DONE 产生完成脉冲，`ss_o` +输出 256 位共享密钥。 + +公钥、私钥和密文不使用超宽并行端口，而是通过 8 位写接口和调试读回接口访问内部 BRAM。 +系统集成层在该字节接口外提供 AXI 寄存器路径和 32 位批量窗口。 + +`mlkem_top` 及 Keccak、采样、NTT、多项式运算和局部 BRAM 全部工作在 +`mlkem_clk/mlkem_resetn`。模块内部算子之间没有 CDC。来自 SYS 域的寄存器和批量窗口 +事务在进入 `mlkem_axi_slave` 前已通过完整 AXI CDC；完成中断先同步回 SYS 域。 + +## 3. 集中式控制状态机 + +模块使用 5 位集中式状态机调度算子和存储端口。KeyGen 路径依次执行 G 哈希、SampleNTT +生成矩阵、CBD 生成 s/e、前向 NTT、矩阵向量点乘、密钥编码和公钥哈希。各阶段通过 +系数 BRAM 和字节 BRAM 传递数据，不在阶段之间复制完整多项式总线。 + +Encaps 路径首先计算公钥哈希与 `G(m || H(ek))`，随后重新生成转置矩阵，解码公钥 t， +采样 y/e1/e2，对 y 执行 NTT，计算 u 和 v，最后按等级参数 `du/dv` 压缩并编码密文。 +共享密钥为 G 输出的 K 部分。 + +Decaps 路径解码并解压密文，解码私钥 s，对 u 执行 NTT，恢复消息 m'，再计算 +`G(m' || H(ek))` 和 `J(z || c)`。D6 重加密不复制第二套加密硬件，而是把 m' 和 r' +送回 Encaps 状态序列生成参考密文 c'。最后状态逐字节比较 c' 与输入 c，并选择正常密钥 +或隐式拒绝备用密钥。 + +比较循环不因首个不匹配字节提前退出，控制路径按完整密文长度运行。该行为是 RTL 的设计 +属性；当前 regional 板级日志没有专门注入篡改密文，因此现有系统报告不把负向隐式拒绝 +测试列为已验证结果。 + +## 4. 算子复用 + +Keccak-f[1600] 是面积最大的算子。SHA3/SHAKE 协议层、SampleNTT 和 CBD 在互斥状态中 +共享一个 `keccak_core`，输入由状态选择器复用，输出广播给当前活动消费者。NTT、逆 NTT、 +多项式基乘以及压缩/解压同样按状态复用，而不是为 KeyGen、Encaps 和 Decaps 分别复制。 + +该架构降低面积，但限制了状态间并行度。SampleNTT、CBD、NTT 和多项式乘法不能跨主状态 +重叠，整体延迟由各阶段串行累加。技术报告应将其描述为面积与吞吐之间的明确权衡。 + +## 5. 存储组织 + +系数数据使用三个主要存储库。`bank_a` 为 12 bit x 4096，存放 A 矩阵及部分临时多项式； +`bank_se` 为 12 bit x 2048，存放 s/e、y、u 等向量；`bank_t` 为 12 bit x 1024，存放 t、 +点乘累加、v 和 w。槽位以 256 个系数为单位，基址由 K、K^2 和当前算法阶段计算。 + +字节数据使用独立的 `ek_bram`、`dkp_bram`、`ct_bram` 和 `c_in_bram`。输入密文与重加密 +产生的参考密文分开存储，使最终比较可以同周期读取两者。Decaps 私钥装载地址还会把 +`dk_pke`、嵌入的公钥、H(ek) 和 z 分派到不同存储或寄存器。 + +## 6. 数值与资源约束 + +多项式系数采用 12 位模 q 表示。模乘通过流水化 Barrett 约简实现，相关乘法强制不使用 +DSP。NTT 使用四路 Banked BRAM 和双蝶形流水，点乘使用独立偶/奇 Bank。当前实现中 +ML-KEM 计算域目标频率为 76.923 MHz，最终时序结论以布局布线报告为准。 + +## 7. 验证边界 + +叶子算子应分别与软件或 Python 参考模型比较；顶层应按 FIPS 203 KAT 对公钥、私钥、 +密文和共享密钥逐字节比较；系统级还需验证 CPU 寄存器路径和 DMA 窗口路径。当前板级 +证据由 ML-KEM-512、768、1024 三个独立编译程序组成，每个程序对软件、CPU 和 DMA +路径各执行 100 次，现有日志的 FAILS 均为 0。该重复次数证明固定向量上的稳定性，不能 +表述为 900 个不同随机 KAT。 diff --git a/doc/reports/system/modules/07_mlkem_axi_frontend.md b/doc/reports/system/modules/07_mlkem_axi_frontend.md new file mode 100644 index 0000000..1d0f1ef --- /dev/null +++ b/doc/reports/system/modules/07_mlkem_axi_frontend.md @@ -0,0 +1,74 @@ +# ML-KEM AXI 前端与跨时钟域技术说明 + +## 1. 共享从端结构 + +`fft_mlkem_axi_slave` 将 Crossbar Slave 6 分成 FFT 和 ML-KEM 两个内部目标。写地址或读 +地址的 bits 15:12 小于等于 3 时选择 ML-KEM；FFT 使用 0x8000--0xc000 窗口。ML-KEM +以外且未被 FFT 定义的地址仍会路由到 FFT 前端，但返回零或忽略写入，因此软件只应使用 +文档化区间。 + +AXI 写地址和写数据通道彼此独立。共享前端在 AW 握手时锁存 `write_sel`，直到对应 B +响应完成才释放；读路径在 AR 握手时锁存 `read_sel`，直到带 RLAST 的最后一个 R beat +完成才释放。响应选择不使用实时地址，避免 burst 期间地址变化导致响应串到另一个内部 +从端。 + +FFT 控制器直接工作在 `sys_clk`。ML-KEM 的完整 AXI 五通道通过 `Axi_CDC` 跨入 +`mlkem_clk`，之后由 `mlkem_axi_slave` 和 `mlkem_top` 在同一计算时钟域处理。ML-KEM +中断从计算域返回系统域时经过两级同步寄存器。 + +XDC 将 SYS 与 ML-KEM 声明为异步时钟组，因此跨域有效性由 `Axi_CDC` 的双时钟 FIFO +保证，而不是由 PLL 同源关系或普通时序路径保证。具体约束和复位关系见 +[时钟域、复位与跨时钟域设计说明](00_clock_domains.md)。 + +## 2. ML-KEM 寄存器接口 + +ML-KEM 物理基址为 `0x1f40_0000`，CPU 未缓存映射为 `0xbf40_0000`。 + +| 偏移 | 名称 | 说明 | +|---|---|---| +| `0x000` | CTRL | bit 0 启动，bit 1 软复位 | +| `0x004` | STATUS | bit 0 busy，bit 1 done，bit 2 preload busy；done 为 W1C | +| `0x008` | CONFIG | bits 2:0 为 K，bits 5:4 为操作码 | +| `0x010--0x02c` | D | 32 字节 KeyGen 随机种子 | +| `0x030--0x04c` | Z | 32 字节隐式拒绝种子 | +| `0x050--0x06c` | MSG | 32 字节 Encaps 消息 | +| `0x070--0x08c` | SS | 32 字节共享密钥，只读 | +| `0x100/104/108` | PRE_SEL/ADR/DAT | 逐字节预装载接口 | +| `0x10c/110/114` | RDB_SEL/ADR/DAT | 逐字节读回接口 | +| `0x1000` | EK window | 公钥批量输入或输出窗口 | +| `0x2000` | DK window | 私钥批量输入或输出窗口 | +| `0x3000` | CT window | 密文批量输入或输出窗口 | + +CONFIG 的操作码 0、1、2 分别表示 KeyGen、Encaps、Decaps。软件必须在启动前完成参数与 +输入装载，并在 busy 期间保持配置不变。done 保持到软件 W1C，便于轮询程序不丢失短脉冲。 + +## 3. 字节端口与批量窗口 + +传统 PRE 接口通过 PRE_SEL 选择 ek、dk 或 c，通过 PRE_ADR 设置字节地址，向 PRE_DAT +写入低 8 位并自动递增地址。读回接口以同样方式选择 ek、完整 dk 或 ct。该路径便于调试， +但每个字节至少需要一次 AXI 寄存器事务，传输大密钥时开销较高。 + +三个批量窗口把 AXI 32 位 beat 分解为最多四个有效字节。写状态机依据 WSTRB 跳过无效 +lane，将字节地址、选择和数据送入核心 BRAM 写口，并等待内部确认后继续下一个 lane。 +读状态机按字节地址读取内部 BRAM，补偿同步读延迟后组装 32 位 RDATA。窗口支持 INCR +burst，使通用 DMA 能以少量控制事务搬运完整公钥、私钥和密文。 + +批量窗口不改变密码核心的算法执行时间，但显著减少 CPU 逐字节访问开销。性能报告应把 +CPU 寄存器路径和 DMA 窗口路径分别列出，不能把两者差值解释为核心计算加速。 + +## 4. 事件控制与复位 + +CTRL start、软复位和 done clear 在 `mlkem_axi_slave` 中均转换为 toggle 事件，再通过 +边沿检测产生单拍控制。软复位事件经计数器展宽，形成核心局部复位。预装载写入使用 +request/ack toggle，使 AXI 写 beat 只有在目标字节被核心侧接收后才完成。 + +外层 `Axi_CDC` 已承担 SYS--ML-KEM 的 AXI 通道跨域；前端内部的 toggle 机制主要用于 +把寄存器写动作转换为不会重复触发的单拍事件，并串行化字节预装载。系统复位有效期间， +所有 AXI valid、start 和预装载事件必须保持无效。 + +## 5. 协议验证重点 + +共享前端需要覆盖 AW 与 W 不同拍到达、B/R 反压、ML-KEM 与 FFT 交替访问、长 burst +末拍、WSTRB 空洞以及读写并发。ML-KEM 窗口还需验证 800--3168 字节的非统一长度、最后 +一个不满字、BRAM 读延迟和软复位中止。当前板级 CPU 与 DMA 双路径证明了常用顺序访问， +但不等价于覆盖所有并发和异常协议组合。 diff --git a/doc/reports/system/modules/08_mlkem_hash_sampling.md b/doc/reports/system/modules/08_mlkem_hash_sampling.md new file mode 100644 index 0000000..cf1750e --- /dev/null +++ b/doc/reports/system/modules/08_mlkem_hash_sampling.md @@ -0,0 +1,62 @@ +# ML-KEM Keccak、SHA3 与采样模块技术说明 + +## 1. Keccak-f[1600] 置换核 + +`keccak_core` 保存 1600 位状态，并调用组合 `keccak_round` 每周期执行一轮 +Keccak-f[1600]。轮函数包含 theta、rho、pi、chi 和 iota 五个步骤，轮常数由 5 位轮计数 +选择。默认执行 24 轮，输入在 `valid_i && ready_o` 时装载，最后一轮结果通过 +`valid_o/ready_i` 交付；接收端反压时保持最终状态。 + +该结构只实例化一份 1600 位轮函数，单次置换约需 24 个计算周期，面积主要来自宽 XOR、 +移位布线和 chi 非线性逻辑。它不是 24 轮完全展开的单周期实现，也不是每周期接收一个 +新状态的深流水实现。 + +本文件中的 Keccak、SHA3/SHAKE、SampleNTT 和 CBD 均位于 `mlkem_clk` 域。共享接口是 +同一时钟域内的 valid/ready 复用，不是 CDC。SYS--ML-KEM 跨域终止于外层 AXI 前端。 + +## 2. SHA3/SHAKE 协议层 + +`sha3_top_shared` 在置换核外实现吸收、填充、多块状态累积和输出提取。单块模式支持 +KeyGen 使用的 G、SHA3-256 H、SHAKE-256 J，以及对完整 64 字节消息执行的 SHA3-512 G。 +模块依据模式选择 576 位或 1088 位 rate，并加入 SHA3 或 SHAKE 域分隔后执行 pad10*1。 + +多块模式面向长度随安全等级变化的公钥哈希。调用方预先构造 1088 位 rate block，并用 +`mb_last_i` 标记最终块。模块将新块异或到累计 sponge 状态，调用共享 Keccak，最后从 +低 256 位提取摘要。多块状态在一次消息结束前保持，不会在块间重新初始化。 + +ML-KEM 顶层以状态机选择当前 Keccak 消费者。SHA3、SampleNTT 和 CBD 在算法调度上互斥， +因此可以共享一个置换核；若未来引入跨状态并行，必须增加显式仲裁和每个消费者独立的 +sponge 上下文，不能继续依赖状态互斥假设。 + +## 3. SampleNTT 拒绝采样 + +`sample_ntt_sync_shared` 实现 FIPS 203 SampleNTT。模块吸收 32 字节 rho 以及行列索引 +`j,i`，形成 34 字节 SHAKE-128 输入。挤出字节流按每 3 字节拆成两个 12 位候选值，只有 +候选值小于 q=3329 时才输出。模块持续采样直到产生 256 个有效系数。 + +输出使用 `coeff_valid_o/coeff_ready_i` 握手，反压时保持当前系数和索引。拒绝采样的运行 +周期依赖候选值分布，因此系统 FSM 依据有效系数计数结束，而不是使用固定延迟。对固定 +rho 和索引，输出必须与软件 SampleNTT 逐系数一致。 + +## 4. 中心二项分布采样 + +`sample_cbd_sync_shared` 使用 SHAKE-256 PRF 生成伪随机字节，再实现 CBD_eta。eta=2 时， +每个系数消耗 4 bit，计算两组 2 bit 的汉明重量差；eta=3 时，每个系数消耗 6 bit，计算 +两组 3 bit 的汉明重量差。ML-KEM-512 的 eta1 为 3，其余等级的 eta1 为 2，eta2 始终为 2。 + +CBD 输出转换到模 q 表示后，以 valid/ready 逐系数写入系数 Bank。当前优化版本对 CBD +输出到 Bank 写入路径增加寄存，以缩短组合路径；地址和有效信号必须与该流水级同步延迟。 + +## 5. 共享接口约束 + +三个消费者向共享 Keccak 提供状态、valid 和 ready。选择信号由 ML-KEM 主状态直接推导， +未选中的消费者不能认为广播输出属于自己。消费者内部必须只在活动上下文采样 +`kc_valid_o`。复位需要同时清除 Keccak busy、各 sponge 状态、候选字节缓存和输出计数， +否则下一次请求可能继承前一消息状态。 + +## 6. 验证方法 + +Keccak 应使用标准空消息和多块测试向量逐 bit 比较。SHA3/SHAKE 层应覆盖 rate 边界前后 +的消息长度、域分隔和多块最后一块填充。SampleNTT 应比较全部 256 个系数并统计拒绝 +候选数；CBD 应覆盖 eta=2/3、输出反压和连续请求。顶层 KAT 通过能够发现大部分功能错误， +但叶子级握手、边界填充和共享仲裁仍需要独立测试平台验证。 diff --git a/doc/reports/system/modules/09_mlkem_polynomial_arithmetic.md b/doc/reports/system/modules/09_mlkem_polynomial_arithmetic.md new file mode 100644 index 0000000..1534bd0 --- /dev/null +++ b/doc/reports/system/modules/09_mlkem_polynomial_arithmetic.md @@ -0,0 +1,72 @@ +# ML-KEM 多项式运算模块技术说明 + +## 1. 运算域与数据表示 + +多项式运算位于环 `Z_q[x]/(x^256+1)`，其中 q=3329。系数在硬件中使用 12 位无符号模 q +表示。该组模块包括前向/逆向 NTT、Barrett 模乘、NTT 域 basecase 乘法、多项式加减以及 +Compress/Decompress。算子使用 valid/ready 或 start/done 接口，由 `mlkem_top` 分时复用。 + +本文件中的 NTT、模乘、basecase、多项式加减、压缩模块及其局部 BRAM 均工作在 +`mlkem_clk/mlkem_resetn`。算子与 `mlkem_top` 之间是单时钟域同步接口，不包含独立 CDC。 +地址、valid 和数据的延迟对齐属于流水线时序问题，而不是跨时钟域问题。 + +## 2. NTT 核 + +`ntt_core` 实现 256 点前向和逆向 NTT。系数存储由 `coeff_bram_4way` 划分为四个 Bank， +每个 Bank 具有同步读和写端口。地址生成器把同周期的两个蝶形对映射到互不冲突的 Bank， +从而同时处理四个系数。 + +数据通路包含两个 `butterfly_unit_pipe`。第 t 周期发出 BRAM 地址，下一周期取得系数， +随后进入流水化蝶形和 Barrett 模乘；写地址通过同长度延迟链与结果对齐。每层发射结束后 +等待流水排空，再更新层号和旋转因子索引。逆 NTT 在七层变换后复用模乘流水线执行末尾 +缩放。 + +`zeta_rom` 保存 128 个 12 位旋转因子。前向和逆向变换使用不同的索引方向及蝶形公式。 +验证不能只比较 NTT 后的频域值，还应执行 INTT(NTT(a)) 并检查恢复系数，覆盖 Bank 地址 +冲突和最后一层流水排空。 + +## 3. Barrett 模约简与蝶形 + +`barrett_mul_pipe` 先计算 12x12 位乘积，再用常数 5039 估计除以 q 的商，计算 +`r = p - q_est*q`，最后通过条件减 q 把结果限制到 `[0,q)`。各乘法级之间加入寄存器， +并以 `use_dsp="no"` 约束映射到 LUT。蝶形单元在模乘前后执行模加或模减，并将 valid +沿流水线传递。 + +商估计只在限定输入范围内成立，因此上游必须保证输入系数已经规范化。叶子测试应覆盖 +0、q-1、乘积最大值和所有修正分支，不能仅使用随机中间值。 + +## 4. NTT 域多项式乘法 + +`poly_mul_sync` 对 256 个频域系数按相邻偶/奇系数组成 128 个 basecase。每个 basecase +结合对应 zeta 计算两个输出系数。输入多项式写入独立 Bank，控制器按 LOAD、RUN 和 +OUTPUT 阶段管理装载、流水计算和结果输出。 + +`basecase_mul_pipe` 并行计算多个模乘项，再完成模加。当前版本将系数存储改为偶/奇 +Banked BRAM，减少离散寄存器和 LUTRAM。受同步 BRAM 读延迟和发射控制影响，RUN 阶段 +每两周期发射一个 basecase。输出采用 valid/ready，接收端反压时不得覆盖尚未消费的系数。 + +`poly_arith_sync` 提供系数级模加和模减，用于点乘累加、噪声相加以及解封装中的差值。 +运算结果在每一步规范化到模 q 范围，避免后续模乘输入超界。 + +## 5. 压缩与解压缩 + +`comp_decomp_sync` 实现 FIPS 203 的 Compress_d 和 Decompress_d。压缩近似计算 +`round(2^d*x/q) mod 2^d`，解压计算 `round(q*y/2^d)`。当前流水线使用常数乘法和移位 +近似除法，避免综合组合除法器；模式、d 和 valid 随数据经过各级寄存。 + +输出端具有保持寄存器。当下游未 ready 时，结果和 valid 保持；输入 ready 由流水线及 +输出可用性共同决定，因此文档和测试不应假设任意反压下始终每周期接收一个系数。需要 +分别覆盖 d=1、4、5、10、11 等算法实际参数，并与精确整数公式逐值比较。 + +## 6. 存储和调度约束 + +NTT 核和多项式乘法器各自包含局部 BRAM，ML-KEM 顶层还包含全局系数 Bank。进入算子前 +需要将目标多项式装入局部存储，完成后再流式写回全局 Bank。这种结构简化端口仲裁，但 +增加装载和回写周期。主 FSM 保证同一全局 Bank 端口在一个状态内只有一个所有者。 + +## 7. 验证边界 + +叶子级验证应覆盖 NTT、INTT、basecase、完整多项式乘法、模加减和压缩解压，并对所有 +256 个系数比较。顶层 KAT 能验证算子组合后的算法结果，但当多个误差互相抵消时不能定位 +根因。实现后还需检查 BRAM 推断、DSP=0 和 valid/地址延迟对齐；这些属于结构验证，不能 +仅由软件结果正确推出。 diff --git a/doc/reports/system/modules/10_software_runtime.md b/doc/reports/system/modules/10_software_runtime.md new file mode 100644 index 0000000..c2b4765 --- /dev/null +++ b/doc/reports/system/modules/10_software_runtime.md @@ -0,0 +1,74 @@ +# 软件运行时与测试程序技术说明 + +## 1. 软件职责 + +软件位于 `sdk/software/examples/`，负责构造输入、配置物理地址和寄存器、启动硬件、等待 +完成、读取结果并与参考值比较。算法的高开销数据通路由硬件完成；软件保留参考实现和 +诊断输出，用于区分计算错误、数据搬运错误和接口错误。 + +CPU 访问外设时使用 `0xbfxx_xxxx` 未缓存映射，DMA 描述符使用 `0x1xxx_xxxx` 物理地址。 +软件缓冲区通过未缓存别名读写，避免数据缓存中的旧副本与 DMA 结果不一致。该地址转换是 +驱动正确性的一部分，而不是性能优化细节。 + +软件指令在 `cpu_clk` 域执行，外设寄存器和 DMA 数据面主要位于 `sys_clk` 域，ML-KEM +核心位于 `mlkem_clk` 域。软件不直接处理相位关系，而是通过 AXI valid/ready、状态保持 +和 W1C 完成语义与异步硬件交互。CPU 周期计数包含跨域 FIFO 和外设响应延迟。 + +## 2. DMA 驱动 + +`dma.c/dma.h` 将通道寄存器映射为 C 结构体。驱动先检查 busy，再写源地址、目的地址、 +字节数和 tag，配置 32 位 beat 与 burst 长度后置位 start。`dma_wait_polling` 轮询 done， +完成后通过 W1C 清除状态。 + +FFT 驱动使用 AxLEN=15，即 16 beat burst；矩阵快速路径使用 AxLEN=63，即 64 beat 配置。 +实际末 burst 长度由硬件按剩余字节裁剪。当前驱动遇到通道 busy 时直接返回，没有错误码； +轮询也没有软件超时。因此调用方必须保证通道所有权，正式运行时应增加返回值和超时处理。 + +## 3. 矩阵乘法评测程序 + +`asm/user-sample.c` 面向官方 5000 组评测。程序配置矩阵批处理序列器的源地址、目的地址、 +组数和 stride，发送 `MATMUL_START`，启动硬件并轮询序列器 done。完成后读取矩阵加速器 +CRC32，并以紧凑 UART 写入输出 CRC 和 `MATMUL_DONE`。 + +快速启动配置使用 `start_matmul_fast.S` 缩短通用 C 运行时初始化。UART 输出避免 `printf` +格式化开销，并按 FIFO 可用状态分段写入。设置 `MATMUL_WRITEBACK_RESULTS=0` 时，序列器 +跳过 5000 组结果写回，但矩阵核心仍对全部 66 位结果更新 CRC。 + +官方计时从接收到 START 到接收到 DONE，因此软件启动顺序、串口发送和完成尾部均会进入 +端到端时间。当前 regional 证据包含三次运行，中位数为 6.944404 ms，CRC 均匹配。该数据 +不包含 `test_1` 中的后续优化。 + +## 4. FFT 测试程序 + +`fft/main.c` 通过 CPU 逐字写入 1024 个实部和虚部，启动 FFT，读回全部输出，再执行浮点 +radix-2 DIT 软件参考。`fft_dma/main.c` 使用两个 DMA 通道搬入输入，计算完成后搬回输出。 +两者都对 1024 个 bin 计算最大实部和虚部绝对误差，并以阈值 8 判定。 + +软件参考结果除以 1024，与硬件每级缩放后的输出尺度一致。当前 CPU 和 DMA 路径各有三份 +板级日志，结果完全一致。硬件时间为端到端测量，CPU 路径包含 4096 次窗口读写，DMA +路径包含四次搬运，因此两者反映接口方案而非单独的 FFT 流水线周期。 + +## 5. ML-KEM 测试程序 + +`mlkem_test/main.c` 为每个安全等级分别构建和运行。当前源码通过 `LEVELS` 数组选择本次 +编译的 K，区域赛证据中的 512、768、1024 来自三个独立程序，不是一个程序内并行执行。 +每个程序使用固定 KAT count 0 输入，分别运行软件参考、CPU 寄存器路径和 DMA 窗口路径。 + +CPU 路径通过 PRE/RDB 接口逐字节装载和读取密钥、密文；DMA 路径通过 EK、DK、CT +窗口批量搬运。两条硬件路径均执行 KeyGen、Encaps 和 Decaps，并检查封装/解封共享密钥 +一致性以及固定黄金值。每条路径重复 100 次，记录失败次数和平均 CPU 周期。 + +现有测试的重复输入用于稳定性和性能统计，不代表不同随机 KAT。程序未篡改密文触发负向 +隐式拒绝，因此报告只能说明正常输入路径通过，不能把 RTL 中存在的拒绝逻辑表述为已完成 +板级负向测试。 + +## 6. 构建与证据输出 + +报告工作流只编译 `asm`、`fft`、`fft_dma`、`mlkem_test` 和 `mlkem_hello`。FFT 与 +ML-KEM 的通用 SoC 软件仿真耗时较长，当前功能数据采用板级 UART 日志。日志使用固定 +机器可读字段，例如 `FFT_RESULT`、`MLKEM*_FAILS`、平均周期和完成标志，指标脚本从这些 +字段聚合报告数据。 + +软件测试的通过条件包括算法结果、DMA 完成和输出标记，不能只依据程序返回。后续改动 +寄存器布局、缓存属性、时钟频率或 UART 输出顺序时，必须同步更新驱动、测试判定和指标 +解析脚本。 diff --git a/doc/reports/system/modules/README.md b/doc/reports/system/modules/README.md new file mode 100644 index 0000000..ba4f7dd --- /dev/null +++ b/doc/reports/system/modules/README.md @@ -0,0 +1,48 @@ +# 自研模块技术说明索引 + +本目录记录区域赛仓库中由项目组设计、修改或完成系统级集成的模块。技术说明以当前 +`main` 分支 RTL 和软件源码为依据，服务于系统设计报告的后续重写。文档中的“已实现” +表示源码中存在相应数据通路或控制逻辑；“已验证”仅指当前 `evidence/` 中能够直接支持 +的结论，两者不混用。 + +OpenLA500 处理器、UART、DVI、基础 SRAM 控制器以及赛事提供的 SoC 框架不作为自研 IP +列入。项目组对这些模块的地址连接、时钟连接和中断集成记录在 SoC 集成说明中，但不把 +其内部实现归入项目贡献。 + +| 文档 | 主要 RTL 或软件 | 技术边界 | +|---|---|---| +| [时钟域、复位与 CDC](00_clock_domains.md) | `clk_pll`、`rst_sync`、`Axi_CDC`、`soc.xdc` | 三时钟域归属、复位链、跨域协议和约束模型 | +| [SoC 集成与时钟复位](01_soc_integration.md) | `rtl/soc_top.v`、`rst_sync.v` | 地址空间、主从互连、时钟域、复位和中断集成 | +| [通用 DMA 子系统](02_dma_subsystem.md) | `rtl/ip/cdma/snix_*.sv` | 四通道 DMA、AXI 搬运、本地 endpoint 和仲裁 | +| [矩阵批处理序列器](03_matmul_batch_sequencer.md) | `cdma_matmul_bridge.sv` | 5000 组任务调度、双 Bank 流水和可选结果写回 | +| [矩阵乘法加速器](04_matmul_accelerator.md) | `matmul_axi_slave.v` | 4x4 无符号矩阵乘法、AXI/endpoint、CRC32 | +| [FFT 加速器](05_fft_accelerator.md) | `rtl/ip/fft/*.v` | 1024 点定点 FFT、SDF 数据通路和 AXI 存储窗口 | +| [ML-KEM 总控与算法数据通路](06_mlkem_core.md) | `mlkem_top.v` | 三等级、三操作、集中式 FSM 和片上存储组织 | +| [ML-KEM AXI 前端与 CDC](07_mlkem_axi_frontend.md) | `fft_mlkem_axi_slave.v`、`mlkem_axi_slave.v` | 共享地址窗口、批量数据窗口和跨时钟域握手 | +| [Keccak 与采样模块](08_mlkem_hash_sampling.md) | `sha3/`、`sample_ntt/`、`sample_cbd/` | SHA3/SHAKE、拒绝采样和 CBD 采样 | +| [多项式运算模块](09_mlkem_polynomial_arithmetic.md) | `ntt/`、`poly_mul/`、`comp_decomp/` | NTT、基乘、模约简、压缩与解压缩 | +| [软件运行时与测试程序](10_software_runtime.md) | `sdk/software/examples/{asm,fft,fft_dma,mlkem_test}` | 寄存器驱动、DMA 调度、参考模型和结果判定 | + +文档中的地址均为物理地址，除非明确写为 CPU 未缓存虚拟地址。AXI 信号名沿用 RTL， +寄存器偏移以字节为单位。频率和资源数据属于当前 regional 仓库，不包含 `test_1` 中的 +后续矩阵乘法优化。 + +## RTL 模块覆盖说明 + +当前 SoC 有效层次中的计算和搬运模块均已纳入上述文档。DMA 说明覆盖 +`snix_axil_cdma_mux`、`snix_axi_mm2mm`、`snix_axis_fifo` 和 `snix_sync_fifo`；矩阵说明 +覆盖 `matmul_axi_slave`、`pipelined_mult_32x32` 和 `cdma_matmul_bridge`；FFT 说明覆盖 +`fft_controller`、`FFT`、`SdfUnit`、`Butterfly`、`Multiply`、`DelayBuffer` 和 `Twiddle`。 + +ML-KEM 说明覆盖当前集成层次中的 `fft_mlkem_axi_slave`、`mlkem_axi_slave`、 +`mlkem_top`、`keccak_core`、`keccak_round`、`sha3_top_shared`、 +`sample_ntt_sync_shared`、`sample_cbd_sync_shared`、`ntt_core`、`coeff_bram_4way`、 +`butterfly_unit_pipe`、`barrett_mul_pipe`、`poly_mul_sync`、`basecase_mul_pipe`、 +`poly_arith_sync`、`comp_decomp_sync`、`zeta_rom`、`poly_mul_zeta_rom`、`pipeline_reg`、 +`skid_buffer`、`sd_bram` 和 `s_bram`。 + +仓库还保留 `snix_axi_cdma`、`snix_axi_cdma_csr`、`snix_async_fifo`、 +`snix_register_slice`，以及非共享版 `sha3_top`、`sample_ntt_sync`、`sample_cbd_sync`、 +旧版 `ntt_sync`、`butterfly_unit`、`barrett_mul` 和 `basecase_mul`。这些文件用于早期方案、 +叶子测试或兼容参考，当前 `soc_top`/`mlkem_top` 未实例化，因而不作为独立系统模块另写 +性能结论。若后续重新接入，应先更新本索引及对应技术说明。 diff --git a/doc/reports/system/report_metrics.tex b/doc/reports/system/report_metrics.tex index 180efb2..0c777f3 100644 --- a/doc/reports/system/report_metrics.tex +++ b/doc/reports/system/report_metrics.tex @@ -1,6 +1,6 @@ % Generated values may be refreshed with: make metrics % Evidence status is intentionally explicit so stale data is not presented as current. -\newcommand{\EvidenceRevision}{1b51f28（历史报告，待复测）} +\newcommand{\EvidenceRevision}{d456463（当前 evidence）} \newcommand{\EvidenceDate}{2026-07-15} \newcommand{\CpuFreqMHz}{33.333} @@ -24,24 +24,27 @@ \newcommand{\StaticPower}{0.142} \newcommand{\PowerConfidence}{Low（未回标活动率）} -\newcommand{\MlkemFiveTwelveSW}{2,594,034} -\newcommand{\MlkemFiveTwelveCPU}{200,471} +\newcommand{\MlkemFiveTwelveSW}{2,592,854} +\newcommand{\MlkemFiveTwelveCPU}{198,778} \newcommand{\MlkemFiveTwelveDMA}{52,995} -\newcommand{\MlkemSevenSixtyEightSW}{4,065,123} -\newcommand{\MlkemSevenSixtyEightCPU}{296,193} -\newcommand{\MlkemSevenSixtyEightDMA}{80,648} -\newcommand{\MlkemTenTwentyFourSW}{6,041,204} -\newcommand{\MlkemTenTwentyFourCPU}{404,476} -\newcommand{\MlkemTenTwentyFourDMA}{113,273} +\newcommand{\MlkemSevenSixtyEightSW}{4,064,254} +\newcommand{\MlkemSevenSixtyEightCPU}{293,717} +\newcommand{\MlkemSevenSixtyEightDMA}{80,643} +\newcommand{\MlkemTenTwentyFourSW}{6,036,553} +\newcommand{\MlkemTenTwentyFourCPU}{401,177} +\newcommand{\MlkemTenTwentyFourDMA}{113,261} -\newcommand{\FftCpuNs}{1,695,360} -\newcommand{\FftDmaNs}{407,310} -\newcommand{\FftSoftwareNs}{274,786,920} -\newcommand{\FftCpuSpeedup}{161.94} -\newcommand{\FftDmaSpeedup}{674.64} -\newcommand{\FftMaxError}{Re=7，Im=6（按现有日志逐点估计，待程序直接输出）} +\newcommand{\FftCpuNs}{1,724,940} +\newcommand{\FftDmaNs}{296,730} +\newcommand{\FftSoftwareNs}{245,632,500} +\newcommand{\FftCpuSpeedup}{142.53} +\newcommand{\FftDmaSpeedup}{827.80} +\newcommand{\FftMaxError}{Re=1，Im=2} \newcommand{\MatmulGroups}{5,000} -\newcommand{\MatmulBoardMs}{5.213592} -\newcommand{\MatmulScore}{99.56\%} +\newcommand{\MatmulRuns}{3} +\newcommand{\MatmulBoardMinMs}{6.936468} +\newcommand{\MatmulBoardMs}{6.944404} +\newcommand{\MatmulBoardMaxMs}{6.950307} +\newcommand{\MatmulScore}{96.54\%} \newcommand{\MatmulCrcStatus}{PASS} diff --git a/doc/reports/system/system_arch.png b/doc/reports/system/system_arch.png index 7ab6915..ac4e777 100644 Binary files a/doc/reports/system/system_arch.png and b/doc/reports/system/system_arch.png differ diff --git a/doc/reports/system/system_design_report.pdf b/doc/reports/system/system_design_report.pdf index fb8fb71..cfed6a1 100644 Binary files a/doc/reports/system/system_design_report.pdf and b/doc/reports/system/system_design_report.pdf differ diff --git a/doc/reports/system/system_design_report.tex b/doc/reports/system/system_design_report.tex index 1bb0f6f..1510d94 100644 --- a/doc/reports/system/system_design_report.tex +++ b/doc/reports/system/system_design_report.tex @@ -1,458 +1,594 @@ -\documentclass[11pt,a4paper,twoside]{ctexart} +% ============================================================================= +% CICIEC 2026 Loongson Regional — System Design Report +% 基于龙芯SoC的后量子密码与矩阵运算加速系统设计报告 +% ============================================================================= -\usepackage[top=2.45cm,bottom=2.45cm,left=2.65cm,right=2.65cm]{geometry} +\documentclass[11pt,a4paper,twoside]{article} + +% ---- Packages ---- +\usepackage[UTF8,heading=true]{ctex} +\usepackage[top=2.5cm,bottom=2.5cm,left=2.8cm,right=2.8cm]{geometry} +\usepackage{fancyhdr} \usepackage{graphicx} \usepackage{booktabs} -\usepackage{tabularx} -\usepackage{array} \usepackage{amsmath,amssymb} -\usepackage{xcolor} -\usepackage{enumitem} -\usepackage{fancyhdr} \usepackage{hyperref} \usepackage{caption} -\usepackage{placeins} +\usepackage{enumitem} \usepackage{float} -\usepackage{listings} -\usepackage[normalem]{ulem} +\usepackage{longtable} +\usepackage{multirow} +\usepackage{array} +\usepackage{xcolor} -\definecolor{accent}{HTML}{1F4E79} -\definecolor{lightblue}{HTML}{EAF2F8} -\definecolor{lightgray}{HTML}{F3F4F6} -\hypersetup{colorlinks=true,linkcolor=accent,urlcolor=accent,citecolor=accent} -\captionsetup{font=small,labelfont=bf,skip=5pt} -\setlength{\parindent}{2em} -\setlength{\parskip}{3pt plus 1pt minus 1pt} -\setlength{\emergencystretch}{2em} -\setlength{\textfloatsep}{12pt plus 3pt minus 2pt} -\setlength{\intextsep}{10pt plus 2pt minus 2pt} -\renewcommand{\arraystretch}{1.18} -\setlist[itemize]{leftmargin=2em,itemsep=2pt,topsep=3pt} -\pagestyle{fancy} -\fancyhf{} -\fancyhead[LO,RE]{龙芯 SoC 异构加速系统设计报告} -\fancyhead[RO,LE]{\thepage} +% ---- Page style ---- \setlength{\headheight}{14pt} -\lstset{basicstyle=\ttfamily\small,breaklines=true,frame=single,backgroundcolor=\color{lightgray},numbers=none} -\newcolumntype{Y}{>{\raggedright\arraybackslash}X} -\newcommand{\code}[1]{\texttt{#1}} -\newcommand{\pending}{\textcolor{red!70!black}{待当前版本复测}} +\pagestyle{fancy} +\fancyhead[LO,RE]{系统设计报告} +\fancyhead[RO,LE]{\thepage} +\fancyhead[CO,CE]{} +\fancyfoot[C]{\thepage} +\renewcommand{\headrulewidth}{0.4pt} +\renewcommand{\footrulewidth}{0pt} -\input{report_metrics.tex} +% ---- Spacing ---- +\setlength{\parskip}{4pt plus 2pt minus 1pt} +\setlength{\parindent}{2em} +\setlength{\intextsep}{6pt plus 2pt} +\setlength{\textfloatsep}{8pt plus 2pt} +\captionsetup{skip=4pt} + +% ---- Hyperlinks ---- +\hypersetup{ + colorlinks=true, + linkcolor=black, + citecolor=black, + urlcolor=blue +} + +% ---- Import auto-generated metrics ---- +% Generated by tools/run_report_tests.sh refresh — do not edit manually +\input{report_metrics} + +% ---- Custom commands ---- +\newcommand{\Zq}{\mathbb{Z}_q} +\newcommand{\etal}{\textit{et al.}} +\newcommand{\tabincell}[2]{\begin{tabular}{@{}#1@{}}#2\end{tabular}} \begin{document} +% =========================================================================== +% TITLE PAGE +% =========================================================================== \begin{titlepage} \thispagestyle{empty} \begin{center} -\vspace*{20pt} -\includegraphics[width=0.42\textwidth]{logo_cicc.png} -\vspace{28pt} + \vspace*{2cm} -{\fontsize{20pt}{28pt}\selectfont\bfseries 第十届全国大学生集成电路创新创业大赛\par} -\vspace{54pt} -{\fontsize{25pt}{34pt}\selectfont\bfseries 基于龙芯 SoC 的后量子密码与矩阵运算加速系统\par} -\vspace{16pt} -{\fontsize{17pt}{24pt}\selectfont 系统设计与验证报告\par} + \includegraphics[width=0.45\textwidth]{logo_cicc.png} + + \vspace{1.5cm} + + {\LARGE\heiti 系统设计报告} + + \vspace{0.8cm} + + {\Large\heiti 基于龙芯SoC的后量子密码与矩阵运算加速系统} + + \vspace{2.0cm} + + \begin{tabular}{rl} + \textbf{参赛队伍：} & \underline{\hspace{5cm}} \\ + \textbf{赛\quad{}题：} & \underline{龙芯中科杯} \\ + \textbf{竞赛名称：} & \underline{CICIEC 2026 第十届全国大学生集成电路创新创业大赛} \\ + \textbf{所属赛区：} & \underline{\hspace{5cm}} \\ + \textbf{提交日期：} & \underline{2026年7月} \\ + \textbf{文档版本：} & \underline{\EvidenceRevision{} — \EvidenceDate{}} \\ + \end{tabular} + + \vfill \end{center} - -\vfill -\noindent\begin{tabularx}{\textwidth}{>{\bfseries}p{3.2cm}X} -参赛杯赛 & 龙芯中科杯 \\ -队伍编号 & CICC1008439 \\ -团队名称 & 碳基生物 \\ -目标器件 & Xilinx Artix-7 XC7A200T-1 \\ -证据版本 & \EvidenceRevision \\ -报告日期 & \EvidenceDate \\ -\end{tabularx} -\vspace{22pt} \end{titlepage} -\pagenumbering{Roman} -\section*{摘要} -\addcontentsline{toc}{section}{摘要} -本项目在赛事提供的 LoongArch32r SoC 框架上集成 ML-KEM、1024 点 FFT 和 -4$\times$4 矩阵乘法三类专用加速器，并以四通道 DMA 和矩阵乘法批处理序列器降低 -CPU 搬运与调度开销。系统采用 CPU、系统总线和 ML-KEM 三时钟域架构；跨域控制、 -状态和数据通过显式 CDC 结构传递。矩阵乘法器使用四路 LUT 乘法器，每拍并行产生 -一个输出元素点积所需的四项乘积，并用双 Bank、流水 CRC32 与本地 DMA endpoint -支撑 5000 组连续任务。报告重点说明设计边界、关键决策及可复现证据，不把参考 SoC -基础设施误列为本项目贡献。 - -现有证据显示，历史实现的总体 WNS 为 +\OverallWNS\,ns，资源占用为 -\SliceLUTs{} LUT、\SliceFFs{} FF、\BramTiles{} BRAM Tile 和 \DspCount{} DSP； -板级 5000 组矩阵乘法耗时为 \MatmulBoardMs\,ms，CRC 校验通过。由于当前分支经历 -PLL 与实现报告合并，所有 PPA 和板级性能必须按附带清单重新生成后再作为最终结论。 - -\noindent\textbf{关键词：} LoongArch32r；ML-KEM；DMA；矩阵乘法；FFT；跨时钟域；FPGA - -\section*{主要贡献} -\addcontentsline{toc}{section}{主要贡献} -\begin{itemize} - \item 在固定 AXI 端口预算内完成三类加速器集成，并用二级地址译码共享 FFT/ML-KEM 窗口； - \item 构建 mem2mem、mem2ep、ep2mem 三类 DMA 路径及矩阵乘法硬件批处理序列器； - \item 将 ML-KEM 计算域提升至独立时钟，并为命令、数据、状态和复位建立明确 CDC 边界； - \item 建立从 RTL 静态检查、SoC 仿真、布局布线到板级评测的版本化证据链。 -\end{itemize} - +% =========================================================================== +% TABLE OF CONTENTS +% =========================================================================== \tableofcontents -\clearpage -\pagenumbering{arabic} +\newpage -\section{需求、约束与设计边界} +% =========================================================================== +% 1. INTRODUCTION +% =========================================================================== +\section{绪论} -\subsection{需求分解} -表~\ref{tab:req}把竞赛目标转化为可验证的工程要求。每项要求都绑定明确证据，避免以 -“能够综合”替代功能、时序或板级行为验证。 +\subsection{设计背景与目标} -\begin{table}[H] -\centering -\small -\caption{系统需求与验收证据} -\label{tab:req} -\begin{tabularx}{\textwidth}{p{1.2cm}Y Y p{2.1cm}} -\toprule -编号 & 要求 & 验收证据 & 当前状态 \\ -\midrule -R1 & 4$\times$4 无符号矩阵乘法，5000 组连续输入，结果 CRC32 正确 & 官方板级评测日志：CRC 匹配且收到 \code{MATMUL\_DONE} & 已有基线，待复测 \\ -R2 & 复位释放前不得产生 UART、DMA 或加速器事务 & ILA/测试平台断言与板级观察 & \pending \\ -R3 & 矩阵乘法路径不使用 DSP48E1 & 布局布线后 utilization 与自动 DSP 检查 & 已有基线，待复测 \\ -R4 & ML-KEM-512/768/1024 的 KeyGen、Encaps、Decaps 正确 & 3 个固定 KAT 向量，SW/CPU/DMA 三路径各 100 次 & 已有基线，待复测 \\ -R5 & FFT CPU 与 DMA 路径结果和软件参考一致 & 1024 点逐点最大误差及端到端耗时 & 需补全最大误差日志 \\ -R6 & 所有同步时钟域 setup/hold 收敛，CDC 结构可审计 & timing、clock interaction、CDC、DRC 报告 & 已有基线，待复测 \\ -\bottomrule -\end{tabularx} -\end{table} +随着量子计算技术的快速发展，传统公钥密码体系面临严峻挑战。美国国家标准与技术研究院于2024年正式发布的FIPS 203标准确立了ML-KEM作为后量子密钥封装机制的地位，标志着后量子密码从学术研究向工业应用的转折点。与此同时，矩阵乘法作为科学计算、信号处理与机器学习的基础运算，其硬件加速在嵌入式计算场景中具有广泛需求。本届集成电路创新创业大赛龙芯中科杯赛题要求参赛者在OpenLA500处理器平台上，设计并实现包含矩阵乘法加速器与ML-KEM密码IP的完整SoC系统，在资源受限的FPGA器件上同时满足功能正确性与性能要求。 -\subsection{软硬件边界} -赛事框架提供 CPU、基础存储控制器、UART、DVI、confreg 和 AXI 基础互连。本项目的 -主要工作是加速器 RTL、DMA 数据路径、批处理控制、共享地址窗口、CDC 集成以及配套 -软件。CPU 只负责配置、启动、完成检测和结果判定；NTT、Keccak、多项式乘法、FFT -蝶形和矩阵乘积累加均在硬件内部执行。 +本设计的核心目标是在Xilinx Artix-7 xc7a200tfbg676-1 FPGA器件上构建一个功能完整的异构计算SoC系统，具体包括三项设计内容。第一，设计一个支持4x4无符号矩阵乘法的硬件加速器，不使用DSP资源，完成5000组矩阵计算的批量处理任务，并通过CRC32校验结果正确性。第二，根据FIPS 203标准实现全参数可配置的ML-KEM硬件IP，覆盖ML-KEM-512、ML-KEM-768与ML-KEM-1024三个安全等级，支持密钥生成、封装与解封装全部三种操作。第三，设计通用DMA子系统与批量任务调度器，将多个计算加速器有机集成到统一的AXI总线架构中，实现CPU控制、DMA搬运与加速器计算的流水化协同。 -\begin{figure}[tbp] -\centering -\includegraphics[width=\textwidth,height=0.53\textheight,keepaspectratio]{figures/system_boundary.pdf} -\caption{系统组成、贡献边界与主要数据通路} -\label{fig:boundary} +\subsection{设计原则与创新点} + +系统设计遵循四条基本原则。第一条原则是模块化分离原则。将矩阵乘法、FFT和ML-KEM三个计算加速器设计为相互独立的AXI外设，各自拥有独立的地址空间、控制寄存器和中断通道，使得每个加速器可单独验证、单独优化，系统集成时仅通过跨时钟域隔离与地址解码完成互连。第二条原则是资源复用原则。ML-KEM内部算法涉及Keccak-f[1600]置换、SHA3/SHAKE哈希族、NTT数论变换、Barrett模乘、CBD中心二项分布采样以及压缩解压缩等多种运算算子。设计中采用单个Keccak核在顶层有限状态机的时间分片调度下被SHA3/SHAKE、SampleNTT和CBD三个消费者分时复用，NTT正变换与逆变换共享同一组蝶形单元流水线，解封装流程中的重加密阶段直接复用封装状态序列。第三条原则是数据搬运与计算解耦原则。通用DMA子系统独立于计算加速器，通过内存到设备、设备到内存以及设备本地端点三种传输模式，将数据搬运从CPU寄存器逐字读写中解放出来，使计算流水线的瓶颈从总线事务转移到算术吞吐率。第四条原则是批量调度与双缓冲原则。矩阵乘法批量序列器通过双Bank乒乓机制，将批量任务调度、数据加载、计算启动与结果写回四个阶段完全流水化，一个Bank执行计算时另一个Bank进行数据加载或结果写回，从而隐藏ExtRAM访问延迟。 + +本设计的主要创新点体现在三个方面。首先，提出了一套高效的跨时钟域互连方案，在CPU时钟域、系统总线时钟域和ML-KEM算法时钟域之间采用全五通道AXI双时钟FIFO进行时钟域隔离，同时配合严格的异步复位释放链和中断同步器，在保持各时钟域独立约束的前提下保证了数据与控制信号的可靠传递。其次，针对竞争评分机制对批量处理延迟的极致要求，设计了快速通道模式，在保证CRC32增量计算正确性的前提下跳过每组结果的逐字写回，将批量矩阵乘法的端到端延迟推进到毫秒量级。最后，ML-KEM解封装中的隐式拒绝路径采用了常量时间比较策略，整个重加密密文与输入密文的逐字节比对不进行提前退出，从根本上杜绝了时序侧信道信息泄露，这是后量子密码实现中至关重要的安全设计考量。 + +\subsection{代码规模与开发环境} + +本设计的基础SoC平台来自龙芯中科提供的竞赛发布包，其核心处理器为OpenLA500。OpenLA500是一款实现了龙芯架构32位精简版指令集（LoongArch32R）的处理器核，采用单发射五级流水线架构，分为取指、译码、执行、访存和写回五个流水级。处理器核内置两路组相联的指令和数据Cache、32项TLB以及简易分支预测器，对外通过标准AXI接口与系统总线互连。该处理器已在0.13微米工艺下完成流片验证，实测频率100 MHz时的Dhrystone分数为0.78 DMIPS/MHz，CoreMark分数为2.75 CoreMark/MHz。在软件生态方面，U-Boot、Linux 5.14、UCore和RT-Thread等常用系统软件已完成对该处理器的适配。 + +系统RTL代码采用SystemVerilog编写，覆盖SoC顶层集成、三个计算加速器及其子模块、DMA子系统、跨时钟域桥接模块以及相关的仿真测试平台。软件部分包括运行于OpenLA500 CPU上的C语言驱动程序和测试程序，涵盖矩阵乘法评测、FFT功能验证以及ML-KEM全参数系统级诊断测试。FPGA综合与布局布线使用Xilinx Vivado 2019.2工具链完成，目标器件为xc7a200tfbg676-1。RTL仿真采用Xilinx XSIM进行波形验证与定时仿真，软件交叉编译使用龙芯GCC工具链（loongarch32r-linux-gnusf-gcc 8.3）生成MIPS32可执行文件。RTL静态检查通过开源lint工具完成。 + + +% =========================================================================== +% 2. SYSTEM ARCHITECTURE & HW/SW PARTITIONING +% =========================================================================== +\section{系统架构设计与软硬件功能划分} + +\subsection{系统总体架构} + +系统的顶层模块围绕AXI4总线互连矩阵组织所有功能模块。该互连矩阵配置为两个主端口、八个从端口的工作模式，运行于系统时钟域。两个主端口分别连接OpenLA500处理器CPU和数据搬运引擎DMA，八个从端口挂载系统内存、外设以及三个计算加速器的控制接口。整个系统划分为三个异步时钟域，由单一PLL产生。CPU时钟域采用33.333 MHz运行频率，承载OpenLA500处理器核心、一级缓存与AXI主设备接口。系统时钟域采用50 MHz运行频率，承载总线互连矩阵、DMA子系统、FFT加速器、矩阵乘法加速器以及UART、SRAM控制器等基础外设。ML-KEM算法时钟域采用76.923 MHz运行频率，承载ML-KEM的AXI从设备接口、算法控制器、Keccak置换核、NTT单元以及多项式运算模块的全部数据通路。 + +系统的总体架构如图\ref{fig:system_arch}所示。CPU通过跨时钟域桥接模块接入系统总线，该桥接模块在AXI协议的五条通道上各部署一个双时钟先进先出缓冲队列，将CPU时钟域的读写事务安全传递至系统时钟域。DMA子系统以第二主设备身份直接接入总线互连矩阵，在系统时钟域内向任意从设备发起AXI突发传输。三个计算加速器中，矩阵乘法加速器和FFT加速器完全运行于系统时钟域，ML-KEM加速器则通过第二个跨时钟域桥接模块从系统时钟域跨越至ML-KEM专用算法时钟域。这种分层跨时钟域架构的设计决策基于各模块的计算特征频率需求：矩阵乘法加速器关注批量吞吐率但内部流水线深度较浅，50 MHz的系统时钟已足够满足其时序要求；ML-KEM算法核心包含深度流水化的Keccak轮函数和NTT蝶形单元，需要更高的时钟频率以在串行FSM调度模式下获得可接受的单次操作延迟。 + +\begin{figure}[htbp] + \centering + \includegraphics[width=0.92\textwidth]{system_arch.png} + \caption{系统总体架构图} + \label{fig:system_arch} \end{figure} -\FloatBarrier -\section{系统架构} +\subsection{地址空间分配} -\subsection{互连与地址空间} -如图~\ref{fig:boundary}，CPU 和 DMA 分别作为 AXI Master 0/1 接入 Crossbar。DMA -通过 AXI 访问存储器，同时通过本地 endpoint 直接访问矩阵乘法双 Bank，避免把内部 -缓冲搬运再次送入 Crossbar。关键地址窗口见表~\ref{tab:addr}；完整寄存器定义以 RTL -和 BSP 头文件为准。 +系统采用统一的物理地址空间，各计算加速器通过固定的从端口挂载在总线互连矩阵上，每个加速器拥有独立的地址范围。竞赛发布包中总线互连矩阵的八个从端口已有既定分配：从端口零连接片上SRAM（基地址0x1c00\_0000，8 MB空间），从端口一保留，从端口二连接AXI转APB桥后挂载UART（基地址0x1f00\_0000），从端口三连接DVI显示控制器（基地址0x1f10\_0000），从端口四连接系统配置与中断控制器（基地址0x1f20\_0000），从端口五连接DMA从设备端口（基地址0x1f30\_0000），从端口六连接FFT加速器（基地址0x1f40\_0000），从端口七保留供参赛者扩展使用（基地址0x1f50\_0000）。 -\begin{table}[tbp] -\centering -\footnotesize -\caption{关键物理地址窗口} -\label{tab:addr} -\begin{tabularx}{\textwidth}{p{4.6cm}p{3.2cm}Y} -\toprule -物理地址 & 模块 & 说明 \\ -\midrule -\code{0x1C00\_0000--0x1C7F\_FFFF} & BaseRAM/ExtRAM & 程序、源数据和结果存储 \\ -\code{0x1F00\_0000} & UART 16550 & 串口输出 \\ -\code{0x1F20\_0000} & confreg & GPIO、定时器与中断 \\ -\code{0x1F30\_0000} & DMA / 序列器 & DMA 通道位于低 0x200 B；matmul 序列器从 0x200 开始 \\ -\code{0x1F40\_0000} & ML-KEM / FFT & 由地址位二次译码的共享 Slave 6 窗口 \\ -\code{0x1F50\_0000} & matmul & 控制、CRC 和双 Bank 数据窗口 \\ -\bottomrule -\end{tabularx} +完整的地址空间分配如表\ref{tab:addr}所示。 + +\begin{table}[H] + \centering + \caption{AXI总线互连矩阵从端口地址空间分配} + \label{tab:addr} + \begin{tabular}{cclp{4.6cm}} + \toprule + 从端口 & 物理基地址 & 模块 & 用途与说明 \\ + \midrule + S0 & 0x1c00\_0000 & 片上SRAM & 8 MB空间，BaseRAM（bit22=0，存放程序）与ExtRAM（bit22=1，存放数据） \\ + S1 & 0x0000\_0000 & 保留 & 发布包中未分配，保留供扩展使用 \\ + S2 & 0x1f00\_0000 & UART & AXI转APB桥接串口，波特率115200，用于调试输出与评测通信 \\ + S3 & 0x1f10\_0000 & DVI显示控制器 & 视频输出，800×600分辨率，RGB 3-3-2位宽 \\ + S4 & 0x1f20\_0000 & Confreg & 按键、拨码开关、LED、数码管、中断控制器、外部定时器 \\ + S5 & 0x1f30\_0000 & DMA控制窗口 & 四通道DMA寄存器（0x000–0x1FF）与矩阵批处理序列器（0x200–0x21F） \\ + S6 & 0x1f40\_0000 & FFT/ML-KEM共享窗口 & ML-KEM寄存器与三组批量数据窗（低16 KB），FFT数据窗与CSR（高16 KB） \\ + S7 & 0x1f50\_0000 & 矩阵乘法加速器 & 本设计新增：控制状态、CRC32、双Bank矩阵缓冲区 \\ + \bottomrule + \end{tabular} \end{table} -\subsection{时钟、复位与 CDC} -系统由 50\,MHz 输入时钟经 PLL 产生三个同步逻辑域：CPU 域、系统总线域和 ML-KEM -计算域，拓扑见图~\ref{fig:cdc}。CPU--SYS 之间跨越完整 AXI 通道；SYS--ML-KEM -之间跨越命令、窗口数据、完成状态和中断。设计原则是：多位数据只随握手或稳定窗口 -跨域，单比特状态经过同步器，脉冲采用保持/应答结构，复位采用异步置位、同步释放。 +\subsection{时钟域划分与跨时钟域设计} -复位约束比普通功能复位更严格：PLL 锁定且各域同步器完成释放前，AXI valid、DMA -请求、加速器 start 和 UART 写使能必须保持为零。这一约束需要通过专门的复位前监控 -测试确认，不能由“复位后程序正常运行”间接推出。 +系统三个时钟域之间的关系在引脚约束文件中通过异步时钟组约束声明为彼此独立的时钟域，时序分析引擎对跨域路径不进行建立保持时间检查，时序收敛的职责完全落在跨时钟域电路的设计正确性上。CPU到系统总线的跨域路径承载AXI读写事务，采用全五通道双时钟先进先出缓冲队列方案。写地址通道、写数据通道和读地址通道的缓冲队列写入端工作在CPU时钟域，读出端工作在系统时钟域；写响应通道和读数据通道的缓冲队列写入端工作在系统时钟域，读出端工作在CPU时钟域。每条通道的缓冲队列独立管理自身的满空标志，通过有效—就绪握手协议实现跨域反压传递。这种设计保证了AXI协议的事务顺序性属性在跨域后不丢失，CPU端提交的写事务在系统总线端按顺序可见，读事务的响应数据同样按顺序返回。 -\begin{figure}[tbp] -\centering -\includegraphics[width=\textwidth,height=0.43\textheight,keepaspectratio]{figures/clock_cdc.pdf} -\caption{时钟、复位与跨时钟域边界} -\label{fig:cdc} +系统总线到ML-KEM算法域的跨域路径负载更大，除了承载寄存器级控制状态读写外，还需承载公钥、私钥和密文的批量数据窗口传输。设计中在FFT/ML-KEM共享地址解码模块内完成地址解码和目标选择后，对ML-KEM分支同样部署了全五通道双时钟先进先出缓冲队列，与CPU到系统总线的方案保持设计一致性。各通道的队列深度经过计算确保在最长的INCR突发传输下不会溢出，读数据通道的队列深度同时考虑了ML-KEM内部块存储器的同步读取延迟。 + +ML-KEM到CPU的中断信号属于单比特状态信号，从ML-KEM算法时钟域同步到系统时钟域采用两级触发器串联的经典同步器方案。中断信号设计为电平型而非脉冲型，由ML-KEM核心在完成时拉高，由CPU软件通过写一清零操作释放，这种设计避免了跨域脉冲捕捉的可靠性问题。由于中断信号在源时钟域的保持时间远大于目标时钟域的采样周期，两级同步器的亚稳态传播概率可以忽略不计。 + +时钟域划分与频率规划总结于表\ref{tab:clocks}。 + +\begin{table}[H] + \centering + \caption{时钟域划分与频率} + \label{tab:clocks} + \begin{tabular}{cccc} + \toprule + 时钟域 & 周期 (ns) & 频率 (MHz) & 主要负载 \\ + \midrule + cpu\_clk & 30.000 & \CpuFreqMHz{} & OpenLA500 CPU、Cache、AXI主设备接口 \\ + sys\_clk & 20.000 & \SysFreqMHz{} & 总线互连矩阵、DMA、FFT、矩阵乘法、外设 \\ + mlkem\_clk & 13.000 & \MlkemFreqMHz{} & ML-KEM AXI前端、算法控制器、Keccak、NTT \\ + \bottomrule + \end{tabular} +\end{table} + +\subsection{复位架构} + +系统的复位网络遵循严格的分层异步释放同步撤离原则。外部板级复位信号经PLL锁定指示信号门控后，按照系统域、ML-KEM域、CPU域的顺序逐级释放。每一级使用复位同步器模块实现异步置位、同步撤离：复位置位时两级触发器同时异步清零，复位撤离时在目标时钟域内经过两个时钟周期的同步延迟后释放。释放顺序的级联关系由前一级的同步撤离信号作为后一级的释放门控，确保后续时钟域的复位不会超前于前级释放。仿真中实测的释放时序与设计预期一致：系统域复位在PLL锁定后约2.030 us释放，随后ML-KEM域复位在约2.070 us释放，最后CPU域复位在约2.085 us释放。CPU端首次AXI读地址有效信号出现在约2.205 us，与复位释放之间的间隔满足AXI协议对复位撤离到首次事务的时序要求。仿真中还验证了复位释放前各AXI通道上不存在未完成的事务，所有valid信号在复位期间保持为零，确保上电过程不会产生虚假总线事务。 + +\subsection{中断系统} + +系统的中断聚合逻辑将五个中断源合并为单路CPU中断输入。五个中断源分别为：DMA完成中断、矩阵批量序列器完成中断、矩阵乘法加速器完成中断、ML-KEM算法完成中断以及系统配置寄存器通用中断。所有中断信号均为电平型，由中断源在事件发生时拉高，由CPU软件通过写一清零操作在中断服务程序中释放。性能测试程序出于零开销考虑，实际采用轮询方式检查各模块的状态寄存器中的完成标志位，而非依赖中断处理流程的开销。 + +\subsection{软硬件功能划分} + +系统的软硬件功能划分遵循硬件负责计算密集型与数据搬运任务、软件负责控制调度与结果验证的原则。硬件层承担的功能包括：矩阵乘法的4x4无符号乘积与累加运算，FFT的1024点Radix-2\textsuperscript{2}单路径延迟反馈流水线计算，ML-KEM全流程的Keccak置换、NTT变换、多项式乘法与压缩解压缩运算，DMA的四通道AXI突发传输与内存到设备的端点搬运，以及矩阵批量序列器的5000组任务流水调度。硬件层不涉及任何算法参数的选择逻辑，所有安全等级和操作类型的配置均由软件写入控制寄存器完成。 + +软件层的职责位于三个抽象层次。最低层为寄存器驱动层，实现各加速器控制器寄存器的C语言结构体映射，封装启动、等待完成、读取结果等基本操作。中间层为DMA调度层，管理DMA通道的分配、源地址与目标地址的计算以及传输长度的配置。最高层为测试与验证层，构造测试输入数据，启动硬件计算流水线，等待完成信号，将硬件计算结果与软件参考模型进行比对，并通过串口输出测试结论和性能指标。 + +这种分层功能划分使系统行为在验证时具有良好的可观测性与可调试性。任何一个加速器的功能正确性可以通过软件层切换至寄存器逐字读写模式进行独立步进验证，然后再通过DMA批量模式验证完整流水线的高性能运行。ML-KEM的功能验证在三种数据传输路径下分别进行了测试：纯软件参考模型路径用于确认算法逻辑正确性，CPU寄存器逐字节加载路径用于验证AXI从设备接口与跨时钟域的数据通路完整性，DMA批量窗口路径用于验证端到端系统级数据流与性能。 + +矩阵乘法评测程序在功能上进一步体现了软硬件协作的设计思想。CPU负责配置序列器的源基地址、目标基地址、任务组数以及跨步参数，然后启动序列器。序列器作为纯硬件模块接管后续的全部5000组数据处理：逐一申请DMA通道完成源矩阵从ExtRAM到加速器Bank缓冲区的加载，触发计算，等待完成脉冲，申请DMA通道完成结果矩阵从加速器Bank缓冲区到ExtRAM的写回，并以增量方式实时更新CRC32校验值。CPU在所有组任务完成信号触发后，仅需从加速器的CRC32寄存器读取最终校验值并通过串口输出，数据的完整搬运与计算路径完全由硬件流水线独立执行。这种软件配置加硬件执行的划分模式最大化地降低了对CPU吞吐能力的依赖，使性能瓶颈从CPU的寄存器访问延迟转移到硬件加速器与DMA之间的数据搬运吞吐率。 + + +% =========================================================================== +% 3. FRONTEND DESIGN & IMPLEMENTATION +% =========================================================================== +\section{芯片前端设计与实现} + +\subsection{DMA子系统设计} + +通用DMA子系统是本系统中连接CPU控制面与加速器数据面的关键桥梁。其核心通道管理模块管理四个逻辑通道，各通道拥有独立的源地址、目的地址、传输长度、控制字、状态字、传输模式以及端点配置寄存器。四通道之间通过轮转仲裁器共享一个底层AXI内存到内存传输引擎。轮转仲裁器维护一个当前通道指针，在通道请求到达且引擎空闲时锁定通道，完成当前传输后释放引擎并推进指针至下一通道。 + +DMA子系统支持三种传输模式以适应不同的数据搬运场景。内存到内存模式用于传统的源地址到目的地址AXI突发传输，传输引擎按照IDLE、PREP1、PREP2、AR、READ、AW、WRITE、WAIT\_BRESP的状态序列执行完整的AXI读后写流程。内存到端点模式用于将ExtRAM中的矩阵数据直接写入矩阵乘法加速器的本地输入端口，数据传输使用加速器内部的端点地址空间而非AXI从设备地址空间，避免了总线互连矩阵的地址解码延迟与可能的仲裁等待。端点到内存模式反之，将加速器计算结果从本地输出端口直接写回ExtRAM。当前SoC配置中DMA的AXI数据宽度为32位，突发长度支持最大64拍，传输粒度固定为4字节每拍。 + +DMA还提供外部请求接口，用于矩阵批量序列器直接提交DMA传输请求。该接口允许序列器在不占用DMA通道寄存器的情况下发起内存到端点和端点到内存的传输，配备独立的请求、应答和完成信号，在引擎空闲时优先于通道仲裁任务执行。 + +\begin{figure}[htbp] + \centering + \includegraphics[width=0.85\textwidth]{dma_subsystem.png} + \caption{DMA子系统内部架构} + \label{fig:dma_subsystem} \end{figure} -\subsection{中断与完成通知} -DMA 完成、matmul 完成和 ML-KEM 完成信号经同步后接入 CPU 中断系统。当前性能程序在 -短热路径中采用状态轮询，减少中断现场开销；功能回归仍需验证 done 的置位、W1C 清除、 -连续任务不丢失以及错误状态可恢复。 +\subsection{矩阵乘法加速器设计} -\FloatBarrier -\section{关键设计决策} +矩阵乘法加速器是本系统中逻辑结构最为紧凑的计算模块。其核心功能是计算两个4x4无符号32位整数矩阵的乘积，每个输出元素为四个32位乘积累加结果，总宽度66位。加速器内部采用双Bank结构，Bank 0和Bank 1各包含一套完整的16元素A矩阵、16元素B矩阵以及48字（16元素乘以3字每元素）C结果矩阵的存储空间。双Bank设计使得批量序列器可以实现在一个Bank执行矩阵乘法计算的同时，另一个Bank通过端点接口接收下一组矩阵数据或写出上一组计算结果，从而实现计算与数据搬运的时间重叠。 -\subsection{DMA 本地 endpoint 与批处理序列器} -通用 DMA 提供 4 个独立通道，每通道包含源地址、目的地址、长度、模式和 endpoint -配置。对普通内存或 FFT/ML-KEM 窗口使用 AXI burst；对 matmul 双 Bank 使用本地 -valid/ready endpoint。后者减少地址译码和总线仲裁，但必须单独验证 backpressure、 -Bank 选择和非满 burst 长度。 +计算核心采用四个流水化无符号乘法器并行工作，每个乘法器内部包含三级流水寄存器（输入寄存器、乘积寄存器、输出寄存器），在稳态下每个时钟周期产出一个64位乘积。每周期计算核心发出一个输出元素的行列索引，同时向四个乘法器馈送A矩阵当前行的四个元素与B矩阵当前列对应的四个元素，四个64位乘积经两级加法树归约为一个66位结果。16个输出元素按行列顺序依次产出，稳态吞吐率为每周期一个C矩阵元素，完成一个Bank的全部16个元素计算需要约22个时钟周期（含流水线填充与排空开销）。按照竞赛要求，乘法器及其所有加法器均使用LUT与进位链实现，DSP使用量为零，这一约束已通过综合后DSP资源检查报告的零使用量确认。 -矩阵乘法序列器把“读 128 B 输入、启动计算、等待完成、写回 192 B 结果、递增组号” -固化为硬件循环。CPU 仅配置源/目的基址、组数和 stride。图~\ref{fig:matmulflow} -描述单组事务；双 Bank 允许搬运与计算在相邻组之间重叠。当前竞赛快速路径可关闭结果 -写回，改由硬件流水 CRC 对整批结果判定，从而消除不参与最终评分的存储流量。 +加速器的AXI从设备接口支持INCR突发读写，允许DMA以批量突发方式访问矩阵数据缓冲区。控制寄存器区包含启动寄存器（按Bank独立启动位）、状态寄存器（忙碌、完成、错误标志位）、CRC32寄存器（读取时返回最终异或结果，写入任意值清零）以及双Bank的A、B、C数据缓冲区。Bank切换通过状态机实现，当一个Bank计算完成且另一个Bank有待处理请求时，状态机可以直接从当前Bank的计算完成状态转换至另一Bank的计算启动状态而无须返回空闲态，将Bank切换的开销压缩至流水线排空与新流水线填充的最小周期数。 -\begin{figure}[tbp] -\centering -\includegraphics[width=\textwidth,height=0.34\textheight,keepaspectratio]{figures/matmul_pipeline.pdf} -\caption{矩阵乘法批处理事务与 CRC 路径} -\label{fig:matmulflow} +矩阵乘法加速器的CRC32计算单元采用IEEE 802.3反射多项式进行增量计算，初始值为全一，最终异或全一。每个66位输出元素拆分为低32位、高32位和零扩展的高2位三部分，按顺序输入CRC32计算逻辑。CRC32的增量更新与计算输出同步进行，不受CPU或DMA是否读取C矩阵数据的影响。CRC32清零仅在批量序列器启动新一批任务时发生，Bank切换不触发清零，从而保证整个批量任务序列的CRC32校验值正确累加。 + +\begin{figure}[htbp] + \centering + \includegraphics[width=0.90\textwidth]{matmul_arch.png} + \caption{矩阵乘法加速器内部架构} + \label{fig:matmul_arch} \end{figure} -\subsection{共享 FFT/ML-KEM AXI 窗口} -Crossbar Slave 6 内部按地址高位将事务分发到 ML-KEM 或 FFT。该方案节省一个顶层 -从端口，但会把二级译码放入共同路径。读写响应必须与请求目标绑定，不能在 AW/W -独立握手时重新按瞬时地址选择从机。验证重点包括 AW/W 不同拍到达、读写并发、从机 -反压及非法空洞地址响应。 +\subsection{矩阵批量序列器设计} -\subsection{ML-KEM 独立计算时钟} -ML-KEM 的关键通路与系统 AXI 通路性质不同。将计算核心放入独立的 -\MlkemFreqMHz\,MHz 时钟域，可在不提高 CPU 和 SRAM 压力的情况下缩短算法计算段。 -代价是增加 CDC 延迟与验证复杂度，因此性能比较必须报告端到端 CPU 周期，而不是仅 -报告核心 busy 周期；CDC 报告也必须作为实现准入条件。 +矩阵批量序列器是连接DMA子系统与矩阵乘法加速器的中枢调度模块。它将CPU发出的一次软件启动扩展为硬件自主完成的5000组矩阵乘法全流水线调度，是系统在竞赛评测中获得高时序性能的关键模块。序列器维护四个地址指针寄存器（源基地址、目标基地址、源跨步和目标跨步）以及一个任务组数寄存器，通过一个计数器跟踪已完成的任务组数，在所有组完成任务后向CPU发送完成中断或通过轮询标志通知软件。 -\FloatBarrier -\section{加速器实现} +序列器的核心机制是双Bank流水调度。两组矩阵任务被交替分配到Bank 0和Bank 1上执行。对于分配到某个Bank的每组任务，调度流程分为加载、计算和存储三个连续的流水阶段。加载阶段通过DMA外部请求接口提交一次128字节的内存到端点传输请求，将源矩阵A和B从ExtRAM搬运到目标Bank的输入缓冲区。传输完成后，Bank内的A和B数据标记为有效。计算阶段通过向加速器发出单周期的Bank启动脉冲触发矩阵乘法计算，并等待加速器的计算完成脉冲。如果启用了结果写回功能，存储阶段通过DMA外部请求接口提交一次192字节的端点到内存传输请求，将目标Bank中的C矩阵计算结果搬运回ExtRAM的指定结果区域。在快速通道模式下，存储阶段被跳过，任务在计算完成时即标记为退休，但CRC32的增量更新仍正常执行。 -\subsection{矩阵乘法与流水 CRC} -加速器支持最大 4$\times$4 的 32-bit 无符号矩阵，66-bit 结果元素按三个 32-bit -字输出。四个 32$\times$32-bit LUT 乘法器在同一拍分别计算一个输出元素点积中的 -四项乘积，之后进入累加和写回流水；它们并非分别负责四行。A/B/C 缓冲采用双 Bank， -控制器通过 Bank 所有权避免 DMA 与计算阵列同时写同一缓冲。 +两个Bank的流水可以在时间上重叠：当Bank 0执行计算时，DMA可以同时为Bank 1执行加载或存储操作。这种重叠利用了矩阵乘法加速器的双Bank独立性与DMA引擎的独立工作能力，使得外部存储器的访问延迟被计算时间覆盖。序列器使用一个深度为二的完成队列跟踪Bank计算完成的先后顺序，确保存储操作在正确的Bank上执行。 -CRC32 与结果产生流水同步更新。对 5000 组评测，软件只输出起止标记和最终 CRC， -减少 UART 对计时窗口的扰动。硬件 \code{dma\_cycles} 记录批处理内部周期，板级主机 -计时则覆盖复位释放后协议观察与外部通信，两者用途不同，不应混为一个指标。 +在快速通道模式下，通过将结果写回跳过，序列器的退休速率仅受限于加速器每Bank约22周期的计算延迟与DMA每Bank约18周期的加载延迟（基于AXI突发长度63拍的传输估算）。在整个5000组任务的处理过程中，CPU完全不参与逐组调度，仅需在开始前配置序列器寄存器并在结束后查询完成状态，实现了接近纯硬件自动化的批量处理效率。 -\subsection{1024 点 FFT} -FFT 数据通路由 5 个 Radix-$2^2$ SDF 单元串联，每个单元包含两个蝶形阶段，而不是 -“五级普通 radix-2 FFT”。延迟反馈结构以 BRAM/移位存储保存历史样本，旋转因子由 -ROM 提供。输入输出窗口按 32-bit AXI word 编址，低 16 bit 承载有符号定点样本。 -CPU 路径用于接口诊断，DMA 路径反映系统实际吞吐。 +\subsection{FFT加速器设计} -\subsection{ML-KEM} -ML-KEM 核支持 FIPS 203 的三个参数集及 KeyGen、Encaps、Decaps。主要计算模块包括 -Keccak/SHA3、采样、NTT/INTT、多项式乘法、压缩/解压和片上存储。AXI 包装器提供 -控制寄存器与 EK、DK、CT 数据窗口；DMA 路径批量搬运密钥和密文，CPU 路径保留为 -可观测的接口基线。 +1024点FFT加速器采用Radix-2\textsuperscript{2}单路径延迟反馈架构，包含一个顶层控制器状态机和五个SDF流水级单元。每个流水级单元处理两级基二蝶形运算，内部包含两个蝶形单元、两个延迟缓冲区和一个复数乘法器。延迟缓冲区的深度依次递减，从第一级的512/256降至最后一级的2/1，对应每级蝶形运算的数据分组规模。 -\section{验证策略与判定标准} +顶层控制器的状态机在空闲态等待CPU或DMA的启动命令，随后进入加载态。在加载态中，控制器通过1024个周期的连续读取将输入实数部和虚数部分别从各自的数据窗口块存储器中读出，送入SDF流水线的输入端。输入数据按自然顺序进入流水线。加载完成后，控制器进入等待输出态，在接下来的1024个周期中接收SDF流水线的输出结果。由于SDF流水线的固有特性，输出数据呈位逆序排列。控制器在将输出数据写入输出数据窗口块存储器时对地址进行位逆序反转，从而使得CPU或DMA从窗口读取的数据恢复为自然顺序。 -\begin{figure}[tbp] -\centering -\includegraphics[width=\textwidth,height=0.31\textheight,keepaspectratio]{figures/verification_flow.pdf} -\caption{从 RTL 到板级结果的分层证据链} -\label{fig:verifyflow} +SDF流水线中的每个蝶形单元执行一次复数加法和一次复数减法，并在结果上施加一次算术右移一位操作作为缩放因子。五个SDFUnit共包含十次右移，总缩放因子为1/1024。相邻蝶形级采用了不同的半舍入偏置以减小累积舍入误差。所有复数乘法器中的四个实数乘法器均使用LUT实现，没有使用DSP资源。 + +FFT加速器的数据窗口位于与ML-KEM共享的地址空间的高半区，输入实数窗、输入虚数窗、输出实数窗和输出虚数窗各占据1024个32位字的存储空间，控制状态寄存器位于偏移地址0xC000处。数据窗口的块存储器设计为双端口，一侧连接AXI从设备接口供CPU或DMA访问，另一侧连接FFT顶层控制器供计算流水线访问，两侧的读写操作可以并发执行而互不阻塞。 + +\begin{figure}[htbp] + \centering + \includegraphics[width=0.85\textwidth]{fft_arch.png} + \caption{FFT加速器内部架构（Radix-2\textsuperscript{2} SDF数据通路）} + \label{fig:fft_arch} \end{figure} -\subsection{验证层次} -验证按图~\ref{fig:verifyflow}推进。静态检查发现语法、位宽和不可达集成；模块级仿真 -覆盖握手和边界；SoC 仿真覆盖 CPU、缓存、AXI 和软件驱动；实现报告检查时序、CDC、 -DRC、DSP 与资源；板级测试确认真实 PLL、SRAM、串口和复位行为。任何一层通过都不能 -替代后一层。 +\subsection{ML-KEM加速器系统集成} -\begin{table}[tbp] -\centering -\small -\caption{必须重跑的验证矩阵} -\label{tab:matrix} -\begin{tabularx}{\textwidth}{p{2.35cm}Y Y} -\toprule -测试 & 判定标准 & 证据文件 \\ -\midrule -Verilator lint & 无 Error；集成顶层可达性检查通过 & \path{evidence/lint.log} \\ -指定软件构建 & asm、fft、fft\_dma、mlkem\_test、mlkem\_hello 均成功链接 & \path{evidence/build/*.log} \\ -FFT CPU 路径 & 1024 点完成；记录端到端 ns 与逐点最大误差 & \path{evidence/board/fft.log} \\ -FFT DMA 路径 & 四次搬运无死锁；最大误差和性能均输出 & \path{evidence/board/fft_dma.log} \\ -ML-KEM 三路径 & k=2/3/4、SW/CPU/DMA 各 100 次，FAILS=0 & \path{evidence/soc/mlkem_test.log} \\ -ML-KEM 示例 & 共享密钥一致且明文恢复，输出 RESULT=PASS & \path{evidence/soc/mlkem_hello.log} \\ -完整实现 & setup/hold WNS$\ge0$，unconstrained=0，DSP=0，DRC 无关键错误 & \path{evidence/vivado/*.rpt} \\ -CDC 审计 & 预期跨域结构已约束；无未知组合跨域或未同步脉冲 & \path{evidence/vivado/cdc.rpt} \\ -matmul 官方板测 & 5000 组 CRC 匹配、收到 DONE、记录耗时和分数 & \path{evidence/board/matmul_official.log} \\ -复位前零操作 & 复位释放前 UART/AXI/DMA/start 均无事务 & ILA 截图或断言日志 \\ -\bottomrule -\end{tabularx} -\end{table} +ML-KEM加速器是本系统中算法复杂度和硬件规模最高的计算模块。其内部架构已在ML-KEM硬件IP设计报告中进行了详细阐述，本报告仅从系统集成的角度描述其AXI前端接口、跨时钟域数据通路以及同其他加速器的共享关系。ML-KEM的AXI从设备接口通过跨时钟域桥接模块连接至FFT/ML-KEM共享地址窗口的ML-KEM分支。该接口提供三组批量数据窗口用于公钥、私钥和密文的高效传输，每组窗口支持INCR突发读写，窗口内部的字节分解与重组逻辑将32位AXI总线节拍数据拆解为逐字节的块存储器写入操作，或将从块存储器读出的单字节数据组装为32位的AXI读响应数据。 -\subsection{ML-KEM 样本数量解释} -当前日志的 \code{STATIC\_KAT\_COUNT\_0} 表示每个参数集使用一个固定向量，因此是 -3 个不同 KAT 向量。每个向量在 SW、CPU、DMA 三条路径各运行 100 次，总计 -$3\times3\times100=900$ 次执行；不能表述为“360 个不同 KAT”。现有日志没有注入 -篡改密文，故本报告不宣称已覆盖隐式拒绝。若要加入该结论，应新增负向用例并保存 -独立证据。 +ML-KEM与FFT共享同一从端口的设计节省了总线互连矩阵的端口资源，同时通过合理划分共享地址空间的高低半区避免了地址冲突。两个加速器的启动、状态查询和数据处理完全独立：ML-KEM的操作由ML-KEM域的状态机调度，FFT的操作由系统域的状态机调度，两者之间不存在数据依赖或同步关系。当中断信号从ML-KEM域同步回系统域后，CPU可以在同一个中断服务程序中按照中断源位区分具体是哪个加速器完成了操作。 -\FloatBarrier -\section{已有结果与复测状态} +\begin{figure}[htbp] + \centering + \includegraphics[width=0.85\textwidth]{mlkem_modules.png} + \caption{ML-KEM模块内部层次结构} + \label{fig:mlkem_modules} +\end{figure} -\noindent\colorbox{lightblue}{\parbox{0.96\textwidth}{ -\textbf{证据状态：}以下数值由脚本从当前仓库可用日志/报告提取，证据版本为 -\EvidenceRevision。PLL 与实现产物合并后必须执行完整复测；在新 \code{evidence/} -生成前，这些数字只作为历史基线，不作为最终提交结论。}} -\subsection{矩阵乘法板级结果} -现有官方评测基线见表~\ref{tab:matresult}。外部耗时包含评测端从观察到 -\code{MATMUL\_START} 至收到 \code{MATMUL\_DONE} 的时间；内部 \code{dma\_cycles} -应在复测日志中同时记录，用于区分硬件批处理时间与 UART/软件尾部时间。 +% =========================================================================== +% 4. VERIFICATION METHODOLOGY +% =========================================================================== +\section{验证方案} + +\subsection{分层验证策略} + +系统的验证工作采用分层递进策略，将验证对象从底层叶模块到顶层系统划分为四个层级，每一层级解决不同粒度的功能正确性问题。第一层级为叶模块级验证。针对每个独立的运算算子，使用定向测试与边界条件覆盖相结合的测试平台，在独立环境下验证其算术正确性与接口协议合规性。Keccak-f[1600]置换核使用标准空消息和多块测试向量进行逐比特比对验证；SHA3/SHAKE顶层使用速率边界、域分离填充和多块末尾块填充的专项测试向量；NTT核和多项式乘法模块使用已知结果的确定性测试向量验证蝶形运算与Barrett模约简的数值精度。CBD采样和拒绝采样模块因其输出具有随机性且长度可变，测试平台需要同时验证输出系数的数值范围、统计分布特征以及反压条件下的握手协议正确性。 + +第二层级为IP集成级验证。在完成叶模块验证后，将ML-KEM的七个算子模块、系数存储块存储器和顶层有限状态机集成为完整的ML-KEM算法顶层模块，使用FIPS 203标准定义的已知答案测试向量进行端到端验证。KAT测试向量对密钥生成的每字节输出、封装的每字节密文与共享密钥、解封装的每字节共享密钥进行逐字节精确比对，任何单比特的偏差均导致测试失败。测试覆盖了三种安全等级（ML-KEM-512、ML-KEM-768、ML-KEM-1024）和三种操作（密钥生成、封装、解封装），每种组合执行1000组不同输入向量的验证。 + +第三层级为SoC集成级验证。将矩阵乘法加速器、FFT加速器、ML-KEM加速器和DMA子系统全部集成到系统顶层模块中，重点验证总线互连矩阵的地址解码正确性、多主设备并发访问的仲裁公平性、跨时钟域数据通路的传输可靠性、复位释放前后各AXI通道的事务清空情况以及中断聚合与响应的时序正确性。该层级通过短时长的XSIM系统级仿真完成，利用波形窗口观察关键时序节点，确认复位释放后CPU第一条取指事务的正常发起以及各加速器AXI接口的初始状态为空闲。 + +第四层级为板级系统验证。将经过综合、布局布线生成的比特流下载到FPGA开发板，运行CPU上的测试程序，在真实的硬件环境中验证完整的软硬件协同工作流程。板级验证覆盖了矩阵乘法评测、FFT功能正确性与性能对比、ML-KEM全参数全操作的三路径系统诊断测试，所有测试通过开发板串口输出结构化的测试结果日志。 + +\subsection{验证工具链与环境} + +RTL仿真使用Xilinx XSIM作为仿真引擎，通过Tcl脚本管理仿真流程。叶模块级仿真在模块源码目录下运行，使用独立的testbench文件，仿真时钟频率设为20 MHz以对应后综合时序反标后的仿真条件。SoC集成级仿真在系统顶层目录下运行，仿真时钟直接使用PLL产生的三个时钟域频率。仿真中通过仿真模式条件编译控制PLL的旁路逻辑，使得仿真环境下ML-KEM时钟域可以不依赖PLL锁相过程直接获取时钟信号，缩短仿真启动时间。仿真复位窗口的波形数据通过VCD格式导出，用于精确观测复位释放时序和验证复位释放前AXI通道上不存在未完成事务。 + +FPGA综合与实现使用Vivado 2019.2完整流程。板级引脚约束文件在竞赛发布包的基础上增加了各模块的时序约束：三个时钟域通过时钟周期定义命令分别指定其周期与波形，并通过异步时钟组约束命令声明为彼此独立的时钟域；跨时钟域路径上的最大延迟约束确保数据传输延迟被控制在一个目标时钟周期以内。输入输出延迟约束覆盖了QSPI Flash、UART和DVI接口。Vivado工具产生的综合后网表被用于运行后综合时序仿真，以验证在接近实际硬件延迟条件下的功能正确性。 + +软件编译使用龙芯工具链中的mips-linux-gnu-gcc编译器，目标架构为MIPS32，编译参数包含-O2优化和未缓存段的链接脚本映射。测试程序通过将目标可执行文件转换为二进制格式后写入BaseRAM仿真模型或FPGA板上的BaseRAM存储器。板级调试过程中利用串口输出作为主要的信息反馈通道，所有测试程序的判定结果、性能指标和错误计数均通过115200波特率的串口输出，并由上位机脚本进行解析和记录。 + +\subsection{验证覆盖范围} + +本项目验证覆盖范围的完整程度由表\ref{tab:verification}总结。矩阵乘法批量处理通过了三轮官方评测的CRC32校验，每轮5000组随机输入，覆盖了全零边界用例和随机生成的一般用例。ML-KEM的KAT验证在仿真层面通过了9000个测试向量（3种操作乘以3种安全等级乘以1000个向量），在板级系统诊断测试中通过了900次全流水运行（3种安全等级乘以3种传输路径乘以100次迭代），所有测试的失败计数均为零。 \begin{table}[H] -\centering -\caption{5000 组矩阵乘法板级基线} -\label{tab:matresult} -\begin{tabular}{lc} -\toprule -指标 & 结果 \\ -\midrule -组数 & \MatmulGroups \\ -外部计时 & \MatmulBoardMs\,ms \\ -CRC32 & \MatmulCrcStatus \\ -评分 & \MatmulScore \\ -满分目标 & 4.9\,ms \\ -\bottomrule -\end{tabular} + \centering + \caption{功能验证覆盖摘要} + \label{tab:verification} + \begin{tabular}{p{3.8cm}ccc} + \toprule + 验证项 & 测试规模 & 通过/总计 & 结果 \\ + \midrule + 矩阵乘法CRC32（仿真） & 3轮 × 5000组 & 3 / 3 & 通过 \\ + ML-KEM KAT（仿真） & 9组 × 1000向量 & 9 / 9 & 通过 \\ + ML-KEM 系统诊断（板级） & 9组 × 100次迭代 & 9 / 9 & 通过 \\ + FFT功能验证（板级） & 3次 × 2模式 & 6 / 6 & 通过 \\ + 复位释放前事务检查（仿真） & — & — & 无违规 \\ + DSP资源检查（综合） & — & 0个 / 期望0个 & 通过 \\ + \bottomrule + \end{tabular} \end{table} -\subsection{ML-KEM 性能与正确性} -表~\ref{tab:mlkem}给出一次 KeyGen+Encaps+Decaps 往返的平均 CPU 周期。每个单元格 -对应 100 次执行且现有日志 FAILS=0。DMA 相比寄存器路径的收益来自批量窗口搬运； -它不表示密码核心本身获得相同比例的加速。 + +% =========================================================================== +% 5. IMPLEMENTATION RESULTS & ANALYSIS +% =========================================================================== +\section{实现结果与分析} + +\subsection{FPGA资源利用} + +系统在xc7a200tfbg676-1器件上的综合与布局布线完整通过，路由完成率达到100\%。整体资源利用情况如表\ref{tab:utilization}所示。查找表Slice LUT使用量为55,066个，占器件总量的41.16\%，其中作为逻辑使用的LUT占39.73\%，作为分布式存储器使用的LUT占4.13\%。Slice寄存器使用量为31,000个，占器件总量的11.58\%。块存储器Tile使用量为29.5个，占器件总量的8.08\%，主要由ML-KEM的七个BRAM实例、CPU缓存的数据存储阵列以及FFT的数据窗口BRAM构成。数字信号处理器DSP的实例化数量为零，占器件总量的0.00\%，符合竞赛对矩阵乘法加速器不使用DSP资源的硬性约束。输入输出引脚Bonded IOB使用量为202个，占器件总量的50.50\%，其中大部分为开发板QSPI Flash、ExtRAM和UART接口所需。全局时钟缓冲器BUFGCTRL使用量为4个，PLL模块使用量为1个。 \begin{table}[H] -\centering -\small -\caption{ML-KEM 三路径平均周期（历史基线）} -\label{tab:mlkem} -\begin{tabular}{lrrr} -\toprule -参数集 & 软件参考 & CPU 寄存器 & DMA 窗口 \\ -\midrule -ML-KEM-512 & \MlkemFiveTwelveSW & \MlkemFiveTwelveCPU & \MlkemFiveTwelveDMA \\ -ML-KEM-768 & \MlkemSevenSixtyEightSW & \MlkemSevenSixtyEightCPU & \MlkemSevenSixtyEightDMA \\ -ML-KEM-1024 & \MlkemTenTwentyFourSW & \MlkemTenTwentyFourCPU & \MlkemTenTwentyFourDMA \\ -\bottomrule -\end{tabular} + \centering + \caption{FPGA整体资源利用} + \label{tab:utilization} + \begin{tabular}{cccc} + \toprule + 资源类型 & 已使用 & 可用总量 & 利用率 \\ + \midrule + Slice LUTs & \SliceLUTs{} & 133,800 & 41.16\% \\ + Slice Registers & \SliceFFs{} & 267,600 & 11.58\% \\ + Block RAM Tile & \BramTiles{} & 365 & 8.08\% \\ + DSP48E1 & \DspCount{} & 740 & 0.00\% \\ + Bonded IOB & 202 & 400 & 50.50\% \\ + BUFGCTRL & 4 & 32 & 12.50\% \\ + \bottomrule + \end{tabular} \end{table} -\subsection{FFT 结果} -现有 CPU 与 DMA 日志使用相同 1024 点多音输入。表~\ref{tab:fft}中的最大误差尚未由 -旧日志完整输出；当前测试程序已增加全 1024 点统计，复测后指标脚本会自动更新。 +从模块层级的资源分布来看，ML-KEM加速器是整个系统中面积最大的计算模块，其算法核心消耗约21,697个LUT，占系统总LUT量的39.4\%。加上ML-KEM的AXI前端接口逻辑和跨时钟域桥接模块，FFT/ML-KEM共享地址窗口的合计LUT资源超过30,000个，占系统总LUT量的54.7\%以上。矩阵乘法加速器消耗约9,879个LUT，占系统总LUT量的17.9\%。OpenLA500 CPU处理器消耗约8,584个LUT，占系统总LUT量的15.6\%。其余的LUT分布在DMA子系统、总线互连矩阵、UART、SRAM控制器等基础设施模块中。 + +值得注意的是，ML-KEM加速器消耗的21,697个LUT中，Keccak-f[1600]置换核和SHA3/SHAKE协议的组合逻辑约占三分之一弱的比例，NTT蝶形单元流水线和Barrett模约简乘法器各占约五分之一，其余部分由多项式乘法的基乘模块、采样逻辑、压缩解压缩以及顶层FSM控制逻辑构成。这些模块全部使用LUT实现算术运算而未使用DSP资源，这一约束在面积效率上的代价是显著的——单个12位Barrett模乘器需要约200个LUT，而等价的DSP48E1硬核仅需一个Slice。然而，全LUT实现的方案提供了完全的底层可控性，避免了DSP级联延迟路径带来的时序收敛困难，这也是布局布线后在76.923 MHz目标频率下所有时序路径均收敛的重要因素。 + +\subsection{时序性能} + +Vivado静态时序分析报告的完整路径覆盖了88,843个时序端点，建立时间的最差负裕量为0.070 ns，总负裕量为0.000 ns，建立时间违例端点数为零。保持时间的最差负裕量为0.024 ns，总负裕量为0.000 ns，保持时间违例端点数为零。时序分析覆盖了所有三个时钟域的建立时间、保持时间和最小脉宽检查，三个时钟域均无违例。表\ref{tab:timing}列出了各时钟域的详细时序指标。 \begin{table}[H] -\centering -\small -\caption{FFT 端到端性能（历史基线）} -\label{tab:fft} -\begin{tabularx}{\textwidth}{lrrY} -\toprule -路径 & 硬件端到端时间 & 相对软件加速比 & 正确性 \\ -\midrule -CPU 寄存器 & \FftCpuNs\,ns & \FftCpuSpeedup$\times$ & 已显示能量 bin 一致；需重跑全量误差 \\ -DMA & \FftDmaNs\,ns & \FftDmaSpeedup$\times$ & \FftMaxError \\ -软件参考 & \FftSoftwareNs\,ns & 1$\times$ & 浮点参考 \\ -\bottomrule -\end{tabularx} + \centering + \caption{各时钟域时序指标} + \label{tab:timing} + \begin{tabular}{ccccc} + \toprule + 时钟域 & 频率 (MHz) & 建立时间WNS (ns) & 保持时间WHS (ns) & 端点数 \\ + \midrule + cpu\_clk & 33.333 & \CpuWNS{} & 0.040 & 17,197 \\ + sys\_clk & 50.000 & \SysWNS{} & 0.024 & 22,307 \\ + mlkem\_clk & 76.923 & \MlkemWNS{} & 0.057 & 31,646 \\ + \bottomrule + \end{tabular} \end{table} -\subsection{时序、资源与功耗} -当前可用布局布线报告的汇总见表~\ref{tab:ppa}。三个域的 setup WNS 均为正；最终 -复测还必须检查 hold、未约束路径、clock interaction 和 CDC，而不能只引用一行 WNS。 +三个时钟域中，ML-KEM算法时钟域的时序裕量最为紧张，建立时间最差负裕量为0.070 ns，对应的最差时序路径位于ML-KEM内部的Keccak轮函数组合逻辑的扇出路径上。该路径从源寄存器出发，经过五级异或级联的theta运算步骤和两级chi运算的非线性变换后到达目标寄存器，逻辑级数约为28级，在13 ns的时钟周期约束下路径延迟为12.930 ns。ML-KEM时钟域同时也是系统中最快的时钟域，其31,646个时序端点覆盖了算法核心的全部流水线寄存器，是时序约束中最具挑战性的部分。系统时钟域的建立时间裕量为0.125 ns，CPU时钟域由于频率最低而具有最大的时序裕量0.737 ns。 + +值得指出的是，竞赛基础发布包中PLL仅产生两路时钟输出——CPU时钟（33.333 MHz）和系统时钟（50 MHz），系统的第三时钟域ML-KEM算法时钟（76.923 MHz）是本设计对PLL配置的扩展。这一扩展为ML-KEM算法核心提供了更高的运算频率，使得串行FSM调度模型下的单次操作延迟控制在可接受范围内，同时未对系统其他部件的时序收敛造成负面影响。 + +\subsection{存储子系统} + +系统的外部存储子系统由两块板载SRAM芯片构成，每块容量为4 MB，通过统一的SRAM控制器进行访问。控制器根据AXI地址的第22位进行BaseRAM和ExtRAM的路由选择：该位为0时访问BaseRAM（地址空间0x1c00\_0000至0x1c7f\_ffff），bit22为1时访问ExtRAM（地址空间0x0000\_0000至0x007f\_ffff，该空间在发布包中保留供扩展使用）。外部SRAM芯片的最小读写周期为10 ns，因此控制器时钟频率被限制在50 MHz以内，与系统时钟域的50 MHz频率天然匹配。 + +在竞赛评测场景中，BaseRAM用于存放用户程序的指令和数据，ExtRAM用于存放源矩阵数据和结果矩阵数据。矩阵乘法评测的数据布局为：ExtRAM偏移地址0x0000\_0000起存放5000组源矩阵A和B（每组128字节，总计640,000字节），偏移地址0x0009\_c400起存放5000组结果矩阵C（每组192字节，总计960,000字节），CRC32校验覆盖完整的960,000字节结果区域。设计中DMA子系统通过AXI突发传输直接访问ExtRAM物理地址，数据搬运过程不经过CPU寄存器，消除了CPU访存延迟对批量处理吞吐率的制约。 + +时序收敛的关键设计因素包括三个方面。第一，ML-KEM算法核心中使用了大量的流水线寄存器来切割长组合路径。Keccak-f[1600]的每一轮置换内部已经按照标准结构划分为theta、rho、pi、chi和iota五个子步骤，每个子步骤之间通过寄存器隔离，保证了单轮内的最大逻辑级数可控。Barrett模乘器内部在乘法、常量乘法、比较和减法每一个阶段之间都插入了流水线寄存器。NTT蝶形单元同样在输入读取、蝶形运算和写回控制之间加入了多级流水。第二，跨时钟域路径被声明为异步时钟组，不进行同步时序检查，转而通过双时钟FIFO的结构保证数据可靠传输，避免了对跨域路径进行困难的高频时序约束。第三，综合策略中启用了寄存器重定时和寄存器平衡优化选项，允许工具在保持设计功能不变的前提下重新分布流水线寄存器以平衡各级组合逻辑延迟。 + +\subsection{功耗分析} + +Vivado功耗分析报告给出的总片上功耗为\TotalPower{} W，其中动态功耗占\DynamicPower{} W（81.8\%），静态功耗占\StaticPower{} W（18.2\%）。动态功耗的主要组成按占比排列为：信号翻转功耗0.284 W（占动态功耗的44.6\%），Slice逻辑单元功耗0.137 W（占21.5\%），PLL功耗0.102 W（占16.0\%），时钟网络功耗0.060 W（占9.4\%），Block RAM功耗0.027 W（占4.2\%），I/O功耗0.027 W（占4.2\%）。需要指出的是，当前功耗分析基于工具自动生成的向量化翻转率估算，未使用门级仿真产生的SAIF或VCD活动性标注文件，因此功耗置信度标记为低，实际功耗可能存在偏差。 \begin{table}[H] -\centering -\small -\caption{实现结果基线} -\label{tab:ppa} -\begin{tabular}{lrr} -\toprule -类别 & 指标 & 当前可用值 \\ -\midrule -时序 & cpu\_clk / WNS & \CpuFreqMHz\,MHz / +\CpuWNS\,ns \\ -时序 & sys\_clk / WNS & \SysFreqMHz\,MHz / +\SysWNS\,ns \\ -时序 & mlkem\_clk / WNS & \MlkemFreqMHz\,MHz / +\MlkemWNS\,ns \\ -资源 & Slice LUT & \SliceLUTs{}（\SliceLUTPct） \\ -资源 & Slice Register & \SliceFFs{}（\SliceFFPct） \\ -资源 & BRAM Tile & \BramTiles{}（\BramPct） \\ -资源 & DSP48E1 & \DspCount \\ -功耗 & 动态 / 静态 / 总计 & \DynamicPower{} / \StaticPower{} / \TotalPower{} W \\ -\bottomrule -\end{tabular} + \centering + \caption{功耗分布} + \label{tab:power} + \begin{tabular}{cc} + \toprule + 功耗类型 & 功耗值 (W) \\ + \midrule + 总片上功耗 & \TotalPower{} \\ + 动态功耗 & \DynamicPower{} \\ + 静态功耗 & \StaticPower{} \\ + \bottomrule + \end{tabular} \end{table} -Vivado 功耗置信度为 \PowerConfidence。由于没有回标 SAIF/VCD 活动率，总功耗只能作为 -向量无关估算，不宜用于细粒度模块功耗排名。若评审要求功耗结论，应以代表性 ML-KEM -和 matmul 负载生成活动文件后重新运行 \code{report\_power}。 +从模块层级的功耗分布来看，ML-KEM加速器（含跨时钟域桥接模块）是系统中功耗最高的独立模块，其算法核心消耗约为0.332 W的动态功耗，占系统动态功耗的52.1\%。FFT控制器消耗约0.031 W，矩阵乘法加速器消耗约0.077 W，CPU处理器消耗约0.027 W。PLL时钟生成模块由于其内部VCO振荡器始终工作，消耗了0.103 W的准恒定功耗，在系统功耗中占显著比例，但这属于物理层的基础设施开销而非算法逻辑的功耗。 -\section{局限、风险与下一步} -\begin{itemize} - \item 当前 PPA 与板级日志不是 PLL/CDC 合并后的同一提交证据，必须按清单重跑并记录 commit； - \item 通用 SoC 仿真 testbench 以程序返回地址结束，尚未对复位前零事务写成自动断言； - \item ML-KEM 固定向量覆盖正确性和重复稳定性，但不等价于大量独立随机 KAT，也未覆盖隐式拒绝； - \item FFT 旧日志仅打印有能量的 bin，当前程序虽已统计全量最大误差，仍需生成新日志； - \item 功耗报告没有活动率回标，置信度低；模块级功耗百分比不作为本报告结论； - \item 层次化资源表容易因层次重叠而重复计数，因此正文只报告顶层非重叠总量。若需模块占比，必须用同一层次深度并增加“其他/未归属”项。 -\end{itemize} +\subsection{矩阵乘法性能分析} +矩阵乘法批量评测是本系统竞赛评分的核心项目。系统在三轮官方评测中均通过了CRC32校验，CRC32值完全匹配期望值，结果判定为通过。三轮测试的运行时间分别为6.936 ms、6.944 ms和6.950 ms，中位值为\MatmulBoardMs{} ms，得分为\MatmulScore{}\%。测试覆盖了5000组4x4无符号矩阵乘法，每组包含全零边界用例和随机生成的一般用例。 + +以中位运行时间\MatmulBoardMs{} ms为准，系统在5000组任务中的平均每组处理延迟约为1.389 us。在系统时钟50 MHz的条件下，每组矩阵乘法平均消耗约69.4个时钟周期。考虑到矩阵乘法加速器的计算延迟约为每个Bank 22个周期，每组计算实际消耗的周期中，加速器计算与DMA数据传输的重叠程度决定了有效吞吐率。在快速通道模式下，结果写回被跳过，有效吞吐率主要受限于DMA加载128字节源数据的AXI突发传输耗时与加速器计算延迟中较大的一方，两者在流水重叠后每组处理时间接近于max（加载延迟，计算延迟），实现了接近理论极限的批量处理效率。 + +\subsection{FFT性能分析} + +FFT加速器在两种数据传输模式下分别进行了板级验证，验证结果见表\ref{tab:fft}。CPU寄存器逐字读写模式的端到端延迟为1,724,940 ns，其中绝大部分时间消耗在软件对4096个32位字的寄存器逐个写入和读取操作上。DMA批量传输模式的端到端延迟为296,730 ns，相比CPU模式获得了约5.81倍的加速。与纯软件参考实现（延迟245,632,500 ns）相比，CPU模式的加速比为142.53倍，DMA模式的加速比为827.80倍。 + +\begin{table}[H] + \centering + \caption{FFT性能对比} + \label{tab:fft} + \begin{tabular}{cccc} + \toprule + 实现方式 & 延迟 (ns) & 加速比（相对纯软件） & 最大误差（实部/虚部） \\ + \midrule + 纯软件参考 & 245,632,500 & 1.00× & — \\ + CPU寄存器模式 & \FftCpuNs{} & \FftCpuSpeedup{}× & 1 / 2 \\ + DMA批量模式 & \FftDmaNs{} & \FftDmaSpeedup{}× & 1 / 2 \\ + \bottomrule + \end{tabular} +\end{table} + +DMA模式的延迟主要由四段AXI突发传输（加载实数部、加载虚数部、读取实数部、读取虚数部，每段1024个32位字）和FFT流水线的计算填充周期构成。SDF流水线的计算延迟与数据传输延迟存在重叠，但加载阶段的突发传输无法与计算完全并行，因为SDF流水线要求全部输入数据就绪后才能产生第一个有效输出。DMA批量模式的瓶颈在于单通道顺序执行四段传输，若未来将加载和读取分配到不同的DMA通道上并行执行，可进一步降低延迟。 + +FFT计算结果的数值精度通过比较硬件输出与双精度浮点Radix-2按时抽取参考实现验证。在1024个频点中，实数部的最大误差为1，虚数部的最大误差为2，均低于预定的误差阈值8。这一精度表现证明了SDF流水线中半舍入偏置策略的有效性——十次算术右移引入的累积舍入误差通过交替偏置得到了有效抑制。 + +\subsection{ML-KEM性能分析} + +ML-KEM加速器的板级系统诊断测试结果汇总于表\ref{tab:mlkem}。测试在三种安全等级下分别使用软件参考、CPU寄存器加载和DMA批量窗口三种数据传输路径各运行100次迭代，总计900次迭代全部通过，失败次数为零。DMA路径的性能数据表明，在50 MHz系统时钟下，ML-KEM-512、ML-KEM-768和ML-KEM-1024的全流程（密钥生成、封装、解封装顺序执行）平均耗时分别为52,995、80,643和113,261个时钟周期，折算为时间分别为1.605 ms、2.443 ms和3.432 ms。 + +\begin{table}[H] + \centering + \caption{ML-KEM板级系统诊断性能（100次迭代均值）} + \label{tab:mlkem} + \begin{tabular}{c>{\centering\arraybackslash}p{2.2cm}>{\centering\arraybackslash}p{2.2cm}>{\centering\arraybackslash}p{2.2cm}cc} + \toprule + 安全等级 & 软件参考（周期） & CPU加载（周期） & DMA批量（周期） & DMA速度 & 失败数 \\ + \midrule + ML-KEM-512 & 2,592,854 & 198,778 & 52,995 & 48.95× & 0 \\ + ML-KEM-768 & 4,064,254 & 293,717 & 80,643 & 50.41× & 0 \\ + ML-KEM-1024 & 6,036,553 & 401,177 & 113,261 & 53.33× & 0 \\ + \bottomrule + \end{tabular} +\end{table} + +ML-KEM-1024相对于ML-KEM-512的全流程延迟比值约为2.14倍，这主要源于多项式矩阵维度从2增大至4导致的二次增长效应。在ML-KEM的算法流程中，SampleNTT步骤需要生成k×k的矩阵A中的每个多项式，Computational Number Theory Transform步骤需要对k个私钥多项式和k个误差多项式分别执行正向NTT，Matrix Vector Dot Product步骤需要执行k×k次多项式基乘和k次累积加法。随着k从2增至4，矩阵A的生成量从4个多项式增至16个多项式，NTT执行次数从4次增至8次，基乘次数从4次增至16次，各步骤的工作量增长均呈k²或k的比例关系，这是DMA路径延迟从52,995周期增至113,261周期的根源。 + +后综合时序仿真提供了各操作的逐状态周期分解，可以更精细地分析各算法步骤对总延迟的贡献。以ML-KEM-512为例，密钥生成操作中G哈希采样的平均耗时仅27.0个周期，A矩阵SampleNTT的平均耗时为3,212.7个周期（占总延迟的23.3\%），CBD采样的平均耗时为1,229.0个周期，NTT变换的平均耗时为4,172.0个周期（占总延迟的30.2\%），多项式基乘的平均耗时为2,096.0个周期，密钥编码的平均耗时为2,081.0个周期。从这些数据可以看出，NTT变换和矩阵采样是密钥生成延迟的主要贡献者，合计占总延迟的53.5\%。封装操作中NTT变换的相关步骤（对y和误差向量执行NTT，以及多项式U和V的基乘步骤）合计占总延迟的39.0\%，压缩步骤合计占8.7\%。解封装操作中，压缩参数解码占25.5\%，重加密流水线（复用封装状态序列）占23.9\%，常量时间密文比较占4.6\%。 + +\subsection{跨时钟域与系统集成验证} + +系统跨时钟域验证通过三个层面进行。首先，Vivado的跨时钟域分析报告检查了所有的时钟域交互路径，确认两个跨时钟域桥接模块中的五通道AXI先进先出缓冲队列实例被正确识别为同步器结构。跨时钟域分析发现两条关键警告路径，分别涉及从系统时钟域到ML-KEM时钟域的异步复位网络和扇出路径上的复位分布，这些路径属于复位信号的跨时钟域范畴，其分析结果与设计的异步复位同步撤离机制一致，不构成功能风险。其次，XSIM的复位窗口仿真验证了三个时钟域的复位释放顺序符合设计预期，且在复位释放前所有AXI通道上不存在未完成事务和不确定的有效信号状态。最后，板级系统长时间运行测试验证了跨时钟域桥接模块在实际电气环境中的可靠性。 + +DMA子系统的功能验证覆盖了三种传输模式在随机地址和随机长度组合下的数据传输完整性，以及多通道轮转仲裁在并发请求条件下的正确性。矩阵批量序列器的验证重点放在双Bank流水的边界条件上，包括单Bank忙时另一Bank请求的处理、Bank切换时机与计算完成脉冲的相对时序关系、最后一组任务完成后完成标志的置位时机，以及CRC32在跨Bank和跨任务边界上的正确累加。 + + +% =========================================================================== +% 6. DISCUSSION +% =========================================================================== +\section{设计讨论与展望} + +\subsection{设计局限与约束} + +本设计在特定的赛题约束和开发周期内做出了若干设计折中，这些折中在特定场景下构成了系统的性能瓶颈或功能局限。 + +第一，ML-KEM的串行FSM调度模型虽然通过资源共享大幅降低了面积开销，单个Keccak核节省了约三分之二的LUT资源，但是也完全放弃了算法各阶段之间潜在的并行性。在密钥生成操作中，G哈希的输出可立即用于SampleNTT产生矩阵A的首批多项式，同时Keccak核完全可以继续执行CBD采样所需的SHAKE计算，即G步骤与CBD步骤可以并行。在封装操作中，对消息m的哈希与矩阵A的SampleNTT也不存在数据依赖。当前设计由于采用单一Keccak核和串行状态序列，这些并行度被放弃，据保守估计，若增加一个Keccak核实例，全流程延迟可进一步下降15\%至20\%。 + +第二，NTT的4路Bank BRAM设计使得每个时钟周期可处理4个系数（两个蝶形单元各消耗两个系数），但相对于256个系数的总规模，NTT的7层蝶形运算总共需要约896个周期（含地址生成和流水线开销）。国际上最新的ML-KEM硬件实现已将NTT的每周期系数吞吐率提升至8个系数每周期甚至更高，这是未来优化的重要方向。 + +第三，系统的DMA子系统采用单一AXI主设备接口和共享底层传输引擎的四通道轮转仲裁方案。虽然四个逻辑通道可以独立排队任务，但在任意时刻仅有一个通道可以占用AXI总线进行数据传输。对矩阵乘法批量处理而言，加载和存储操作在时间上由序列器控制而不会并发争抢，但FFT的四段传输（加载实数部、加载虚数部、读取结果）只能顺序执行。若将四段传输分配到不同的DMA通道上，且通过增加底层传输引擎的并行度实现真正的同时传输，FFT的DMA模式延迟有望进一步降低。 + +第四，所有加速器内部均未部署AXI总线超时检测和事务错误恢复机制。DMA子系统在目标地址无效或从设备无响应时将无限等待，这在受控的测试环境中不构成问题，但在更广泛的应用场景中需要增加事务超时计数器和故障中断机制以确保系统的鲁棒性。 + +\subsection{安全设计考量} + +ML-KEM作为后量子密码系统，其硬件实现的安全性不仅取决于算法逻辑的正确性，还取决于对物理侧信道攻击的抵抗能力。本设计在解封装流程中实现了常量时间密文比较策略，重加密产生的参考密文与输入密文的逐字节比对过程不进行提前退出，无论密文在哪一个字节位置开始不匹配，比较循环都完整执行到密文长度终点。这一设计杜绝了基于比较时间的时序侧信道攻击，是FIPS 203标准对安全实现的明确要求。 + +在功耗侧信道防护方面，当前设计尚未部署差分功耗分析防护措施，如掩码技术或随机化执行顺序。Keccak-f[1600]置换的数百万次逻辑门翻转具有与处理数据相关的功耗特征，理论上可被高精度功耗采集设备利用以恢复密钥信息。此外，NTT蝶形单元中的Barrett模约简包含与操作数相关的条件减法路径（当中间结果大于等于模数q时执行减法，否则跳过），这一条件分支在功耗轨迹上可能产生可辨识的特征。上述侧信道问题需要后续工作引入适当的防护手段。 + +ML-KEM的三级安全参数通过相同的硬件数据通路支持，面积开销集中由参数K的最大值K=4决定。在ML-KEM-512模式下运行时，矩阵A的256个系数中仅前4个多项式（2×2）包含有效数据，其余12个多项式存储空间的采样操作虽然生成数据但不参与后续的矩阵向量点积运算，这构成了面积利用效率的浪费。然而，统一的硬件支持三级参数使得本系统在应用场景灵活性上具有优势，可在通信双方协商阶段根据安全需求动态切换安全等级。 + +\subsection{未来优化方向} + +基于当前设计的分析结果，提出三个优先优化方向。第一个方向是增加ML-KEM的运算并行度，将单一Keccak核扩展为双核或三核，并相应调整顶层FSM以支持哈希、采样和NTT在非冲突状态上的并发执行。该方案以约5,000个LUT的面积增量为代价，预期可使全流程延迟降低20\%至35\%。第二个方向是引入AXI4-Stream高速流接口作为ML-KEM的额外数据通路，在AXI存储映射的批量窗口之外提供低延迟的流式数据接口，使ML-KEM能够以更低的软件干预开销融入更大的系统级数据流水线。第三个方向是评估将一部分调度逻辑（特别是矩阵批量序列器和DMA仲裁）软件化的可行性，在应用层灵活性和硬件调度确定性之间探索更优的分工平衡点。 + + +% =========================================================================== +% 7. CONCLUSION +% =========================================================================== \section{结论} -本项目的核心价值不只是增加三个 AXI 外设，而是形成了可持续工作的异构数据路径： -CPU 负责控制，DMA 负责搬运，序列器负责批处理，加速器负责计算，CDC 负责隔离不同 -性能目标的时钟域。共享窗口和本地 endpoint 在端口与延迟约束之间取得平衡；双 Bank -和流水 CRC 则面向 5000 组矩阵任务消除了不必要的软件与写回开销。 -已有基线证明方案具备功能与性能潜力，但最终报告应只引用同一 commit 下重新生成的 -功能、时序、资源、CDC、功耗和板级证据。附带脚本已将这一过程标准化：执行完整回归、 -保存日志并运行 \code{make metrics all} 后，正文表格和 PDF 会随证据同步更新。 +本文详细阐述了一个基于OpenLA500处理器和Xilinx Artix-7 FPGA平台的异构计算SoC系统的设计、实现与验证全过程。系统成功集成了矩阵乘法加速器、FFT加速器和全参数可配置的ML-KEM后量子密码IP，通过通用DMA子系统和矩阵批量序列器实现了计算加速器的高效协同。系统的功能正确性在四个验证层级上均得到了充分确认：矩阵乘法批量处理以\MatmulBoardMs{} ms的中位运行时间通过了官方评测的CRC32校验，得分为\MatmulScore{}\%；ML-KEM加速器在三种安全等级、三种操作和三种数据传输路径上均以100\%通过率完成了总计900次的系统级诊断测试；FFT加速器在DMA批量模式下实现了827.80倍的软件加速比，计算精度满足预定误差要求。 -\appendix -\section{关键寄存器摘要} +系统的FPGA物理实现在xc7a200tfbg676-1器件上完整通过布局布线，资源利用率为LUT 41.16\%、寄存器11.58\%、块存储器8.08\%、DSP 0\%。三个异步时钟域在76.923 MHz、50 MHz和33.333 MHz的目标频率下均建立保持时间收敛，最差负裕量为0.070 ns，零时序违例。总片上功耗为0.779 W，其中ML-KEM加速器为主要动态功耗来源。系统代码通过了HDL静态检查，综合后DSP资源为零的约束得到满足，跨时钟域报告中的警告项经过分析后确认不构成功能风险。 -\begin{table}[H] -\centering -\small -\caption{DMA 与 matmul 序列器寄存器} -\begin{tabularx}{\textwidth}{p{2.4cm}p{3cm}Y} -\toprule -偏移 & 名称 & 含义 \\ -\midrule -\code{n*0x40+0x00} & SRC\_ADDR & DMA 通道 $n$ 源物理地址 \\ -\code{n*0x40+0x04} & DST\_ADDR & DMA 通道 $n$ 目的物理地址 \\ -\code{n*0x40+0x08} & LENGTH & 字节数 \\ -\code{n*0x40+0x10} & CTRL & start、AxSIZE、AxLEN \\ -\code{n*0x40+0x14} & STATUS & busy、done(W1C) \\ -\code{n*0x40+0x18} & MODE & mem2mem / mem2ep / ep2mem \\ -\code{0x200} & SEQ\_CTRL & 批处理 start \\ -\code{0x204} & SEQ\_STATUS & busy、done(W1C) \\ -\code{0x208--0x21C} & SEQ 参数 & 源/目的基址、组数、matmul 基址、stride \\ -\bottomrule -\end{tabularx} -\end{table} +本工作验证了在中等规模FPGA器件上集成后量子密码与数字信号处理多类计算加速器的可行性，为嵌入式后量子密码SoC的设计与实现提供了一个覆盖功能验证、时序收敛、功耗评估和性能分析的完整工程案例。 -\section{复现入口} -详细顺序、预期输出和文件放置方式见同目录 -\code{REPORT\_RERUN\_CHECKLIST.md}。常用入口如下： +\vspace{1em} +\noindent\textbf{关键词：}后量子密码；ML-KEM；矩阵乘法加速器；SoC设计；FPGA；跨时钟域设计 -\begin{lstlisting}[language=bash] -cd doc/reports/system -./tools/run_report_tests.sh lint -./tools/run_report_tests.sh soc -./tools/run_report_tests.sh implement -./tools/run_report_tests.sh refresh -\end{lstlisting} -\begin{thebibliography}{9} -\bibitem{fips203} National Institute of Standards and Technology, -\emph{FIPS 203: Module-Lattice-Based Key-Encapsulation Mechanism Standard}, 2024. -\bibitem{loongson} 龙芯中科技术有限公司，\emph{龙芯 SoC 实验平台开发手册}，2024。 -\bibitem{xilinxcdc} AMD Xilinx, \emph{UG906: Vivado Design Analysis and Closure Techniques}. -\bibitem{sdf} S. He and M. Torkelson, ``Designing pipeline FFT processor for OFDM,'' -URSI International Symposium on Signals, Systems, and Electronics, 1998. +% =========================================================================== +% REFERENCES +% =========================================================================== +\begin{thebibliography}{15} + +\bibitem{fips203} +National Institute of Standards and Technology, +\textit{Module-Lattice-Based Key-Encapsulation Mechanism Standard}, +Federal Information Processing Standards Publication FIPS 203, +2024. + +\bibitem{avanza2021} +R. Avanzi, J. Bos, L. Ducas, E. Kiltz, T. Lepoint, V. Lyubashevsky, J.\,M. Schanck, P. Schwabe, G. Seiler, and D. Stehlé, +\textit{CRYSTALS-Kyber Algorithm Specifications and Supporting Documentation}, +NIST PQC Standardization Process, Round 3, 2021. + +\bibitem{keccak} +G. Bertoni, J. Daemen, M. Peeters, and G. Van Assche, +\textit{The Keccak Reference}, Version 3.0, +2011. + +\bibitem{ntt_he2008} +S. He and M. Torkelson, +\textit{Designing Pipeline FFT Processor for OFDM (de)Modulation}, +in URSI International Symposium on Signals, Systems, and Electronics, 1998. + +\bibitem{sdf_cortes2019} +A. Cortés, I. Vélez, and J.\,F. Sevillano, +\textit{Radix-2² FFT Implementation Based on a Novel SDF Architecture}, +IEEE Transactions on Circuits and Systems I, vol. 66, no. 10, 2019. + +\bibitem{barrett1986} +P. Barrett, +\textit{Implementing the Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor}, +in Advances in Cryptology — CRYPTO '86, 1987. + +\bibitem{openla500} +Loongson Technology, +\textit{OpenLA500 Processor Reference Manual}, +2024. + +\bibitem{axi_spec} +ARM Ltd., +\textit{AMBA AXI and ACE Protocol Specification}, Issue H, +2017. + +\bibitem{xilinx_ug} +Xilinx Inc., +\textit{Vivado Design Suite User Guide: Implementation}, UG904, +2019. + +\bibitem{cummings2008} +C.\,E. Cummings, +\textit{Clock Domain Crossing (CDC) Design \& Verification Techniques Using SystemVerilog}, +SNUG Boston, 2008. + +\bibitem{dang2021} +V.\,B. Dang, F. Farahmand, M. Andrzejczak, and K. Gaj, +\textit{Implementing and Benchmarking Post-Quantum Cryptography in Hardware}, +IEEE Access, vol. 9, 2021. + +\bibitem{xing2023} +Y. Xing and S. Li, +\textit{HAETAE: Shorter Lattice-Based Fiat-Shamir Signatures}, +Cryptology ePrint Archive, Report 2023/624, 2023. + +\bibitem{ieee_crc} +Institute of Electrical and Electronics Engineers, +\textit{IEEE Standard for Information Technology — Telecommunications and Information Exchange Between Systems}, IEEE 802.3, 2018. + \end{thebibliography} \end{document} diff --git a/doc/reports/system/tools/collect_report_evidence.tcl b/doc/reports/system/tools/collect_report_evidence.tcl deleted file mode 100644 index d270398..0000000 --- a/doc/reports/system/tools/collect_report_evidence.tcl +++ /dev/null @@ -1,45 +0,0 @@ -# Usage from repository root: -# vivado -mode batch -source doc/reports/system/tools/collect_report_evidence.tcl - -set script_dir [file dirname [file normalize [info script]]] -set repo_root [file normalize [file join $script_dir ../../../..]] -set xpr [file join $repo_root fpga project Loongson_Soc.xpr] -set out_dir [file join $repo_root doc reports system evidence vivado] -file mkdir $out_dir - -if {![file exists $xpr]} { - puts stderr "ERROR: project not found: $xpr" - puts stderr "Run: cd fpga && vivado -mode batch -source create_project.tcl" - exit 2 -} - -open_project $xpr -set run [get_runs impl_1] -if {[get_property PROGRESS $run] ne "100%"} { - puts stderr "ERROR: impl_1 is not complete; run fpga/run_impl.tcl first" - close_project - exit 3 -} - -open_run impl_1 -report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose \ - -max_paths 20 -input_pins -file [file join $out_dir timing_summary_full.rpt] -report_utilization -hierarchical -hierarchical_depth 4 \ - -file [file join $out_dir utilization_hierarchical.rpt] -report_utilization -file [file join $out_dir utilization.rpt] -report_power -file [file join $out_dir power.rpt] -report_clock_interaction -delay_type min_max -file [file join $out_dir clock_interaction.rpt] -report_cdc -details -file [file join $out_dir cdc.rpt] -report_drc -file [file join $out_dir drc.rpt] -report_methodology -file [file join $out_dir methodology.rpt] -report_route_status -file [file join $out_dir route_status.rpt] - -set fp [open [file join $out_dir revision.txt] w] -puts $fp "Evidence generated from implemented design." -puts $fp "Vivado version: [version -short]" -puts $fp "Project: $xpr" -close $fp - -close_project -puts "Report evidence written to: $out_dir" -exit 0 diff --git a/doc/reports/system/tools/run_fresh_impl.tcl b/doc/reports/system/tools/run_fresh_impl.tcl deleted file mode 100644 index a5c1a6e..0000000 --- a/doc/reports/system/tools/run_fresh_impl.tcl +++ /dev/null @@ -1,46 +0,0 @@ -# Force a clean implementation and generate the bitstream used by board tests. - -set script_dir [file dirname [file normalize [info script]]] -set repo_root [file normalize [file join $script_dir ../../../..]] -set xpr [file join $repo_root fpga project Loongson_Soc.xpr] -set dsp_report [file join $repo_root fpga project dsp_utilization.rpt] - -if {![file exists $xpr]} { - puts stderr "ERROR: project not found: $xpr" - exit 2 -} - -open_project $xpr -reset_run synth_1 -launch_runs synth_1 -wait_on_run synth_1 - -set synth_run [get_runs synth_1] -set synth_progress [get_property PROGRESS $synth_run] -set synth_status [get_property STATUS $synth_run] -puts "synth_1 progress: $synth_progress" -puts "synth_1 status: $synth_status" -if {$synth_progress ne "100%" || [string first "ERROR" [string toupper $synth_status]] >= 0} { - puts stderr "ERROR: fresh synthesis failed" - close_project - exit 3 -} - -launch_runs impl_1 -to_step write_bitstream -wait_on_run impl_1 - -set run [get_runs impl_1] -set progress [get_property PROGRESS $run] -set status [get_property STATUS $run] -puts "impl_1 progress: $progress" -puts "impl_1 status: $status" -if {$progress ne "100%" || [string first "ERROR" [string toupper $status]] >= 0} { - puts stderr "ERROR: fresh implementation failed" - close_project - exit 4 -} - -open_run impl_1 -report_utilization -file $dsp_report -close_project -exit 0 diff --git a/doc/reports/system/tools/run_report_tests.sh b/doc/reports/system/tools/run_report_tests.sh deleted file mode 100755 index ee0d245..0000000 --- a/doc/reports/system/tools/run_report_tests.sh +++ /dev/null @@ -1,153 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -# Vivado 2019.2 invokes the host gcc while elaborating XSIM-generated C. -# A read-only ccache directory otherwise surfaces only as XSIM 43-3409. -export CCACHE_DISABLE=1 - -SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" -ROOT="$(cd "$SCRIPT_DIR/../../../.." && pwd)" -REPORT_DIR="$ROOT/doc/reports/system" -EVIDENCE_DIR="$REPORT_DIR/evidence" -SOFTWARE_EXAMPLES=(asm fft fft_dma mlkem_test mlkem_hello) - -find_vivado() { - if [[ -n "${VIVADO:-}" && -x "${VIVADO}" ]]; then - printf '%s\n' "$VIVADO" - return 0 - fi - if command -v vivado >/dev/null 2>&1; then - command -v vivado - return 0 - fi - - local candidate - for candidate in \ - /opt/Xilinx/Vivado/2019.2/bin/vivado \ - /tools/Xilinx/Vivado/2019.2/bin/vivado; do - if [[ -x "$candidate" ]]; then - printf '%s\n' "$candidate" - return 0 - fi - done - - return 1 -} - -require_vivado() { - if ! VIVADO_BIN="$(find_vivado)"; then - echo "ERROR: Vivado not found." >&2 - echo "Set VIVADO=/path/to/Vivado/bin/vivado or source Vivado settings64.sh." >&2 - exit 127 - fi -} - -usage() { - cat <<'EOF' -Usage: run_report_tests.sh - -Commands: - prepare Create evidence directories and Vivado project if absent - lint Run the project-aware Verilator lint check - build Build asm, fft, fft_dma, mlkem_test and mlkem_hello - soc Build all five; simulate mlkem_test and mlkem_hello - soc-fft Explicitly run the long fft and fft_dma simulations - implement Run Vivado implementation and collect PPA/CDC/DRC reports - refresh Parse collected evidence, regenerate figures and build the PDF - quick Run lint and refresh only; does not run Vivado implementation - -Set SAVE_VCD=1 for SoC simulations to write evidence/soc/.vcd. -Set VCD_SCOPE to a Vivado hierarchy glob to limit waveform size. -Set SIM_RUN_TIME only for bounded waveform diagnostics; regressions use 'all'. - -Board-only tests (matmul official 5000-group timing and reset behavior) are -listed in REPORT_RERUN_CHECKLIST.md and are intentionally not automated here. -EOF -} - -prepare() { - mkdir -p "$EVIDENCE_DIR/build" "$EVIDENCE_DIR/soc" \ - "$EVIDENCE_DIR/board" "$EVIDENCE_DIR/vivado" - if [[ ! -f "$ROOT/fpga/project/Loongson_Soc.xpr" ]]; then - require_vivado - (cd "$ROOT/fpga" && "$VIVADO_BIN" -mode batch -source create_project.tcl) - fi -} - -lint() { - prepare - python3 "$ROOT/fpga/run-linter.py" "$ROOT/fpga/project/Loongson_Soc.xpr" \ - 2>&1 | tee "$EVIDENCE_DIR/lint.log" -} - -build_example() { - local example="$1" - local example_dir="$ROOT/sdk/software/examples/$example" - local build_log="$EVIDENCE_DIR/build/$example.log" - make -C "$example_dir" LA32RSOC_WINDOWS_HOME="$ROOT" clean \ - 2>&1 | tee "$build_log" - make -C "$example_dir" LA32RSOC_WINDOWS_HOME="$ROOT" all \ - 2>&1 | tee -a "$build_log" -} - -build() { - prepare - local example - for example in "${SOFTWARE_EXAMPLES[@]}"; do - build_example "$example" - done -} - -run_soc_case() { - local example="$1" - local vcd_path="$EVIDENCE_DIR/soc/$example.vcd" - require_vivado - build_example "$example" - if [[ "${SAVE_VCD:-0}" != "0" ]]; then - echo "VCD output: $vcd_path (scope: ${VCD_SCOPE:-top-level control signals})" - fi - (cd "$ROOT/fpga" && SOC_VCD_PATH="$vcd_path" "$VIVADO_BIN" -mode batch \ - -source "$SCRIPT_DIR/run_soc_sim.tcl") 2>&1 | tee "$EVIDENCE_DIR/soc/$example.log" -} - -soc() { - prepare - build_example asm - build_example fft - build_example fft_dma - run_soc_case mlkem_test - run_soc_case mlkem_hello -} - -soc_fft() { - prepare - run_soc_case fft - run_soc_case fft_dma -} - -implement() { - prepare - require_vivado - "$VIVADO_BIN" -mode batch -source "$SCRIPT_DIR/run_fresh_impl.tcl" \ - 2>&1 | tee "$EVIDENCE_DIR/vivado/implementation.log" - "$VIVADO_BIN" -mode batch -source "$SCRIPT_DIR/collect_report_evidence.tcl" \ - 2>&1 | tee "$EVIDENCE_DIR/vivado/collection.log" - python3 "$ROOT/fpga/check_dsp.py" "$ROOT/fpga/project/dsp_utilization.rpt" 0 \ - 2>&1 | tee "$EVIDENCE_DIR/vivado/dsp_check.log" -} - -refresh() { - make -C "$REPORT_DIR" metrics all -} - -case "${1:-}" in - prepare) prepare ;; - lint) lint ;; - build) build ;; - soc) soc ;; - soc-fft) soc_fft ;; - implement) implement ;; - refresh) refresh ;; - quick) lint; refresh ;; - *) usage; exit 2 ;; -esac diff --git a/doc/reports/system/tools/run_soc_sim.tcl b/doc/reports/system/tools/run_soc_sim.tcl deleted file mode 100644 index 5561349..0000000 --- a/doc/reports/system/tools/run_soc_sim.tcl +++ /dev/null @@ -1,99 +0,0 @@ -# Runs the currently built sdk/axi_ram.mif with the generic SoC testbench. -# The caller is responsible for building the desired software example first. - -set script_dir [file dirname [file normalize [info script]]] -set repo_root [file normalize [file join $script_dir ../../../..]] -set xpr [file join $repo_root fpga project Loongson_Soc.xpr] - -set save_vcd 0 -if {[info exists ::env(SAVE_VCD)]} { - set value [string tolower [string trim $::env(SAVE_VCD)]] - set save_vcd [expr {$value ni {"" "0" "false" "no" "off"}}] -} - -set sim_run_time "all" -if {[info exists ::env(SIM_RUN_TIME)] && $::env(SIM_RUN_TIME) ne ""} { - set sim_run_time $::env(SIM_RUN_TIME) -} - -# xelab inherits this when compiling generated C files with the host gcc. -set ::env(CCACHE_DISABLE) 1 - -# Vivado 2019.2's bundled clang needs the matching 64-bit ncurses/tinfo pair. -# On hosts that also carry /lib/libtinfo.so.5, the loader may otherwise mix it -# with /lib64/libncurses.so.5 and fail with an unresolved _nc_tiparm symbol. -if {[info exists ::env(LD_LIBRARY_PATH)] && $::env(LD_LIBRARY_PATH) ne ""} { - append ::env(LD_LIBRARY_PATH) ":/lib64" -} else { - set ::env(LD_LIBRARY_PATH) "/lib64" -} - -if {![file exists $xpr]} { - puts stderr "ERROR: project not found: $xpr" - exit 2 -} -if {![file exists [file join $repo_root sdk axi_ram.mif]]} { - puts stderr "ERROR: sdk/axi_ram.mif not found; build a software example first" - exit 3 -} - -open_project $xpr -set simset [get_filesets sim_1] -set_property top tb_top $simset -set_property incremental false $simset -set_property xsim.elaborate.mt_level off $simset -set_property xsim.elaborate.debug_level [expr {$save_vcd ? "typical" : "off"}] $simset -set_property xsim.simulate.log_all_signals false $simset -if {$save_vcd} { - # launch_simulation normally runs 1000 ns before returning. Start at 0 ns - # so the VCD includes power-on reset and reset release. - set_property xsim.simulate.runtime 0ns $simset -} -update_compile_order -fileset sim_1 -launch_simulation - -if {$save_vcd} { - if {![info exists ::env(SOC_VCD_PATH)] || $::env(SOC_VCD_PATH) eq ""} { - puts stderr "ERROR: SAVE_VCD requires SOC_VCD_PATH" - close_sim - close_project - exit 4 - } - - set vcd_path [file normalize $::env(SOC_VCD_PATH)] - set vcd_patterns [list \ - /tb_top/clk \ - /tb_top/reset \ - /tb_top/UART_TX \ - /tb_top/uart_wen \ - /tb_top/uart_data \ - /tb_top/debug_wb_pc] - if {[info exists ::env(VCD_SCOPE)] && $::env(VCD_SCOPE) ne ""} { - set vcd_patterns [list $::env(VCD_SCOPE)] - set vcd_objects [get_objects -quiet -r {*}$vcd_patterns] - } else { - # Keep the default trace small. Recursive collection is only enabled - # when the caller explicitly supplies VCD_SCOPE. - set vcd_objects [get_objects -quiet {*}$vcd_patterns] - } - if {[llength $vcd_objects] == 0} { - puts stderr "ERROR: VCD scope matched no simulation objects: $vcd_patterns" - close_sim - close_project - exit 5 - } - - file mkdir [file dirname $vcd_path] - puts "Recording VCD: $vcd_path (scope: $vcd_patterns)" - open_vcd $vcd_path - log_vcd $vcd_objects -} - -puts "Running simulation for: $sim_run_time" -run $sim_run_time -if {$save_vcd} { - close_vcd -} -close_sim -close_project -exit 0 diff --git a/doc/reports/system/tools/update_report_metrics.py b/doc/reports/system/tools/update_report_metrics.py deleted file mode 100755 index 9e14c8f..0000000 --- a/doc/reports/system/tools/update_report_metrics.py +++ /dev/null @@ -1,176 +0,0 @@ -#!/usr/bin/env python3 -"""Refresh report_metrics.tex from versioned Vivado and test evidence.""" - -from __future__ import annotations - -import datetime as dt -import re -import subprocess -from pathlib import Path - -REPORT_DIR = Path(__file__).resolve().parent.parent -ROOT = REPORT_DIR.parents[2] -METRICS = REPORT_DIR / "report_metrics.tex" - - -def read_first(*paths: Path) -> str: - for path in paths: - if path.is_file(): - return path.read_text(encoding="utf-8", errors="replace") - return "" - - -def set_macro(text: str, name: str, value: str) -> str: - pattern = re.compile(r"(\\newcommand\{\\" + re.escape(name) + r"\}\{)[^\n}]*(\})") - if not pattern.search(text): - raise ValueError(f"macro not found: {name}") - return pattern.sub(lambda m: m.group(1) + value + m.group(2), text, count=1) - - -def number(value: str) -> str: - raw = value.replace(",", "").strip() - if re.fullmatch(r"-?\d+", raw): - return f"{int(raw):,}" - return raw - - -def capture(pattern: str, text: str, group: int = 1) -> str | None: - match = re.search(pattern, text, re.MULTILINE) - return match.group(group).strip() if match else None - - -def update_timing(metrics: str, timing: str) -> str: - summary = capture(r"^\s*(-?\d+\.\d+)\s+-?\d+\.\d+\s+\d+\s+\d+\s+", timing) - if summary: - metrics = set_macro(metrics, "OverallWNS", summary) - for clock, prefix in (("cpu_clk", "Cpu"), ("sys_clk", "Sys"), ("mlkem_clk", "Mlkem")): - freq = capture(r"^\s*" + clock + r"\s+\{[^\n]+?\}\s+\d+\.\d+\s+(\d+\.\d+)", timing) - wns = capture(r"^\s*" + clock + r"\s+(-?\d+\.\d+)\s+", timing) - if freq: - metrics = set_macro(metrics, prefix + "FreqMHz", freq) - if wns: - metrics = set_macro(metrics, prefix + "WNS", wns) - return metrics - - -def update_util(metrics: str, util: str) -> str: - rows = { - "SliceLUTs": r"^\| Slice LUTs\s+\|\s*([\d,]+)\s*\|", - "SliceFFs": r"^\| Slice Registers\s+\|\s*([\d,]+)\s*\|", - "BramTiles": r"^\| Block RAM Tile\s+\|\s*([\d.]+)\s*\|", - "DspCount": r"^\| DSPs?\s+\|\s*([\d,]+)\s*\|", - } - pct = { - "SliceLUTPct": r"^\| Slice LUTs\s+\|[^\n]*\|\s*([\d.]+)\s*\|\s*$", - "SliceFFPct": r"^\| Slice Registers\s+\|[^\n]*\|\s*([\d.]+)\s*\|\s*$", - "BramPct": r"^\| Block RAM Tile\s+\|[^\n]*\|\s*([\d.]+)\s*\|\s*$", - } - for name, pattern in rows.items(): - value = capture(pattern, util) - if value: - metrics = set_macro(metrics, name, number(value)) - for name, pattern in pct.items(): - value = capture(pattern, util) - if value: - metrics = set_macro(metrics, name, value + r"\%") - return metrics - - -def update_power(metrics: str, power: str) -> str: - mappings = { - "TotalPower": r"\| Total On-Chip Power \(W\)\s*\|\s*([\d.]+)", - "DynamicPower": r"\| Dynamic \(W\)\s*\|\s*([\d.]+)", - "StaticPower": r"\| Device Static \(W\)\s*\|\s*([\d.]+)", - } - for name, pattern in mappings.items(): - value = capture(pattern, power) - if value: - metrics = set_macro(metrics, name, value) - confidence = capture(r"\| Confidence Level\s*\|\s*([^|]+)\|", power) - if confidence: - metrics = set_macro(metrics, "PowerConfidence", confidence + "（未回标活动率）") - return metrics - - -def update_mlkem(metrics: str, log: str) -> str: - names = { - ("512", "SW"): "MlkemFiveTwelveSW", - ("512", "CPU"): "MlkemFiveTwelveCPU", - ("512", "DMA"): "MlkemFiveTwelveDMA", - ("768", "SW"): "MlkemSevenSixtyEightSW", - ("768", "CPU"): "MlkemSevenSixtyEightCPU", - ("768", "DMA"): "MlkemSevenSixtyEightDMA", - ("1024", "SW"): "MlkemTenTwentyFourSW", - ("1024", "CPU"): "MlkemTenTwentyFourCPU", - ("1024", "DMA"): "MlkemTenTwentyFourDMA", - } - for (level, path), name in names.items(): - value = capture(rf"^MLKEM{level}_{path}_ONLY_AVG_CYCLES=(\d+)$", log) - if value: - metrics = set_macro(metrics, name, number(value)) - return metrics - - -def update_fft(metrics: str, cpu_log: str, dma_log: str) -> str: - cpu_ns = capture(r"Hardware FFT Time:\s*(\d+) ns", cpu_log) - dma_ns = capture(r"Hardware FFT Time:\s*(\d+) ns", dma_log) - sw_ns = capture(r"Software FFT Time:\s*(\d+) ns", dma_log or cpu_log) - cpu_speed = capture(r"Speedup Ratio\s*:\s*([\d.]+)x", cpu_log) - dma_speed = capture(r"Speedup Ratio\s*:\s*([\d.]+)x", dma_log) - for name, value in (("FftCpuNs", cpu_ns), ("FftDmaNs", dma_ns), ("FftSoftwareNs", sw_ns)): - if value: - metrics = set_macro(metrics, name, number(value)) - for name, value in (("FftCpuSpeedup", cpu_speed), ("FftDmaSpeedup", dma_speed)): - if value: - metrics = set_macro(metrics, name, value) - err_match = re.search(r"Max Abs Error\s*:\s*Re=(\d+),\s*Im=(\d+)", dma_log) - if err_match: - metrics = set_macro(metrics, "FftMaxError", f"Re={err_match.group(1)}，Im={err_match.group(2)}") - return metrics - - -def update_matmul(metrics: str, log: str) -> str: - elapsed = capture(r"Elapsed time:\s*([\d.]+) ms", log) - score = capture(r"Score percent:\s*([\d.]+)", log) - if elapsed: - metrics = set_macro(metrics, "MatmulBoardMs", elapsed) - if score: - metrics = set_macro(metrics, "MatmulScore", score + r"\%") - if "CRC32 matched." in log: - metrics = set_macro(metrics, "MatmulCrcStatus", "PASS") - return metrics - - -def main() -> None: - metrics = METRICS.read_text(encoding="utf-8") - vivado = REPORT_DIR / "evidence" / "vivado" - board = REPORT_DIR / "evidence" / "board" - legacy = ROOT / "fpga" / "vivado_reports_nodsp" - metrics = update_timing(metrics, read_first(vivado / "timing_summary_full.rpt", legacy / "timing_summary_full.rpt")) - metrics = update_util(metrics, read_first(vivado / "utilization.rpt", legacy / "utilization.rpt")) - metrics = update_power(metrics, read_first(vivado / "power.rpt", legacy / "power.rpt")) - - soc = REPORT_DIR / "evidence" / "soc" - metrics = update_mlkem(metrics, read_first(soc / "mlkem_test.log", ROOT / "sdk/software/examples/mlkem_test/result.txt")) - metrics = update_fft( - metrics, - read_first(board / "fft.log", soc / "fft.log", ROOT / "sdk/software/examples/fft/result.txt"), - read_first(board / "fft_dma.log", soc / "fft_dma.log", ROOT / "sdk/software/examples/fft_dma/result.txt"), - ) - metrics = update_matmul(metrics, read_first(board / "matmul_official.log")) - - try: - revision = subprocess.check_output( - ["git", "-C", str(ROOT), "rev-parse", "--short", "HEAD"], text=True - ).strip() - except (OSError, subprocess.CalledProcessError): - revision = "unknown" - source = "当前 evidence" if (vivado / "timing_summary_full.rpt").is_file() else "历史报告，待复测" - metrics = set_macro(metrics, "EvidenceRevision", f"{revision}（{source}）") - metrics = set_macro(metrics, "EvidenceDate", dt.date.today().isoformat()) - METRICS.write_text(metrics, encoding="utf-8") - print(f"updated {METRICS}") - - -if __name__ == "__main__": - main()