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update system design report

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2026-07-15 11:09:57 +08:00
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
| Date : Wed Jul 15 05:09:34 2026
| Host : Roc_Wang running 64-bit major release (build 9200)
| Command : report_power -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/power.rpt
| Design : soc_top
| Device : xc7a200tfbg676-1
| Design State : routed
| Grade : commercial
| Process : typical
| Characterization : Production
-------------------------------------------------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 0.779 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.637 |
| Device Static (W) | 0.142 |
| Effective TJA (C/W) | 1.9 |
| Max Ambient (C) | 83.5 |
| Junction Temperature (C) | 26.5 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks | 0.060 | 7 | --- | --- |
| Slice Logic | 0.137 | 103629 | --- | --- |
| LUT as Logic | 0.128 | 53158 | 133800 | 39.73 |
| CARRY4 | 0.005 | 3669 | 33450 | 10.97 |
| Register | 0.002 | 31000 | 267600 | 11.58 |
| LUT as Distributed RAM | 0.001 | 740 | 46200 | 1.60 |
| LUT as Shift Register | <0.001 | 1168 | 46200 | 2.53 |
| F7/F8 Muxes | <0.001 | 2449 | 133800 | 1.83 |
| Others | 0.000 | 333 | --- | --- |
| Signals | 0.284 | 78815 | --- | --- |
| Block RAM | 0.027 | 29.5 | 365 | 8.08 |
| PLL | 0.102 | 1 | 10 | 10.00 |
| I/O | 0.027 | 202 | 400 | 50.50 |
| Static Power | 0.142 | | | |
| Total | 0.779 | | | |
+--------------------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 1.000 | 0.545 | 0.512 | 0.033 |
| Vccaux | 1.800 | 0.085 | 0.054 | 0.031 |
| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 1.000 | 0.003 | 0.002 | 0.001 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
+-----------+-------------+-----------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 1.9 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 3.4 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+------------------+------------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+------------------+------------------------------------------+-----------------+
| clk | clk | 20.0 |
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.0 |
| mlkem_clk | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 13.0 |
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
+------------------+------------------------------------------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+----------------------------+-----------+
| Name | Power (W) |
+----------------------------+-----------+
| soc_top | 0.637 |
| pll_clk.u_clk_pll | 0.103 |
| inst | 0.103 |
| u_Axi_CDC | 0.002 |
| u_axi_uart_controller | 0.002 |
| uart0 | 0.001 |
| regs | 0.001 |
| u_cdma_matmul_bridge | 0.001 |
| u_confreg | 0.001 |
| u_cpu | 0.027 |
| addr_trans | 0.002 |
| tlb_entry | 0.002 |
| btb | 0.003 |
| dcache | 0.004 |
| icache | 0.005 |
| u_csr | 0.001 |
| u_mul | 0.008 |
| u_fft_mlkem_axi_slave | 0.373 |
| u_fft_controller | 0.031 |
| u_FFT | 0.028 |
| u_out0 | 0.001 |
| u_out1 | 0.001 |
| u_mlkem_axi_cdc | 0.003 |
| wFifo | 0.001 |
| u_mlkem_axi_slave | 0.339 |
| u_mlkem | 0.332 |
| u_matmul_axi_slave | 0.077 |
| mult_inst[0].u_mult | 0.003 |
| mult_inst[1].u_mult | 0.002 |
| mult_inst[2].u_mult | 0.002 |
| mult_inst[3].u_mult | 0.002 |
| u_snix_axil_cdma_mux_8ch | 0.008 |
| u_core_engine | 0.004 |
| axis_fifo_u0 | 0.002 |
+----------------------------+-----------+