update system design report

2026-07-15 11:09:57 +08:00
parent c4d36515cc
commit fe20f28a72
46 changed files with 35507 additions and 1285 deletions
--- a/doc/reports/system/evidence/vivado/clocks.rpt
+++ b/doc/reports/system/evidence/vivado/clocks.rpt
@@ -0,0 +1,76 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
+| Date         : Wed Jul 15 05:09:25 2026
+| Host         : Roc_Wang running 64-bit major release  (build 9200)
+| Command      : report_clocks -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/clocks.rpt
+| Design       : soc_top
+| Device       : 7a200t-fbg676
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+---------------------------------------------------------------------------------------------------------------------
+
+Clock Report
+
+
+Attributes
+  P: Propagated
+  G: Generated
+  A: Auto-derived
+  R: Renamed
+  V: Virtual
+  I: Inverted
+  S: Pin phase-shifted with Latency mode
+
+Clock             Period(ns)  Waveform(ns)    Attributes  Sources
+clk               20.000      {0.000 10.000}  P           {clk}
+clkfbout_clk_pll  20.000      {0.000 10.000}  P,G,A       {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
+cpu_clk           30.000      {0.000 15.000}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
+mlkem_clk         13.000      {0.000 6.500}   P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
+sys_clk           20.000      {0.000 10.000}  P,G,A,R     {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
+
+
+====================================================
+Generated Clocks
+====================================================
+
+Generated Clock     : clkfbout_clk_pll
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Multiply By         : 1
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
+
+Generated Clock     : cpu_clk
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Edges               : {1 2 3}
+Edge Shifts(ns)     : {0.000 5.000 10.000}
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
+
+Generated Clock     : mlkem_clk
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Edges               : {1 2 3}
+Edge Shifts(ns)     : {0.000 -3.500 -7.000}
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
+
+Generated Clock     : sys_clk
+Master Source       : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
+Master Clock        : clk
+Multiply By         : 1
+Generated Sources   : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
+
+
+
+====================================================
+User Uncertainty
+====================================================
+
+
+
+====================================================
+User Jitter
+====================================================
+
+Clock  Jitter(ns)
+clk    0.200
+