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update system design report

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FallenSigh
2026-07-15 11:09:57 +08:00
parent c4d36515cc
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doc/reports/system/evidence/README.md
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@@ -2,12 +2,23 @@
Generated logs and Vivado reports used by `system_design_report.tex` live here:
- `soc/`: UART output from SoC simulations
- `soc/`: short SoC simulation evidence; `reset_window.vcd` records reset and pre-reset transaction signals
- `build/`: software build logs for the five selected examples
- `vivado/`: timing, utilization, CDC, DRC, route and power reports
- `board/`: official matmul evaluation plus FFT/FFT-DMA board UART logs
- `vivado/`: timing, utilization, DRC, route and power reports
- `board/`: official matmul evaluation plus FFT and ML-KEM board UART logs
The report currently consumes these board filenames:
- `fft_1.log`, `fft_2.log`, `fft_3.log`
- `fft_dma_1.log`, `fft_dma_2.log`, `fft_dma_3.log`
- `mlkem_test_512.log`, `mlkem_test_768.log`, `mlkem_test_1024.log`
- `mlkem_hello.log`
- `matmul_official.log` (three complete official runs in one file)
Reset screenshots derived from `soc/reset_window.vcd` belong in `../figures/` as
`reset_release.png` and `reset_no_transaction.png`.
Run `../tools/run_report_tests.sh refresh` after replacing evidence. Large generated
artifacts such as `.vcd`, `.wdb`, `.jou`, `.str`, implementation checkpoints and
bitstreams do not belong in Git. SoC VCD files may be generated here temporarily with
`SAVE_VCD=1`; archive them separately when they are needed as report evidence.
artifacts such as `.wdb`, `.jou`, `.str`, implementation checkpoints and bitstreams do
not belong in Git. The short reset VCD may be retained as report evidence; avoid tracing
the complete SoC for long software runs because the result can grow to several GB.