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FallenSigh
2026-07-15 11:09:57 +08:00
parent c4d36515cc
commit fe20f28a72
46 changed files with 35507 additions and 1285 deletions
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doc/reports/system/evidence/README.md
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Generated logs and Vivado reports used by `system_design_report.tex` live here:
- `soc/`: UART output from SoC simulations
- `soc/`: short SoC simulation evidence; `reset_window.vcd` records reset and pre-reset transaction signals
- `build/`: software build logs for the five selected examples
- `vivado/`: timing, utilization, CDC, DRC, route and power reports
- `board/`: official matmul evaluation plus FFT/FFT-DMA board UART logs
- `vivado/`: timing, utilization, DRC, route and power reports
- `board/`: official matmul evaluation plus FFT and ML-KEM board UART logs
The report currently consumes these board filenames:
- `fft_1.log`, `fft_2.log`, `fft_3.log`
- `fft_dma_1.log`, `fft_dma_2.log`, `fft_dma_3.log`
- `mlkem_test_512.log`, `mlkem_test_768.log`, `mlkem_test_1024.log`
- `mlkem_hello.log`
- `matmul_official.log` (three complete official runs in one file)
Reset screenshots derived from `soc/reset_window.vcd` belong in `../figures/` as
`reset_release.png` and `reset_no_transaction.png`.
Run `../tools/run_report_tests.sh refresh` after replacing evidence. Large generated
artifacts such as `.vcd`, `.wdb`, `.jou`, `.str`, implementation checkpoints and
bitstreams do not belong in Git. SoC VCD files may be generated here temporarily with
`SAVE_VCD=1`; archive them separately when they are needed as report evidence.
artifacts such as `.wdb`, `.jou`, `.str`, implementation checkpoints and bitstreams do
not belong in Git. The short reset VCD may be retained as report evidence; avoid tracing
the complete SoC for long software runs because the result can grow to several GB.

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doc/reports/system/evidence/vivado/cdc.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
| Date : Wed Jul 15 05:09:36 2026
| Host : Roc_Wang running 64-bit major release (build 9200)
| Command : report_cdc -details -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/cdc.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
------------------------------------------------------------------------------------------------------------------------
CDC Report
ID Severity Count Description
------ -------- ----- -------------------------------------------------------
CDC-3 Info 1 1-bit synchronized with ASYNC_REG property
CDC-6 Warning 20 Multi-bit synchronized with ASYNC_REG property
CDC-7 Critical 1 Asynchronous reset unknown CDC circuitry
CDC-9 Info 3 Asynchronous reset synchronized with ASYNC_REG property
CDC-11 Critical 2 Fan-out from launch flop to destination clock
CDC-15 Warning 313 Clock enable controlled CDC structure detected
Source Clock: sys_clk
Destination Clock: cpu_clk
CDC Type: User Ignored
Row ID Severity Description Depth Exception Source (From) Destination (To)
--- ------ -------- ---------------------------------------------- ----- ------------------- ---------------------------------------------- ------------------------------------------------------------
1 CDC-11 Critical Fan-out from launch flop to destination clock 2 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C pll_clk.u_rst_cpu/delay_reg[0]/CLR
2 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2:0]/C u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D
3 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2:0]/C u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D
4 CDC-11 Critical Fan-out from launch flop to destination clock 2 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR
5 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2:0]/C u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D
6 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D
7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D
8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D
9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D
10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D
11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D
12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D
13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D
14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D
15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D
16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D
17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D
18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D
19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D
20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D
21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D
22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D
23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D
24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D
25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D
26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D
27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D
28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D
29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D
30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D
31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D
32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D
33 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D
34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D
35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D
36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D
37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D
38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D
39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D
40 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3:0]/C u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D
41 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3:0]/C u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D
42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_confreg/int_out_or_q2_reg/C u_cpu/u_csr/csr_estat_reg[2]/D
43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_cdma_matmul_bridge/seq_done_flag_reg/C u_cpu/u_csr/csr_estat_reg[3]/D
44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_matmul_axi_slave/done_reg/C u_cpu/u_csr/csr_estat_reg[4]/D
45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C u_cpu/u_csr/csr_estat_reg[5]/D
Source Clock: sys_clk
Destination Clock: mlkem_clk
CDC Type: User Ignored
Row ID Severity Description Depth Exception Source (From) Destination (To)
--- ------ -------- ------------------------------------------------------- ----- ------------------- -------------------------------------------------------------------------- ----------------------------------------------------------------------------------------
1 CDC-7 Critical Asynchronous reset unknown CDC circuitry 0 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C pll_clk.u_rst_mlkem/delay_reg[0]/CLR
2 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D
3 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D
4 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D
5 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D
6 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D
7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D
8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D
9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D
10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D
11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D
12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D
13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11]/D
14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D
15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D
16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D
17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D
18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D
19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D
20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D
21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D
22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D
23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D
24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D
25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D
26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D
27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D
28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D
29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D
30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D
31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D
32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D
33 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D
34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D
35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D
36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D
37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D
38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D
39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[5]/D
40 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D
41 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D
42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D
43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D
44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D
45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D
46 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12]/D
47 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D
48 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D
49 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D
50 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D
51 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D
52 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D
53 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D
54 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D
55 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D
56 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D
57 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR
58 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D
59 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D
60 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D
61 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D
62 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D
63 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D
64 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/D
65 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D
66 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D
67 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D
68 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D
69 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/D
70 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D
71 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10]/D
72 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D
73 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D
74 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D
75 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D
76 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D
77 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D
78 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/D
79 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D
80 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D
81 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D
82 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D
83 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D
84 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D
85 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D
86 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D
87 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D
88 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D
89 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D
90 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D
91 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D
92 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D
93 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32]/D
94 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D
95 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D
96 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D
97 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D
98 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D
Source Clock: cpu_clk
Destination Clock: sys_clk
CDC Type: User Ignored
Row ID Severity Description Depth Exception Source (From) Destination (To)
--- ------ -------- ------------------------------------------------------- ----- ------------------- ---------------------------------------------- ------------------------------------------------------------
1 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D
2 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[1]/D
3 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D
4 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D
5 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D
6 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D
7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D
8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D
9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D
10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D
11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D
12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/D
13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D
14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D
15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[14]/D
16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D
17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[16]/D
18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[17]/D
19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D
20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D
21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[20]/D
22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D
23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D
24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D
25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D
26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D
27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/D
28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[27]/D
29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[28]/D
30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D
31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D
32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D
33 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D
34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/D
35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/D
36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D
37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D
38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[38]/D
39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[39]/D
40 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[40]/D
41 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D
42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D
43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[43]/D
44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D
45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D
46 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D
47 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[47]/D
48 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D
49 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D
50 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[50]/D
51 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/D
52 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[52]/D
53 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/D
54 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2:0]/C u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D
55 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D
56 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D
57 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D
58 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D
59 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[4]/D
60 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D
61 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D
62 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D
63 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D
64 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[9]/D
65 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[10]/D
66 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[11]/D
67 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D
68 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D
69 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[14]/D
70 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[15]/D
71 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[16]/D
72 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/D
73 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D
74 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D
75 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[20]/D
76 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D
77 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D
78 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[23]/D
79 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D
80 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D
81 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[26]/D
82 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[27]/D
83 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[28]/D
84 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[29]/D
85 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D
86 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D
87 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D
88 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D
89 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[34]/D
90 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D
91 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D
92 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[38]/D
93 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D
94 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/D
95 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D
96 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D
97 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D
98 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D
99 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D
100 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/D
101 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D
102 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D
103 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D
104 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/D
105 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D
106 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/D
107 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D
108 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 Asynch Clock Groups pll_clk.u_rst_cpu/delay_reg[1]/C u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR
109 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2:0]/C u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D
110 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2:0]/C u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D
111 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3:0]/C u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D
112 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D
113 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D
114 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D
115 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[3]/D
116 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[4]/D
117 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/D
118 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D
119 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D
120 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D
121 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/D
122 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D
123 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[11]/D
124 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D
125 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D
126 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D
127 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[15]/D
128 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D
129 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/D
130 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D
131 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D
132 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[20]/D
133 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/D
134 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D
135 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D
136 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D
137 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D
138 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[26]/D
139 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/D
140 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D
141 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D
142 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D
143 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D
144 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[32]/D
145 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[33]/D
146 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D
147 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/D
148 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D
149 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3:0]/C u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D
Source Clock: mlkem_clk
Destination Clock: sys_clk
CDC Type: User Ignored
Row ID Severity Description Depth Exception Source (From) Destination (To)
--- ------ -------- ------------------------------------------------------- ----- ------------------- ------------------------------------------------------------------------- ----------------------------------------------------------------------------------------
1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D
2 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D
3 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D
4 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D
5 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 Asynch Clock Groups pll_clk.u_rst_mlkem/delay_reg[1]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR
6 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D
7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D
8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D
9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D
10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D
11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D
12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D
13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D
14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D
15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D
16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D
17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D
18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D
19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D
20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D
21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D
22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D
23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D
24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D
25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D
26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D
27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D
28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D
29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D
30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D
31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D
32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D
33 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D
34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D
35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D
36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D
37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D
38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D
39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D
40 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D
41 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D
42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D
43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D
44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D
45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D
46 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D
47 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D
48 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D

28
doc/reports/system/evidence/vivado/clock_interaction.rpt Normal file
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@@ -0,0 +1,28 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
| Date : Wed Jul 15 05:09:35 2026
| Host : Roc_Wang running 64-bit major release (build 9200)
| Command : report_clock_interaction -delay_type min_max -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/clock_interaction.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
---------------------------------------------------------------------------------------------------------------------------------------------------------------
Clock Interaction Report
Clock Interaction Table
-----------------------
WNS TNS Failing TNS Total WNS Path WHS THS Failing THS Total WHS Path Clock-Pair Inter-Clock
From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Clock Edges WHS(ns) THS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints
---------------- ---------------- ----------- ------- ------- ----------- ----------- --------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- -------------------
cpu_clk cpu_clk rise - rise 0.74 0.00 0 17264 30.00 rise - rise 0.04 0.00 0 17264 0.00 Clean Timed
cpu_clk sys_clk 0 162 0 162 Ignored Asynchronous Groups
mlkem_clk mlkem_clk rise - rise 0.07 0.00 0 48386 13.00 rise - rise 0.06 0.00 0 48386 0.00 Clean Timed
mlkem_clk sys_clk 0 61 0 61 Ignored Asynchronous Groups
sys_clk cpu_clk 0 59 0 59 Ignored Asynchronous Groups
sys_clk mlkem_clk 0 112 0 112 Ignored Asynchronous Groups
sys_clk sys_clk rise - rise 0.12 0.00 0 23193 20.00 rise - rise 0.02 0.00 0 23193 0.00 Clean Timed

76
doc/reports/system/evidence/vivado/clocks.rpt Normal file
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@@ -0,0 +1,76 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
| Date : Wed Jul 15 05:09:25 2026
| Host : Roc_Wang running 64-bit major release (build 9200)
| Command : report_clocks -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/clocks.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
---------------------------------------------------------------------------------------------------------------------
Clock Report
Attributes
P: Propagated
G: Generated
A: Auto-derived
R: Renamed
V: Virtual
I: Inverted
S: Pin phase-shifted with Latency mode
Clock Period(ns) Waveform(ns) Attributes Sources
clk 20.000 {0.000 10.000} P {clk}
clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
cpu_clk 30.000 {0.000 15.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
mlkem_clk 13.000 {0.000 6.500} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
====================================================
Generated Clocks
====================================================
Generated Clock : clkfbout_clk_pll
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk
Multiply By : 1
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
Generated Clock : cpu_clk
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 5.000 10.000}
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
Generated Clock : mlkem_clk
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 -3.500 -7.000}
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
Generated Clock : sys_clk
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk
Multiply By : 1
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
====================================================
User Uncertainty
====================================================
====================================================
User Jitter
====================================================
Clock Jitter(ns)
clk 0.200

248
doc/reports/system/evidence/vivado/drc.rpt Normal file
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@@ -0,0 +1,248 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
| Date : Wed Jul 15 05:09:39 2026
| Host : Roc_Wang running 64-bit major release (build 9200)
| Command : report_drc -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/drc.rpt
| Design : soc_top
| Device : xc7a200tfbg676-1
| Speed File : -1
| Design State : Fully Routed
---------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: impl_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 42
+-----------+----------+----------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+----------------------------+------------+
| CHECK-3 | Warning | Report rule limit reached | 2 |
| REQP-1839 | Warning | RAMB36 async control check | 20 |
| REQP-1840 | Warning | RAMB18 async control check | 20 |
+-----------+----------+----------------------------+------------+
2. REPORT DETAILS
-----------------
CHECK-3#1 Warning
Report rule limit reached
REQP-1839 rule limit reached: 20 violations have been found.
Related violations: <none>
CHECK-3#2 Warning
Report rule limit reached
REQP-1840 rule limit reached: 20 violations have been found.
Related violations: <none>
REQP-1839#1 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#2 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#3 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#4 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#5 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#6 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#7 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#8 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#9 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#10 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#11 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#12 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#13 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#14 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#15 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#16 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#17 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#18 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#19 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#20 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#1 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#2 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#3 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#4 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#5 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#6 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#7 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#8 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#9 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#10 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#11 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#12 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#13 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#14 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#15 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#16 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#17 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#18 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#19 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#20 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
| Date : Wed Jul 15 05:09:49 2026
| Host : Roc_Wang running 64-bit major release (build 9200)
| Command : report_methodology -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/methodology.rpt
| Design : soc_top
| Device : xc7a200tfbg676-1
| Speed File : -1
| Design State : Fully Routed
-------------------------------------------------------------------------------------------------------------------------------
Report Methodology
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: impl_1
Design limits: <entire design considered>
Max violations: <unlimited>
Violations found: 115
+-----------+----------+-------------------------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+-------------------------------------------------------------------+------------+
| LUTAR-1 | Warning | LUT drives async reset alert | 1 |
| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 8 |
| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 6 |
| SYNTH-16 | Warning | Address collision | 16 |
| TIMING-9 | Warning | Unknown CDC Logic | 1 |
| TIMING-10 | Warning | Missing property on synchronizer | 1 |
| TIMING-18 | Warning | Missing input or output delay | 76 |
| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 4 |
| XDCC-1 | Warning | Scoped Clock constraint overwritten with the same name | 1 |
| XDCC-7 | Warning | Scoped Clock constraint overwritten on the same source | 1 |
+-----------+----------+-------------------------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
LUTAR-1#1 Warning
LUT drives async reset alert
LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 15633 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>
SYNTH-5#1 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#2 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#3 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#4 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#5 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#6 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#7 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#8 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-6#1 Warning
Timing of a block RAM might be sub-optimal
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>
SYNTH-6#2 Warning
Timing of a block RAM might be sub-optimal
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>
SYNTH-6#3 Warning
Timing of a block RAM might be sub-optimal
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>
SYNTH-6#4 Warning
Timing of a block RAM might be sub-optimal
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>
SYNTH-6#5 Warning
Timing of a block RAM might be sub-optimal
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>
SYNTH-6#6 Warning
Timing of a block RAM might be sub-optimal
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>
SYNTH-16#1 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#2 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#3 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#4 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#5 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#6 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#7 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#8 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#9 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#10 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#11 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#12 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#13 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#14 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#15 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#16 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
TIMING-9#1 Warning
Unknown CDC Logic
One or more asynchronous Clock Domain Crossing has been detected between 2 clock domains through a set_false_path or a set_clock_groups or set_max_delay -datapath_only constraint but no double-registers logic synchronizer has been found on the side of the capture clock. It is recommended to run report_cdc for a complete and detailed CDC coverage. Please consider using XPM_CDC to avoid Critical severities
Related violations: <none>
TIMING-10#1 Warning
Missing property on synchronizer
One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage
Related violations: <none>
TIMING-18#1 Warning
Missing input or output delay
An input delay is missing on UART_RX relative to clock(s) clk
Related violations: <none>
TIMING-18#2 Warning
Missing input or output delay
An input delay is missing on UART_TX relative to clock(s) clk
Related violations: <none>
TIMING-18#3 Warning
Missing input or output delay
An input delay is missing on dip_sw[0] relative to clock(s) clk
Related violations: <none>
TIMING-18#4 Warning
Missing input or output delay
An input delay is missing on dip_sw[10] relative to clock(s) clk
Related violations: <none>
TIMING-18#5 Warning
Missing input or output delay
An input delay is missing on dip_sw[11] relative to clock(s) clk
Related violations: <none>
TIMING-18#6 Warning
Missing input or output delay
An input delay is missing on dip_sw[12] relative to clock(s) clk
Related violations: <none>
TIMING-18#7 Warning
Missing input or output delay
An input delay is missing on dip_sw[13] relative to clock(s) clk
Related violations: <none>
TIMING-18#8 Warning
Missing input or output delay
An input delay is missing on dip_sw[14] relative to clock(s) clk
Related violations: <none>
TIMING-18#9 Warning
Missing input or output delay
An input delay is missing on dip_sw[15] relative to clock(s) clk
Related violations: <none>
TIMING-18#10 Warning
Missing input or output delay
An input delay is missing on dip_sw[16] relative to clock(s) clk
Related violations: <none>
TIMING-18#11 Warning
Missing input or output delay
An input delay is missing on dip_sw[17] relative to clock(s) clk
Related violations: <none>
TIMING-18#12 Warning
Missing input or output delay
An input delay is missing on dip_sw[18] relative to clock(s) clk
Related violations: <none>
TIMING-18#13 Warning
Missing input or output delay
An input delay is missing on dip_sw[19] relative to clock(s) clk
Related violations: <none>
TIMING-18#14 Warning
Missing input or output delay
An input delay is missing on dip_sw[1] relative to clock(s) clk
Related violations: <none>
TIMING-18#15 Warning
Missing input or output delay
An input delay is missing on dip_sw[20] relative to clock(s) clk
Related violations: <none>
TIMING-18#16 Warning
Missing input or output delay
An input delay is missing on dip_sw[21] relative to clock(s) clk
Related violations: <none>
TIMING-18#17 Warning
Missing input or output delay
An input delay is missing on dip_sw[22] relative to clock(s) clk
Related violations: <none>
TIMING-18#18 Warning
Missing input or output delay
An input delay is missing on dip_sw[23] relative to clock(s) clk
Related violations: <none>
TIMING-18#19 Warning
Missing input or output delay
An input delay is missing on dip_sw[24] relative to clock(s) clk
Related violations: <none>
TIMING-18#20 Warning
Missing input or output delay
An input delay is missing on dip_sw[25] relative to clock(s) clk
Related violations: <none>
TIMING-18#21 Warning
Missing input or output delay
An input delay is missing on dip_sw[26] relative to clock(s) clk
Related violations: <none>
TIMING-18#22 Warning
Missing input or output delay
An input delay is missing on dip_sw[27] relative to clock(s) clk
Related violations: <none>
TIMING-18#23 Warning
Missing input or output delay
An input delay is missing on dip_sw[28] relative to clock(s) clk
Related violations: <none>
TIMING-18#24 Warning
Missing input or output delay
An input delay is missing on dip_sw[29] relative to clock(s) clk
Related violations: <none>
TIMING-18#25 Warning
Missing input or output delay
An input delay is missing on dip_sw[2] relative to clock(s) clk
Related violations: <none>
TIMING-18#26 Warning
Missing input or output delay
An input delay is missing on dip_sw[30] relative to clock(s) clk
Related violations: <none>
TIMING-18#27 Warning
Missing input or output delay
An input delay is missing on dip_sw[31] relative to clock(s) clk
Related violations: <none>
TIMING-18#28 Warning
Missing input or output delay
An input delay is missing on dip_sw[3] relative to clock(s) clk
Related violations: <none>
TIMING-18#29 Warning
Missing input or output delay
An input delay is missing on dip_sw[4] relative to clock(s) clk
Related violations: <none>
TIMING-18#30 Warning
Missing input or output delay
An input delay is missing on dip_sw[5] relative to clock(s) clk
Related violations: <none>
TIMING-18#31 Warning
Missing input or output delay
An input delay is missing on dip_sw[6] relative to clock(s) clk
Related violations: <none>
TIMING-18#32 Warning
Missing input or output delay
An input delay is missing on dip_sw[7] relative to clock(s) clk
Related violations: <none>
TIMING-18#33 Warning
Missing input or output delay
An input delay is missing on dip_sw[8] relative to clock(s) clk
Related violations: <none>
TIMING-18#34 Warning
Missing input or output delay
An input delay is missing on dip_sw[9] relative to clock(s) clk
Related violations: <none>
TIMING-18#35 Warning
Missing input or output delay
An input delay is missing on touch_btn[0] relative to clock(s) clk
Related violations: <none>
TIMING-18#36 Warning
Missing input or output delay
An input delay is missing on touch_btn[1] relative to clock(s) clk
Related violations: <none>
TIMING-18#37 Warning
Missing input or output delay
An input delay is missing on touch_btn[2] relative to clock(s) clk
Related violations: <none>
TIMING-18#38 Warning
Missing input or output delay
An input delay is missing on touch_btn[3] relative to clock(s) clk
Related violations: <none>
TIMING-18#39 Warning
Missing input or output delay
An output delay is missing on dpy0[0] relative to clock(s) clk
Related violations: <none>
TIMING-18#40 Warning
Missing input or output delay
An output delay is missing on dpy0[1] relative to clock(s) clk
Related violations: <none>
TIMING-18#41 Warning
Missing input or output delay
An output delay is missing on dpy0[2] relative to clock(s) clk
Related violations: <none>
TIMING-18#42 Warning
Missing input or output delay
An output delay is missing on dpy0[3] relative to clock(s) clk
Related violations: <none>
TIMING-18#43 Warning
Missing input or output delay
An output delay is missing on dpy0[4] relative to clock(s) clk
Related violations: <none>
TIMING-18#44 Warning
Missing input or output delay
An output delay is missing on dpy0[5] relative to clock(s) clk
Related violations: <none>
TIMING-18#45 Warning
Missing input or output delay
An output delay is missing on dpy0[6] relative to clock(s) clk
Related violations: <none>
TIMING-18#46 Warning
Missing input or output delay
An output delay is missing on dpy0[7] relative to clock(s) clk
Related violations: <none>
TIMING-18#47 Warning
Missing input or output delay
An output delay is missing on dpy1[0] relative to clock(s) clk
Related violations: <none>
TIMING-18#48 Warning
Missing input or output delay
An output delay is missing on dpy1[1] relative to clock(s) clk
Related violations: <none>
TIMING-18#49 Warning
Missing input or output delay
An output delay is missing on dpy1[2] relative to clock(s) clk
Related violations: <none>
TIMING-18#50 Warning
Missing input or output delay
An output delay is missing on dpy1[3] relative to clock(s) clk
Related violations: <none>
TIMING-18#51 Warning
Missing input or output delay
An output delay is missing on dpy1[4] relative to clock(s) clk
Related violations: <none>
TIMING-18#52 Warning
Missing input or output delay
An output delay is missing on dpy1[5] relative to clock(s) clk
Related violations: <none>
TIMING-18#53 Warning
Missing input or output delay
An output delay is missing on dpy1[6] relative to clock(s) clk
Related violations: <none>
TIMING-18#54 Warning
Missing input or output delay
An output delay is missing on dpy1[7] relative to clock(s) clk
Related violations: <none>
TIMING-18#55 Warning
Missing input or output delay
An output delay is missing on leds[0] relative to clock(s) clk
Related violations: <none>
TIMING-18#56 Warning
Missing input or output delay
An output delay is missing on leds[10] relative to clock(s) clk
Related violations: <none>
TIMING-18#57 Warning
Missing input or output delay
An output delay is missing on leds[11] relative to clock(s) clk
Related violations: <none>
TIMING-18#58 Warning
Missing input or output delay
An output delay is missing on leds[12] relative to clock(s) clk
Related violations: <none>
TIMING-18#59 Warning
Missing input or output delay
An output delay is missing on leds[13] relative to clock(s) clk
Related violations: <none>
TIMING-18#60 Warning
Missing input or output delay
An output delay is missing on leds[14] relative to clock(s) clk
Related violations: <none>
TIMING-18#61 Warning
Missing input or output delay
An output delay is missing on leds[15] relative to clock(s) clk
Related violations: <none>
TIMING-18#62 Warning
Missing input or output delay
An output delay is missing on leds[1] relative to clock(s) clk
Related violations: <none>
TIMING-18#63 Warning
Missing input or output delay
An output delay is missing on leds[2] relative to clock(s) clk
Related violations: <none>
TIMING-18#64 Warning
Missing input or output delay
An output delay is missing on leds[3] relative to clock(s) clk
Related violations: <none>
TIMING-18#65 Warning
Missing input or output delay
An output delay is missing on leds[4] relative to clock(s) clk
Related violations: <none>
TIMING-18#66 Warning
Missing input or output delay
An output delay is missing on leds[5] relative to clock(s) clk
Related violations: <none>
TIMING-18#67 Warning
Missing input or output delay
An output delay is missing on leds[6] relative to clock(s) clk
Related violations: <none>
TIMING-18#68 Warning
Missing input or output delay
An output delay is missing on leds[7] relative to clock(s) clk
Related violations: <none>
TIMING-18#69 Warning
Missing input or output delay
An output delay is missing on leds[8] relative to clock(s) clk
Related violations: <none>
TIMING-18#70 Warning
Missing input or output delay
An output delay is missing on leds[9] relative to clock(s) clk
Related violations: <none>
TIMING-18#71 Warning
Missing input or output delay
An output delay is missing on video_de relative to clock(s) clk
Related violations: <none>
TIMING-18#72 Warning
Missing input or output delay
An output delay is missing on video_hsync relative to clock(s) clk
Related violations: <none>
TIMING-18#73 Warning
Missing input or output delay
An output delay is missing on video_red[0] relative to clock(s) clk
Related violations: <none>
TIMING-18#74 Warning
Missing input or output delay
An output delay is missing on video_red[1] relative to clock(s) clk
Related violations: <none>
TIMING-18#75 Warning
Missing input or output delay
An output delay is missing on video_red[2] relative to clock(s) clk
Related violations: <none>
TIMING-18#76 Warning
Missing input or output delay
An output delay is missing on video_vsync relative to clock(s) clk
Related violations: <none>
TIMING-47#1 Warning
False path or asynchronous clock group between synchronous clocks
A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
Related violations: <none>
TIMING-47#2 Warning
False path or asynchronous clock group between synchronous clocks
A Clock Group timing constraint is set between synchronous clocks mlkem_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
Related violations: <none>
TIMING-47#3 Warning
False path or asynchronous clock group between synchronous clocks
A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
Related violations: <none>
TIMING-47#4 Warning
False path or asynchronous clock group between synchronous clocks
A Clock Group timing constraint is set between synchronous clocks sys_clk and mlkem_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
Related violations: <none>
XDCC-1#1 Warning
Scoped Clock constraint overwritten with the same name
A new clock constraint create_clock overrides a previous scoped clock constraint with the same name. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: c:/Users/11747/Desktop/ciciec2026/fpga/constraints/soc.xdc (Line: 4))
Previous: create_clock -period 20.000 [get_ports clk] (Source: c:/Users/11747/Desktop/ciciec2026/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
Related violations: <none>
XDCC-7#1 Warning
Scoped Clock constraint overwritten on the same source
A new clock constraint create_clock overrides a previous scoped clock constraint defined on the same source. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: c:/Users/11747/Desktop/ciciec2026/fpga/constraints/soc.xdc (Line: 4))
Previous: create_clock -period 20.000 [get_ports clk] (Source: c:/Users/11747/Desktop/ciciec2026/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
Related violations: <none>

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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
| Date : Wed Jul 15 05:09:34 2026
| Host : Roc_Wang running 64-bit major release (build 9200)
| Command : report_power -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/power.rpt
| Design : soc_top
| Device : xc7a200tfbg676-1
| Design State : routed
| Grade : commercial
| Process : typical
| Characterization : Production
-------------------------------------------------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 0.779 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.637 |
| Device Static (W) | 0.142 |
| Effective TJA (C/W) | 1.9 |
| Max Ambient (C) | 83.5 |
| Junction Temperature (C) | 26.5 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks | 0.060 | 7 | --- | --- |
| Slice Logic | 0.137 | 103629 | --- | --- |
| LUT as Logic | 0.128 | 53158 | 133800 | 39.73 |
| CARRY4 | 0.005 | 3669 | 33450 | 10.97 |
| Register | 0.002 | 31000 | 267600 | 11.58 |
| LUT as Distributed RAM | 0.001 | 740 | 46200 | 1.60 |
| LUT as Shift Register | <0.001 | 1168 | 46200 | 2.53 |
| F7/F8 Muxes | <0.001 | 2449 | 133800 | 1.83 |
| Others | 0.000 | 333 | --- | --- |
| Signals | 0.284 | 78815 | --- | --- |
| Block RAM | 0.027 | 29.5 | 365 | 8.08 |
| PLL | 0.102 | 1 | 10 | 10.00 |
| I/O | 0.027 | 202 | 400 | 50.50 |
| Static Power | 0.142 | | | |
| Total | 0.779 | | | |
+--------------------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 1.000 | 0.545 | 0.512 | 0.033 |
| Vccaux | 1.800 | 0.085 | 0.054 | 0.031 |
| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 1.000 | 0.003 | 0.002 | 0.001 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
+-----------+-------------+-----------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 1.9 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 3.4 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+------------------+------------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+------------------+------------------------------------------+-----------------+
| clk | clk | 20.0 |
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.0 |
| mlkem_clk | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 13.0 |
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
+------------------+------------------------------------------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+----------------------------+-----------+
| Name | Power (W) |
+----------------------------+-----------+
| soc_top | 0.637 |
| pll_clk.u_clk_pll | 0.103 |
| inst | 0.103 |
| u_Axi_CDC | 0.002 |
| u_axi_uart_controller | 0.002 |
| uart0 | 0.001 |
| regs | 0.001 |
| u_cdma_matmul_bridge | 0.001 |
| u_confreg | 0.001 |
| u_cpu | 0.027 |
| addr_trans | 0.002 |
| tlb_entry | 0.002 |
| btb | 0.003 |
| dcache | 0.004 |
| icache | 0.005 |
| u_csr | 0.001 |
| u_mul | 0.008 |
| u_fft_mlkem_axi_slave | 0.373 |
| u_fft_controller | 0.031 |
| u_FFT | 0.028 |
| u_out0 | 0.001 |
| u_out1 | 0.001 |
| u_mlkem_axi_cdc | 0.003 |
| wFifo | 0.001 |
| u_mlkem_axi_slave | 0.339 |
| u_mlkem | 0.332 |
| u_matmul_axi_slave | 0.077 |
| mult_inst[0].u_mult | 0.003 |
| mult_inst[1].u_mult | 0.002 |
| mult_inst[2].u_mult | 0.002 |
| mult_inst[3].u_mult | 0.002 |
| u_snix_axil_cdma_mux_8ch | 0.008 |
| u_core_engine | 0.004 |
| axis_fifo_u0 | 0.002 |
+----------------------------+-----------+

5
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Evidence generated from implemented design.
Vivado version: 2019.2
Project: C:/Users/11747/Desktop/ciciec2026/fpga/project/Loongson_Soc.xpr
Git revision: d45646342b79cefbc30775b5045e34c1f0d26ad6
Generated at: 2026-07-15 05:09:50 +0800

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Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 114880 :
# of nets not needing routing.......... : 36054 :
# of internally routed nets........ : 35589 :
# of nets with no loads............ : 465 :
# of routable nets..................... : 78826 :
# of fully routed nets............. : 78826 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

32030
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
| Date : Wed Jul 15 05:09:26 2026
| Host : Roc_Wang running 64-bit major release (build 9200)
| Command : report_utilization -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/utilization.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Routed
-------------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 55066 | 0 | 133800 | 41.16 |
| LUT as Logic | 53158 | 0 | 133800 | 39.73 |
| LUT as Memory | 1908 | 0 | 46200 | 4.13 |
| LUT as Distributed RAM | 740 | 0 | | |
| LUT as Shift Register | 1168 | 0 | | |
| Slice Registers | 31000 | 0 | 267600 | 11.58 |
| Register as Flip Flop | 31000 | 0 | 267600 | 11.58 |
| Register as Latch | 0 | 0 | 267600 | 0.00 |
| F7 Muxes | 2130 | 0 | 66900 | 3.18 |
| F8 Muxes | 319 | 0 | 33450 | 0.95 |
+----------------------------+-------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 24 | Yes | - | Set |
| 17683 | Yes | - | Reset |
| 126 | Yes | Set | - |
| 13167 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+--------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------------------------------------+-------+-------+-----------+-------+
| Slice | 17126 | 0 | 33450 | 51.20 |
| SLICEL | 11119 | 0 | | |
| SLICEM | 6007 | 0 | | |
| LUT as Logic | 53158 | 0 | 133800 | 39.73 |
| using O5 output only | 5 | | | |
| using O6 output only | 42769 | | | |
| using O5 and O6 | 10384 | | | |
| LUT as Memory | 1908 | 0 | 46200 | 4.13 |
| LUT as Distributed RAM | 740 | 0 | | |
| using O5 output only | 0 | | | |
| using O6 output only | 60 | | | |
| using O5 and O6 | 680 | | | |
| LUT as Shift Register | 1168 | 0 | | |
| using O5 output only | 123 | | | |
| using O6 output only | 997 | | | |
| using O5 and O6 | 48 | | | |
| Slice Registers | 31000 | 0 | 267600 | 11.58 |
| Register driven from within the Slice | 16668 | | | |
| Register driven from outside the Slice | 14332 | | | |
| LUT in front of the register is unused | 5924 | | | |
| LUT in front of the register is used | 8408 | | | |
| Unique Control Sets | 930 | | 33450 | 2.78 |
+--------------------------------------------+-------+-------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 29.5 | 0 | 365 | 8.08 |
| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
| RAMB36E1 only | 10 | | | |
| RAMB18 | 39 | 0 | 730 | 5.34 |
| RAMB18E1 only | 39 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 740 | 0.00 |
+-----------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 202 | 202 | 400 | 50.50 |
| IOB Master Pads | 97 | | | |
| IOB Slave Pads | 102 | | | |
| Bonded IPADs | 0 | 0 | 26 | 0.00 |
| Bonded OPADs | 0 | 0 | 16 | 0.00 |
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
| PHASER_REF | 0 | 0 | 10 | 0.00 |
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
| IN_FIFO | 0 | 0 | 40 | 0.00 |
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
| IBUFDS | 0 | 0 | 384 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
| ILOGIC | 0 | 0 | 400 | 0.00 |
| OLOGIC | 0 | 0 | 400 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
| BUFIO | 0 | 0 | 40 | 0.00 |
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
| BUFMRCE | 0 | 0 | 20 | 0.00 |
| BUFHCE | 0 | 0 | 120 | 0.00 |
| BUFR | 0 | 0 | 40 | 0.00 |
+------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+-----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+-----------+-------+---------------------+
| LUT6 | 26800 | LUT |
| FDCE | 17683 | Flop & Latch |
| FDRE | 13167 | Flop & Latch |
| LUT3 | 10370 | LUT |
| LUT4 | 8684 | LUT |
| LUT2 | 8543 | LUT |
| LUT5 | 8274 | LUT |
| CARRY4 | 3669 | CarryLogic |
| MUXF7 | 2130 | MuxFx |
| RAMD32 | 1060 | Distributed Memory |
| SRLC32E | 992 | Distributed Memory |
| LUT1 | 871 | LUT |
| RAMS32 | 328 | Distributed Memory |
| MUXF8 | 319 | MuxFx |
| SRL16E | 224 | Distributed Memory |
| FDSE | 126 | Flop & Latch |
| IBUF | 104 | IO |
| OBUF | 98 | IO |
| OBUFT | 66 | IO |
| RAMB18E1 | 39 | Block Memory |
| RAMD64E | 32 | Distributed Memory |
| FDPE | 24 | Flop & Latch |
| RAMB36E1 | 10 | Block Memory |
| BUFG | 4 | Clock |
| PLLE2_ADV | 1 | Clock |
+-----------+-------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
| clk_pll | 1 |
+----------+------+

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doc/reports/system/evidence/vivado/utilization_hierarchical.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
| Date : Wed Jul 15 05:09:25 2026
| Host : Roc_Wang running 64-bit major release (build 9200)
| Command : report_utilization -hierarchical -hierarchical_depth 4 -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/utilization_hierarchical.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Routed
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Utilization by Hierarchy
1. Utilization by Hierarchy
---------------------------
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| soc_top | (top) | 55066 | 53158 | 740 | 1168 | 31000 | 10 | 39 | 0 |
| (soc_top) | (top) | 927 | 919 | 8 | 0 | 4 | 0 | 0 | 0 |
| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| inst | clk_pll_clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 368 | 368 | 0 | 0 | 151 | 0 | 0 | 0 |
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_92 | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_75 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_91 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_76 | 17 | 17 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_90 | 17 | 17 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_77 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_89 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 32 | 32 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_86 | 26 | 26 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_87 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_88 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_83 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_84 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_85 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_80 | 24 | 24 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_81 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_82 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7 | 21 | 21 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 90 | 90 | 0 | 0 | 25 | 0 | 0 | 0 |
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 74 | 74 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1_79 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 |
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 |
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1_78 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 |
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 52 | 52 | 0 | 0 | 17 | 0 | 0 | 0 |
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 36 | 36 | 0 | 0 | 8 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 |
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 23 | 23 | 0 | 0 | 14 | 0 | 0 | 0 |
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 15 | 15 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 8 | 8 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_Axi_CDC | Axi_CDC | 427 | 299 | 128 | 0 | 317 | 0 | 0 | 0 |
| arFifo | StreamFifoCC_3_58 | 192 | 156 | 36 | 0 | 77 | 0 | 0 | 0 |
| (arFifo) | StreamFifoCC_3_58 | 186 | 150 | 36 | 0 | 65 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_73 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_74 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
| awFifo | StreamFifoCC_59 | 110 | 74 | 36 | 0 | 79 | 0 | 0 | 0 |
| (awFifo) | StreamFifoCC_59 | 103 | 67 | 36 | 0 | 65 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_10_70 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_71 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_72 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| bFifo | StreamFifoCC_2_60 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 |
| (bFifo) | StreamFifoCC_2_60 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_5_67 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_4_68 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_6_69 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| rFifo | StreamFifoCC_4_61 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 |
| (rFifo) | StreamFifoCC_4_61 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_65 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_1_66 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| wFifo | StreamFifoCC_1_62 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 |
| (wFifo) | StreamFifoCC_1_62 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_7_63 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_8_64 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| u_axi_axil_adapter | axi_axil_adapter | 1245 | 1245 | 0 | 0 | 161 | 0 | 0 | 0 |
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 640 | 640 | 0 | 0 | 81 | 0 | 0 | 0 |
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 605 | 605 | 0 | 0 | 80 | 0 | 0 | 0 |
| u_axi_dvi | axi_dvi | 284 | 284 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_axi_ram | axi_wrap_ram_sp_external | 356 | 356 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_sram_sp | axi2sram_sp_external | 356 | 356 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_uart_controller | axi_uart_controller | 684 | 668 | 16 | 0 | 457 | 0 | 0 | 0 |
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 252 | 252 | 0 | 0 | 120 | 0 | 0 | 0 |
| uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
| regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
| (regs) | uart_regs | 118 | 118 | 0 | 0 | 155 | 0 | 0 | 0 |
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 |
| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 |
| u_cdma_matmul_bridge | cdma_matmul_bridge | 248 | 248 | 0 | 0 | 578 | 0 | 0 | 0 |
| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 |
| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 |
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
| u_cpu | core_top | 8584 | 8284 | 300 | 0 | 5591 | 0 | 20 | 0 |
| (u_cpu) | core_top | 561 | 513 | 48 | 0 | 1 | 0 | 0 | 0 |
| addr_trans | addr_trans | 2240 | 2100 | 140 | 0 | 1244 | 0 | 0 | 0 |
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
| tlb_entry | tlb_entry | 2240 | 2100 | 140 | 0 | 1204 | 0 | 0 | 0 |
| axi_bridge | axi_bridge | 39 | 39 | 0 | 0 | 214 | 0 | 0 | 0 |
| btb | btb | 1041 | 961 | 80 | 0 | 1611 | 0 | 0 | 0 |
| (btb) | btb | 1039 | 959 | 80 | 0 | 1611 | 0 | 0 | 0 |
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
| dcache | dcache | 551 | 519 | 32 | 0 | 146 | 0 | 10 | 0 |
| (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_46 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_47 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_48 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_49 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_50 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_51 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_52 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_53 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
| lfsr | lfsr_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram_55 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_56 | 42 | 42 | 0 | 0 | 0 | 0 | 1 | 0 |
| exe_stage | exe_stage | 666 | 666 | 0 | 0 | 233 | 0 | 0 | 0 |
| (exe_stage) | exe_stage | 635 | 635 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
| icache | icache | 233 | 233 | 0 | 0 | 55 | 0 | 10 | 0 |
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_38 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_39 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_40 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_41 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_42 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_43 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_44 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_45 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
| id_stage | id_stage | 1054 | 1054 | 0 | 0 | 108 | 0 | 0 | 0 |
| if_stage | if_stage | 134 | 134 | 0 | 0 | 173 | 0 | 0 | 0 |
| mem_stage | mem_stage | 115 | 115 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_csr | csr | 201 | 201 | 0 | 0 | 663 | 0 | 0 | 0 |
| u_div | div | 141 | 141 | 0 | 0 | 107 | 0 | 0 | 0 |
| u_mul | mul | 938 | 938 | 0 | 0 | 592 | 0 | 0 | 0 |
| wb_stage | wb_stage | 682 | 682 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 30142 | 28868 | 112 | 1162 | 18251 | 10 | 18 | 0 |
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 |
| u_fft_controller | fft_controller | 6934 | 5894 | 0 | 1040 | 1083 | 8 | 4 | 0 |
| (u_fft_controller) | fft_controller | 118 | 118 | 0 | 0 | 100 | 0 | 0 | 0 |
| u_FFT | FFT | 6782 | 5742 | 0 | 1040 | 983 | 8 | 0 | 0 |
| SU1 | SdfUnit | 2144 | 1376 | 0 | 768 | 197 | 2 | 0 | 0 |
| SU2 | SdfUnit__parameterized0 | 1567 | 1375 | 0 | 192 | 197 | 2 | 0 | 0 |
| SU3 | SdfUnit__parameterized1 | 1416 | 1368 | 0 | 48 | 197 | 2 | 0 | 0 |
| SU4 | SdfUnit__parameterized2 | 1397 | 1365 | 0 | 32 | 197 | 2 | 0 | 0 |
| SU5 | SdfUnit__parameterized3 | 258 | 258 | 0 | 0 | 195 | 0 | 0 | 0 |
| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_in1 | my_bram0_21 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out0 | my_bram0_22 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out1 | my_bram0_23 | 32 | 32 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_mlkem_axi_cdc | Axi_CDC_5 | 336 | 224 | 112 | 0 | 272 | 0 | 0 | 0 |
| arFifo | StreamFifoCC_3 | 50 | 22 | 28 | 0 | 55 | 0 | 0 | 0 |
| (arFifo) | StreamFifoCC_3 | 42 | 14 | 28 | 0 | 43 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_19 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_20 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| awFifo | StreamFifoCC | 39 | 15 | 24 | 0 | 49 | 0 | 0 | 0 |
| (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 |
| (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
| rFifo | StreamFifoCC_4 | 65 | 37 | 28 | 0 | 72 | 0 | 0 | 0 |
| (rFifo) | StreamFifoCC_4 | 58 | 30 | 28 | 0 | 56 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 |
| wFifo | StreamFifoCC_1 | 164 | 136 | 28 | 0 | 69 | 0 | 0 | 0 |
| (wFifo) | StreamFifoCC_1 | 159 | 131 | 28 | 0 | 53 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| u_mlkem_axi_slave | mlkem_axi_slave | 22873 | 22751 | 0 | 122 | 16890 | 2 | 14 | 0 |
| (u_mlkem_axi_slave) | mlkem_axi_slave | 1179 | 1179 | 0 | 0 | 1064 | 0 | 0 | 0 |
| u_mlkem | mlkem_top | 21697 | 21575 | 0 | 122 | 15826 | 2 | 14 | 0 |
| (u_mlkem) | mlkem_top | 2633 | 2633 | 0 | 0 | 5010 | 0 | 0 | 0 |
| u_bank_a | sd_bram__parameterized0 | 61 | 61 | 0 | 0 | 0 | 1 | 1 | 0 |
| u_bank_se | sd_bram__parameterized1 | 77 | 77 | 0 | 0 | 0 | 1 | 0 | 0 |
| u_bank_t | sd_bram__parameterized2 | 632 | 632 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_c_in_bram | sd_bram | 1301 | 1301 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_cbd | sample_cbd_sync_shared | 2739 | 2739 | 0 | 0 | 3186 | 0 | 0 | 0 |
| u_comp | comp_decomp_sync | 620 | 618 | 0 | 2 | 319 | 0 | 0 | 0 |
| u_ct_bram | sd_bram_6 | 10 | 10 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_dkp_bram | sd_bram_7 | 74 | 74 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_ek_bram | sd_bram_8 | 304 | 304 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_keccak | keccak_core | 5258 | 5258 | 0 | 0 | 1618 | 0 | 0 | 0 |
| u_ntt | ntt_core | 1900 | 1817 | 0 | 83 | 1062 | 0 | 4 | 0 |
| u_pmul | poly_mul_sync | 2058 | 2021 | 0 | 37 | 584 | 0 | 4 | 0 |
| u_sha3 | sha3_top_shared | 1955 | 1955 | 0 | 0 | 2378 | 0 | 0 | 0 |
| u_snt | sample_ntt_sync_shared | 2109 | 2109 | 0 | 0 | 1669 | 0 | 0 | 0 |
| u_matmul_axi_slave | matmul_axi_slave | 9879 | 9697 | 176 | 6 | 3243 | 0 | 0 | 0 |
| (u_matmul_axi_slave) | matmul_axi_slave | 5761 | 5579 | 176 | 6 | 2475 | 0 | 0 | 0 |
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[1].u_mult | pipelined_mult_32x32_2 | 999 | 999 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 1060 | 1060 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[3].u_mult | pipelined_mult_32x32_4 | 997 | 997 | 0 | 0 | 192 | 0 | 0 | 0 |
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1557 | 1557 | 0 | 0 | 1476 | 0 | 1 | 0 |
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 600 | 600 | 0 | 0 | 1180 | 0 | 0 | 0 |
| u_core_engine | snix_axi_mm2mm | 960 | 960 | 0 | 0 | 296 | 0 | 1 | 0 |
| (u_core_engine) | snix_axi_mm2mm | 750 | 750 | 0 | 0 | 243 | 0 | 0 | 0 |
| axis_fifo_u0 | snix_axis_fifo | 210 | 210 | 0 | 0 | 53 | 0 | 1 | 0 |
| u_fifo | snix_sync_fifo | 210 | 210 | 0 | 0 | 53 | 0 | 1 | 0 |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining