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Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

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FallenSigh
2026-06-23 01:22:45 +08:00
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.gitignore vendored Normal file
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# ========================================
# Vivado project & IP files (not tracked)
# ========================================
fpga/.Xil/
fpga/project/
*.xpr
*.xci
*.xcix
*.xdc
*.bd
*.dcp
*.jou
*.log
*.backup.jou
*.backup.log
webtalk*.log
webtalk*.jou
*.wdb
*.pb
*.str
vivado_pid*.txt
*.bit
# ========================================
# OS generated files
# ========================================
.DS_Store
.DS_Store?
._*
.Spotlight-V100
.Trashes
ehthumbs.db
Thumbs.db
desktop.ini
# ========================================
# Editor / IDE
# ========================================
.idea/
.vscode/
*.swp
*.swo
*~
\#*\#
.\#*
# ========================================
# Python
# ========================================
__pycache__/
*.pyc
*.pyo
*.egg-info/

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doc/2026集创赛龙芯中科杯初赛.pdf Normal file
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# 集成电路创新创业大赛 龙芯中科杯 阶段任务三 矩阵乘法器 IP 设计说明
## 1. 参赛任务与设计自由度
本题希望参赛者在保证测试流程能够正确运行的前提下，获得尽可能大的设计自由度。参赛者可以自行决定矩阵乘法器的内部微结构、是否实现 DMA、CPU 与加速器之间的数据搬运方式、批量计算调度方式以及 C 程序中的驱动策略。
参赛者至少需要设计两部分内容：
1. **乘法加速器**：在 `rtl/` 中实现并接入 SoC 的矩阵乘法硬件 IP。
2. **C 程序**：运行在 SoC CPU 上，负责按数据布局读取输入、配置并启动加速器、等待计算完成，并将结果写回 ExtRAM 中的指定结果区域。
无论内部实现如何，最终都必须满足本文定义的数据布局、结果格式和测试流程要求。测试只关心程序能否在解除复位后正确运行，并在串口输出完成标志后，从 ExtRAM 中读取到正确结果。
## 2. 设计目标与接口
参赛者需要设计一个矩阵乘法器 IP，用于完成：
```text
C = A x B
```
矩阵最大规模为 `4x4 * 4x4`。对于较小规模矩阵，例如 `2x3 * 3x2`，仍使用 4x4 数据槽位存储，未使用位置填 0，硬件可按统一的 4x4 规则计算，不影响有效结果。
每个输入元素为 32 bit。若采用无符号计算，每个输出元素为 4 项 32x32 乘积累加结果，结果宽度为 66 bit。实现中不得使用 FPGA DSP 资源，乘法运算应由 LUT、寄存器、加法器、移位器等基础逻辑构成。
矩阵乘法器 IP 固定作为 AXI slave 外设接入 SoC 的 `axiOut_7` 位置，由 CPU 通过 memory-mapped register 方式进行配置、启动和查询。寄存器接口可以按参赛者实现需要进行扩展或调整，但软件程序必须能够配合该接口完成测试任务。
## 3. RAM 数据布局
测试使用 ExtRAM 存放源矩阵和结果矩阵。数据采用“源数据连续区 + 结果连续区”的批量布局：前部连续存放 n 组源矩阵 A/B，排列方式为 `A0, B0, A1, B1, ... A(n-1), B(n-1)`；后部连续存放 n 组结果矩阵 C。
每组源数据占：
```text
A: 16 word = 64 Byte
B: 16 word = 64 Byte
A + B: 32 word = 128 Byte
```
每组结果数据占：
```text
C: 16 * 3 word = 48 word = 192 Byte
```
因此每组完整数据总占用：
```text
(1 + 1 + 3) * 16 * 32 bit = 80 word = 320 Byte
```
批量布局如下：
```text
SRC_BASE + 0 * 128:
group0_A[16]
group0_B[16]
SRC_BASE + 1 * 128:
group1_A[16]
group1_B[16]
...
SRC_BASE + (n - 1) * 128:
group(n-1)_A[16]
group(n-1)_B[16]
DST_BASE:
group0_C[48]
group1_C[48]
...
group(n-1)_C[48]
```
第 i 组矩阵的地址计算规则为：
```text
A_i = SRC_BASE + i * 128
B_i = SRC_BASE + i * 128 + 64
C_i = DST_BASE + i * 192
```
默认可令：
```text
DST_BASE = SRC_BASE + n * 128
```
即结果区紧跟在 n 组源数据之后。IP 不应假设源区和结果区必须相邻，DMA 模式下应以 `SRC_BASE` 和 `DST_BASE` 寄存器为准。
矩阵 A、B 均按 row-major 存储，每个元素占 1 个 32 bit word：
```text
A[0][0], A[0][1], A[0][2], A[0][3],
A[1][0], ...
A[3][3]
```
矩阵 C 同样按 row-major 存储，每个元素占 3 个 32 bit word，用于保存 66 bit 结果：
```text
C[i][j] word0 = result[31:0]
C[i][j] word1 = result[63:32]
C[i][j] word2 = {30'b0, result[65:64]}
```
## 4. 测试流程
测试流程如下：
1. 保持 SoC 处于复位状态。
2. 测试平台向存储器写入待运行程序和矩阵输入数据。
3. 解除 SoC 复位，同时开始计时。
4. SoC CPU 运行参赛者编写的 C 程序。程序应完成输入数据读取、加速器配置、矩阵乘法计算调度、结果写回以及完成通知。
5. 测试平台监听串口输出。当串口输出约定的特定字符串时，停止计时。
6. 停止计时后，测试平台读取 ExtRAM 中的结果数据，并按本文定义的结果布局进行校验。
因此，C 程序必须在所有矩阵结果已经写回 ExtRAM 后，再通过串口输出完成标志。若提前输出完成标志，测试平台会立即停止计时并读取结果，可能导致校验失败。
## 5. 发布包环境修改
发布包工程保持统一顶层引脚约束，使用提供的 `fpga/constraints/soc.xdc`。参赛者不需要、也不应修改板级引脚约束。
工程需要在 SoC 顶层中为矩阵乘法器预留接入点：
1. 将矩阵乘法器 IP 的 AXI slave 接口连接到 `AxiCrossbar_2x8` 的 `axiOut_7`。
2. 为矩阵乘法器分配地址空间 `0x1f50_0000`，对应 crossbar slave7。
3. 若支持 DMA，可将矩阵乘法器的 AXI master 接口连接到当前预留的 master1 通路。
4. 保留 BaseRAM/ExtRAM 的统一连接方式。BaseRAM 可用于存放程序指令，ExtRAM 用于存放源矩阵和结果矩阵。
5. 软件 BSP 中增加矩阵乘法器寄存器基地址和驱动接口，例如：
```c
#define MATMUL_BASE 0x1f500000
```
硬件部分建议限制为 `rtl/` 目录内文件替换或新增；软件部分应提供用于运行矩阵任务的 C 程序及必要的 BSP/驱动适配。工程、引脚约束、测试框架和资源检查流程保持统一，以保证结果可复现。

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#!/usr/bin/env python3
import os
import re
import sys
from pathlib import Path
from typing import List
def usage() -> None:
print("Usage: python3 check_dsp.py <dsp-utilization-report> [max-dsp]", file=sys.stderr)
def extract_dsp_used(report: Path) -> int:
if not report.is_file():
raise FileNotFoundError(f"DSP utilization report not found: {report}")
used_values = []
for line in report.read_text(errors="replace").splitlines():
stripped = line.strip()
if not stripped.startswith("|") or "DSP" not in stripped.upper():
continue
columns = [col.strip() for col in stripped.strip("|").split("|")]
if len(columns) < 2:
continue
if not re.fullmatch(r"DSPs?", columns[0], re.IGNORECASE):
continue
match = re.fullmatch(r"\d+", columns[1])
if match:
used_values.append(int(match.group(0)))
if not used_values:
raise ValueError(f"No DSP utilization row found in {report}")
return max(used_values)
def main(argv: List[str]) -> int:
if len(argv) not in (2, 3):
usage()
return 2
report = Path(argv[1])
max_allowed = int(argv[2]) if len(argv) == 3 else int(os.environ.get("DSP_MAX", "0"))
used = extract_dsp_used(report)
print(f"DSP used: {used}, allowed: {max_allowed}")
if used > max_allowed:
print(f"ERROR: DSP usage {used} exceeds allowed limit {max_allowed}", file=sys.stderr)
return 1
return 0
if __name__ == "__main__":
try:
sys.exit(main(sys.argv))
except Exception as exc:
print(f"ERROR: {exc}", file=sys.stderr)
sys.exit(1)

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# SET PROJECT NAME
set project_name Loongson_Soc
set project_path ./project
set project_part xc7a200tfbg676-1
# CLEAR
file delete -force $project_path
create_project -force $project_name $project_path -part $project_part
# Add conventional sources
add_files -scan_for_includes ../rtl
# Add IPs
add_files -norecurse -scan_for_includes ../rtl/ip/PLL_2019_2/clk_pll.xci
# Add simulation files
add_files -fileset sim_1 ../sim/
# Add constraints
add_files -fileset constrs_1 -quiet ./constraints
set_property top soc_top [current_fileset]
set_property -name "top" -value "tb_top" -objects [get_filesets sim_1]
set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]

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# open project
open_project project/Loongson_Soc.xpr
# generate Bitstream
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
set impl_run [get_runs impl_1]
set impl_progress [get_property PROGRESS $impl_run]
set impl_status [get_property STATUS $impl_run]
puts "impl_1 progress: $impl_progress"
puts "impl_1 status: $impl_status"
set bit_files [glob -nocomplain project/Loongson_Soc.runs/impl_1/*.bit]
if {[llength $bit_files] == 0} {
puts "ERROR: Bitstream file was not generated!"
exit 1
}
puts "Generated bitstream files:"
foreach bit_file $bit_files {
puts " $bit_file"
}
close_project
exit 0

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#!/usr/bin/env python3
from lxml import etree
import chardet
import sys
import os
from pathlib import Path
from typing import Tuple, List, Set
import shutil
import subprocess
import tempfile
import traceback
import re
def usage():
print("Usage: python3 run-linter.py <path-to-vivado-xpr>", file=sys.stderr)
def is_header(f: Path):
with f.open('rb') as fd:
return -1 == fd.read().find(b'endmodule')
def transcoding(src: Path, target: Path):
with src.open("rb") as fd:
rawdata = fd.read()
res = chardet.detect(rawdata)
detected = res['encoding'] if res['confidence'] > 0.5 else None
encodings = ["utf-8", "gb18030"]
if detected and detected.lower() not in ("utf-8", "gb18030"):
encodings.append(detected)
for encoding in encodings:
try:
s = rawdata.decode(encoding)
break
except UnicodeDecodeError:
continue
else:
print("Transcoding", src, "with replacement characters")
s = rawdata.decode("utf-8", "replace")
with target.open("wb") as wfd:
wfd.write(s.encode('utf-8'))
def parse_project(xpr: Path) -> Tuple[str, Set[str], Set[str], Set[str]]:
prjname = os.path.splitext(xpr.name)[0]
prjdir = xpr.parent.resolve()
repo_root = prjdir.parent.parent
srcdir = prjdir / (prjname + ".srcs")
topname = ''
target = prjdir / '.lint'
tree = etree.parse(str(xpr))
srclist = set()
headerlist = set()
inclist = set()
skipped_ip_count = 0
for fileset in tree.xpath("/Project/FileSets/FileSet"):
if fileset.attrib['Type'] != 'DesignSrcs' and \
fileset.attrib['Type'] != 'BlockSrcs':
continue
for child in fileset:
if child.tag == 'File':
tmp = child.attrib['Path']
if tmp.endswith((".xci", ".xcix")):
skipped_ip_count += 1
continue
tmp = tmp.replace('$PSRCDIR', str(srcdir))
tmp = tmp.replace('$PPRDIR', str(prjdir))
vlog = Path(tmp).resolve()
if not vlog.is_file():
print("Source file", vlog, "does not exist")
continue
vlog_target = target / vlog.relative_to(repo_root)
vlog_target.parent.mkdir(exist_ok=True, parents=True)
# shutil.copy(vlog, vlog_target)
transcoding(vlog, vlog_target)
inclist.add(str(vlog_target.parent))
if is_header(vlog_target):
headerlist.add(str(vlog_target))
else:
srclist.add(str(vlog_target))
elif child.tag == 'Config' and fileset.attrib['Type'] == 'DesignSrcs':
topname = child.xpath("./Option[@Name='TopModule']")[0].attrib['Val']
return (topname, headerlist, srclist, inclist)
def verilator_supports_warning(verilator: str, env, warning: str) -> bool:
with tempfile.TemporaryDirectory() as tmpdir:
probe = Path(tmpdir) / "verilator_warning_probe.v"
probe.write_text("module verilator_warning_probe; endmodule\n", encoding="utf-8")
res = subprocess.run(
[verilator, "--lint-only", "-Wno-" + warning, str(probe)],
stdout=subprocess.PIPE,
stderr=subprocess.STDOUT,
universal_newlines=True,
env=env,
)
return "Unknown warning specified" not in res.stdout
def strip_verilog_comments(text: str) -> str:
text = re.sub(r"/\*.*?\*/", "", text, flags=re.S)
return re.sub(r"//.*", "", text)
def find_module_body(text: str, module_name: str) -> str:
pattern = re.compile(r"\bmodule\s+" + re.escape(module_name) + r"\b.*?\bendmodule\b", re.S)
m = pattern.search(text)
return m.group(0) if m else ""
def find_top_source(topname: str, srclist: Set[str]) -> Tuple[Path, str]:
module_re = re.compile(r"\bmodule\s+" + re.escape(topname) + r"\b")
for src in sorted(srclist):
path = Path(src)
text = path.read_text(encoding="utf-8", errors="replace")
if module_re.search(strip_verilog_comments(text)):
return path, text
return Path(), ""
def module_is_instantiated(module_name: str, text: str) -> bool:
code = strip_verilog_comments(text)
pattern = re.compile(
r"(?<!\bmodule\s)\b"
+ re.escape(module_name)
+ r"\s*(?:#\s*\(.*?\)\s*)?[A-Za-z_][A-Za-z0-9_$]*\s*\(",
re.S,
)
return bool(pattern.search(code))
def extract_module_definitions(sources: Set[str]) -> Tuple[dict, dict]:
module_sources = {}
module_bodies = {}
for src in sorted(sources):
path = Path(src)
text = path.read_text(encoding="utf-8", errors="replace")
code = strip_verilog_comments(text)
for m in re.finditer(r"\bmodule\s+([A-Za-z_][A-Za-z0-9_$]*)\b.*?\bendmodule\b", code, re.S):
name = m.group(1)
module_sources.setdefault(name, path)
module_bodies.setdefault(name, m.group(0))
return module_sources, module_bodies
def find_instantiated_modules(text: str, module_names: Set[str]) -> Set[str]:
return {
module
for module in module_names
if module_is_instantiated(module, text)
}
def find_reachable_modules(topname: str, module_bodies: dict) -> Set[str]:
reachable = set()
pending = [topname]
module_names = set(module_bodies)
while pending:
module = pending.pop()
if module in reachable:
continue
reachable.add(module)
body = module_bodies.get(module, "")
for child in find_instantiated_modules(body, module_names - reachable):
pending.append(child)
return reachable
def run_design_sanity_checks(prjdir: Path, topname: str, srclist: Set[str]):
issues = []
top_source, top_text = find_top_source(topname, srclist)
if not top_text:
issues.append("Top module '{}' was not found in lint source set.".format(topname))
else:
for lineno, line in enumerate(top_text.splitlines(), start=1):
if "add your code" in line.lower():
issues.append(
"{}:{}: template placeholder remains in top module; the SoC integration is likely incomplete.".format(
top_source, lineno
)
)
module_sources, module_bodies = extract_module_definitions(srclist)
reachable_modules = find_reachable_modules(topname, module_bodies)
unreachable_modules = sorted(set(module_bodies) - reachable_modules)
if len(module_bodies) >= 20 and len(unreachable_modules) > len(module_bodies) // 2:
shown_modules = ", ".join(unreachable_modules[:12])
if len(unreachable_modules) > 12:
shown_modules += ", ..."
issues.append(
"{}: only {} of {} project modules are reachable from top '{}'; unreachable modules include: {}.".format(
top_source,
len(reachable_modules & set(module_bodies)),
len(module_bodies),
topname,
shown_modules,
)
)
if issues:
sanity_log = prjdir / "linter-sanity.log"
sanity_log.write_text("\n".join(issues) + "\n", encoding="utf-8")
print("HDL sanity check failed.")
for issue in issues:
print(issue)
print("Full log:", sanity_log)
sys.exit(1)
def run_linter(prjdir: Path, topname: str, headerlist: Set[str], srclist: Set[str], inclist: Set[str]):
linter_log = prjdir / "linter.log"
linter_args = prjdir / "linter.args"
verilator = os.environ.get("VERILATOR") or shutil.which("verilator") or shutil.which("verilator_bin.exe")
if not verilator:
print("ERROR: verilator was not found in PATH.", file=sys.stderr)
print("Install verilator in the CI image, set VERILATOR, or remove the HDL lint step from .gitlab-ci.yml.", file=sys.stderr)
sys.exit(127)
env = os.environ.copy()
if os.name == "nt" and "VERILATOR_ROOT" not in env:
verilator_root = Path(verilator).resolve().parent.parent / "share" / "verilator"
if verilator_root.is_dir():
env["VERILATOR_ROOT"] = str(verilator_root)
timescale_warning = None
for warning in ("TIMESCALEMOD", "TIMESCALE"):
if verilator_supports_warning(verilator, env, warning):
timescale_warning = warning
break
args = [
verilator,
"--lint-only",
"-Wall",
"-Wno-fatal",
"-Wno-DECLFILENAME",
"-Wno-PINCONNECTEMPTY",
"-Wno-UNUSED",
"-GSIMULATION=1",
]
if timescale_warning:
args.append("-Wno-" + timescale_warning)
args += ['--top-module', topname]
incargs = [ '-I' + i for i in inclist]
args += incargs
args += sorted(headerlist)
args += srclist
if os.name == "nt":
response_args = [str(arg).replace("\\", "/") for arg in args[1:]]
linter_args.write_text("\n".join(response_args) + "\n", encoding="utf-8")
run_args = [verilator, "-f", str(linter_args)]
else:
run_args = args
with linter_log.open("w", encoding="utf-8") as log:
res = subprocess.run(run_args, stdout=log, stderr=subprocess.STDOUT, env=env)
if res.returncode != 0:
log_text = linter_log.read_text(encoding="utf-8", errors="replace")
error_lines = [
line for line in log_text.splitlines()
if "%Error" in line or "Error:" in line or "ERROR:" in line
]
print("HDL lint failed.")
if error_lines:
print("Key errors:")
for line in error_lines[:20]:
print(line)
if len(error_lines) > 20:
print("... {} more error lines omitted".format(len(error_lines) - 20))
else:
print("No explicit error line found in Verilator output.")
print("Return code:", res.returncode)
print("Full log:", linter_log)
sys.exit(res.returncode)
print("HDL lint passed.")
if __name__ == "__main__":
try:
if len(sys.argv) != 2:
usage()
sys.exit(2)
xpr = Path(sys.argv[1])
if not xpr.is_file():
print("Vivado project file does not exist:", xpr, file=sys.stderr)
sys.exit(2)
topname, headerlist, srclist, inclist = parse_project(xpr)
if not topname:
print("Top module was not found in project:", xpr, file=sys.stderr)
sys.exit(1)
if not srclist:
print("No Verilog source files were found in project:", xpr, file=sys.stderr)
sys.exit(1)
run_design_sanity_checks(xpr.parent, topname, srclist)
run_linter(xpr.parent, topname, headerlist, srclist, inclist)
except Exception:
traceback.print_exc()
sys.exit(1)

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# bit.tcl
open_project project/Loongson_Soc.xpr
# Add myCPU
# add_files -scan_for_includes mysrc
# Add xilinx_ip in myCPU
# add_files -quiet [glob -nocomplain mysrc/xilinx_ip/*/*.xci]
# add_files -quiet [glob -nocomplain mysrc/xilinx_ip/*/*.xcix]
# Upgrade IPs
upgrade_ip -quiet [get_ips]
# run_impl
launch_runs impl_1
wait_on_run impl_1
# check impl status
if {[get_property PROGRESS [get_runs impl_1]] != "100%"} {
puts "ERROR: Implementation failed!"
exit 1
}
# open_run impl_1
open_run impl_1
report_utilization -file project/dsp_utilization.rpt -pb project/dsp_utilization.pb
# report_timing_summary -delay_type min_max -report_unconstrained \
# -file lab/lab1.runs/impl_1/timing_summary.rpt
close_project
exit 0

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`define SRAM_Init_File "../../../../../../sdk/axi_ram.mif"
`define USE_CACHE
`define Lawcmd 4
`define Lawdirqid 4
`define Lawstate 2
`define Lawscseti 2
`define Lawid 4
`define Lawaddr 32
`define Lawlen 8
`define Lawsize 3
`define Lawburst 2
`define Lawlock 2
`define Lawcache 4
`define Lawprot 3
`define Lawvalid 1
`define Lawready 1
`define Lwid 4
`define Lwdata 32
`define Lwstrb 4
`define Lwlast 1
`define Lwvalid 1
`define Lwready 1
`define Lbid 4
`define Lbresp 2
`define Lbvalid 1
`define Lbready 1
`define Larcmd 4
`define Larcpuno 10
`define Larid 4
`define Laraddr 32
`define Larlen 8
`define Larsize 3
`define Larburst 2
`define Larlock 2
`define Larcache 4
`define Larprot 3
`define Larvalid 1
`define Larready 1
`define Lrstate 2
`define Lrscseti 2
`define Lrid 4
`define Lrdata 32
`define Lrresp 2
`define Lrlast 1
`define Lrvalid 1
`define Lrready 1
`define Lrrequest 1
`define LID 4
`define LADDR 32
`define LLEN 8
`define LSIZE 3
`define LDATA 32
`define LSTRB 4
`define LBURST 2
`define LLOCK 2
`define LCACHE 4
`define LPROT 3
`define LRESP 2

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rtl/ip/APB_UART/URT/raminfr.v Normal file
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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
module raminfr(clk, we, a, dpra, di, dpo);
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;
input we;
input [addr_width-1:0] a;
input [addr_width-1:0] dpra;
input [data_width-1:0] di;
output [data_width-1:0] dpo;
reg [data_width-1:0] ram [depth-1:0];
wire [data_width-1:0] di;
wire [addr_width-1:0] a;
wire [addr_width-1:0] dpra;
always @(posedge clk) begin
if (we)
ram[a] <= di;
end
reg [data_width-1:0] dpo;
always @(posedge clk)
dpo <= ram[dpra];
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`define UART_ADDR_WIDTH 3
`define UART_DATA_WIDTH 8
// Register addresses
`define UART_REG_RB `UART_ADDR_WIDTH'd0 // receiver buffer
`define UART_REG_TR `UART_ADDR_WIDTH'd0 // transmitter
`define UART_REG_IE `UART_ADDR_WIDTH'd1 // Interrupt enable
`define UART_REG_II `UART_ADDR_WIDTH'd2 // Interrupt identification
`define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control
`define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control
`define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control
`define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status
`define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status
`define UART_REG_SR `UART_ADDR_WIDTH'd7 // Scratch register
`define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2)
`define UART_REG_DL2 `UART_ADDR_WIDTH'd1
// Interrupt Enable register bits
`define UART_IE_RDA 0 // Received Data available interrupt
`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt
`define UART_IE_RLS 2 // Receiver Line Status Interrupt
`define UART_IE_MS 3 // Modem Status Interrupt
// Interrupt Identification register bits
`define UART_II_IP 0 // Interrupt pending when 0
`define UART_II_II 3:1 // Interrupt identification
// Interrupt identification values for bits 3:1
`define UART_II_RLS 3'b011 // Receiver Line Status
`define UART_II_RDA 3'b010 // Receiver Data available
`define UART_II_TI 3'b110 // Timeout Indication
`define UART_II_THRE 3'b001 // Transmitter Holding Register empty
`define UART_II_MS 3'b000 // Modem Status
// FIFO Control Register bits
`define UART_FC_TL 1:0 // Trigger level
// FIFO trigger level values
`define UART_FC_1 2'b00
`define UART_FC_4 2'b01
`define UART_FC_8 2'b10
`define UART_FC_14 2'b11
// Line Control register bits
`define UART_LC_BITS 1:0 // bits in character
`define UART_LC_SB 2 // stop bits
`define UART_LC_PE 3 // parity enable
`define UART_LC_EP 4 // even parity
`define UART_LC_SP 5 // stick parity
`define UART_LC_BC 6 // Break control
`define UART_LC_DL 7 // Divisor Latch access bit
// Modem Control register bits
`define UART_MC_DTR 0
`define UART_MC_RTS 1
`define UART_MC_OUT1 2
`define UART_MC_OUT2 3
`define UART_MC_LB 4 // Loopback mode
// Line Status Register bits
`define UART_LS_DR 0 // Data ready
`define UART_LS_OE 1 // Overrun Error
`define UART_LS_PE 2 // Parity Error
`define UART_LS_FE 3 // Framing Error
`define UART_LS_BI 4 // Break interrupt
`define UART_LS_TFE 5 // Transmit FIFO is empty
`define UART_LS_TE 6 // Transmitter Empty indicator
`define UART_LS_EI 7 // Error indicator
// Modem Status Register bits
`define UART_MS_DCTS 0 // Delta signals
`define UART_MS_DDSR 1
`define UART_MS_TERI 2
`define UART_MS_DDCD 3
`define UART_MS_CCTS 4 // Complement signals
`define UART_MS_CDSR 5
`define UART_MS_CRI 6
`define UART_MS_CDCD 7
// FIFO parameter defines
`define UART_FIFO_WIDTH 8
`define UART_FIFO_DEPTH 16
`define UART_FIFO_POINTER_W 4
`define UART_FIFO_COUNTER_W 5
`define UART_FIFO_REC_WIDTH 11

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "uart_defines.h"
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
counter_t, rf_count, rf_data_out, rf_error_bit,
rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
input clk;
input wb_rst_i;
input [7:0] lcr;
input rf_pop;
input srx_pad_i;
input enable;
input rx_reset;
input lsr_mask;
output [9:0] counter_t;
output [`UART_FIFO_COUNTER_W-1:0] rf_count;
output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
output rf_overrun;
output rf_error_bit;
output [3:0] rstate;
output rf_push_pulse;
reg [3:0] rstate;
reg [3:0] rcounter16;
reg [2:0] rbit_counter;
reg [7:0] rshift;
reg rparity;
reg rparity_error;
reg rframing_error;
reg rbit_in;
reg rparity_xor;
reg [7:0] counter_b;
reg rf_push_q;
reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
wire[`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_push_pulse;
reg rf_push;
wire rf_pop;
wire rf_overrun;
wire[`UART_FIFO_COUNTER_W-1:0] rf_count;
wire rf_error_bit;
wire break_error = (counter_b == 0);
uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
.clk ( clk ),
.wb_rst_i ( wb_rst_i ),
.data_in ( rf_data_in ),
.data_out ( rf_data_out ),
.push ( rf_push_pulse),
.pop ( rf_pop ),
.overrun ( rf_overrun ),
.count ( rf_count ),
.error_bit ( rf_error_bit ),
.fifo_reset ( rx_reset ),
.reset_status( lsr_mask )
);
wire rcounter16_eq_7 = (rcounter16 == 4'd7);
wire rcounter16_eq_0 = (rcounter16 == 4'd0);
wire rcounter16_eq_1 = (rcounter16 == 4'd1);
wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1;
parameter sr_idle = 4'd0;
parameter sr_rec_start = 4'd1;
parameter sr_rec_bit = 4'd2;
parameter sr_rec_parity = 4'd3;
parameter sr_rec_stop = 4'd4;
parameter sr_check_parity = 4'd5;
parameter sr_rec_prepare = 4'd6;
parameter sr_end_bit = 4'd7;
parameter sr_ca_lc_parity = 4'd8;
parameter sr_wait1 = 4'd9;
parameter sr_push = 4'd10;
always @(posedge clk ) begin
if (wb_rst_i) begin
rstate <= sr_idle;
rbit_in <= 1'b0;
rcounter16 <= 0;
rbit_counter <= 0;
rparity_xor <= 1'b0;
rframing_error <= 1'b0;
rparity_error <= 1'b0;
rparity <= 1'b0;
rshift <= 0;
rf_push <= 1'b0;
rf_data_in <= 0;
end
else if (enable) begin
case (rstate)
sr_idle : begin
rf_push <= 1'b0;
rf_data_in <= 0;
rcounter16 <= 4'b1110;
if (srx_pad_i==1'b0 & ~break_error) begin
rstate <= sr_rec_start;
end
end
sr_rec_start : begin
rf_push <= 1'b0;
if (rcounter16_eq_7)
if (srx_pad_i==1'b1)
rstate <= sr_idle;
else
rstate <= sr_rec_prepare;
else rstate<=rstate;
rcounter16 <= rcounter16_minus_1;
end
sr_rec_prepare: begin
case (lcr[1:0])
2'b00 : rbit_counter <= 3'b100;
2'b01 : rbit_counter <= 3'b101;
2'b10 : rbit_counter <= 3'b110;
2'b11 : rbit_counter <= 3'b111;
endcase
if (rcounter16_eq_0) begin
rstate <= sr_rec_bit;
rcounter16 <= 4'b1110;
rshift <= 0;
end
else
rstate <= sr_rec_prepare;
rcounter16 <= rcounter16_minus_1;
end
sr_rec_bit : begin
if (rcounter16_eq_0) rstate <= sr_end_bit;
if (rcounter16_eq_7)
case (lcr[1:0])
2'b00 : rshift[4:0] <= {srx_pad_i, rshift[4:1]};
2'b01 : rshift[5:0] <= {srx_pad_i, rshift[5:1]};
2'b10 : rshift[6:0] <= {srx_pad_i, rshift[6:1]};
2'b11 : rshift[7:0] <= {srx_pad_i, rshift[7:1]};
endcase
rcounter16 <= rcounter16_minus_1;
end
sr_end_bit : begin
if (rbit_counter==3'b0)
if (lcr[`UART_LC_PE])
rstate <= sr_rec_parity;
else begin
rstate <= sr_rec_stop;
rparity_error<= 1'b0;
end
else begin
rstate <= sr_rec_bit;
rbit_counter <= rbit_counter - 1'b1;
end
rcounter16 <= 4'b1110;
end
sr_rec_parity : begin
if (rcounter16_eq_7) begin
rparity <= srx_pad_i;
rstate <= sr_ca_lc_parity;
end
rcounter16 <= rcounter16_minus_1;
end
sr_ca_lc_parity:begin
rcounter16 <= rcounter16_minus_1;
rparity_xor <= ^{rshift,rparity};
rstate <= sr_check_parity;
end
sr_check_parity: begin
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
2'b00: rparity_error <= rparity_xor == 0;
2'b01: rparity_error <= ~rparity;
2'b10: rparity_error <= rparity_xor == 1;
2'b11: rparity_error <= rparity;
endcase
rcounter16 <= rcounter16_minus_1;
rstate <= sr_wait1;
end
sr_wait1 :
if (rcounter16_eq_0) begin
rstate <= sr_rec_stop;
rcounter16 <= 4'b1110;
end
else rcounter16 <= rcounter16_minus_1;
sr_rec_stop : begin
if (rcounter16_eq_7) begin
rframing_error <= !srx_pad_i;
rstate <= sr_push;
end
rcounter16 <= rcounter16_minus_1;
end
sr_push : begin
if(srx_pad_i | break_error) begin
if(break_error)
rf_data_in <= {8'b0, 3'b100};
else
rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= 1'b1;
rstate <= sr_idle;
end
else if(~rframing_error) begin
rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= 1'b1;
rcounter16 <= 4'b1110;
rstate <= sr_rec_start;
end
end
default : rstate <= sr_idle;
endcase
end
end
always @ (posedge clk ) begin
if(wb_rst_i) rf_push_q <= 0;
else rf_push_q <= rf_push;
end
assign rf_push_pulse = rf_push & ~rf_push_q;
reg [9:0] toc_value;
always @(lcr)
case (lcr[3:0])
4'b0000 : toc_value = 447;
4'b0100 : toc_value = 479;
4'b0001, 4'b1000 : toc_value = 511;
4'b1100 : toc_value = 543;
4'b0010, 4'b0101, 4'b1001 : toc_value = 575;
4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639;
4'b0111, 4'b1011, 4'b1110 : toc_value = 703;
4'b1111 : toc_value = 767;
endcase
wire [7:0] brc_value;
assign brc_value = toc_value[9:2];
always @(posedge clk ) begin
if (wb_rst_i) counter_b <= 8'd159;
else if (srx_pad_i) counter_b <= brc_value;
else if (enable & counter_b != 8'b0)
counter_b <= counter_b - 1;
end
reg [9:0] counter_t;
always @(posedge clk ) begin
if (wb_rst_i) counter_t <= 10'd639;
else if(rf_push_pulse || rf_pop || rf_count == 0)
counter_t <= toc_value;
else if (enable && counter_t != 10'b0)
counter_t <= counter_t - 1;
end
endmodule

711
rtl/ip/APB_UART/URT/uart_regs.v Normal file
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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "uart_defines.h"
`define UART_DL1 7:0
`define UART_DL2 15:8
`define UART_DL3 23:16
module uart_regs (clk, rst, clk_carrier,
addr, dat_i, dat_o, we, re,
modem_inputs,
rts_pad_o, dtr_pad_o,
stx_pad_o,TXD_i,srx_pad_i,RXD_o,
int_o,
usart_mode,
rx_en,
tx2rx_en
);
input clk;
input rst ;
input clk_carrier;
input [2:0] addr;
input [7:0] dat_i;
output [7:0] dat_o;
input we;
input re;
output stx_pad_o;
input srx_pad_i;
input TXD_i;
output RXD_o;
input [3:0] modem_inputs;
output rts_pad_o;
output dtr_pad_o;
output int_o;
output usart_mode;
output tx2rx_en;
output rx_en;
wire [3:0] modem_inputs;
reg enable;
wire stx_pad_o;
wire srx_pad_i;
wire srx_pad;
reg [7:0] dat_o;
wire [2:0] addr;
wire [7:0] dat_i;
reg [3:0] ier;
reg [3:0] iir;
reg [1:0] fcr;
reg [4:0] mcr;
reg infrared;
reg rx_pol;
reg [7:0] lcr;
reg [7:0] msr;
reg [23:0] dl;
reg start_dlc;
reg lsr_mask_d;
reg msi_reset;
reg [15:0] dlc;
reg int_o;
reg [3:0] trigger_level;
reg rx_reset;
reg tx_reset;
wire dlab;
wire usart_mode;
wire usart_rx_en;
wire usart_tx_en;
wire tx2rx_en;
reg sclk_reg;
reg sclk_en_reg;
reg [7:0] mode_reg;
reg [7:0] fi_di_reg;
reg [7:0] sclk_count;
reg [2:0] repeat_reg;
wire usart_normal;
wire usart_irda;
wire usart_t0;
wire usart_t1;
wire rx_en;
wire tx_en;
wire sclk_por;
assign usart_normal = mode_reg[1:0]==2'h0;
assign usart_irda = mode_reg[1:0]==2'h1;
assign usart_t0 = mode_reg[1:0]==2'h2;
assign usart_t1 = mode_reg[1:0]==2'h3;
assign usart_tx_en = mode_reg[2]==1'b0;
assign usart_rx_en = mode_reg[2]==1'b1;
assign sclk_por = mode_reg[3];
assign RXD_o = sclk_reg^sclk_por;
assign usart_mode = usart_t0 || usart_t1;
assign rx_en = usart_normal || usart_irda || usart_mode && usart_rx_en;
assign tx_en = usart_normal || usart_irda || usart_mode && usart_tx_en;
always @(posedge clk )
begin
if (rst) begin
mode_reg <= 8'h0;
fi_di_reg <= 8'h0;
repeat_reg<= 3'h4;
sclk_en_reg<= 1'b0;
end
else if (we && addr==`UART_REG_SR)begin
if(dlab)
fi_di_reg <= dat_i;
else
mode_reg <= dat_i;
end
else begin
if(enable) sclk_en_reg <= mode_reg[4];
repeat_reg <= mode_reg[7:5];
end
end
always @(posedge clk)
begin
if(rst) begin
sclk_count <= 8'b0;
sclk_reg <=1'b0;
end
else if(usart_mode&&(fi_di_reg>8'h1)&&sclk_en_reg) begin
if(sclk_count == fi_di_reg[7:1]) begin
sclk_reg <= 1'b1;
sclk_count <= sclk_count + 1'b1;
end
else if(sclk_count == fi_di_reg) begin
sclk_reg <= 1'b0;
sclk_count <= 8'b0;
end
else begin
sclk_count <= sclk_count + 1'b1;
end
end
else begin
sclk_reg <=1'b0;
sclk_count <= 8'b0;
end
end
wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i;
wire loopback;
wire cts, dsr, ri, dcd;
wire cts_c, dsr_c, ri_c, dcd_c;
wire rts_pad_o, dtr_pad_o;
wire [7:0] lsr;
wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
wire lsr_mask;
assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
: {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign dlab = lcr[`UART_LC_DL];
assign loopback = mcr[4];
assign rts_pad_o = mcr[`UART_MC_RTS];
assign dtr_pad_o = mcr[`UART_MC_DTR];
wire rls_int;
wire rda_int;
wire ti_int;
wire thre_int;
wire ms_int;
wire tf_push;
reg rf_pop;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_error_bit;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
wire [9:0] counter_t;
wire thre_set_en;
reg [7:0] block_cnt;
reg [7:0] block_value;
wire current_finish;
wire max_repeat_time;
wire serial_out;
wire serial_out_modulated = ~ (clk_carrier & serial_out);
uart_transmitter transmitter(.clk(clk), .wb_rst_i(rst), .lcr(lcr), .tf_push(tf_push), .wb_dat_i(dat_i),
.tx2rx_en (tx2rx_en),
.usart_mode(usart_mode),
.srx_pad_i(TXD_i),
.enable (enable && tx_en),
.usart_t0(usart_t0),
.repeat_time(repeat_reg ),
.current_finish(current_finish),
.max_repeat_time(max_repeat_time),
.stx_pad_o(serial_out), .tstate(tstate), .tf_count(tf_count),
.tx_reset(tx_reset), .lsr_mask(lsr_mask));
wire rcv_pad_i;
assign rcv_pad_i = ~usart_mode ? srx_pad_i : (rx_en ? TXD_i : 1'b1);
uart_sync_flops i_uart_sync_flops(
.rst_i (rst),
.clk_i (clk),
.stage1_rst_i (1'b0),
.stage1_clk_en_i (1'b1),
.async_dat_i (rcv_pad_i),
.sync_dat_o (srx_pad)
);
defparam i_uart_sync_flops.width = 1;
defparam i_uart_sync_flops.init_value = 1'b1;
wire serial_in = loopback ? serial_out : rx_pol ? ~srx_pad : srx_pad;
assign stx_pad_o = loopback ? 1'b1 : infrared ? serial_out_modulated : serial_out;
wire rf_overrun;
wire rf_push_pulse;
uart_receiver receiver(.clk(clk), .wb_rst_i(rst), .lcr(lcr), .rf_pop(rf_pop), .srx_pad_i(serial_in),
.enable(enable && rx_en),
.counter_t(counter_t), .rf_count(rf_count), .rf_data_out(rf_data_out), .rf_error_bit(rf_error_bit),
.rf_overrun(rf_overrun), .rx_reset(rx_reset), .lsr_mask(lsr_mask), .rstate(rstate), .rf_push_pulse(rf_push_pulse));
always @(dl or dlab or ier or iir or fi_di_reg or mode_reg
or lcr or lsr or msr or rf_data_out or addr )
begin
case (addr)
`UART_REG_RB : dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
`UART_REG_IE : dat_o = dlab ? dl[`UART_DL2] : ier;
`UART_REG_II : dat_o = dlab ? dl[`UART_DL3] : {4'b1100,iir};
`UART_REG_LC : dat_o = lcr;
`UART_REG_LS : dat_o = lsr;
`UART_REG_MS : dat_o = msr;
`UART_REG_SR : dat_o = dlab ? fi_di_reg : mode_reg;
default : dat_o = 8'b0;
endcase
end
always @(posedge clk )
begin
if (rst)
rf_pop <= 0;
else
if (rf_pop)
rf_pop <= 0;
else
if (re && addr == `UART_REG_RB && !dlab)
rf_pop <= 1;
end
wire lsr_mask_condition;
wire iir_read;
wire msr_read;
wire fifo_read;
wire fifo_write;
assign lsr_mask_condition = (re && addr == `UART_REG_LS && !dlab);
assign iir_read = (re && addr == `UART_REG_II && !dlab);
assign msr_read = (re && addr == `UART_REG_MS && !dlab);
assign fifo_read = (re && addr == `UART_REG_RB && !dlab);
assign fifo_write = (we && addr == `UART_REG_TR && !dlab);
always @(posedge clk )
begin
if (rst)
lsr_mask_d <= 0;
else
lsr_mask_d <= lsr_mask_condition;
end
assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
always @(posedge clk )
begin
if (rst)
msi_reset <= 1;
else
if (msi_reset)
msi_reset <= 0;
else
if (msr_read)
msi_reset <= 1;
end
always @(posedge clk )
if (rst)
lcr <= 8'b00000011;
else
if (we && addr==`UART_REG_LC)
lcr <= dat_i;
always @(posedge clk )
if (rst)
begin
ier <= 4'b0000;
dl[`UART_DL2] <= 8'b0;
end
else
if (we && addr==`UART_REG_IE)
if (dlab)
begin
dl[`UART_DL2] <= dat_i;
end
else
ier <= dat_i[3:0];
else
ier<= ier;
always @(posedge clk )
if (rst) begin
fcr <= 2'b11;
rx_reset <= 0;
tx_reset <= 0;
dl[`UART_DL3] <= 8'h0;
end else
if (we && addr==`UART_REG_FC) begin
if(dlab) dl[`UART_DL3] <= dat_i;
else begin
fcr <= dat_i[7:6];
rx_reset <= dat_i[1];
tx_reset <= dat_i[2];
end
end else begin
rx_reset <= 0;
tx_reset <= 0;
end
always @(posedge clk )
if (rst) begin
mcr <= 5'b0;
infrared <= 1'b0;
rx_pol <= 1'b0; end
else
if(we && addr==`UART_REG_MC) begin
mcr <= dat_i[4:0];
infrared <= dat_i[7];
rx_pol <= dat_i[6]; end
assign tf_push = we & addr==`UART_REG_TR & !dlab;
always @(posedge clk )
if (rst)
begin
dl[`UART_DL1] <= 8'b0;
start_dlc <= 1'b0;
end
else
if (we && addr==`UART_REG_TR)
if (dlab)
begin
dl[`UART_DL1] <= dat_i;
start_dlc <= 1'b1;
end
else
begin
start_dlc <= 1'b0;
end
else
begin
start_dlc <= 1'b0;
end
always @(fcr)
case (fcr[`UART_FC_TL])
2'b00 : trigger_level = 1;
2'b01 : trigger_level = 4;
2'b10 : trigger_level = 8;
2'b11 : trigger_level = 14;
endcase
reg [3:0] delayed_modem_signals;
always @(posedge clk )
begin
if (rst)
begin
msr <= 0;
delayed_modem_signals[3:0] <= 0;
end
else begin
msr[`UART_MS_DDCD:`UART_MS_DCTS] <= msi_reset ? 4'b0 :
msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
msr[`UART_MS_CDCD:`UART_MS_CCTS] <= {dcd_c, ri_c, dsr_c, cts_c};
delayed_modem_signals[3:0] <= {dcd, ri, dsr, cts};
end
end
assign lsr0 = (rf_count==0 && rf_push_pulse);
assign lsr1 = rf_overrun;
assign lsr2 = rf_data_out[1];
assign lsr3 = rf_data_out[0];
assign lsr4 = rf_data_out[2];
assign lsr5 = current_finish && (tf_count==5'b0 && thre_set_en);
assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == 3'd0));
assign lsr7 = rf_error_bit | rf_overrun;
reg lsr0_d;
always @(posedge clk )
if (rst) lsr0_d <= 0;
else lsr0_d <= lsr0;
always @(posedge clk )
if (rst) lsr0r <= 0;
else lsr0r <= (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 :
lsr0r || (lsr0 && ~lsr0_d);
reg lsr1_d;
always @(posedge clk )
if (rst) lsr1_d <= 0;
else lsr1_d <= lsr1;
always @(posedge clk )
if (rst) lsr1r <= 0;
else lsr1r <= lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d);
reg lsr2_d;
always @(posedge clk )
if (rst) lsr2_d <= 0;
else lsr2_d <= lsr2;
always @(posedge clk )
if (rst) lsr2r <= 0;
else lsr2r <= lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d);
reg lsr3_d;
always @(posedge clk )
if (rst) lsr3_d <= 0;
else lsr3_d <= lsr3;
always @(posedge clk )
if (rst) lsr3r <= 0;
else lsr3r <= lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d);
reg lsr4_d;
always @(posedge clk )
if (rst) lsr4_d <= 0;
else lsr4_d <= lsr4;
always @(posedge clk )
if (rst) lsr4r <= 0;
else lsr4r <= lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
reg lsr5_d;
always @(posedge clk )
if (rst) lsr5_d <= 1;
else lsr5_d <= lsr5;
always @(posedge clk )
if (rst) lsr5r <= 1;
else lsr5r <= (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
reg lsr6_d;
always @(posedge clk )
if (rst) lsr6_d <= 1;
else lsr6_d <= lsr6;
always @(posedge clk )
if (rst) lsr6r <= 1;
else lsr6r <= (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
reg lsr7_d;
always @(posedge clk )
if (rst) lsr7_d <= 0;
else lsr7_d <= lsr7;
always @(posedge clk )
if (rst) lsr7r <= 0;
else lsr7r <= lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
reg [8:0] M_cnt;
wire [8:0] M_next = M_cnt + dl[`UART_DL3];
wire M_toggle = M_cnt[8] ^ M_next[8];
always @(posedge clk )
begin
if (rst) begin
dlc <= 0;
M_cnt <= 8'h0;
end
else if (start_dlc | ~ (|dlc)) begin
dlc <= dl - 1 + M_toggle;
M_cnt <= M_next;
end
else
dlc <= dlc - 1;
end
always @(posedge clk )
begin
if (rst)
enable <= 1'b0;
else if (|dl & ~(|dlc))
enable <= 1'b1;
else
enable <= 1'b0;
end
always @(lcr)
case (lcr[3:0])
4'b0000 : block_value = 95;
4'b0100 : block_value = 103;
4'b0001, 4'b1000 : block_value = 111;
4'b1100 : block_value = 119;
4'b0010, 4'b0101, 4'b1001 : block_value = 127;
4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143;
4'b0111, 4'b1011, 4'b1110 : block_value = 159;
4'b1111 : block_value = 175;
endcase
always @(posedge clk )
begin
if (rst)
block_cnt <= 8'd0;
else
if(lsr5r & fifo_write)
block_cnt <= usart_t0 ? (block_value + 8'h16) : block_value;
else
if (enable & block_cnt != 8'b0)
block_cnt <= block_cnt - 1;
end
assign thre_set_en = ~(|block_cnt);
assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
assign thre_int = ier[`UART_IE_THRE]&& lsr[`UART_LS_TFE];
assign ms_int = ier[`UART_IE_MS] && (usart_t0 ? max_repeat_time : (| msr[3:0]));
assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
reg rls_int_d;
reg thre_int_d;
reg ms_int_d;
reg ti_int_d;
reg rda_int_d;
always @(posedge clk )
if (rst) rls_int_d <= 0;
else rls_int_d <= rls_int;
always @(posedge clk )
if (rst) rda_int_d <= 0;
else rda_int_d <= rda_int;
always @(posedge clk )
if (rst) thre_int_d <= 0;
else thre_int_d <= thre_int;
always @(posedge clk )
if (rst) ms_int_d <= 0;
else ms_int_d <= ms_int;
always @(posedge clk )
if (rst) ti_int_d <= 0;
else ti_int_d <= ti_int;
wire rls_int_rise;
wire thre_int_rise;
wire ms_int_rise;
wire ti_int_rise;
wire rda_int_rise;
assign rda_int_rise = rda_int & ~rda_int_d;
assign rls_int_rise = rls_int & ~rls_int_d;
assign thre_int_rise = thre_int & ~thre_int_d;
assign ms_int_rise = ms_int & ~ms_int_d;
assign ti_int_rise = ti_int & ~ti_int_d;
reg rls_int_pnd;
reg rda_int_pnd;
reg thre_int_pnd;
reg ms_int_pnd;
reg ti_int_pnd;
always @(posedge clk )
if (rst) rls_int_pnd <= 0;
else
rls_int_pnd <= lsr_mask ? 0 :
rls_int_rise ? 1 :
rls_int_pnd && ier[`UART_IE_RLS];
reg d1_fifo_read;
always @( posedge clk ) d1_fifo_read <= fifo_read;
always @(posedge clk)
if (rst) rda_int_pnd <= 0;
else rda_int_pnd <= ((rf_count == {1'b0,trigger_level}) && d1_fifo_read) ? 0 :
rda_int_rise ? 1 :
rda_int_pnd && ier[`UART_IE_RDA];
always @(posedge clk )
if (rst) thre_int_pnd <= 0;
else
thre_int_pnd <= fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :
thre_int_rise ? 1 :
thre_int_pnd && ier[`UART_IE_THRE];
always @(posedge clk )
if (rst) ms_int_pnd <= 0;
else
ms_int_pnd <= msr_read ? 0 : ms_int_rise ? 1 :
ms_int_pnd && ier[`UART_IE_MS];
always @(posedge clk )
if (rst) ti_int_pnd <= 0;
else
ti_int_pnd <= fifo_read ? 0 : ti_int_rise ? 1 :
ti_int_pnd && ier[`UART_IE_RDA];
always @(posedge clk )
begin
if (rst) int_o <= 1'b0;
else int_o <= rls_int_pnd ? ~lsr_mask :
rda_int_pnd ? 1 :
ti_int_pnd ? ~fifo_read:
thre_int_pnd? !(fifo_write & iir_read) :
ms_int_pnd ? ~msr_read :
0;
end
always @(posedge clk )
begin
if (rst)
iir <= 1;
else
if (rls_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_RLS;
iir[`UART_II_IP] <= 1'b0;
end else
if (rda_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_RDA;
iir[`UART_II_IP] <= 1'b0;
end
else if (ti_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_TI;
iir[`UART_II_IP] <= 1'b0;
end
else if (thre_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_THRE;
iir[`UART_II_IP] <= 1'b0;
end
else if (ms_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_MS;
iir[`UART_II_IP] <= 1'b0;
end else
begin
iir[`UART_II_II] <= 0;
iir[`UART_II_IP] <= 1'b1;
end
end
endmodule

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rtl/ip/APB_UART/URT/uart_rfifo.v Normal file
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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "uart_defines.h"
module uart_rfifo (clk,
wb_rst_i, data_in, data_out,
push,
pop,
overrun,
count,
error_bit,
fifo_reset,
reset_status
);
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
output error_bit;
wire [fifo_width-1:0] data_out;
wire [7:0] data8_out;
reg [2:0] fifo[fifo_depth-1:0];
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,8,fifo_depth) rfifo (.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in[fifo_width-1:fifo_width-8]),
.dpo(data8_out)
);
always @(posedge clk)
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 1'b0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
fifo[2] <= 0;
fifo[3] <= 0;
fifo[4] <= 0;
fifo[5] <= 0;
fifo[6] <= 0;
fifo[7] <= 0;
fifo[8] <= 0;
fifo[9] <= 0;
fifo[10]<= 0;
fifo[11]<= 0;
fifo[12]<= 0;
fifo[13]<= 0;
fifo[14]<= 0;
fifo[15]<= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 1'b0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
fifo[2] <= 0;
fifo[3] <= 0;
fifo[4] <= 0;
fifo[5] <= 0;
fifo[6] <= 0;
fifo[7] <= 0;
fifo[8] <= 0;
fifo[9] <= 0;
fifo[10]<= 0;
fifo[11]<= 0;
fifo[12]<= 0;
fifo[13]<= 0;
fifo[14]<= 0;
fifo[15]<= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth)
begin
top <= top_plus_1;
fifo[top] <= data_in[2:0];
count <= count + 1'b1;
end
2'b01 : if(count>0)
begin
fifo[bottom] <= 0;
bottom <= bottom + 1'b1;
count <= count - 1'b1;
end
2'b11 : begin
bottom <= bottom + 1'b1;
top <= top_plus_1;
fifo[top] <= data_in[2:0];
end
default: ;
endcase
end
end
always @(posedge clk)
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & ~pop & (count==fifo_depth))
overrun <= 1'b1;
end
assign data_out = {data8_out,fifo[bottom]};
wire [2:0] word0 = fifo[0];
wire [2:0] word1 = fifo[1];
wire [2:0] word2 = fifo[2];
wire [2:0] word3 = fifo[3];
wire [2:0] word4 = fifo[4];
wire [2:0] word5 = fifo[5];
wire [2:0] word6 = fifo[6];
wire [2:0] word7 = fifo[7];
wire [2:0] word8 = fifo[8];
wire [2:0] word9 = fifo[9];
wire [2:0] word10 = fifo[10];
wire [2:0] word11 = fifo[11];
wire [2:0] word12 = fifo[12];
wire [2:0] word13 = fifo[13];
wire [2:0] word14 = fifo[14];
wire [2:0] word15 = fifo[15];
assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
endmodule

76
rtl/ip/APB_UART/URT/uart_sync_flops.v Normal file
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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
module uart_sync_flops
(
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter Tp = 1;
parameter width = 1;
parameter init_value = 1'b0;
input rst_i;
input clk_i;
input stage1_rst_i;
input stage1_clk_en_i;
input [width-1:0] async_dat_i;
output [width-1:0] sync_dat_o;
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
always @ (posedge clk_i)
begin
if (rst_i)
flop_0 <= {width{init_value}};
else
flop_0 <= async_dat_i;
end
always @ (posedge clk_i)
begin
if (rst_i)
sync_dat_o <= {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= flop_0;
end
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "uart_defines.h"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
push,
pop,
overrun,
count,
fifo_reset,
reset_status
);
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo (.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk)
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 1'b0;
count <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 1'b0;
count <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth)
begin
top <= top_plus_1;
count <= count + 1'b1;
end
2'b01 : if(count>0)
begin
bottom <= bottom + 1'b1;
count <= count - 1'b1;
end
2'b11 : begin
bottom <= bottom + 1'b1;
top <= top_plus_1;
end
default: ;
endcase
end
end
always @(posedge clk)
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & (count==fifo_depth))
overrun <= 1'b1;
end
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "uart_defines.h"
module UART_TOP(
PCLK, PRST_,
PSEL, PENABLE, PADDR, PWRITE,
PWDATA, URT_PRDATA,
INT, clk_carrier,
TXD_i, TXD_o, TXD_oe,
RXD_i, RXD_o, RXD_oe,
RTS, CTS, DSR,
DCD, DTR, RI
);
input PCLK, PRST_;
input PSEL, PENABLE, PWRITE;
input [7:0] PADDR;
input [7:0] PWDATA;
output [7:0] URT_PRDATA;
output INT;
input clk_carrier;
input TXD_i;
output TXD_o;
output TXD_oe;
input RXD_i;
output RXD_o;
output RXD_oe;
output RTS;
input CTS, DSR, DCD;
output DTR;
input RI;
wire prst = !PRST_;
wire we = PSEL & PENABLE & PWRITE;
wire re = PSEL & PENABLE & !PWRITE;
wire rx_en;
wire tx2rx_en;
wire isomode;
assign TXD_oe = isomode&&(rx_en||tx2rx_en) ? 1'b1:1'b0;
assign RXD_oe =~isomode;
uart_regs regs(
.clk (PCLK ),
.rst (prst ),
.clk_carrier (clk_carrier),
.addr (PADDR[2:0] ),
.dat_i (PWDATA ),
.dat_o (URT_PRDATA ),
.we (we ),
.re (re ),
.modem_inputs({ CTS, DSR, RI, DCD } ),
.rts_pad_o (RTS ),
.dtr_pad_o (DTR ),
.stx_pad_o (TXD_o ),
.TXD_i (TXD_i ),
.srx_pad_i (RXD_i ),
.RXD_o (RXD_o ),
.int_o ( INT ),
.tx2rx_en (tx2rx_en ),
.rx_en (rx_en ),
.usart_mode (isomode )
);
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "uart_defines.h"
module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i,
enable,stx_pad_o, tstate, tf_count, tx_reset, lsr_mask,
usart_t0,srx_pad_i,repeat_time,max_repeat_time,current_finish,
usart_mode,tx2rx_en);
input clk;
input wb_rst_i;
input [7:0] lcr;
input tf_push;
input [7:0] wb_dat_i;
input enable;
input tx_reset;
input lsr_mask;
input usart_mode;
input usart_t0,srx_pad_i;
input [2:0] repeat_time;
output current_finish;
output max_repeat_time;
output tx2rx_en;
reg tx2rx_en;
output stx_pad_o;
output [2:0] tstate;
output [`UART_FIFO_COUNTER_W-1:0] tf_count;
reg [2:0] tstate;
reg [4:0] counter;
reg [2:0] bit_counter;
reg [6:0] shift_out;
reg stx_o_tmp;
reg parity_xor;
reg tf_pop;
reg bit_out;
reg tx_error;
reg [2:0] error_time;
wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
wire tf_push;
wire tf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0]tf_count;
assign tf_data_in = wb_dat_i;
uart_tfifo fifo_tx(
.clk ( clk ),
.wb_rst_i( wb_rst_i ),
.data_in ( tf_data_in ),
.data_out( tf_data_out ),
.push ( tf_push ),
.pop ( tf_pop ),
.overrun ( tf_overrun ),
.count ( tf_count ),
.fifo_reset ( tx_reset),
.reset_status(lsr_mask )
);
parameter s_idle = 3'd0;
parameter s_send_start = 3'd1;
parameter s_send_byte = 3'd2;
parameter s_send_parity = 3'd3;
parameter s_send_stop = 3'd4;
parameter s_pop_byte = 3'd5;
parameter s_send_guard1 = 3'd6;
reg [7:0]tf_data_bak;
wire max_repeat_time = (error_time==(repeat_time+1'b1)) & usart_mode & usart_t0;
always @(posedge clk )
begin
if (wb_rst_i)
begin
tx_error <= 1'b0;
error_time <= 3'b0;
tstate <= s_idle;
stx_o_tmp <= 1'b1;
counter <= 5'b0;
shift_out <= 7'b0;
bit_out <= 1'b0;
parity_xor <= 1'b0;
tf_pop <= 1'b0;
bit_counter <= 3'b0;
tx2rx_en <= 1'b0;
tf_data_bak <= 8'h0;
end
else
if (enable)
begin
case (tstate)
s_idle :if ((~|tf_count)&(error_time==(repeat_time+1'b1)||~tx_error||~usart_mode))
begin
tstate <= s_idle;
stx_o_tmp <= 1'b1;
tx_error <= 1'b0;
end
else begin
tf_pop <= 1'b0;
stx_o_tmp <= 1'b1;
tstate <= s_pop_byte;
end
s_pop_byte : begin
if(tx_error&(error_time !=(repeat_time+1'b1)))
begin
tf_pop <= 1'b0;
case (lcr[1:0])
2'b00 : begin
bit_counter <= 3'b100;
parity_xor <= ^tf_data_bak[4:0];
end
2'b01 : begin
bit_counter <= 3'b101;
parity_xor <= ^tf_data_bak[5:0];
end
2'b10 : begin
bit_counter <= 3'b110;
parity_xor <= ^tf_data_bak[6:0];
end
2'b11 : begin
bit_counter <= 3'b111;
parity_xor <= ^tf_data_bak[7:0];
end
endcase
{shift_out[6:0], bit_out} <= tf_data_bak;
end
else begin
tf_pop <= 1'b1;
error_time <= 3'h0;
case (lcr[1:0])
2'b00 : begin
bit_counter <= 3'b100;
parity_xor <= ^tf_data_out[4:0];
end
2'b01 : begin
bit_counter <= 3'b101;
parity_xor <= ^tf_data_out[5:0];
end
2'b10 : begin
bit_counter <= 3'b110;
parity_xor <= ^tf_data_out[6:0];
end
2'b11 : begin
bit_counter <= 3'b111;
parity_xor <= ^tf_data_out[7:0];
end
endcase
{shift_out[6:0], bit_out} <= tf_data_out;
tf_data_bak <= tf_data_out;
end
tstate <= s_send_start;
end
s_send_start : begin
tf_pop <= 1'b0;
if (~|counter)
counter <= 5'b01111;
else if (counter == 5'b00001)
begin
counter <= 0;
tstate <= s_send_byte;
end
else
counter <= counter - 1'b1;
stx_o_tmp <= 1'b0;
end
s_send_byte : begin
if (~|counter)
counter <= 5'b01111;
else if (counter == 5'b00001)
begin
if (bit_counter > 3'b0) begin
bit_counter <= bit_counter - 1'b1;
{shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]};
tstate <= s_send_byte;
end
else
if (~lcr[`UART_LC_PE]) begin
tstate <= s_send_stop;
end
else begin
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
2'b00: bit_out <= ~parity_xor;
2'b01: bit_out <= 1'b1;
2'b10: bit_out <= parity_xor;
2'b11: bit_out <= 1'b0;
endcase
tstate <= s_send_parity;
end
counter <= 0;
end
else counter <= counter - 1'b1;
stx_o_tmp <= bit_out;
end
s_send_parity : begin
if (~|counter) counter <= 5'b01111;
else if (counter == 5'b00001) begin
counter <= 4'b0;
tstate <= usart_mode ? s_send_guard1 : s_send_stop;
end
else counter <= counter - 1'b1;
stx_o_tmp <= bit_out;
end
s_send_stop : begin
if (~|counter) begin
if(usart_t0)
counter <= tx_error ? 5'b11101 : 5'b01101;
else
casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
3'b0xx: counter <= 5'b01101;
3'b100: counter <= 5'b10101;
default: counter <= 5'b11101;
endcase
end
else if (counter == 5'b00001) begin
counter <= 5'b0;
tx2rx_en<= 1'b0;
tstate <= s_idle;
end
else counter <= counter - 1'b1;
stx_o_tmp <= 1'b1;
end
s_send_guard1:begin
if (~|counter) begin
tx2rx_en <= 1'b1;
counter <= usart_t0 ? 5'b01111:5'b01101;
end
else if (counter == 5'b00001) begin
counter <= 5'b0;
tx_error <= !srx_pad_i;
error_time<= error_time + !srx_pad_i;
tx2rx_en <= usart_t0 ? 1'b1 : 1'b0;
tstate <= usart_t0 ? s_send_stop : s_idle;
end
else counter <= counter - 1'b1;
stx_o_tmp <= 1'b1;
end
default :
tstate <= s_idle;
endcase
end
else tf_pop <= 1'b0;
end
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp;
assign current_finish = usart_mode ? ( (tstate==3'b0)&(tx_error & (error_time ==repeat_time+1'b1) |~tx_error) ) : 1'b1;
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`define APB_DEV0 6'h00
`define APB_DEV1 6'h1e
module apb_mux2 (
clk,
rst_n,
apb_ack_cpu,
apb_rw_cpu,
apb_psel_cpu,
apb_enab_cpu,
apb_addr_cpu,
apb_datai_cpu,
apb_datao_cpu,
apb_high_24b_rd,
apb_high_24b_wr,
apb_word_trans_cpu,
apb_ready_dma,
apb_rw_dma,
apb_psel_dma,
apb_enab_dma,
apb_addr_dma,
apb_wdata_dma,
apb_rdata_dma,
apb_valid_dma,
apb_valid_cpu,
dma_grant,
apb0_req,
apb0_ack,
apb0_rw,
apb0_psel,
apb0_enab,
apb0_addr,
apb0_datai,
apb0_datao,
apb1_req,
apb1_ack,
apb1_rw,
apb1_psel,
apb1_enab,
apb1_addr,
apb1_datai,
apb1_datao
);
parameter ADDR_APB = 20,
DATA_APB = 8,
DATA_APB_32 = 32;
input clk,rst_n;
output apb_ready_dma;
input apb_rw_dma;
input apb_psel_dma;
input apb_enab_dma;
input [ADDR_APB-1:0] apb_addr_dma;
input [31:0] apb_wdata_dma;
output[31:0] apb_rdata_dma;
output dma_grant;
input apb_valid_dma;
input apb_valid_cpu;
output apb_ack_cpu;
input apb_rw_cpu;
input apb_psel_cpu;
input apb_enab_cpu;
input [ADDR_APB-1:0] apb_addr_cpu;
input [DATA_APB-1:0] apb_datai_cpu;
output[DATA_APB-1:0] apb_datao_cpu;
output [23:0] apb_high_24b_rd;
input [23:0] apb_high_24b_wr;
output apb_word_trans_cpu;
output apb0_req;
input apb0_ack;
output apb0_rw;
output apb0_psel;
output apb0_enab;
output[ADDR_APB-1:0] apb0_addr;
output[DATA_APB-1:0] apb0_datai;
input [DATA_APB-1:0] apb0_datao;
output apb1_req;
input apb1_ack;
output apb1_rw;
output apb1_psel;
output apb1_enab;
output[ADDR_APB-1:0] apb1_addr;
output[31:0] apb1_datai;
input [31:0] apb1_datao;
wire apb_ack;
wire apb_rw;
wire apb_psel;
wire apb_enab;
wire [ADDR_APB-1:0] apb_addr;
wire [DATA_APB-1:0] apb_datai;
wire [23:0]high_24b_wr;
wire [23:0]high_24b_rd;
wire [7:0]apb_datao ;
wire dma_grant;
arb_2_1 arb_2_1(.clk(clk), .rst_n(rst_n), .valid0(apb_valid_cpu), .valid1(apb_valid_dma), .dma_grant(dma_grant));
assign apb_addr = dma_grant ? apb_addr_dma:apb_addr_cpu;
assign apb_rw = dma_grant ? apb_rw_dma:apb_rw_cpu;
assign apb_psel = dma_grant ? apb_psel_dma:apb_psel_cpu;
assign apb_enab = dma_grant ? apb_enab_dma:apb_enab_cpu;
assign apb_datai = dma_grant ? apb_wdata_dma[7:0]:apb_datai_cpu;
assign high_24b_wr = dma_grant ? apb_wdata_dma[31:8]:apb_high_24b_wr;
assign high_24b_rd = apb1_req ? apb1_datao[31:8] : 24'h0;
assign apb_word_trans_cpu = dma_grant ? 1'h0: apb1_req;
assign apb_high_24b_rd = dma_grant ? 24'h0: high_24b_rd;
assign apb_datao_cpu = dma_grant ? 8'h0: apb_datao;
assign apb_rdata_dma = dma_grant ? {high_24b_rd,apb_datao }:32'h0;
assign apb_ack_cpu = ~dma_grant & apb_ack;
assign apb_ready_dma = dma_grant & apb_ack;
assign apb0_req = (apb_addr[ADDR_APB-1:14] ==`APB_DEV0);
//assign apb1_req = (apb_addr[ADDR_APB-1:14] ==`APB_DEV1);
assign apb1_req = !apb0_req;
assign apb0_psel = apb_psel && apb0_req ;
assign apb1_psel = apb_psel && apb1_req;
assign apb0_enab = apb_enab && apb0_req ;
assign apb1_enab = apb_enab && apb1_req;
assign apb_ack = apb0_req ? apb0_ack :
apb1_req ? apb1_ack :
1'b0;
assign apb_datao = apb0_req ? apb0_datao :
apb1_req ? apb1_datao[7:0] :
8'b0;
assign apb0_addr = apb_addr;
assign apb0_datai = apb_datai;
assign apb0_rw = apb_rw;
assign apb1_addr = apb_addr;
assign apb1_datai = {high_24b_wr,apb_datai};
assign apb1_rw = apb_rw;
endmodule
module arb_2_1( clk, rst_n, valid0, valid1, dma_grant);
input clk;
input rst_n;
input valid0;
input valid1;
output dma_grant;
reg dma_grant;
always @(posedge clk)
if(~rst_n)
dma_grant<= 1'b0;
else if(valid0&&~valid1)
dma_grant<= 1'b0;
else if(valid1&&~valid0)
dma_grant<= 1'b1;
else if(valid0&&valid1&&~dma_grant)
dma_grant<= 1'b0;
else if(valid0&&valid1&&dma_grant)
dma_grant<= 1'b1;
else dma_grant<= 1'b0;
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "config.h"
module axi2apb_bridge(
clk,
rst_n,
axi_s_awid,
axi_s_awaddr,
axi_s_awlen,
axi_s_awsize,
axi_s_awburst,
axi_s_awlock,
axi_s_awcache,
axi_s_awprot,
axi_s_awvalid,
axi_s_awready,
axi_s_wid,
axi_s_wdata,
axi_s_wstrb,
axi_s_wlast,
axi_s_wvalid,
axi_s_wready,
axi_s_bid,
axi_s_bresp,
axi_s_bvalid,
axi_s_bready,
axi_s_arid,
axi_s_araddr,
axi_s_arlen,
axi_s_arsize,
axi_s_arburst,
axi_s_arlock,
axi_s_arcache,
axi_s_arprot,
axi_s_arvalid,
axi_s_arready,
axi_s_rid,
axi_s_rdata,
axi_s_rresp,
axi_s_rlast,
axi_s_rvalid,
axi_s_rready,
apb_valid_cpu,
cpu_grant,
apb_word_trans,
apb_high_24b_rd,
apb_high_24b_wr,
apb_clk,
apb_reset_n,
reg_psel,
reg_enable,
reg_rw,
reg_addr,
reg_datai,
reg_ready_1,
reg_datao
);
parameter L_ADDR_APB = 20;
input clk;
input rst_n;
input [`LID :0] axi_s_awid;
input [`Lawaddr -1 :0] axi_s_awaddr;
input [`Lawlen -1 :0] axi_s_awlen;
input [`Lawsize -1 :0] axi_s_awsize;
input [`Lawburst -1 :0] axi_s_awburst;
input [`Lawlock -1 :0] axi_s_awlock;
input [`Lawcache -1 :0] axi_s_awcache;
input [`Lawprot -1 :0] axi_s_awprot;
input axi_s_awvalid;
output axi_s_awready;
input [`LID :0] axi_s_wid;
input [`Lwdata -1 :0] axi_s_wdata;
input [`Lwstrb -1 :0] axi_s_wstrb;
input axi_s_wlast;
input axi_s_wvalid;
output axi_s_wready;
output [`LID :0] axi_s_bid;
output [`Lbresp -1 :0] axi_s_bresp;
output axi_s_bvalid;
input axi_s_bready;
input [`LID :0] axi_s_arid;
input [`Laraddr -1 :0] axi_s_araddr;
input [`Larlen -1 :0] axi_s_arlen;
input [`Larsize -1 :0] axi_s_arsize;
input [`Larburst -1 :0] axi_s_arburst;
input [`Larlock -1 :0] axi_s_arlock;
input [`Larcache -1 :0] axi_s_arcache;
input [`Larprot -1 :0] axi_s_arprot;
input axi_s_arvalid;
output axi_s_arready;
output [`LID :0] axi_s_rid;
output [`Lrdata -1 :0] axi_s_rdata;
output [`Lrresp -1 :0] axi_s_rresp;
output axi_s_rlast;
output axi_s_rvalid;
input axi_s_rready;
input apb_word_trans;
input cpu_grant;
output apb_valid_cpu;
input [23:0] apb_high_24b_rd;
output [23:0] apb_high_24b_wr;
output apb_clk;
output apb_reset_n;
output reg_psel;
output reg_enable;
output reg_rw;
output[L_ADDR_APB-1:0] reg_addr;
output[7:0] reg_datai;
input [7:0] reg_datao;
input reg_ready_1;
wire csr_rw_send_axi_rsp_done;
wire reg_ready;
parameter CSR_RW_SM_IDLE = 4'b0001,
CSR_RW_SM_GET_AXI_ADDR = 4'b0010,
CSR_RW_SM_SEND_AXI_RSP = 4'b1000;
reg reg_psel;
reg reg_enable;
reg axi_s_sel_rd;
reg axi_s_sel_wr;
reg[3:0] csr_rw_sm;
reg[3:0] csr_rw_sm_nxt;
reg[L_ADDR_APB-1:0] axi_s_req_addr;
reg[`LID:0] axi_s_w_id;
reg[`LID:0] axi_s_r_id;
reg[23:0] apb_high_24b_wr;
assign apb_clk = clk;
assign apb_reset_n = rst_n;
assign reg_rw = axi_s_sel_wr;
assign reg_addr = axi_s_req_addr;
assign reg_ready = reg_enable & reg_ready_1;
assign apb_valid_cpu = axi_s_sel_wr | axi_s_sel_rd | axi_s_awvalid | axi_s_arvalid;
reg axi_s_rlast;
reg axi_s_rvalid;
reg axi_s_wready;
reg axi_s_awready;
reg axi_s_arready;
reg [3:0]axi_s_rstrb;
reg [3:0]apb_s_wstrb;
reg [31:0]reg_datai_32;
reg [31:0]reg_datao_32;
reg [2:0] rd_count;
reg [2:0] apb_rd_size;
reg [2:0] apb_wr_size;
reg [7:0] reg_datai;
reg axi_s_bvalid;
always@(posedge clk)
begin
if(!rst_n)
begin
reg_datai_32 <= 32'h0;
reg_datao_32 <= 32'h0;
axi_s_req_addr <= 20'h0;
apb_s_wstrb <= 4'b0;
axi_s_rstrb <= 4'b0;
axi_s_wready <= 1'b0;
reg_enable <= 1'b0;
reg_psel <= 1'b0;
rd_count <= 3'b0;
apb_rd_size <= 3'b0;
apb_wr_size <= 3'b0;
axi_s_rlast <= 1'b0;
axi_s_rvalid <= 1'b0;
reg_datai <= 8'b0;
axi_s_awready <= 1'b0;
axi_s_arready <= 1'b0;
axi_s_bvalid <= 1'b0;
axi_s_sel_wr <= 1'b0;
axi_s_sel_rd <= 1'b0;
axi_s_w_id <= 'h0;
axi_s_r_id <= 'h0;
apb_high_24b_wr <= 24'h0;
end
else begin
if(axi_s_awvalid & ~axi_s_bvalid & ~axi_s_sel_rd & (csr_rw_sm == CSR_RW_SM_IDLE) &cpu_grant) begin
axi_s_req_addr <= axi_s_awaddr[L_ADDR_APB-1:0];
axi_s_awready <= 1'b1;
axi_s_sel_wr <= 1'b1;
apb_wr_size <= axi_s_awsize;
end
else if(axi_s_sel_wr) begin
axi_s_awready <= 1'b0;
if(axi_s_wvalid && ~axi_s_wready) begin
`ifdef AXI128
axi_s_req_addr <= (axi_s_wstrb[15:0]==16'h0002)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h1):
(axi_s_wstrb[15:0]==16'h0004)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h2):
(axi_s_wstrb[15:0]==16'h0008)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h3):
(axi_s_wstrb[15:0]==16'h0010)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'h4):
(axi_s_wstrb[15:0]==16'h0020)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h5):
(axi_s_wstrb[15:0]==16'h0040)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h6):
(axi_s_wstrb[15:0]==16'h0080)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h7):
(axi_s_wstrb[15:0]==16'h0100)&&(axi_s_req_addr[ 3]==1'h0)? (axi_s_req_addr + 4'h8):
(axi_s_wstrb[15:0]==16'h0200)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h9):
(axi_s_wstrb[15:0]==16'h0400)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'ha):
(axi_s_wstrb[15:0]==16'h0800)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hb):
(axi_s_wstrb[15:0]==16'h1000)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'hc):
(axi_s_wstrb[15:0]==16'h2000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hd):
(axi_s_wstrb[15:0]==16'h4000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'he):
(axi_s_wstrb[15:0]==16'h8000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hf):
(axi_s_wstrb[15:0]==16'h0006)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h1):
(axi_s_wstrb[15:0]==16'h000c)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h2):
(axi_s_wstrb[15:0]==16'h0018)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h3):
(axi_s_wstrb[15:0]==16'h0030)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'h4):
(axi_s_wstrb[15:0]==16'h0060)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h5):
(axi_s_wstrb[15:0]==16'h00c0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h6):
(axi_s_wstrb[15:0]==16'h0180)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h7):
(axi_s_wstrb[15:0]==16'h0300)&&(axi_s_req_addr[ 3]==1'h0)? (axi_s_req_addr + 4'h8):
(axi_s_wstrb[15:0]==16'h0600)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h9):
(axi_s_wstrb[15:0]==16'h0c00)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'ha):
(axi_s_wstrb[15:0]==16'h1800)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hb):
(axi_s_wstrb[15:0]==16'h3000)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'hc):
(axi_s_wstrb[15:0]==16'h6000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hd):
(axi_s_wstrb[15:0]==16'hc000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'he):
(axi_s_wstrb[15:0]==16'h001e)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h1):
(axi_s_wstrb[15:0]==16'h003c)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h2):
(axi_s_wstrb[15:0]==16'h0078)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h3):
(axi_s_wstrb[15:0]==16'h00f0)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'h4):
(axi_s_wstrb[15:0]==16'h01e0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h5):
(axi_s_wstrb[15:0]==16'h03c0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h6):
(axi_s_wstrb[15:0]==16'h0780)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h7):
(axi_s_wstrb[15:0]==16'h0f00)&&(axi_s_req_addr[ 3]==1'h0)? (axi_s_req_addr + 4'h8):
(axi_s_wstrb[15:0]==16'h1e00)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h9):
(axi_s_wstrb[15:0]==16'h3c00)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'ha):
(axi_s_wstrb[15:0]==16'h7800)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hb):
(axi_s_wstrb[15:0]==16'hf000)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'hc):
(axi_s_wstrb[15:0]==16'h01fe)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h1):
(axi_s_wstrb[15:0]==16'h03fc)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h2):
(axi_s_wstrb[15:0]==16'h07f8)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h3):
(axi_s_wstrb[15:0]==16'h0ff0)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'h4):
(axi_s_wstrb[15:0]==16'h1fe0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h5):
(axi_s_wstrb[15:0]==16'h3fc0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h6):
(axi_s_wstrb[15:0]==16'h7f80)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h7):
(axi_s_wstrb[15:0]==16'hff00)&&(axi_s_req_addr[ 3]==1'h0)? (axi_s_req_addr + 4'h8): axi_s_req_addr ;
`elsif AXI64
axi_s_req_addr <= (axi_s_wstrb[7:0]==8'h02)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
(axi_s_wstrb[7:0]==8'h04)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2):
(axi_s_wstrb[7:0]==8'h08)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3):
(axi_s_wstrb[7:0]==8'h10)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 2'h4):
(axi_s_wstrb[7:0]==8'h20)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h5):
(axi_s_wstrb[7:0]==8'h40)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h6):
(axi_s_wstrb[7:0]==8'h80)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h7):
(axi_s_wstrb[7:0]==8'h06)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
(axi_s_wstrb[7:0]==8'h0c)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2):
(axi_s_wstrb[7:0]==8'h18)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3):
(axi_s_wstrb[7:0]==8'h30)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 2'h4):
(axi_s_wstrb[7:0]==8'h60)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h5):
(axi_s_wstrb[7:0]==8'hc0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h6):
(axi_s_wstrb[7:0]==8'h1e)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
(axi_s_wstrb[7:0]==8'h3c)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2):
(axi_s_wstrb[7:0]==8'h78)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3):
(axi_s_wstrb[7:0]==8'hf0)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 2'h4): axi_s_req_addr ;
`else
axi_s_req_addr <= (axi_s_wstrb[3:0]==4'h2)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
(axi_s_wstrb[3:0]==4'h4)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2):
(axi_s_wstrb[3:0]==4'h8)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3):
(axi_s_wstrb[3:0]==4'h6)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
(axi_s_wstrb[3:0]==4'hc)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2): axi_s_req_addr ;
`endif
axi_s_wready <= 1'b1;
reg_psel <= 1'b0;
reg_enable <= 1'b0;
axi_s_w_id <= axi_s_wid;
`ifdef AXI128
case({axi_s_req_addr[3:0]})
4'b0000: begin apb_s_wstrb <= axi_s_wstrb[ 3: 0]; reg_datai_32 <=axi_s_wdata[ 31: 0]; end
4'b0001: begin apb_s_wstrb <= axi_s_wstrb[ 4: 1]; reg_datai_32 <=axi_s_wdata[ 39: 8]; end
4'b0010: begin apb_s_wstrb <= axi_s_wstrb[ 5: 2]; reg_datai_32 <=axi_s_wdata[ 47: 16]; end
4'b0011: begin apb_s_wstrb <= axi_s_wstrb[ 6: 3]; reg_datai_32 <=axi_s_wdata[ 55: 24]; end
4'b0100: begin apb_s_wstrb <= axi_s_wstrb[ 7: 4]; reg_datai_32 <=axi_s_wdata[ 63: 32]; end
4'b0101: begin apb_s_wstrb <= axi_s_wstrb[ 8: 5]; reg_datai_32 <=axi_s_wdata[ 71: 40]; end
4'b0110: begin apb_s_wstrb <= axi_s_wstrb[ 9: 6]; reg_datai_32 <=axi_s_wdata[ 79: 48]; end
4'b0111: begin apb_s_wstrb <= axi_s_wstrb[10: 7]; reg_datai_32 <=axi_s_wdata[ 87: 56]; end
4'b1000: begin apb_s_wstrb <= axi_s_wstrb[11: 8]; reg_datai_32 <=axi_s_wdata[ 95: 64]; end
4'b1001: begin apb_s_wstrb <= axi_s_wstrb[12: 9]; reg_datai_32 <=axi_s_wdata[103: 72]; end
4'b1010: begin apb_s_wstrb <= axi_s_wstrb[13:10]; reg_datai_32 <=axi_s_wdata[111: 80]; end
4'b1011: begin apb_s_wstrb <= axi_s_wstrb[14:11]; reg_datai_32 <=axi_s_wdata[119: 88]; end
4'b1100: begin apb_s_wstrb <= axi_s_wstrb[15:12]; reg_datai_32 <=axi_s_wdata[127: 96]; end
4'b1101: begin apb_s_wstrb <= {1'b0, axi_s_wstrb[15:13]}; reg_datai_32 <={ 8'b0, axi_s_wdata[127:104]}; end
4'b1110: begin apb_s_wstrb <= {2'b0, axi_s_wstrb[15:14]}; reg_datai_32 <={16'b0, axi_s_wdata[127:112]}; end
4'b1111: begin apb_s_wstrb <= {3'b0, axi_s_wstrb[ 15]}; reg_datai_32 <={24'b0, axi_s_wdata[127:120]}; end
default: begin apb_s_wstrb <= 4'b0; reg_datai_32 <=32'h0; end
endcase
`elsif AXI64
case({axi_s_req_addr[2:0]})
3'b000: begin apb_s_wstrb <= axi_s_wstrb[3:0]; reg_datai_32 <=axi_s_wdata[31: 0]; end
3'b001: begin apb_s_wstrb <= axi_s_wstrb[4:1]; reg_datai_32 <=axi_s_wdata[39: 8]; end
3'b010: begin apb_s_wstrb <= axi_s_wstrb[5:2]; reg_datai_32 <=axi_s_wdata[47:16]; end
3'b011: begin apb_s_wstrb <= axi_s_wstrb[6:3]; reg_datai_32 <=axi_s_wdata[55:24]; end
3'b100: begin apb_s_wstrb <= axi_s_wstrb[7:4]; reg_datai_32 <=axi_s_wdata[63:32]; end
3'b101: begin apb_s_wstrb <= {1'b0, axi_s_wstrb[7:5]}; reg_datai_32 <={8 'b0, axi_s_wdata[63:40]}; end
3'b110: begin apb_s_wstrb <= {2'b0, axi_s_wstrb[7:6]}; reg_datai_32 <={16'b0, axi_s_wdata[63:48]}; end
3'b111: begin apb_s_wstrb <= {3'b0, axi_s_wstrb[ 7]}; reg_datai_32 <={24'b0, axi_s_wdata[63:56]}; end
default: begin apb_s_wstrb <= 4'b0; reg_datai_32 <=32'h0; end
endcase
`else
case({axi_s_req_addr[1:0]})
2'b00: begin apb_s_wstrb <= axi_s_wstrb[3:0]; reg_datai_32 <=axi_s_wdata[31:0]; end
2'b01: begin apb_s_wstrb <= {1'b0,axi_s_wstrb[3:1]}; reg_datai_32 <={8'h0,axi_s_wdata[31:8]}; end
2'b10: begin apb_s_wstrb <= {2'b0,axi_s_wstrb[3:2]}; reg_datai_32 <={16'b0,axi_s_wdata[31:16]}; end
2'b11: begin apb_s_wstrb <= {3'b0,axi_s_wstrb[3]}; reg_datai_32 <={24'b0,axi_s_wdata[31:24]}; end
default: begin apb_s_wstrb <= 4'b0; reg_datai_32 <=32'h0; end
endcase
`endif
end
else if((~reg_psel) && (apb_s_wstrb!=4'h0) ) begin
reg_psel <= 1'b1;
reg_enable <= 1'b0;
reg_datai <= (apb_s_wstrb == 4'h1) ? reg_datai_32[7:0]:
(apb_s_wstrb == 4'h2) ? reg_datai_32[15:8]:
(apb_s_wstrb == 4'h6) ? reg_datai_32[15:8]:
(apb_s_wstrb == 4'h4) ? reg_datai_32[23:16]:
(apb_s_wstrb == 4'h8) ? reg_datai_32[31:24]: reg_datai_32[7:0];
apb_high_24b_wr <= reg_datai_32[31:8];
if(axi_s_bready) axi_s_bvalid <= 1'b0;
end
else if(apb_word_trans & apb_s_wstrb==4'hf ) begin
if(~reg_ready)begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
else begin
reg_psel <= 1'b0;
reg_enable <= 1'b0;
axi_s_sel_wr <= 1'b0;
axi_s_bvalid <= 1'b1;
apb_s_wstrb <= 4'b0;
end
reg_datai <= reg_datai_32[7:0];
apb_high_24b_wr <= reg_datai_32[31:8];
axi_s_wready <= 1'b0;
end
else if(apb_s_wstrb[0]) begin
if(~reg_ready)begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
reg_datai <= reg_datai_32[7:0];
end
else begin
if(apb_s_wstrb[3:1] ==3'b0)
begin
reg_psel <= 1'b0;
axi_s_sel_wr<= 1'b0;
axi_s_bvalid <= 1'b1;
end
else
reg_psel <= 1'b1;
reg_enable <= 1'b0;
apb_s_wstrb[0] <= 1'b0;
axi_s_req_addr <= axi_s_req_addr +1'b1;
reg_datai <= reg_datai_32[15:8];
end
axi_s_wready <= 1'b0;
end
else if (apb_s_wstrb[1]) begin
if(~reg_ready)begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
else begin
if(apb_s_wstrb[3:2] ==2'b0)
begin
reg_psel <= 1'b0;
axi_s_sel_wr <= 1'b0;
axi_s_bvalid <= 1'b1;
end
else
reg_psel <= 1'b1;
reg_enable <= 1'b0;
apb_s_wstrb[1] <= 1'b0;
axi_s_req_addr <= axi_s_req_addr +1'b1;
reg_datai <= reg_datai_32[23:16];
end
axi_s_wready <= 1'b0;
end
else if (apb_s_wstrb[2]) begin
if(~reg_ready)begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
else begin
if(apb_s_wstrb[3] ==1'b0)
begin
reg_psel <= 1'b0;
axi_s_sel_wr <= 1'b0;
axi_s_bvalid <= 1'b1;
end
else
reg_psel <= 1'b1;
reg_enable <= 1'b0;
apb_s_wstrb[2] <= 1'b0;
axi_s_req_addr <= axi_s_req_addr +1'b1;
reg_datai <= reg_datai_32[31:24];
end
axi_s_wready <= 1'b0;
end
else if (apb_s_wstrb[3]) begin
if(~reg_ready)begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
else begin
reg_psel <= 1'b0;
reg_enable <= 1'b0;
axi_s_sel_wr <= 1'b0;
axi_s_bvalid <= 1'b1;
apb_s_wstrb[3] <= 1'b0;
end
axi_s_wready <= 1'b0;
end
else begin
reg_psel <= 1'b0;
reg_enable <= 1'b0;
reg_datai <= 8'h0;
apb_s_wstrb <= 4'h0;
axi_s_wready <= 1'b0;
if(csr_rw_sm == CSR_RW_SM_IDLE) axi_s_sel_wr <= 1'b0;
end
end
else if(axi_s_arvalid & ~axi_s_arready & ~axi_s_bvalid & (csr_rw_sm == CSR_RW_SM_IDLE)&cpu_grant)
begin
reg_enable <= 1'b0;
reg_psel <= 1'b1;
axi_s_arready <= 1'b1;
axi_s_sel_rd <= 1'b1;
axi_s_r_id <= axi_s_arid;
apb_rd_size <= axi_s_arsize;
axi_s_req_addr <= axi_s_araddr[L_ADDR_APB-1:0];
axi_s_rstrb <= axi_s_araddr[3:0];
if(axi_s_arsize==3'b010)
rd_count<= 3'h4;
else if(axi_s_arsize==3'b01)
rd_count<= 3'h2;
else if(axi_s_arsize==3'b0)
rd_count<= 3'h1;
end
else if(axi_s_sel_rd)
begin
axi_s_arready <= 1'b0;
if(apb_word_trans)
begin
if(reg_ready)
begin
reg_psel <= rd_count==3'b10;
reg_enable <= 1'b0;
rd_count <= rd_count-3'b1;
axi_s_rlast <= apb_rd_size==3'h2|rd_count==2'b1;
axi_s_rvalid <= apb_rd_size==3'h2|rd_count==2'b1;
axi_s_sel_rd <= rd_count==3'b10;
reg_datao_32 <= {apb_high_24b_rd,reg_datao};
end
else begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
end
else if(rd_count==3'h4)
begin
if(reg_ready)
begin
reg_psel <= 1'b1;
reg_enable <= 1'b0;
rd_count <= rd_count-3'h1;
reg_datao_32[7:0] <= reg_datao;
axi_s_req_addr <= axi_s_req_addr +1'b1;
end
else begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
end
else if(rd_count==3'h3)
begin
if(reg_ready)
begin
reg_psel <= 1'b1;
reg_enable <= 1'b0;
rd_count <= rd_count-3'h1;
reg_datao_32[15:8] <= reg_datao;
axi_s_req_addr <= axi_s_req_addr +1'b1;
end
else begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
end
else if(rd_count==3'h2)
begin
if(reg_ready)
begin
reg_psel <= 1'b1;
reg_enable <= 1'b0;
rd_count <= rd_count-3'h1;
axi_s_req_addr <= axi_s_req_addr +1'b1;
if(apb_rd_size==3'h2 )
reg_datao_32[23:16] <= reg_datao;
else if(apb_rd_size==3'h1)
reg_datao_32[7:0] <= reg_datao;
end
else begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
end
else if(rd_count==3'h1)
begin
if(reg_ready)
begin
reg_psel <= 1'b0;
reg_enable <= 1'b0;
axi_s_rlast <= 1'b1;
axi_s_rvalid <= 1'b1;
axi_s_sel_rd <= 1'b0;
if(apb_rd_size==3'h2 )
reg_datao_32[31:24] <= reg_datao;
else if(apb_rd_size==3'h1)
reg_datao_32[15:8] <= reg_datao;
else if(apb_rd_size==3'h0)
reg_datao_32[7:0] <= reg_datao;
end
else begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
end// end if(rd_count)
else begin
axi_s_arready <= 1'b0;
axi_s_rlast <= 1'b1;
axi_s_rvalid <= 1'b1;
reg_psel <= 1'b0;
reg_enable <= 1'b0;
if(axi_s_rvalid && axi_s_rready)
begin
reg_datao_32 <= 32'h0;
axi_s_rlast <= 1'b0;
axi_s_rvalid <= 1'b0;
end
if(csr_rw_sm == CSR_RW_SM_IDLE) axi_s_sel_rd <= 1'b0;
if(axi_s_bready) axi_s_bvalid <= 1'b0;
end
end//end if(axi_s_sel_rd)
else begin
reg_psel <= 1'b0;
reg_enable <= 1'b0;
axi_s_sel_wr <= 1'b0;
axi_s_sel_rd <= 1'b0;
axi_s_wready <= 1'b0;
axi_s_arready <= 1'b0;
axi_s_req_addr <= 32'h0;
reg_datai_32 <= 32'h0;
if(axi_s_bready) axi_s_bvalid <= 1'b0;
if(axi_s_rvalid && axi_s_rready)
begin
reg_datao_32 <= 32'h0;
axi_s_rlast <= 1'b0;
axi_s_rvalid <= 1'b0;
end
end
end//end if(rst_n)
end//end always
assign csr_rw_send_axi_rsp_done = csr_rw_sm == CSR_RW_SM_SEND_AXI_RSP && axi_s_rlast && axi_s_rready || axi_s_bvalid && axi_s_bready;
assign axi_s_bid = axi_s_w_id;
assign axi_s_rid = axi_s_r_id;
assign axi_s_bresp = 2'b00;
assign axi_s_rresp = 2'b00;
`ifdef AXI128
assign axi_s_rdata= ( axi_s_rstrb == 4'h0) ? {96'b0, reg_datao_32 } :
( axi_s_rstrb == 4'h1) ? {88'b0, reg_datao_32, 8'b0 } :
( axi_s_rstrb == 4'h2) ? {80'b0, reg_datao_32, 16'b0 } :
( axi_s_rstrb == 4'h3) ? {72'b0, reg_datao_32, 24'b0 } :
( axi_s_rstrb == 4'h4) ? {64'b0, reg_datao_32, 32'b0 } :
( axi_s_rstrb == 4'h5) ? {56'b0, reg_datao_32, 40'b0 } :
( axi_s_rstrb == 4'h6) ? {48'b0, reg_datao_32, 48'b0 } :
( axi_s_rstrb == 4'h7) ? {40'b0, reg_datao_32, 56'b0 } :
( axi_s_rstrb == 4'h8) ? {32'b0, reg_datao_32, 64'b0 } :
( axi_s_rstrb == 4'h9) ? {24'b0, reg_datao_32, 72'b0 } :
( axi_s_rstrb == 4'ha) ? {16'b0, reg_datao_32, 80'b0 } :
( axi_s_rstrb == 4'hb) ? { 8'b0, reg_datao_32, 88'b0 } :
( axi_s_rstrb == 4'hc) ? {reg_datao_32, 96'b0 } :
( axi_s_rstrb == 4'hd) ? {reg_datao_32[23:0], 104'b0 } :
( axi_s_rstrb == 4'he) ? {reg_datao_32[15:0], 112'b0 } :
( axi_s_rstrb == 4'hf) ? {reg_datao_32[ 7:0], 120'b0 } : 128'h0;
`elsif AXI64
assign axi_s_rdata= ( axi_s_rstrb[2:0] == 3'h0) ? {32'b0, reg_datao_32 } :
( axi_s_rstrb[2:0] == 3'h1) ? {24'b0, reg_datao_32, 8'b0 } :
( axi_s_rstrb[2:0] == 3'h2) ? {16'b0, reg_datao_32, 16'b0 } :
( axi_s_rstrb[2:0] == 3'h3) ? { 8'b0, reg_datao_32, 24'b0 } :
( axi_s_rstrb[2:0] == 3'h4) ? {reg_datao_32, 32'b0 } :
( axi_s_rstrb[2:0] == 3'h5) ? {reg_datao_32[23:0], 40'b0 } :
( axi_s_rstrb[2:0] == 3'h6) ? {reg_datao_32[15:0], 48'b0 } :
( axi_s_rstrb[2:0] == 3'h7) ? {reg_datao_32[ 7:0], 56'b0 } : 64'h0;
`else
assign axi_s_rdata= ( axi_s_rstrb[1:0] == 2'h0) ? { reg_datao_32 } :
( axi_s_rstrb[1:0] == 2'h1) ? {reg_datao_32[23:0], 8'h0} :
( axi_s_rstrb[1:0] == 2'h2) ? {reg_datao_32[15:0],16'h0} :
( axi_s_rstrb[1:0] == 2'h3) ? {reg_datao_32[7:0], 24'h0} : 32'h0;
`endif
always@(csr_rw_sm or axi_s_awvalid or axi_s_arvalid or axi_s_sel_rd or axi_s_sel_wr or
axi_s_wready or csr_rw_send_axi_rsp_done or cpu_grant) begin
case(csr_rw_sm)
CSR_RW_SM_IDLE:
if((axi_s_awvalid || axi_s_arvalid)&&~(axi_s_sel_wr||axi_s_sel_rd)&cpu_grant)
csr_rw_sm_nxt = CSR_RW_SM_GET_AXI_ADDR;
else
csr_rw_sm_nxt = CSR_RW_SM_IDLE;
CSR_RW_SM_GET_AXI_ADDR:
if(axi_s_sel_wr)
csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP;
else if(axi_s_sel_rd)
csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP;
else
csr_rw_sm_nxt = CSR_RW_SM_GET_AXI_ADDR;
CSR_RW_SM_SEND_AXI_RSP:
if(csr_rw_send_axi_rsp_done)
csr_rw_sm_nxt = CSR_RW_SM_IDLE;
else
csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP;
default:
csr_rw_sm_nxt = CSR_RW_SM_IDLE;
endcase
end
always@(posedge clk) begin
if(!rst_n)
csr_rw_sm <= CSR_RW_SM_IDLE;
else
csr_rw_sm <= csr_rw_sm_nxt;
end
endmodule

356
rtl/ip/APB_UART/axi_uart_controller.v Normal file
View File

@@ -0,0 +1,356 @@
/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "config.h"
module axi_uart_controller
(
clk,
rst_n,
axi_s_awid,
axi_s_awaddr,
axi_s_awlen,
axi_s_awsize,
axi_s_awburst,
axi_s_awlock,
axi_s_awcache,
axi_s_awprot,
axi_s_awvalid,
axi_s_awready,
axi_s_wid,
axi_s_wdata,
axi_s_wstrb,
axi_s_wlast,
axi_s_wvalid,
axi_s_wready,
axi_s_bid,
axi_s_bresp,
axi_s_bvalid,
axi_s_bready,
axi_s_arid,
axi_s_araddr,
axi_s_arlen,
axi_s_arsize,
axi_s_arburst,
axi_s_arlock,
axi_s_arcache,
axi_s_arprot,
axi_s_arvalid,
axi_s_arready,
axi_s_rid,
axi_s_rdata,
axi_s_rresp,
axi_s_rlast,
axi_s_rvalid,
axi_s_rready,
apb_rw_dma,
apb_psel_dma,
apb_enab_dma,
apb_addr_dma,
apb_valid_dma,
apb_wdata_dma,
apb_rdata_dma,
apb_ready_dma,
dma_grant,
dma_req_o,
dma_ack_i,
uart0_txd_i,
uart0_txd_o,
uart0_txd_oe,
uart0_rxd_i,
uart0_rxd_o,
uart0_rxd_oe,
uart0_rts_o,
uart0_dtr_o,
uart0_cts_i,
uart0_dsr_i,
uart0_dcd_i,
uart0_ri_i,
uart0_int
);
parameter ADDR_APB = 20,
DATA_APB = 8;
input clk;
input rst_n;
input [`LID :0] axi_s_awid;
input [`Lawaddr -1 :0] axi_s_awaddr;
input [`Lawlen -1 :0] axi_s_awlen;
input [`Lawsize -1 :0] axi_s_awsize;
input [`Lawburst -1 :0] axi_s_awburst;
input [`Lawlock -1 :0] axi_s_awlock;
input [`Lawcache -1 :0] axi_s_awcache;
input [`Lawprot -1 :0] axi_s_awprot;
input axi_s_awvalid;
output axi_s_awready;
input [`LID :0] axi_s_wid;
input [`Lwdata -1 :0] axi_s_wdata;
input [`Lwstrb -1 :0] axi_s_wstrb;
input axi_s_wlast;
input axi_s_wvalid;
output axi_s_wready;
output [`LID :0] axi_s_bid;
output [`Lbresp -1 :0] axi_s_bresp;
output axi_s_bvalid;
input axi_s_bready;
input [`LID :0] axi_s_arid;
input [`Laraddr -1 :0] axi_s_araddr;
input [`Larlen -1 :0] axi_s_arlen;
input [`Larsize -1 :0] axi_s_arsize;
input [`Larburst -1 :0] axi_s_arburst;
input [`Larlock -1 :0] axi_s_arlock;
input [`Larcache -1 :0] axi_s_arcache;
input [`Larprot -1 :0] axi_s_arprot;
input axi_s_arvalid;
output axi_s_arready;
output [`LID :0] axi_s_rid;
output [`Lrdata -1 :0] axi_s_rdata;
output [`Lrresp -1 :0] axi_s_rresp;
output axi_s_rlast;
output axi_s_rvalid;
input axi_s_rready;
output apb_ready_dma;
input apb_rw_dma;
input apb_psel_dma;
input apb_enab_dma;
input [ADDR_APB-1:0] apb_addr_dma;
input [31:0] apb_wdata_dma;
output[31:0] apb_rdata_dma;
input apb_valid_dma;
output dma_grant;
output dma_req_o;
input dma_ack_i;
input uart0_txd_i;
output uart0_txd_o;
output uart0_txd_oe;
input uart0_rxd_i;
output uart0_rxd_o;
output uart0_rxd_oe;
output uart0_rts_o;
output uart0_dtr_o;
input uart0_cts_i;
input uart0_dsr_i;
input uart0_dcd_i;
input uart0_ri_i;
output uart0_int;
assign dma_req_o = 1'b0;
assign nand_dma_ack_i = dma_ack_i;
wire apb_ready_cpu;
wire apb_rw_cpu;
wire apb_psel_cpu;
wire apb_enab_cpu;
wire [ADDR_APB-1 :0] apb_addr_cpu;
wire [DATA_APB-1:0] apb_datai_cpu;
wire [DATA_APB-1:0] apb_datao_cpu;
wire apb_clk_cpu;
wire apb_reset_n_cpu;
wire apb_word_trans_cpu;
wire apb_valid_cpu;
wire dma_grant;
wire [23:0] apb_high_24b_rd;
wire [23:0] apb_high_24b_wr;
wire apb_rw_dma;
wire apb_psel_dma;
wire apb_enab_dma;
wire [31:0] apb_wdata_dma;
wire [31:0] apb_rdata_dma;
wire apb_clk_dma;
wire apb_reset_n_dma;
wire apb_uart0_req;
wire apb_uart0_ack;
wire apb_uart0_rw;
wire apb_uart0_enab;
wire apb_uart0_psel;
wire [ADDR_APB -1:0] apb_uart0_addr;
wire [DATA_APB -1:0] apb_uart0_datai;
wire [DATA_APB -1:0] apb_uart0_datao;
wire apb_nand_req;
wire apb_nand_ack;
wire apb_nand_rw;
wire apb_nand_enab;
wire apb_nand_psel;
wire [ADDR_APB -1:0] apb_nand_addr;
wire [31:0] apb_nand_datai;
wire [31:0] apb_nand_datao;
axi2apb_bridge AA_axi2apb_bridge_cpu
(
.clk (clk ),
.rst_n (rst_n ),
.axi_s_awid (axi_s_awid ),
.axi_s_awaddr (axi_s_awaddr ),
.axi_s_awlen (axi_s_awlen ),
.axi_s_awsize (axi_s_awsize ),
.axi_s_awburst (axi_s_awburst ),
.axi_s_awlock (axi_s_awlock ),
.axi_s_awcache (axi_s_awcache ),
.axi_s_awprot (axi_s_awprot ),
.axi_s_awvalid (axi_s_awvalid ),
.axi_s_awready (axi_s_awready ),
.axi_s_wid (axi_s_wid ),
.axi_s_wdata (axi_s_wdata ),
.axi_s_wstrb (axi_s_wstrb ),
.axi_s_wlast (axi_s_wlast ),
.axi_s_wvalid (axi_s_wvalid ),
.axi_s_wready (axi_s_wready ),
.axi_s_bid (axi_s_bid ),
.axi_s_bresp (axi_s_bresp ),
.axi_s_bvalid (axi_s_bvalid ),
.axi_s_bready (axi_s_bready ),
.axi_s_arid (axi_s_arid ),
.axi_s_araddr (axi_s_araddr ),
.axi_s_arlen (axi_s_arlen ),
.axi_s_arsize (axi_s_arsize ),
.axi_s_arburst (axi_s_arburst ),
.axi_s_arlock (axi_s_arlock ),
.axi_s_arcache (axi_s_arcache ),
.axi_s_arprot (axi_s_arprot ),
.axi_s_arvalid (axi_s_arvalid ),
.axi_s_arready (axi_s_arready ),
.axi_s_rid (axi_s_rid ),
.axi_s_rdata (axi_s_rdata ),
.axi_s_rresp (axi_s_rresp ),
.axi_s_rlast (axi_s_rlast ),
.axi_s_rvalid (axi_s_rvalid ),
.axi_s_rready (axi_s_rready ),
.apb_word_trans (apb_word_trans_cpu ),
.apb_high_24b_rd (apb_high_24b_rd ),
.apb_high_24b_wr (apb_high_24b_wr ),
.apb_valid_cpu (apb_valid_cpu ),
.cpu_grant (~dma_grant ),
.apb_clk (apb_clk_cpu ),
.apb_reset_n (apb_reset_n_cpu ),
.reg_psel (apb_psel_cpu ),
.reg_enable (apb_enab_cpu ),
.reg_rw (apb_rw_cpu ),
.reg_addr (apb_addr_cpu ),
.reg_datai (apb_datai_cpu ),
.reg_datao (apb_datao_cpu ),
.reg_ready_1 (apb_ready_cpu )
);
apb_mux2 u_apb_mux2
(
.clk (clk ),
.rst_n (rst_n ),
.apb_ready_dma (apb_ready_dma ),
.apb_rw_dma (apb_rw_dma ),
.apb_addr_dma (apb_addr_dma ),
.apb_psel_dma (apb_psel_dma ),
.apb_enab_dma (apb_enab_dma ),
.apb_wdata_dma (apb_wdata_dma ),
.apb_rdata_dma (apb_rdata_dma ),
.apb_valid_dma (apb_valid_dma ),
.apb_valid_cpu (apb_valid_cpu ),
.dma_grant (dma_grant ),
.apb_ack_cpu (apb_ready_cpu ),
.apb_rw_cpu (apb_rw_cpu ),
.apb_addr_cpu (apb_addr_cpu ),
.apb_psel_cpu (apb_psel_cpu ),
.apb_enab_cpu (apb_enab_cpu ),
.apb_datai_cpu (apb_datai_cpu ),
.apb_datao_cpu (apb_datao_cpu ),
.apb_high_24b_rd (apb_high_24b_rd),
.apb_high_24b_wr (apb_high_24b_wr),
.apb_word_trans_cpu (apb_word_trans_cpu ),
.apb0_req (apb_uart0_req ),
.apb0_ack (apb_uart0_ack ),
.apb0_rw (apb_uart0_rw ),
.apb0_psel (apb_uart0_psel ),
.apb0_enab (apb_uart0_enab ),
.apb0_addr (apb_uart0_addr ),
.apb0_datai (apb_uart0_datai ),
.apb0_datao (apb_uart0_datao ),
.apb1_req ( ),
.apb1_ack (1'b1 ),
.apb1_rw ( ),
.apb1_enab ( ),
.apb1_psel ( ),
.apb1_addr ( ),
.apb1_datai ( ),
.apb1_datao (32'b0 )
);
//uart0
assign apb_uart0_ack = apb_uart0_enab;
UART_TOP uart0
(
.PCLK (clk ),
.clk_carrier (1'b0 ),
.PRST_ (rst_n ),
.PSEL (apb_uart0_psel ),
.PENABLE (apb_uart0_enab ),
.PADDR (apb_uart0_addr[7:0] ),
.PWRITE (apb_uart0_rw ),
.PWDATA (apb_uart0_datai ),
.URT_PRDATA (apb_uart0_datao ),
.INT (uart0_int ),
.TXD_o (uart0_txd_o ),
.TXD_i (uart0_txd_i ),
.TXD_oe (uart0_txd_oe ),
.RXD_o (uart0_rxd_o ),
.RXD_i (uart0_rxd_i ),
.RXD_oe (uart0_rxd_oe ),
.RTS (uart0_rts_o ),
.CTS (uart0_cts_i ),
.DSR (uart0_dsr_i ),
.DCD (uart0_dcd_i ),
.DTR (uart0_dtr_o ),
.RI (uart0_ri_i )
);
endmodule

6331
rtl/ip/Bus_interconnects/AxiCrossbar_2x8.v Normal file
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1608
rtl/ip/Bus_interconnects/Axi_CDC.v Normal file
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520
rtl/ip/Bus_interconnects/axi2sram_dp.v Normal file
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//+FHDR-----------------------------------------------------------------
// (C) Copyright Loongson Technology Corporation Limited. All rights reserved
// Loongson Confidential Proprietary
//-FHDR-----------------------------------------------------------------
module axi2sram_dp#(
parameter BUS_WIDTH = 32,
parameter DATA_WIDTH = 64,
parameter CPU_WIDTH = 32
)
(
input wire aclk ,
input wire aresetn ,
output wire [BUS_WIDTH-1 :0] ram_raddr,
input wire [DATA_WIDTH-1 :0] ram_rdata,
output wire ram_ren ,
output wire [BUS_WIDTH-1 :0] ram_waddr,
output wire [DATA_WIDTH-1 :0] ram_wdata,
output wire [DATA_WIDTH/8-1 :0] ram_wen ,
input wire [BUS_WIDTH-1 :0] m_araddr ,
input wire [1 :0] m_arburst,
input wire [3 :0] m_arcache,
input wire [4 :0] m_arid ,
input wire [3 :0] m_arlen ,
input wire [1 :0] m_arlock ,
input wire [2 :0] m_arprot ,
output wire m_arready,
input wire [2 :0] m_arsize ,
input wire m_arvalid,
input wire [BUS_WIDTH-1 :0] m_awaddr ,
input wire [1 :0] m_awburst,
input wire [3 :0] m_awcache,
input wire [4 :0] m_awid ,
input wire [3 :0] m_awlen ,
input wire [1 :0] m_awlock ,
input wire [2 :0] m_awprot ,
output wire m_awready,
input wire [2 :0] m_awsize ,
input wire m_awvalid,
output wire [4 :0] m_bid ,
input wire m_bready ,
output wire [1 :0] m_bresp ,
output wire m_bvalid ,
output wire [DATA_WIDTH-1 :0] m_rdata ,
output wire [4 :0] m_rid ,
output wire m_rlast ,
input wire m_rready ,
output wire [1 :0] m_rresp ,
output wire m_rvalid ,
input wire [DATA_WIDTH-1 :0] m_wdata ,
input wire m_wlast ,
output wire m_wready ,
input wire [DATA_WIDTH/8-1 :0] m_wstrb ,
input wire m_wvalid
);
localparam ADDR_INCR_BASE=($clog2(DATA_WIDTH) - 3);
wire [BUS_WIDTH+13-1 :0] ram_r_a_data ;
reg [BUS_WIDTH-1 :0] ram_r_a_data_araddr ;
wire [BUS_WIDTH-1 :0] ram_r_a_data_araddr_fixed ;
wire [BUS_WIDTH-1 :0] ram_r_a_data_araddr_incr ;
wire [BUS_WIDTH-1 :0] ram_r_a_data_araddr_next ;
wire ram_r_a_data_araddr_update ;
wire [BUS_WIDTH-1 :0] ram_r_a_data_araddr_wrap ;
reg [1 :0] ram_r_a_data_arburst ;
wire ram_r_a_data_arburst_fixed ;
wire ram_r_a_data_arburst_incr ;
wire ram_r_a_data_arburst_wrap ;
reg [4 :0] ram_r_a_data_arid ;
reg [3 :0] ram_r_a_data_arlen ;
wire ram_r_a_data_arlen_last ;
reg [2 :0] ram_r_a_data_arsize ;
wire ram_r_a_data_push ;
wire ram_r_a_full ;
wire ram_r_a_pop ;
wire ram_r_a_push ;
wire [BUS_WIDTH+14-1 :0] ram_r_a_push_data ;
reg [BUS_WIDTH+14-1 :0] ram_r_a_queue_datas ;
wire [BUS_WIDTH-1 :0] ram_r_a_queue_datas_araddr ;
wire [1 :0] ram_r_a_queue_datas_arburst;
wire [4 :0] ram_r_a_queue_datas_arid ;
wire [3 :0] ram_r_a_queue_datas_arlen ;
wire [2 :0] ram_r_a_queue_datas_arsize ;
wire ram_r_a_queue_empty ;
wire ram_r_a_queue_full ;
wire ram_r_a_queue_pop ;
wire ram_r_a_queue_push ;
reg ram_r_a_queue_valid ;
reg ram_r_a_valid ;
wire [BUS_WIDTH-1 :0] ram_r_addr ;
wire ram_r_allow_out ;
wire [DATA_WIDTH-1 :0] ram_r_data ;
wire ram_r_en ;
reg [3 :0] ram_r_rcur ;
wire ram_r_rcur_reset ;
reg [4 :0] ram_r_rid ;
reg ram_r_rlast ;
reg ram_r_rvalid ;
wire [BUS_WIDTH+13-1 :0] ram_w_a_data ;
reg [BUS_WIDTH-1 :0] ram_w_a_data_awaddr ;
wire [BUS_WIDTH-1 :0] ram_w_a_data_awaddr_fixed ;
wire [BUS_WIDTH-1 :0] ram_w_a_data_awaddr_incr ;
wire [BUS_WIDTH-1 :0] ram_w_a_data_awaddr_next ;
wire ram_w_a_data_awaddr_update ;
wire [BUS_WIDTH-1 :0] ram_w_a_data_awaddr_wrap ;
reg [1 :0] ram_w_a_data_awburst ;
wire ram_w_a_data_awburst_fixed ;
wire ram_w_a_data_awburst_incr ;
wire ram_w_a_data_awburst_wrap ;
reg [4 :0] ram_w_a_data_awid ;
reg [3 :0] ram_w_a_data_awlen ;
reg [2 :0] ram_w_a_data_awsize ;
wire ram_w_a_data_push ;
wire ram_w_a_full ;
wire ram_w_a_pop ;
wire ram_w_a_push ;
wire [BUS_WIDTH+14-1 :0] ram_w_a_push_data ;
reg [BUS_WIDTH+14-1 :0] ram_w_a_queue_datas ;
wire [BUS_WIDTH-1 :0] ram_w_a_queue_datas_awaddr ;
wire [1 :0] ram_w_a_queue_datas_awburst;
wire [4 :0] ram_w_a_queue_datas_awid ;
wire [3 :0] ram_w_a_queue_datas_awlen ;
wire [2 :0] ram_w_a_queue_datas_awsize ;
wire ram_w_a_queue_empty ;
wire ram_w_a_queue_full ;
wire ram_w_a_queue_pop ;
wire ram_w_a_queue_push ;
reg ram_w_a_queue_valid ;
reg ram_w_a_valid ;
wire [BUS_WIDTH-1 :0] ram_w_addr ;
wire ram_w_allow_out ;
reg [4 :0] ram_w_b_data ;
wire ram_w_b_data_push ;
wire ram_w_b_full ;
wire ram_w_b_pop ;
wire ram_w_b_push ;
reg [4 :0] ram_w_b_queue_datas ;
wire ram_w_b_queue_empty ;
wire ram_w_b_queue_full ;
wire ram_w_b_queue_pop ;
wire ram_w_b_queue_push ;
reg ram_w_b_queue_valid ;
reg ram_w_b_valid ;
wire ram_w_en ;
wire ram_w_go ;
wire [DATA_WIDTH/8-1 :0] ram_w_strb ;
reg [DATA_WIDTH-1 :0] ram_w_wdata ;
reg ram_w_wlast ;
reg [DATA_WIDTH/8-1 :0] ram_w_wstrb ;
reg ram_w_wvalid ;
assign m_arready = !ram_r_a_full;
assign m_awready = !ram_w_a_full;
assign m_bid = ram_w_b_data;
assign m_bresp = 2'h0;
assign m_bvalid = ram_w_b_valid;
assign m_rdata = ram_rdata ;
assign m_rid = ram_r_rid ;
assign m_rlast = ram_r_rlast ;
assign m_rresp = 2'h0;
assign m_rvalid = ram_r_rvalid;
assign m_wready = ram_w_allow_out || !ram_w_wvalid;
assign ram_r_a_data = {ram_r_a_data_arburst,ram_r_a_data_arsize,ram_r_a_data_arlen,ram_r_a_data_araddr,ram_r_a_data_arid};
assign ram_r_a_data_araddr_fixed = ram_r_a_data_araddr;
assign ram_r_a_data_araddr_incr [ADDR_INCR_BASE-1:0] = ram_r_a_data_araddr[ADDR_INCR_BASE-1:0];
assign ram_r_a_data_araddr_incr [BUS_WIDTH-1 :ADDR_INCR_BASE ] = ram_r_a_data_araddr[BUS_WIDTH-1:ADDR_INCR_BASE] + {{BUS_WIDTH-ADDR_INCR_BASE-1{1'b0}},1'b1};
assign ram_r_a_data_araddr_next = {BUS_WIDTH{ram_r_a_data_arburst_fixed}} & ram_r_a_data_araddr_fixed
| {BUS_WIDTH{ram_r_a_data_arburst_incr }} & ram_r_a_data_araddr_incr
| {BUS_WIDTH{ram_r_a_data_arburst_wrap }} & ram_r_a_data_araddr_wrap ;
assign ram_r_a_data_araddr_update = ram_r_en && !ram_r_a_data_arlen_last;
assign ram_r_a_data_araddr_wrap [ADDR_INCR_BASE-1 :0] = ram_r_a_data_araddr[ADDR_INCR_BASE-1 :0];
assign ram_r_a_data_araddr_wrap [BUS_WIDTH-1:ADDR_INCR_BASE+4] = ram_r_a_data_araddr[BUS_WIDTH-1:ADDR_INCR_BASE+4];
assign ram_r_a_data_araddr_wrap [ADDR_INCR_BASE+3 :ADDR_INCR_BASE] = ram_r_a_data_araddr[ADDR_INCR_BASE+3:ADDR_INCR_BASE] & ~ram_r_a_data_arlen | ram_r_a_data_arlen & ram_r_a_data_araddr[ADDR_INCR_BASE+3:ADDR_INCR_BASE] + 4'h1;
assign ram_r_a_data_arburst_fixed = ram_r_a_data_arburst == 2'h0;
assign ram_r_a_data_arburst_incr = ram_r_a_data_arburst == 2'h1;
assign ram_r_a_data_arburst_wrap = ram_r_a_data_arburst == 2'h2;
assign ram_r_a_data_arlen_last = ram_r_a_data_arlen == ram_r_rcur;
assign ram_r_a_data_push = ram_r_a_push && (ram_r_a_pop || !ram_r_a_valid);
assign ram_r_a_full = ram_r_a_queue_full;
assign ram_r_a_pop = ram_r_en && ram_r_a_data_arlen_last;
assign ram_r_a_push = m_arvalid && !ram_r_a_full ;
//assign ram_r_a_push_data = {m_arburst,m_arsize ,m_arlen,m_araddr,m_arid};
assign ram_r_a_push_data = {m_araddr,m_arburst,m_arsize,m_arlen,m_arid};
assign ram_r_a_queue_datas_araddr = ram_r_a_queue_datas[BUS_WIDTH-1+14:14];
assign ram_r_a_queue_datas_arburst = ram_r_a_queue_datas[13 :12];
assign ram_r_a_queue_datas_arid = ram_r_a_queue_datas[4 : 0];
assign ram_r_a_queue_datas_arlen = ram_r_a_queue_datas[8 : 5];
assign ram_r_a_queue_datas_arsize = ram_r_a_queue_datas[11 : 9];
assign ram_r_a_queue_empty = !ram_r_a_queue_valid;
assign ram_r_a_queue_full = ram_r_a_queue_valid;
assign ram_r_a_queue_pop = ram_r_a_pop && !ram_r_a_queue_empty;
assign ram_r_a_queue_push = ram_r_a_push && ram_r_a_valid && !ram_r_a_pop && !ram_r_a_queue_full;
assign ram_r_addr = ram_r_a_data_araddr;
assign ram_r_allow_out = m_rready || !m_rvalid;
assign ram_r_data = ram_rdata;
assign ram_r_en = ram_r_a_valid && ram_r_allow_out;
assign ram_r_rcur_reset = !aresetn || ram_r_a_pop;
assign ram_w_a_data = {ram_w_a_data_awaddr,ram_w_a_data_awburst,ram_w_a_data_awsize ,ram_w_a_data_awlen,ram_w_a_data_awid};
assign ram_w_a_data_awaddr_fixed = ram_w_a_data_awaddr;
assign ram_w_a_data_awaddr_incr [ADDR_INCR_BASE-1 :0] = ram_w_a_data_awaddr[ADDR_INCR_BASE-1:0];
assign ram_w_a_data_awaddr_incr [BUS_WIDTH-1:ADDR_INCR_BASE] = ram_w_a_data_awaddr[BUS_WIDTH-1:ADDR_INCR_BASE] + {{BUS_WIDTH-ADDR_INCR_BASE-1{1'b0}},1'b1};
assign ram_w_a_data_awaddr_next = {BUS_WIDTH{ram_w_a_data_awburst_fixed}} & ram_w_a_data_awaddr_fixed
| {BUS_WIDTH{ram_w_a_data_awburst_incr }} & ram_w_a_data_awaddr_incr
| {BUS_WIDTH{ram_w_a_data_awburst_wrap }} & ram_w_a_data_awaddr_wrap ;
assign ram_w_a_data_awaddr_update = ram_w_en && !ram_w_wlast;
assign ram_w_a_data_awaddr_wrap [ADDR_INCR_BASE-1 :0] = ram_w_a_data_awaddr[ADDR_INCR_BASE-1 :0];
assign ram_w_a_data_awaddr_wrap [BUS_WIDTH-1:ADDR_INCR_BASE+4] = ram_w_a_data_awaddr[BUS_WIDTH-1:ADDR_INCR_BASE+4];
assign ram_w_a_data_awaddr_wrap [ADDR_INCR_BASE+3:ADDR_INCR_BASE] = ram_w_a_data_awaddr[ADDR_INCR_BASE+3:ADDR_INCR_BASE] & ~ram_w_a_data_awlen | ram_w_a_data_awlen & ram_w_a_data_awaddr[ADDR_INCR_BASE+3:ADDR_INCR_BASE] + 4'h1;
assign ram_w_a_data_awburst_fixed = ram_w_a_data_awburst == 2'h0;
assign ram_w_a_data_awburst_incr = ram_w_a_data_awburst == 2'h1;
assign ram_w_a_data_awburst_wrap = ram_w_a_data_awburst == 2'h2;
assign ram_w_a_data_push = ram_w_a_push && (ram_w_a_pop || !ram_w_a_valid);
assign ram_w_a_full = ram_w_a_queue_full;
assign ram_w_a_pop = ram_w_en && ram_w_wlast ;
assign ram_w_a_push = m_awvalid && !ram_w_a_full;
assign ram_w_a_push_data = {m_awaddr,m_awburst,m_awsize ,m_awlen,m_awid};
assign ram_w_a_queue_datas_awaddr = ram_w_a_queue_datas[BUS_WIDTH-1+14:14];
assign ram_w_a_queue_datas_awburst = ram_w_a_queue_datas[13 :12];
assign ram_w_a_queue_datas_awid = ram_w_a_queue_datas[4 : 0];
assign ram_w_a_queue_datas_awlen = ram_w_a_queue_datas[8 : 5];
assign ram_w_a_queue_datas_awsize = ram_w_a_queue_datas[11 : 9];
assign ram_w_a_queue_empty = !ram_w_a_queue_valid;
assign ram_w_a_queue_full = ram_w_a_queue_valid;
assign ram_w_a_queue_pop = ram_w_a_pop && !ram_w_a_queue_empty;
assign ram_w_a_queue_push = ram_w_a_push && ram_w_a_valid && !ram_w_a_pop && !ram_w_a_queue_full;
assign ram_w_addr = ram_w_a_data_awaddr;
assign ram_w_allow_out = ram_w_a_valid && !ram_w_b_full;
assign ram_w_b_data_push = ram_w_b_push && (ram_w_b_pop || !ram_w_b_valid);
assign ram_w_b_full = ram_w_b_queue_full;
assign ram_w_b_pop = m_bready && ram_w_b_valid;
assign ram_w_b_push = ram_w_a_pop ;
assign ram_w_b_queue_empty = !ram_w_b_queue_valid;
assign ram_w_b_queue_full = ram_w_b_queue_valid;
assign ram_w_b_queue_pop = ram_w_b_pop && !ram_w_b_queue_empty;
assign ram_w_b_queue_push = ram_w_b_push && ram_w_b_valid && !ram_w_b_pop && !ram_w_b_queue_full;
assign ram_w_en = ram_w_wvalid && ram_w_allow_out && aresetn;
assign ram_w_go = m_wvalid && m_wready;
assign ram_w_strb = ram_w_wstrb;
assign ram_raddr = ram_r_addr ;
assign ram_ren = ram_r_en ;
assign ram_waddr = ram_w_addr ;
assign ram_wdata = ram_w_wdata;
assign ram_wen = ram_w_strb & {DATA_WIDTH/8{ram_w_en}};
always@(posedge aclk)
begin
if(ram_r_rcur_reset)
begin
ram_r_rcur<=4'h0;
end
else
if(ram_r_en)
begin
ram_r_rcur<=ram_r_rcur + 4'h1;
end
end
always@(posedge aclk)
begin
if(ram_r_en)
begin
ram_r_rid<=ram_r_a_data_arid;
end
end
always@(posedge aclk)
begin
if(ram_r_en)
begin
ram_r_rlast<=ram_r_a_data_arlen_last;
end
end
always@(posedge aclk)
begin
if(!aresetn)
begin
ram_r_rvalid<=1'h0;
end
else
if(ram_r_en)
begin
ram_r_rvalid<=1'h1;
end
else
if(m_rready)
begin
ram_r_rvalid<=1'h0;
end
end
always@(posedge aclk)
begin
if(!aresetn)
begin
ram_r_a_valid<=1'h0;
end
else
if(ram_r_a_push)
begin
ram_r_a_valid<=1'h1;
end
else
if(ram_r_a_pop)
begin
ram_r_a_valid<=ram_r_a_queue_valid;
end
end
always@(posedge aclk)
begin
if(!aresetn)
begin
ram_r_a_queue_valid<=1'h0;
end
else
if(ram_r_a_queue_push)
begin
ram_r_a_queue_valid<=1'h1;
end
else
if(ram_r_a_queue_pop)
begin
ram_r_a_queue_valid<=1'h0;
end
end
always@(posedge aclk)
begin
if(ram_r_a_queue_push)
begin
ram_r_a_queue_datas<=ram_r_a_push_data;
end
end
always@(posedge aclk)
begin
if(ram_r_a_data_push)
begin
ram_r_a_data_arburst<=m_arburst;
ram_r_a_data_arid <=m_arid ;
ram_r_a_data_arlen <=m_arlen ;
ram_r_a_data_arsize <=m_arsize ;
end
else
if(ram_r_a_pop)
begin
ram_r_a_data_arburst<=ram_r_a_queue_datas_arburst;
ram_r_a_data_arid <=ram_r_a_queue_datas_arid ;
ram_r_a_data_arlen <=ram_r_a_queue_datas_arlen ;
ram_r_a_data_arsize <=ram_r_a_queue_datas_arsize ;
end
end
always@(posedge aclk)
begin
if(ram_r_a_data_push)
begin
ram_r_a_data_araddr<=m_araddr;
end
else
if(ram_r_a_pop)
begin
ram_r_a_data_araddr<=ram_r_a_queue_datas_araddr;
end
else
begin
if(ram_r_a_data_araddr_update)
begin
ram_r_a_data_araddr<=ram_r_a_data_araddr_next;
end
end
end
always@(posedge aclk)
begin
if(ram_w_go)
begin
ram_w_wdata<=m_wdata;
ram_w_wlast<=m_wlast;
ram_w_wstrb<=m_wstrb;
end
end
always@(posedge aclk)
begin
if(!aresetn)
begin
ram_w_wvalid<=1'h0;
end
else
if(ram_w_go)
begin
ram_w_wvalid<=1'h1;
end
else
if(ram_w_en)
begin
ram_w_wvalid<=1'h0;
end
end
always@(posedge aclk)
begin
if(!aresetn)
begin
ram_w_a_valid<=1'h0;
end
else
if(ram_w_a_push)
begin
ram_w_a_valid<=1'h1;
end
else
if(ram_w_a_pop)
begin
ram_w_a_valid<=ram_w_a_queue_valid;
end
end
always@(posedge aclk)
begin
if(!aresetn)
begin
ram_w_a_queue_valid<=1'h0;
end
else
if(ram_w_a_queue_push)
begin
ram_w_a_queue_valid<=1'h1;
end
else
if(ram_w_a_queue_pop)
begin
ram_w_a_queue_valid<=1'h0;
end
end
always@(posedge aclk)
begin
if(ram_w_a_queue_push)
begin
ram_w_a_queue_datas<=ram_w_a_push_data;
end
end
always@(posedge aclk)
begin
if(ram_w_a_data_push)
begin
ram_w_a_data_awburst<=m_awburst;
ram_w_a_data_awid <=m_awid ;
ram_w_a_data_awlen <=m_awlen ;
ram_w_a_data_awsize <=m_awsize ;
end
else
if(ram_w_a_pop)
begin
ram_w_a_data_awburst<=ram_w_a_queue_datas_awburst;
ram_w_a_data_awid <=ram_w_a_queue_datas_awid ;
ram_w_a_data_awlen <=ram_w_a_queue_datas_awlen ;
ram_w_a_data_awsize <=ram_w_a_queue_datas_awsize ;
end
end
always@(posedge aclk)
begin
if(ram_w_a_data_push)
begin
ram_w_a_data_awaddr<=m_awaddr;
end
else
if(ram_w_a_pop)
begin
ram_w_a_data_awaddr<=ram_w_a_queue_datas_awaddr;
end
else
begin
if(ram_w_a_data_awaddr_update)
begin
ram_w_a_data_awaddr<=ram_w_a_data_awaddr_next;
end
end
end
always@(posedge aclk)
begin
if(!aresetn)
begin
ram_w_b_valid<=1'h0;
end
else
if(ram_w_b_push)
begin
ram_w_b_valid<=1'h1;
end
else
if(ram_w_b_pop)
begin
ram_w_b_valid<=ram_w_b_queue_valid;
end
end
always@(posedge aclk)
begin
if(!aresetn)
begin
ram_w_b_queue_valid<=1'h0;
end
else
if(ram_w_b_queue_push)
begin
ram_w_b_queue_valid<=1'h1;
end
else
if(ram_w_b_queue_pop)
begin
ram_w_b_queue_valid<=1'h0;
end
end
always@(posedge aclk)
begin
if(ram_w_b_queue_push)
begin
ram_w_b_queue_datas<=ram_w_a_data_awid;
end
end
always@(posedge aclk)
begin
if(ram_w_b_data_push)
begin
ram_w_b_data<=ram_w_a_data_awid;
end
else
if(ram_w_b_pop)
begin
ram_w_b_data<=ram_w_b_queue_datas;
end
end
endmodule // soc_axi_sram_bridge

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// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// ----------------------------
// AXI to SRAM Adapter
// ----------------------------
// Author: Florian Zaruba (zarubaf@iis.ee.ethz.ch)
//
// Description: Manages AXI transactions
// Supports all burst accesses but only on aligned addresses and with full data width.
// Assertions should guide you if there is something unsupported happening.
//
module axi2sram_sp #(
parameter AXI_ID_WIDTH = 5,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_DATA_WIDTH = 32
)(
input clk,
input resetn,
input [AXI_ADDR_WIDTH-1:0] s_araddr ,
input [1 :0] s_arburst,
input [3 :0] s_arcache,
input [AXI_ID_WIDTH-1 :0] s_arid ,
input [3 :0] s_arlen ,
input [1 :0] s_arlock ,
input [2 :0] s_arprot ,
output reg s_arready,
input [2 :0] s_arsize ,
input s_arvalid,
input [AXI_ADDR_WIDTH-1:0] s_awaddr ,
input [1 :0] s_awburst,
input [3 :0] s_awcache,
input [AXI_ID_WIDTH :0] s_awid ,
input [3 :0] s_awlen ,
input [1 :0] s_awlock ,
input [2 :0] s_awprot ,
output reg s_awready,
input [2 :0] s_awsize ,
input s_awvalid,
output reg [AXI_ID_WIDTH-1 :0] s_bid ,
input s_bready ,
output reg [1 :0] s_bresp ,
output reg s_bvalid ,
output reg [AXI_DATA_WIDTH-1:0] s_rdata ,
output reg [AXI_ID_WIDTH :0] s_rid ,
output reg s_rlast ,
input s_rready ,
output reg [1 :0] s_rresp ,
output reg s_rvalid ,
input [AXI_DATA_WIDTH-1:0] s_wdata ,
input s_wlast ,
output reg s_wready ,
input [AXI_DATA_WIDTH/8-1:0] s_wstrb ,
input s_wvalid ,
output reg req_o,
output reg we_o,
output reg [AXI_ADDR_WIDTH-1:0] addr_o,
output reg [AXI_DATA_WIDTH/8-1:0] be_o,
output reg [AXI_DATA_WIDTH-1:0] data_o,
input [AXI_DATA_WIDTH-1:0] data_i
);
// AXI has the following rules governing the use of bursts:
// - for wrapping bursts, the burst length must be 2, 4, 8, or 16
// - a burst must not cross a 4KB address boundary
// - early termination of bursts is not supported.
localparam LOG_NR_BYTES = $clog2(AXI_DATA_WIDTH/8);
reg [AXI_ID_WIDTH-1:0] ax_req_d_id;
reg [AXI_ADDR_WIDTH-1:0] ax_req_d_addr;
reg [7:0] ax_req_d_len;
reg [2:0] ax_req_d_size;
reg [1:0] ax_req_d_burst;
reg [AXI_ID_WIDTH-1:0] ax_req_q_id;
reg [AXI_ADDR_WIDTH-1:0] ax_req_q_addr;
reg [7:0] ax_req_q_len;
reg [2:0] ax_req_q_size;
reg [1:0] ax_req_q_burst;
reg [2:0] state_d;
reg [2:0] state_q;
localparam IDLE = 3'h0;
localparam READ = 3'h1;
localparam WRITE = 3'h2;
localparam SEND_B = 3'h3;
localparam WAIT_WVALID = 3'h4;
localparam FIXED = 2'b00;
localparam INCR = 2'b01;
localparam WRAP = 2'b10;
reg [AXI_ADDR_WIDTH-1:0] req_addr_d, req_addr_q;
reg [7:0] cnt_d, cnt_q;
function automatic [AXI_ADDR_WIDTH-1:0] get_wrap_boundary;
input [AXI_ADDR_WIDTH-1:0] unaligned_address;
input [7:0] len;
begin
get_wrap_boundary = 'h0;
// for wrapping transfers ax_len can only be of size 1, 3, 7 or 15
if (len == 4'b1)
get_wrap_boundary[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES];
else if (len == 4'b11)
get_wrap_boundary[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES];
else if (len == 4'b111)
get_wrap_boundary[AXI_ADDR_WIDTH-1:3+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:2+LOG_NR_BYTES];
else if (len == 4'b1111)
get_wrap_boundary[AXI_ADDR_WIDTH-1:4+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:4+LOG_NR_BYTES];
end
endfunction
reg [AXI_ADDR_WIDTH-1:0] aligned_address;
reg [AXI_ADDR_WIDTH-1:0] wrap_boundary;
reg [AXI_ADDR_WIDTH-1:0] upper_wrap_boundary;
reg [AXI_ADDR_WIDTH-1:0] cons_addr;
always @ (*) begin
// address generation
aligned_address = {ax_req_q_addr[AXI_ADDR_WIDTH-1:LOG_NR_BYTES], {{LOG_NR_BYTES}{1'b0}}};
wrap_boundary = get_wrap_boundary(ax_req_q_addr, ax_req_q_len);
// this will overflow
upper_wrap_boundary = wrap_boundary + ((ax_req_q_len + 1) << LOG_NR_BYTES);
// calculate consecutive address
cons_addr = aligned_address + (cnt_q << LOG_NR_BYTES);
// Transaction attributes
// default assignments
state_d = state_q;
ax_req_d_id = ax_req_q_id;
ax_req_d_addr = ax_req_q_addr;
ax_req_d_len = ax_req_q_len;
ax_req_d_size = ax_req_q_size;
ax_req_d_burst = ax_req_q_burst;
req_addr_d = req_addr_q;
cnt_d = cnt_q;
// Memory default assignments
data_o = s_wdata;
be_o = s_wstrb;
we_o = 1'b0;
req_o = 1'b0;
addr_o = 'h0;
// AXI assignments
// request
s_awready = 1'b0;
s_arready = 1'b0;
// read response channel
s_rvalid = 1'b0;
s_rdata = data_i;
s_rresp = 'h0;
s_rlast = 'h0;
s_rid = ax_req_q_id;
// slave write data channel
s_wready = 1'b0;
// write response channel
s_bvalid = 1'b0;
s_bresp = 1'b0;
s_bid = 1'b0;
case (state_q)
IDLE: begin
// Wait for a read or write
// ------------
// Read
// ------------
if (s_arvalid) begin
s_arready = 1'b1;
// sample ax
ax_req_d_id = s_arid;
ax_req_d_addr = s_araddr;
ax_req_d_len = s_arlen;
ax_req_d_size = s_arsize;
ax_req_d_burst = s_arburst;
state_d = READ;
// we can request the first address, this saves us time
req_o = 1'b1;
addr_o = s_araddr;
// save the address
req_addr_d = s_araddr;
// save the ar_len
cnt_d = 1;
// ------------
// Write
// ------------
end else if (s_awvalid) begin
s_awready = 1'b1;
s_wready = 1'b1;
addr_o = s_awaddr;
// sample ax
ax_req_d_id = s_awid;
ax_req_d_addr = s_awaddr;
ax_req_d_len = s_awlen;
ax_req_d_size = s_awsize;
ax_req_d_burst = s_awburst;
// we've got our first w_valid so start the write process
if (s_wvalid) begin
req_o = 1'b1;
we_o = 1'b1;
state_d = (s_wlast) ? SEND_B : WRITE;
cnt_d = 1;
// we still have to wait for the first w_valid to arrive
end else
state_d = WAIT_WVALID;
end
end
// ~> we are still missing a w_valid
WAIT_WVALID: begin
s_wready = 1'b1;
addr_o = ax_req_q_addr;
// we can now make our first request
if (s_wvalid) begin
req_o = 1'b1;
we_o = 1'b1;
state_d = (s_wlast) ? SEND_B : WRITE;
cnt_d = 1;
end
end
READ: begin
// keep request to memory high
req_o = 1'b1;
addr_o = req_addr_q;
// send the response
s_rvalid = 1'b1;
s_rdata = data_i;
s_rid = ax_req_q_id;
s_rlast = (cnt_q == ax_req_q_len + 1);
// check that the master is ready, the slave must not wait on this
if (s_rready) begin
// ----------------------------
// Next address generation
// ----------------------------
// handle the correct burst type
case (ax_req_q_burst)
FIXED, INCR: addr_o = cons_addr;
WRAP: begin
// check if the address reached warp boundary
if (cons_addr == upper_wrap_boundary) begin
addr_o = wrap_boundary;
// address warped beyond boundary
end else if (cons_addr > upper_wrap_boundary) begin
addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
// we are still in the incremental regime
end else begin
addr_o = cons_addr;
end
end
endcase
// we need to change the address here for the upcoming request
// we sent the last byte -> go back to idle
if (s_rlast) begin
state_d = IDLE;
// we already got everything
req_o = 1'b0;
end
// save the request address for the next cycle
req_addr_d = addr_o;
// we can decrease the counter as the master has consumed the read data
cnt_d = cnt_q + 1;
// TODO: configure correct byte-lane
end
end
// ~> we already wrote the first word here
WRITE: begin
s_wready = 1'b1;
// consume a word here
if (s_wvalid) begin
req_o = 1'b1;
we_o = 1'b1;
// ----------------------------
// Next address generation
// ----------------------------
// handle the correct burst type
case (ax_req_q_burst)
FIXED, INCR: addr_o = cons_addr;
WRAP: begin
// check if the address reached warp boundary
if (cons_addr == upper_wrap_boundary) begin
addr_o = wrap_boundary;
// address warped beyond boundary
end else if (cons_addr > upper_wrap_boundary) begin
addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
// we are still in the incremental regime
end else begin
addr_o = cons_addr;
end
end
endcase
// save the request address for the next cycle
req_addr_d = addr_o;
// we can decrease the counter as the master has consumed the read data
cnt_d = cnt_q + 1;
if (s_wlast)
state_d = SEND_B;
end
end
// ~> send a write acknowledge back
SEND_B: begin
s_bvalid = 1'b1;
s_bid = ax_req_q_id;
if (s_bready)
state_d = IDLE;
end
endcase
end
// --------------
// Registers
// --------------
always @(posedge clk or negedge resetn) begin
if (~resetn) begin
state_q <= IDLE;
ax_req_q_addr <= 32'h0;
ax_req_q_burst <= 2'h0;
ax_req_q_id <= 'h0;
ax_req_q_len <= 8'h0;
ax_req_q_size <= 3'h0;
req_addr_q <= 'h0;
cnt_q <= 8'h0;
end else begin
state_q <= state_d;
ax_req_q_addr <= ax_req_d_addr;
ax_req_q_burst <= ax_req_d_burst;
ax_req_q_id <= ax_req_d_id;
ax_req_q_len <= ax_req_d_len;
ax_req_q_size <= ax_req_d_size;
req_addr_q <= req_addr_d;
cnt_q <= cnt_d;
end
end
endmodule

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// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// ----------------------------
// AXI to SRAM Adapter
// ----------------------------
// Author: Florian Zaruba (zarubaf@iis.ee.ethz.ch)
//
// Description: Manages AXI transactions
// Supports all burst accesses but only on aligned addresses and with full data width.
// Assertions should guide you if there is something unsupported happening.
//
module axi2sram_sp_external #(
parameter AXI_ID_WIDTH = 5,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_DATA_WIDTH = 32
)(
input clk,
input resetn,
input [AXI_ADDR_WIDTH-1:0] s_araddr ,
input [1 :0] s_arburst,
input [3 :0] s_arcache,
input [AXI_ID_WIDTH-1 :0] s_arid ,
input [7 :0] s_arlen ,
input s_arlock ,
input [2 :0] s_arprot ,
output reg s_arready,
input [2 :0] s_arsize ,
input s_arvalid,
input [AXI_ADDR_WIDTH-1:0] s_awaddr ,
input [1 :0] s_awburst,
input [3 :0] s_awcache,
input [AXI_ID_WIDTH-1 :0] s_awid ,
input [7 :0] s_awlen ,
input s_awlock ,
input [2 :0] s_awprot ,
output reg s_awready,
input [2 :0] s_awsize ,
input s_awvalid,
output reg [AXI_ID_WIDTH-1 :0] s_bid ,
input s_bready ,
output reg [1 :0] s_bresp ,
output reg s_bvalid ,
output reg [AXI_DATA_WIDTH-1:0] s_rdata ,
output reg [AXI_ID_WIDTH-1 :0] s_rid ,
output reg s_rlast ,
input s_rready ,
output reg [1 :0] s_rresp ,
output reg s_rvalid ,
input [AXI_DATA_WIDTH-1:0] s_wdata ,
input s_wlast ,
output reg s_wready ,
input [AXI_DATA_WIDTH/8-1:0] s_wstrb ,
input s_wvalid ,
output reg req_o,
output reg we_o,
output reg [AXI_ADDR_WIDTH-1:0] addr_o,
output reg [AXI_DATA_WIDTH/8-1:0] be_o,
output reg [AXI_DATA_WIDTH-1:0] data_o,
input [AXI_DATA_WIDTH-1:0] data_i
);
// AXI has the following rules governing the use of bursts:
// - for wrapping bursts, the burst length must be 2, 4, 8, or 16
// - a burst must not cross a 4KB address boundary
// - early termination of bursts is not supported.
localparam LOG_NR_BYTES = $clog2(AXI_DATA_WIDTH/8);
reg [AXI_ID_WIDTH-1:0] ax_req_d_id;
reg [AXI_ADDR_WIDTH-1:0] ax_req_d_addr;
reg [7:0] ax_req_d_len;
reg [2:0] ax_req_d_size;
reg [1:0] ax_req_d_burst;
reg [AXI_ID_WIDTH-1:0] ax_req_q_id;
reg [AXI_ADDR_WIDTH-1:0] ax_req_q_addr;
reg [7:0] ax_req_q_len;
reg [2:0] ax_req_q_size;
reg [1:0] ax_req_q_burst;
reg [2:0] state_d;
reg [2:0] state_q;
localparam IDLE = 3'h0;
localparam READ = 3'h1;
localparam WRITE = 3'h2;
localparam SEND_B = 3'h3;
localparam WAIT_WVALID = 3'h4;
localparam WRITE_NOP = 3'h5;
localparam READ_ADDR = 3'h6;
localparam FIXED = 2'b00;
localparam INCR = 2'b01;
localparam WRAP = 2'b10;
reg [AXI_ADDR_WIDTH-1:0] req_addr_d, req_addr_q;
reg [7:0] cnt_d, cnt_q;
function automatic [AXI_ADDR_WIDTH-1:0] get_wrap_boundary;
input [AXI_ADDR_WIDTH-1:0] unaligned_address;
input [7:0] len;
begin
get_wrap_boundary = 'h0;
// for wrapping transfers ax_len can only be of size 1, 3, 7 or 15
if (len == 4'b1)
get_wrap_boundary[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES];
else if (len == 4'b11)
get_wrap_boundary[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES];
else if (len == 4'b111)
get_wrap_boundary[AXI_ADDR_WIDTH-1:3+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:2+LOG_NR_BYTES];
else if (len == 4'b1111)
get_wrap_boundary[AXI_ADDR_WIDTH-1:4+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:4+LOG_NR_BYTES];
end
endfunction
reg [AXI_ADDR_WIDTH-1:0] aligned_address;
reg [AXI_ADDR_WIDTH-1:0] wrap_boundary;
reg [AXI_ADDR_WIDTH-1:0] upper_wrap_boundary;
reg [AXI_ADDR_WIDTH-1:0] cons_addr;
always @ (*) begin
// address generation
aligned_address = {ax_req_q_addr[AXI_ADDR_WIDTH-1:LOG_NR_BYTES], {{LOG_NR_BYTES}{1'b0}}};
wrap_boundary = get_wrap_boundary(ax_req_q_addr, ax_req_q_len);
// this will overflow
upper_wrap_boundary = wrap_boundary + ((ax_req_q_len + 1) << LOG_NR_BYTES);
// calculate consecutive address
cons_addr = aligned_address + (cnt_q << LOG_NR_BYTES);
// Transaction attributes
// default assignments
state_d = state_q;
ax_req_d_id = ax_req_q_id;
ax_req_d_addr = ax_req_q_addr;
ax_req_d_len = ax_req_q_len;
ax_req_d_size = ax_req_q_size;
ax_req_d_burst = ax_req_q_burst;
req_addr_d = req_addr_q;
cnt_d = cnt_q;
// Memory default assignments
data_o = s_wdata;
be_o = s_wstrb;
we_o = 1'b0;
req_o = 1'b0;
addr_o = 'h0;
// AXI assignments
// request
s_awready = 1'b0;
s_arready = 1'b0;
// read response channel
s_rvalid = 1'b0;
s_rresp = 'h0;
s_rlast = 'h0;
s_rid = ax_req_q_id;
// slave write data channel
s_wready = 1'b0;
// write response channel
s_bvalid = 1'b0;
s_bresp = 1'b0;
s_bid = 1'b0;
case (state_q)
IDLE: begin
// Wait for a read or write
// ------------
// Read
// ------------
if (s_arvalid) begin
s_arready = 1'b1;
// sample ax
ax_req_d_id = s_arid;
ax_req_d_addr = s_araddr;
ax_req_d_len = s_arlen;
ax_req_d_size = s_arsize;
ax_req_d_burst = s_arburst;
state_d = READ;
// we can request the first address, this saves us time
req_o = 1'b1;
addr_o = s_araddr;
// save the address
req_addr_d = s_araddr;
// save the ar_len
cnt_d = 1;
// ------------
// Write
// ------------
end else if (s_awvalid) begin
s_awready = 1'b1;
s_wready = 1'b1;
addr_o = s_awaddr;
// sample ax
ax_req_d_id = s_awid;
ax_req_d_addr = s_awaddr;
ax_req_d_len = s_awlen;
ax_req_d_size = s_awsize;
ax_req_d_burst = s_awburst;
// we've got our first w_valid so start the write process
if (s_wvalid) begin
req_o = 1'b1;
we_o = 1'b1;
state_d = (s_wlast) ? SEND_B : WRITE_NOP;
cnt_d = 1;
// we still have to wait for the first w_valid to arrive
end else
state_d = WAIT_WVALID;
end
end
// ~> we are still missing a w_valid
WAIT_WVALID: begin
s_wready = 1'b1;
addr_o = ax_req_q_addr;
// we can now make our first request
if (s_wvalid) begin
req_o = 1'b1;
we_o = 1'b1;
state_d = (s_wlast) ? SEND_B : WRITE;
cnt_d = 1;
end
end
READ: begin
// keep request to memory high
req_o = 1'b1;
addr_o = req_addr_q;
// send the response
s_rvalid = 1'b1;
s_rdata = data_i;
s_rid = ax_req_q_id;
s_rlast = (cnt_q == ax_req_q_len + 1);
// check that the master is ready, the slave must not wait on this
if (s_rready) begin
// we sent the last byte -> go back to idle
if (s_rlast) begin
state_d = IDLE;
// we already got everything
end
else begin
state_d = READ_ADDR;
end
end
end
READ_ADDR: begin
// keep request to memory high
req_o = 1'b1;
// send the response
s_rvalid = 1'b0;
// ----------------------------
// Next address generation
// ----------------------------
// handle the correct burst type
case (ax_req_q_burst)
FIXED, INCR: addr_o = cons_addr;
WRAP: begin
// check if the address reached warp boundary
if (cons_addr == upper_wrap_boundary) begin
addr_o = wrap_boundary;
// address warped beyond boundary
end else if (cons_addr > upper_wrap_boundary) begin
addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
// we are still in the incremental regime
end else begin
addr_o = cons_addr;
end
end
endcase
// we need to change the address here for the upcoming request
// we can decrease the counter as the master has consumed the read data
cnt_d = cnt_q + 1;
// save the request address for the next cycle
req_addr_d = addr_o;
state_d = READ;
end
//ext SRAM need nop between continuous write operations
WRITE_NOP: begin
s_wready = 1'b0;
state_d = WRITE;
end
// ~> we already wrote the first word here
WRITE: begin
s_wready = 1'b1;
state_d = WRITE_NOP;
// consume a word here
if (s_wvalid) begin
req_o = 1'b1;
we_o = 1'b1;
// ----------------------------
// Next address generation
// ----------------------------
// handle the correct burst type
case (ax_req_q_burst)
FIXED, INCR: addr_o = cons_addr;
WRAP: begin
// check if the address reached warp boundary
if (cons_addr == upper_wrap_boundary) begin
addr_o = wrap_boundary;
// address warped beyond boundary
end else if (cons_addr > upper_wrap_boundary) begin
addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES);
// we are still in the incremental regime
end else begin
addr_o = cons_addr;
end
end
endcase
// save the request address for the next cycle
req_addr_d = addr_o;
// we can decrease the counter as the master has consumed the read data
cnt_d = cnt_q + 1;
if (s_wlast)
state_d = SEND_B;
end
end
// ~> send a write acknowledge back
SEND_B: begin
s_bvalid = 1'b1;
s_bid = ax_req_q_id;
if (s_bready)
state_d = IDLE;
end
endcase
end
// --------------
// Registers
// --------------
always @(posedge clk or negedge resetn) begin
if (~resetn) begin
state_q <= IDLE;
ax_req_q_addr <= 32'h0;
ax_req_q_burst <= 2'h0;
ax_req_q_id <= 'h0;
ax_req_q_len <= 8'h0;
ax_req_q_size <= 3'h0;
req_addr_q <= 'h0;
cnt_q <= 8'h0;
end else begin
state_q <= state_d;
ax_req_q_addr <= ax_req_d_addr;
ax_req_q_burst <= ax_req_d_burst;
ax_req_q_id <= ax_req_d_id;
ax_req_q_len <= ax_req_d_len;
ax_req_q_size <= ax_req_d_size;
req_addr_q <= req_addr_d;
cnt_q <= cnt_d;
end
end
// always @(posedge clk or negedge resetn) begin
// if (~resetn) begin
// s_rdata <= 'h0;
// end else begin
// if(req_o == 1'b1 && we_o == 1'b0)
// s_rdata <= data_i;
// else
// s_rdata <= s_rdata;
// end
// end
endmodule

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module axi_dvi #
(
parameter WIDTH = 12, // hdata and vdata width (in bits)
parameter HSIZE = 800, // Horizontal size of visible area
parameter HFP = 856, // Horizontal front porch
parameter HSP = 976, // Horizontal sync pulse
parameter HMAX = 1040, // Horizontal total size
parameter VSIZE = 600, // Vertical size of visible area
parameter VFP = 637, // Vertical front porch
parameter VSP = 643, // Vertical sync pulse
parameter VMAX = 666, // Vertical total size
parameter HSPP = 1, // Horizontal sync pulse polarity (1 for positive)
parameter VSPP = 1 // Vertical sync pulse polarity (1 for positive)
)
(
input s_awvalid,
output s_awready,
input [31:0] s_awaddr,
input [4:0] s_awid,
input [7:0] s_awlen,
input [2:0] s_awsize,
input [1:0] s_awburst,
input [0:0] s_awlock,
input [3:0] s_awcache,
input [2:0] s_awprot,
input s_wvalid,
output s_wready,
input [31:0] s_wdata,
input [3:0] s_wstrb,
input s_wlast,
output s_bvalid,
input s_bready,
output [4:0] s_bid,
output [1:0] s_bresp,
input s_arvalid,
output s_arready,
input [31:0] s_araddr,
input [4:0] s_arid,
input [7:0] s_arlen,
input [2:0] s_arsize,
input [1:0] s_arburst,
input [0:0] s_arlock,
input [3:0] s_arcache,
input [2:0] s_arprot,
output s_rvalid,
input s_rready,
output [31:0] s_rdata,
output [4:0] s_rid,
output [1:0] s_rresp,
output s_rlast,
output video_clk, // Video clock signal
output hsync, // Horizontal sync signal
output vsync, // Vertical sync signal
output data_enable, // Data enable signal
output [2:0] video_red, // Red color signal (3 bits)
output [2:0] video_green, // Green color signal (3 bits)
output [1:0] video_blue, // Blue color signal (2 bits)
input aclk,
input aresetn
);
reg [31:0] DVI_RECT_DIR,DVI_RECT_L_W,DVI_SQU_DIR,DVI_SQU_R;
reg busy,write,R_or_W;
reg s_wready;
wire ar_enter = s_arvalid & s_arready;
wire r_retire = s_rvalid & s_rready & s_rlast;
wire aw_enter = s_awvalid & s_awready;
wire w_enter = s_wvalid & s_wready & s_wlast;
wire b_retire = s_bvalid & s_bready;
assign s_arready = ~busy & (!R_or_W| !s_awvalid);
assign s_awready = ~busy & ( R_or_W| !s_arvalid);
always@(posedge aclk)
if(~aresetn) busy <= 1'b0;
else if(ar_enter|aw_enter) busy <= 1'b1;
else if(r_retire|b_retire) busy <= 1'b0;
reg [3 :0] buf_id;
reg [31:0] buf_addr;
reg [7 :0] buf_len;
reg [2 :0] buf_size;
reg [1 :0] buf_burst;
reg buf_lock;
reg [3 :0] buf_cache;
reg [2 :0] buf_prot;
always@(posedge aclk) begin
if(~aresetn) begin
R_or_W <= 1'b0;
buf_id <= 'b0;
buf_addr <= 'b0;
buf_len <= 'b0;
buf_size <= 'b0;
buf_burst <= 'b0;
buf_lock <= 'b0;
buf_cache <= 'b0;
buf_prot <= 'b0;
end
else
if(ar_enter | aw_enter) begin
R_or_W <= ar_enter;
buf_id <= ar_enter ? s_arid : s_awid ;
buf_addr <= ar_enter ? s_araddr : s_awaddr ;
buf_len <= ar_enter ? s_arlen : s_awlen ;
buf_size <= ar_enter ? s_arsize : s_awsize ;
buf_burst <= ar_enter ? s_arburst: s_awburst;
buf_lock <= ar_enter ? s_arlock : s_awlock ;
buf_cache <= ar_enter ? s_arcache: s_awcache;
buf_prot <= ar_enter ? s_arprot : s_awprot ;
end
end
always@(posedge aclk)
if(~aresetn) write <= 1'b0;
else if(aw_enter) write <= 1'b1;
else if(ar_enter) write <= 1'b0;
always@(posedge aclk)
if(~aresetn) s_wready <= 1'b0;
else if(aw_enter) s_wready <= 1'b1;
else if(w_enter & s_wlast) s_wready <= 1'b0;
reg [31:0] s_rdata;
reg s_rvalid,s_rlast;
wire [31:0] rdata_d = buf_addr[15:0] == 16'h0 ? DVI_RECT_DIR :
buf_addr[15:0] == 16'h4 ? DVI_RECT_L_W :
buf_addr[15:0] == 16'h8 ? DVI_SQU_DIR :
buf_addr[15:0] == 16'hc ? DVI_SQU_R :
32'd0;
always@(posedge aclk)begin
if(~aresetn) begin
s_rdata <= 'b0;
s_rvalid <= 1'b0;
s_rlast <= 1'b0;
end
else if(busy & !write & !r_retire)
begin
s_rdata <= rdata_d;
s_rvalid <= 1'b1;
s_rlast <= 1'b1;
end
else if(r_retire)
begin
s_rvalid <= 1'b0;
end
end
reg s_bvalid;
always@(posedge aclk) begin
if(~aresetn) s_bvalid <= 1'b0;
else if(w_enter) s_bvalid <= 1'b1;
else if(b_retire) s_bvalid <= 1'b0;
end
assign s_rid = buf_id;
assign s_bid = buf_id;
assign s_bresp = 2'b0;
assign s_rresp = 2'b0;
//-------------------------------{dvi controller}begin----------------------------//
wire write_reg_en[3:0];
assign write_reg_en[0] = w_enter & (buf_addr[15:0]==16'h0);
assign write_reg_en[1] = w_enter & (buf_addr[15:0]==16'h4);
assign write_reg_en[2] = w_enter & (buf_addr[15:0]==16'h8);
assign write_reg_en[3] = w_enter & (buf_addr[15:0]==16'hc);
always @(posedge aclk) begin
if(!aresetn) begin
DVI_RECT_DIR <= 32'h0;
end
else if (write_reg_en[0]) begin
DVI_RECT_DIR <= s_wdata;
end
end
always @(posedge aclk) begin
if(!aresetn) begin
DVI_RECT_L_W <= 32'h0;
end
else if (write_reg_en[1]) begin
DVI_RECT_L_W <= s_wdata;
end
end
always @(posedge aclk) begin
if(!aresetn) begin
DVI_SQU_DIR <= 32'h0;
end
else if (write_reg_en[2]) begin
DVI_SQU_DIR <= s_wdata;
end
end
always @(posedge aclk) begin
if(!aresetn) begin
DVI_SQU_R <= 32'h0;
end
else if (write_reg_en[3]) begin
DVI_SQU_R <= s_wdata;
end
end
reg [WIDTH-1:0] hdata = 0; // Horizontal position counter
reg [WIDTH-1:0] vdata = 0; // Vertical position counter
wire hdata_in_range;
wire vdata_in_range;
wire hdata1_in_range;
wire vdata1_in_range;
always @(posedge aclk) begin
if (hdata == (HMAX - 1)) // If horizontal counter reaches max
hdata <= 0; // Reset horizontal counter
else
hdata <= hdata + 1; // Increment horizontal counter
end
// Vertical counter (vdata) logic
always @(posedge aclk) begin
if (hdata == (HMAX - 1)) begin
if (vdata == (VMAX - 1)) // If vertical counter reaches max
vdata <= 0; // Reset vertical counter
else
vdata <= vdata + 1; // Increment vertical counter
end
end
// Horizontal sync signal generation (hsync)
assign video_clk = aclk; // Example: using input clock as video clock
assign hsync = ((hdata >= HFP) && (hdata < HSP)) ? HSPP : !HSPP;
assign vsync = ((vdata >= VFP) && (vdata < VSP)) ? VSPP : !VSPP;
assign data_enable = ((hdata < HSIZE) & (vdata < VSIZE));
assign hdata_in_range = (hdata > (DVI_RECT_DIR[31:16]-DVI_RECT_L_W[31:16])) && (hdata < (DVI_RECT_DIR[31:16]+DVI_RECT_L_W[31:16]));
// Check if vdata is in the range specified by DVI_RECT_L_W
assign vdata_in_range = (vdata > DVI_RECT_DIR[15:0]) && (vdata <(DVI_RECT_DIR[15:0]+DVI_RECT_L_W[15:0]));
assign hdata1_in_range = (hdata > (DVI_SQU_DIR[31:16]-DVI_SQU_R[31:16])) && (hdata < (DVI_SQU_DIR[31:16]+DVI_SQU_R[31:16]));
// Check if vdata is in the range specified by DVI_RECT_L_W
assign vdata1_in_range = (vdata > (DVI_SQU_DIR[15:0]-DVI_SQU_R[15:0])) && (vdata <(DVI_SQU_DIR[15:0]+DVI_SQU_R[15:0]));
// Set video output colors based on conditions
assign video_red = ((hdata_in_range && vdata_in_range)||(hdata1_in_range && vdata1_in_range)) ? 3'b111 : 3'b0;
assign video_green = 3'b0;
assign video_blue = 2'b0;
//--------------------------------{dvi controller}end-----------------------------//
endmodule

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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
// Date : Tue Jun 23 00:27:14 2026
// Host : fedora running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v
// Design : clk_pll
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a200tfbg676-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module clk_pll
(cpu_clk,
sys_clk,
resetn,
locked,
clk_in1);
output cpu_clk;
output sys_clk;
input resetn;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire cpu_clk;
wire locked;
wire resetn;
wire sys_clk;
clk_pll_clk_pll_clk_wiz inst
(.clk_in1(clk_in1),
.cpu_clk(cpu_clk),
.locked(locked),
.resetn(resetn),
.sys_clk(sys_clk));
endmodule
(* ORIG_REF_NAME = "clk_pll_clk_wiz" *)
module clk_pll_clk_pll_clk_wiz
(cpu_clk,
sys_clk,
resetn,
locked,
clk_in1);
output cpu_clk;
output sys_clk;
input resetn;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_clk_pll;
wire clkfbout_buf_clk_pll;
wire clkfbout_clk_pll;
wire cpu_clk;
wire cpu_clk_clk_pll;
wire locked;
wire reset_high;
wire resetn;
wire sys_clk;
wire sys_clk_clk_pll;
wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_pll),
.O(clkfbout_buf_clk_pll));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_pll));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(cpu_clk_clk_pll),
.O(cpu_clk));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(sys_clk_clk_pll),
.O(sys_clk));
(* BOX_TYPE = "PRIMITIVE" *)
PLLE2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(31),
.CLKFBOUT_PHASE(0.000000),
.CLKIN1_PERIOD(20.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE(47),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT1_DIVIDE(31),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.STARTUP_WAIT("FALSE"))
plle2_adv_inst
(.CLKFBIN(clkfbout_buf_clk_pll),
.CLKFBOUT(clkfbout_clk_pll),
.CLKIN1(clk_in1_clk_pll),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKOUT0(cpu_clk_clk_pll),
.CLKOUT1(sys_clk_clk_pll),
.CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PWRDWN(1'b0),
.RST(reset_high));
LUT1 #(
.INIT(2'h1))
plle2_adv_inst_i_1
(.I0(resetn),
.O(reset_high));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif

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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-- Date : Tue Jun 23 00:27:14 2026
-- Host : fedora running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl
-- Design : clk_pll
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a200tfbg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_pll_clk_pll_clk_wiz is
port (
cpu_clk : out STD_LOGIC;
sys_clk : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_pll_clk_pll_clk_wiz : entity is "clk_pll_clk_wiz";
end clk_pll_clk_pll_clk_wiz;
architecture STRUCTURE of clk_pll_clk_pll_clk_wiz is
signal clk_in1_clk_pll : STD_LOGIC;
signal clkfbout_buf_clk_pll : STD_LOGIC;
signal clkfbout_clk_pll : STD_LOGIC;
signal cpu_clk_clk_pll : STD_LOGIC;
signal reset_high : STD_LOGIC;
signal sys_clk_clk_pll : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_pll,
O => clkfbout_buf_clk_pll
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_clk_pll
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => cpu_clk_clk_pll,
O => cpu_clk
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => sys_clk_clk_pll,
O => sys_clk
);
plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => 31,
CLKFBOUT_PHASE => 0.000000,
CLKIN1_PERIOD => 20.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE => 47,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT1_DIVIDE => 31,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
STARTUP_WAIT => "FALSE"
)
port map (
CLKFBIN => clkfbout_buf_clk_pll,
CLKFBOUT => clkfbout_clk_pll,
CLKIN1 => clk_in1_clk_pll,
CLKIN2 => '0',
CLKINSEL => '1',
CLKOUT0 => cpu_clk_clk_pll,
CLKOUT1 => sys_clk_clk_pll,
CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PWRDWN => '0',
RST => reset_high
);
plle2_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => reset_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_pll is
port (
cpu_clk : out STD_LOGIC;
sys_clk : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_pll : entity is true;
end clk_pll;
architecture STRUCTURE of clk_pll is
begin
inst: entity work.clk_pll_clk_pll_clk_wiz
port map (
clk_in1 => clk_in1,
cpu_clk => cpu_clk,
locked => locked,
resetn => resetn,
sys_clk => sys_clk
);
end STRUCTURE;

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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
// Date : Tue Jun 23 00:27:14 2026
// Host : fedora running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.v
// Design : clk_pll
// Purpose : Stub declaration of top-level module interface
// Device : xc7a200tfbg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_pll(cpu_clk, sys_clk, resetn, locked, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="cpu_clk,sys_clk,resetn,locked,clk_in1" */;
output cpu_clk;
output sys_clk;
input resetn;
output locked;
input clk_in1;
endmodule

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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-- Date : Tue Jun 23 00:27:14 2026
-- Host : fedora running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl
-- Design : clk_pll
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a200tfbg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_pll is
Port (
cpu_clk : out STD_LOGIC;
sys_clk : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end clk_pll;
architecture stub of clk_pll is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "cpu_clk,sys_clk,resetn,locked,clk_in1";
begin
end;

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/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4 to AXI4-Lite adapter
*/
module axi_axil_adapter #
(
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of input (slave) AXI interface data bus in bits
parameter AXI_DATA_WIDTH = 32,
// Width of input (slave) AXI interface wstrb (width of data bus in words)
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
// Width of AXI ID signal
parameter AXI_ID_WIDTH = 8,
// Width of output (master) AXI lite interface data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of output (master) AXI lite interface wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
parameter CONVERT_BURST = 1,
// When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
parameter CONVERT_NARROW_BURST = 0
)
(
input wire clk,
input wire rst,
/*
* AXI slave interface
*/
input wire [AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [7:0] s_axi_awlen,
input wire [2:0] s_axi_awsize,
input wire [1:0] s_axi_awburst,
input wire s_axi_awlock,
input wire [3:0] s_axi_awcache,
input wire [2:0] s_axi_awprot,
input wire s_axi_awvalid,
output wire s_axi_awready,
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [AXI_STRB_WIDTH-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire s_axi_wvalid,
output wire s_axi_wready,
output wire [AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
input wire [AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [ADDR_WIDTH-1:0] s_axi_araddr,
input wire [7:0] s_axi_arlen,
input wire [2:0] s_axi_arsize,
input wire [1:0] s_axi_arburst,
input wire s_axi_arlock,
input wire [3:0] s_axi_arcache,
input wire [2:0] s_axi_arprot,
input wire s_axi_arvalid,
output wire s_axi_arready,
output wire [AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
/*
* AXI lite master interface
*/
output wire [ADDR_WIDTH-1:0] m_axil_awaddr,
output wire [2:0] m_axil_awprot,
output wire m_axil_awvalid,
input wire m_axil_awready,
output wire [AXIL_DATA_WIDTH-1:0] m_axil_wdata,
output wire [AXIL_STRB_WIDTH-1:0] m_axil_wstrb,
output wire m_axil_wvalid,
input wire m_axil_wready,
input wire [1:0] m_axil_bresp,
input wire m_axil_bvalid,
output wire m_axil_bready,
output wire [ADDR_WIDTH-1:0] m_axil_araddr,
output wire [2:0] m_axil_arprot,
output wire m_axil_arvalid,
input wire m_axil_arready,
input wire [AXIL_DATA_WIDTH-1:0] m_axil_rdata,
input wire [1:0] m_axil_rresp,
input wire m_axil_rvalid,
output wire m_axil_rready
);
axi_axil_adapter_wr #(
.ADDR_WIDTH(ADDR_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.CONVERT_BURST(CONVERT_BURST),
.CONVERT_NARROW_BURST(CONVERT_NARROW_BURST)
)
axi_axil_adapter_wr_inst (
.clk(clk),
.rst(rst),
/*
* AXI slave interface
*/
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
/*
* AXI lite master interface
*/
.m_axil_awaddr(m_axil_awaddr),
.m_axil_awprot(m_axil_awprot),
.m_axil_awvalid(m_axil_awvalid),
.m_axil_awready(m_axil_awready),
.m_axil_wdata(m_axil_wdata),
.m_axil_wstrb(m_axil_wstrb),
.m_axil_wvalid(m_axil_wvalid),
.m_axil_wready(m_axil_wready),
.m_axil_bresp(m_axil_bresp),
.m_axil_bvalid(m_axil_bvalid),
.m_axil_bready(m_axil_bready)
);
axi_axil_adapter_rd #(
.ADDR_WIDTH(ADDR_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.CONVERT_BURST(CONVERT_BURST),
.CONVERT_NARROW_BURST(CONVERT_NARROW_BURST)
)
axi_axil_adapter_rd_inst (
.clk(clk),
.rst(rst),
/*
* AXI slave interface
*/
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
/*
* AXI lite master interface
*/
.m_axil_araddr(m_axil_araddr),
.m_axil_arprot(m_axil_arprot),
.m_axil_arvalid(m_axil_arvalid),
.m_axil_arready(m_axil_arready),
.m_axil_rdata(m_axil_rdata),
.m_axil_rresp(m_axil_rresp),
.m_axil_rvalid(m_axil_rvalid),
.m_axil_rready(m_axil_rready)
);
endmodule
`resetall

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/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4 to AXI4-Lite adapter (read)
*/
module axi_axil_adapter_rd #
(
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of input (slave) AXI interface data bus in bits
parameter AXI_DATA_WIDTH = 32,
// Width of input (slave) AXI interface wstrb (width of data bus in words)
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
// Width of AXI ID signal
parameter AXI_ID_WIDTH = 8,
// Width of output (master) AXI lite interface data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of output (master) AXI lite interface wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
parameter CONVERT_BURST = 1,
// When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
parameter CONVERT_NARROW_BURST = 0
)
(
input wire clk,
input wire rst,
/*
* AXI slave interface
*/
input wire [AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [ADDR_WIDTH-1:0] s_axi_araddr,
input wire [7:0] s_axi_arlen,
input wire [2:0] s_axi_arsize,
input wire [1:0] s_axi_arburst,
input wire s_axi_arlock,
input wire [3:0] s_axi_arcache,
input wire [2:0] s_axi_arprot,
input wire s_axi_arvalid,
output wire s_axi_arready,
output wire [AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
/*
* AXI lite master interface
*/
output wire [ADDR_WIDTH-1:0] m_axil_araddr,
output wire [2:0] m_axil_arprot,
output wire m_axil_arvalid,
input wire m_axil_arready,
input wire [AXIL_DATA_WIDTH-1:0] m_axil_rdata,
input wire [1:0] m_axil_rresp,
input wire m_axil_rvalid,
output wire m_axil_rready
);
parameter AXI_ADDR_BIT_OFFSET = $clog2(AXI_STRB_WIDTH);
parameter AXIL_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_WIDTH);
parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
parameter AXIL_WORD_WIDTH = AXIL_STRB_WIDTH;
parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
parameter AXIL_WORD_SIZE = AXIL_DATA_WIDTH/AXIL_WORD_WIDTH;
parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
parameter AXIL_BURST_SIZE = $clog2(AXIL_STRB_WIDTH);
// output bus is wider
parameter EXPAND = AXIL_STRB_WIDTH > AXI_STRB_WIDTH;
parameter DATA_WIDTH = EXPAND ? AXIL_DATA_WIDTH : AXI_DATA_WIDTH;
parameter STRB_WIDTH = EXPAND ? AXIL_STRB_WIDTH : AXI_STRB_WIDTH;
// required number of segments in wider bus
parameter SEGMENT_COUNT = EXPAND ? (AXIL_STRB_WIDTH / AXI_STRB_WIDTH) : (AXI_STRB_WIDTH / AXIL_STRB_WIDTH);
// data width and keep width per segment
parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT;
parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
// bus width assertions
initial begin
if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin
$error("Error: AXI slave interface data width not evenly divisble (instance %m)");
$finish;
end
if (AXIL_WORD_SIZE * AXIL_STRB_WIDTH != AXIL_DATA_WIDTH) begin
$error("Error: AXI lite master interface data width not evenly divisble (instance %m)");
$finish;
end
if (AXI_WORD_SIZE != AXIL_WORD_SIZE) begin
$error("Error: word size mismatch (instance %m)");
$finish;
end
if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin
$error("Error: AXI slave interface word width must be even power of two (instance %m)");
$finish;
end
if (2**$clog2(AXIL_WORD_WIDTH) != AXIL_WORD_WIDTH) begin
$error("Error: AXI lite master interface word width must be even power of two (instance %m)");
$finish;
end
end
localparam SAFE_EXP_MSB = (AXIL_ADDR_BIT_OFFSET > AXI_ADDR_BIT_OFFSET) ? AXIL_ADDR_BIT_OFFSET - 1 : AXI_ADDR_BIT_OFFSET;
localparam SAFE_EXP_LSB = AXI_ADDR_BIT_OFFSET;
localparam SAFE_NAR_MSB = (AXI_ADDR_BIT_OFFSET > AXIL_ADDR_BIT_OFFSET) ? AXI_ADDR_BIT_OFFSET - 1 : AXIL_ADDR_BIT_OFFSET;
localparam SAFE_NAR_LSB = AXIL_ADDR_BIT_OFFSET;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_DATA = 2'd1,
STATE_DATA_READ = 2'd2,
STATE_DATA_SPLIT = 2'd3;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [AXI_ID_WIDTH-1:0] id_reg = {AXI_ID_WIDTH{1'b0}}, id_next;
reg [ADDR_WIDTH-1:0] addr_reg = {ADDR_WIDTH{1'b0}}, addr_next;
reg [DATA_WIDTH-1:0] data_reg = {DATA_WIDTH{1'b0}}, data_next;
reg [1:0] resp_reg = 2'd0, resp_next;
reg [7:0] burst_reg = 8'd0, burst_next;
reg [2:0] burst_size_reg = 3'd0, burst_size_next;
reg [7:0] master_burst_reg = 8'd0, master_burst_next;
reg [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
reg s_axi_arready_reg = 1'b0, s_axi_arready_next;
reg [AXI_ID_WIDTH-1:0] s_axi_rid_reg = {AXI_ID_WIDTH{1'b0}}, s_axi_rid_next;
reg [AXI_DATA_WIDTH-1:0] s_axi_rdata_reg = {AXI_DATA_WIDTH{1'b0}}, s_axi_rdata_next;
reg [1:0] s_axi_rresp_reg = 2'd0, s_axi_rresp_next;
reg s_axi_rlast_reg = 1'b0, s_axi_rlast_next;
reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
reg [ADDR_WIDTH-1:0] m_axil_araddr_reg = {ADDR_WIDTH{1'b0}}, m_axil_araddr_next;
reg [2:0] m_axil_arprot_reg = 3'd0, m_axil_arprot_next;
reg m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
reg m_axil_rready_reg = 1'b0, m_axil_rready_next;
assign s_axi_arready = s_axi_arready_reg;
assign s_axi_rid = s_axi_rid_reg;
assign s_axi_rdata = s_axi_rdata_reg;
assign s_axi_rresp = s_axi_rresp_reg;
assign s_axi_rlast = s_axi_rlast_reg;
assign s_axi_rvalid = s_axi_rvalid_reg;
assign m_axil_araddr = m_axil_araddr_reg;
assign m_axil_arprot = m_axil_arprot_reg;
assign m_axil_arvalid = m_axil_arvalid_reg;
assign m_axil_rready = m_axil_rready_reg;
always @* begin
state_next = STATE_IDLE;
id_next = id_reg;
addr_next = addr_reg;
data_next = data_reg;
resp_next = resp_reg;
burst_next = burst_reg;
burst_size_next = burst_size_reg;
master_burst_next = master_burst_reg;
master_burst_size_next = master_burst_size_reg;
s_axi_arready_next = 1'b0;
s_axi_rid_next = s_axi_rid_reg;
s_axi_rdata_next = s_axi_rdata_reg;
s_axi_rresp_next = s_axi_rresp_reg;
s_axi_rlast_next = s_axi_rlast_reg;
s_axi_rvalid_next = s_axi_rvalid_reg && !s_axi_rready;
m_axil_araddr_next = m_axil_araddr_reg;
m_axil_arprot_next = m_axil_arprot_reg;
m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_arready;
m_axil_rready_next = 1'b0;
if (SEGMENT_COUNT == 1) begin
// master output is same width; direct transfer with no splitting/merging
case (state_reg)
STATE_IDLE: begin
// idle state; wait for new burst
s_axi_arready_next = !m_axil_arvalid;
if (s_axi_arready && s_axi_arvalid) begin
s_axi_arready_next = 1'b0;
id_next = s_axi_arid;
m_axil_araddr_next = s_axi_araddr;
addr_next = s_axi_araddr;
burst_next = s_axi_arlen;
burst_size_next = s_axi_arsize;
m_axil_arprot_next = s_axi_arprot;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
// data state; transfer read data
m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;
if (m_axil_rready && m_axil_rvalid) begin
s_axi_rid_next = id_reg;
s_axi_rdata_next = m_axil_rdata;
s_axi_rresp_next = m_axil_rresp;
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b1;
burst_next = burst_reg - 1;
addr_next = addr_reg + (1 << burst_size_reg);
if (burst_reg == 0) begin
// last data word, return to idle
m_axil_rready_next = 1'b0;
s_axi_rlast_next = 1'b1;
s_axi_arready_next = !m_axil_arvalid;
state_next = STATE_IDLE;
end else begin
// start new AXI lite read
m_axil_araddr_next = addr_next;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;
end
end else begin
state_next = STATE_DATA;
end
end
endcase
end else if (EXPAND) begin
// master output is wider; split reads
case (state_reg)
STATE_IDLE: begin
// idle state; wait for new burst
s_axi_arready_next = !m_axil_arvalid;
if (s_axi_arready && s_axi_arvalid) begin
s_axi_arready_next = 1'b0;
id_next = s_axi_arid;
m_axil_araddr_next = s_axi_araddr;
addr_next = s_axi_araddr;
burst_next = s_axi_arlen;
burst_size_next = s_axi_arsize;
if (CONVERT_BURST && s_axi_arcache[1] && (CONVERT_NARROW_BURST || s_axi_arsize == AXI_BURST_SIZE)) begin
// split reads
// require CONVERT_BURST and arcache[1] set
master_burst_size_next = AXIL_BURST_SIZE;
state_next = STATE_DATA_READ;
end else begin
// output narrow burst
master_burst_size_next = s_axi_arsize;
state_next = STATE_DATA;
end
m_axil_arprot_next = s_axi_arprot;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;
if (m_axil_rready && m_axil_rvalid) begin
s_axi_rid_next = id_reg;
s_axi_rdata_next = m_axil_rdata >> (addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB] * AXI_DATA_WIDTH);
s_axi_rresp_next = m_axil_rresp;
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b1;
burst_next = burst_reg - 1;
addr_next = addr_reg + (1 << burst_size_reg);
if (burst_reg == 0) begin
// last data word, return to idle
m_axil_rready_next = 1'b0;
s_axi_rlast_next = 1'b1;
s_axi_arready_next = !m_axil_arvalid;
state_next = STATE_IDLE;
end else begin
// start new AXI lite read
m_axil_araddr_next = addr_next;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;
end
end else begin
state_next = STATE_DATA;
end
end
STATE_DATA_READ: begin
m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;
if (m_axil_rready && m_axil_rvalid) begin
s_axi_rid_next = id_reg;
data_next = m_axil_rdata;
resp_next = m_axil_rresp;
s_axi_rdata_next = m_axil_rdata >> (addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB] * AXI_DATA_WIDTH);
s_axi_rresp_next = m_axil_rresp;
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b1;
burst_next = burst_reg - 1;
addr_next = addr_reg + (1 << burst_size_reg);
if (burst_reg == 0) begin
m_axil_rready_next = 1'b0;
s_axi_arready_next = !m_axil_arvalid;
s_axi_rlast_next = 1'b1;
state_next = STATE_IDLE;
end else if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
// start new AXI lite read
m_axil_araddr_next = addr_next;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA_READ;
end else begin
m_axil_rready_next = 1'b0;
state_next = STATE_DATA_SPLIT;
end
end else begin
state_next = STATE_DATA_READ;
end
end
STATE_DATA_SPLIT: begin
m_axil_rready_next = 1'b0;
if (s_axi_rready || !s_axi_rvalid) begin
s_axi_rid_next = id_reg;
s_axi_rdata_next = data_reg >> (addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB] * AXI_DATA_WIDTH);
s_axi_rresp_next = resp_reg;
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b1;
burst_next = burst_reg - 1;
addr_next = addr_reg + (1 << burst_size_reg);
if (burst_reg == 0) begin
s_axi_arready_next = !m_axil_arvalid;
s_axi_rlast_next = 1'b1;
state_next = STATE_IDLE;
end else if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
// start new AXI lite read
m_axil_araddr_next = addr_next;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA_READ;
end else begin
state_next = STATE_DATA_SPLIT;
end
end else begin
state_next = STATE_DATA_SPLIT;
end
end
endcase
end else begin
// master output is narrower; merge reads and possibly split burst
case (state_reg)
STATE_IDLE: begin
// idle state; wait for new burst
s_axi_arready_next = !m_axil_arvalid;
resp_next = 2'd0;
if (s_axi_arready && s_axi_arvalid) begin
s_axi_arready_next = 1'b0;
id_next = s_axi_arid;
m_axil_araddr_next = s_axi_araddr;
addr_next = s_axi_araddr;
burst_next = s_axi_arlen;
burst_size_next = s_axi_arsize;
if (s_axi_arsize > AXIL_BURST_SIZE) begin
// need to adjust burst size
if (s_axi_arlen >> (8+AXIL_BURST_SIZE-s_axi_arsize) != 0) begin
// limit burst length to max
master_burst_next = (8'd255 << (s_axi_arsize-AXIL_BURST_SIZE)) | ((~s_axi_araddr & (8'hff >> (8-s_axi_arsize))) >> AXIL_BURST_SIZE);
end else begin
master_burst_next = (s_axi_arlen << (s_axi_arsize-AXIL_BURST_SIZE)) | ((~s_axi_araddr & (8'hff >> (8-s_axi_arsize))) >> AXIL_BURST_SIZE);
end
master_burst_size_next = AXIL_BURST_SIZE;
end else begin
// pass through narrow (enough) burst
master_burst_next = s_axi_arlen;
master_burst_size_next = s_axi_arsize;
end
m_axil_arprot_next = s_axi_arprot;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;
if (m_axil_rready && m_axil_rvalid) begin
data_next[addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axil_rdata;
if (m_axil_rresp) begin
resp_next = m_axil_rresp;
end
s_axi_rid_next = id_reg;
s_axi_rdata_next = data_next;
s_axi_rresp_next = resp_next;
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b0;
master_burst_next = master_burst_reg - 1;
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
m_axil_araddr_next = addr_next;
if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
data_next = {DATA_WIDTH{1'b0}};
burst_next = burst_reg - 1;
s_axi_rvalid_next = 1'b1;
end
if (master_burst_reg == 0) begin
if (burst_next >> (8+AXIL_BURST_SIZE-burst_size_reg) != 0) begin
// limit burst length to max
master_burst_next = 8'd255;
end else begin
master_burst_next = (burst_next << (burst_size_reg-AXIL_BURST_SIZE)) | (8'hff >> (8-burst_size_reg) >> AXIL_BURST_SIZE);
end
if (burst_reg == 0) begin
m_axil_rready_next = 1'b0;
s_axi_rlast_next = 1'b1;
s_axi_rvalid_next = 1'b1;
s_axi_arready_next = !m_axil_arvalid;
state_next = STATE_IDLE;
end else begin
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;
end
end else begin
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;
end
end else begin
state_next = STATE_DATA;
end
end
endcase
end
end
always @(posedge clk) begin
state_reg <= state_next;
id_reg <= id_next;
addr_reg <= addr_next;
data_reg <= data_next;
resp_reg <= resp_next;
burst_reg <= burst_next;
burst_size_reg <= burst_size_next;
master_burst_reg <= master_burst_next;
master_burst_size_reg <= master_burst_size_next;
s_axi_arready_reg <= s_axi_arready_next;
s_axi_rid_reg <= s_axi_rid_next;
s_axi_rdata_reg <= s_axi_rdata_next;
s_axi_rresp_reg <= s_axi_rresp_next;
s_axi_rlast_reg <= s_axi_rlast_next;
s_axi_rvalid_reg <= s_axi_rvalid_next;
m_axil_araddr_reg <= m_axil_araddr_next;
m_axil_arprot_reg <= m_axil_arprot_next;
m_axil_arvalid_reg <= m_axil_arvalid_next;
m_axil_rready_reg <= m_axil_rready_next;
if (rst) begin
state_reg <= STATE_IDLE;
s_axi_arready_reg <= 1'b0;
s_axi_rvalid_reg <= 1'b0;
m_axil_arvalid_reg <= 1'b0;
m_axil_rready_reg <= 1'b0;
end
end
endmodule
`resetall

570
rtl/ip/axi_axil_adapter/axi_axil_adapter_wr.v Normal file
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@@ -0,0 +1,570 @@
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4 to AXI4-Lite adapter (write)
*/
module axi_axil_adapter_wr #
(
// Width of address bus in bits
parameter ADDR_WIDTH = 32,
// Width of input (slave) AXI interface data bus in bits
parameter AXI_DATA_WIDTH = 32,
// Width of input (slave) AXI interface wstrb (width of data bus in words)
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
// Width of AXI ID signal
parameter AXI_ID_WIDTH = 8,
// Width of output (master) AXI lite interface data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of output (master) AXI lite interface wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
parameter CONVERT_BURST = 1,
// When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
parameter CONVERT_NARROW_BURST = 0
)
(
input wire clk,
input wire rst,
/*
* AXI slave interface
*/
input wire [AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [7:0] s_axi_awlen,
input wire [2:0] s_axi_awsize,
input wire [1:0] s_axi_awburst,
input wire s_axi_awlock,
input wire [3:0] s_axi_awcache,
input wire [2:0] s_axi_awprot,
input wire s_axi_awvalid,
output wire s_axi_awready,
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [AXI_STRB_WIDTH-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire s_axi_wvalid,
output wire s_axi_wready,
output wire [AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
/*
* AXI lite master interface
*/
output wire [ADDR_WIDTH-1:0] m_axil_awaddr,
output wire [2:0] m_axil_awprot,
output wire m_axil_awvalid,
input wire m_axil_awready,
output wire [AXIL_DATA_WIDTH-1:0] m_axil_wdata,
output wire [AXIL_STRB_WIDTH-1:0] m_axil_wstrb,
output wire m_axil_wvalid,
input wire m_axil_wready,
input wire [1:0] m_axil_bresp,
input wire m_axil_bvalid,
output wire m_axil_bready
);
parameter AXI_ADDR_BIT_OFFSET = $clog2(AXI_STRB_WIDTH);
parameter AXIL_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_WIDTH);
parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
parameter AXIL_WORD_WIDTH = AXIL_STRB_WIDTH;
parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
parameter AXIL_WORD_SIZE = AXIL_DATA_WIDTH/AXIL_WORD_WIDTH;
parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
parameter AXIL_BURST_SIZE = $clog2(AXIL_STRB_WIDTH);
// output bus is wider
parameter EXPAND = AXIL_STRB_WIDTH > AXI_STRB_WIDTH;
parameter DATA_WIDTH = EXPAND ? AXIL_DATA_WIDTH : AXI_DATA_WIDTH;
parameter STRB_WIDTH = EXPAND ? AXIL_STRB_WIDTH : AXI_STRB_WIDTH;
// required number of segments in wider bus
parameter SEGMENT_COUNT = EXPAND ? (AXIL_STRB_WIDTH / AXI_STRB_WIDTH) : (AXI_STRB_WIDTH / AXIL_STRB_WIDTH);
// data width and keep width per segment
parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT;
parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
// bus width assertions
initial begin
if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin
$error("Error: AXI slave interface data width not evenly divisble (instance %m)");
$finish;
end
if (AXIL_WORD_SIZE * AXIL_STRB_WIDTH != AXIL_DATA_WIDTH) begin
$error("Error: AXI lite master interface data width not evenly divisble (instance %m)");
$finish;
end
if (AXI_WORD_SIZE != AXIL_WORD_SIZE) begin
$error("Error: word size mismatch (instance %m)");
$finish;
end
if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin
$error("Error: AXI slave interface word width must be even power of two (instance %m)");
$finish;
end
if (2**$clog2(AXIL_WORD_WIDTH) != AXIL_WORD_WIDTH) begin
$error("Error: AXI lite master interface word width must be even power of two (instance %m)");
$finish;
end
end
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_DATA = 2'd1,
STATE_DATA_2 = 2'd2,
STATE_RESP = 2'd3;
// 添加安全的位选边界，防止 ModelSim 报 Range Reversed 错误
localparam SAFE_EXP_MSB = (AXIL_ADDR_BIT_OFFSET > AXI_ADDR_BIT_OFFSET) ? AXIL_ADDR_BIT_OFFSET - 1 : AXI_ADDR_BIT_OFFSET;
localparam SAFE_EXP_LSB = AXI_ADDR_BIT_OFFSET;
localparam SAFE_NAR_MSB = (AXI_ADDR_BIT_OFFSET > AXIL_ADDR_BIT_OFFSET) ? AXI_ADDR_BIT_OFFSET - 1 : AXIL_ADDR_BIT_OFFSET;
localparam SAFE_NAR_LSB = AXIL_ADDR_BIT_OFFSET;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [AXI_ID_WIDTH-1:0] id_reg = {AXI_ID_WIDTH{1'b0}}, id_next;
reg [ADDR_WIDTH-1:0] addr_reg = {ADDR_WIDTH{1'b0}}, addr_next;
reg [DATA_WIDTH-1:0] data_reg = {DATA_WIDTH{1'b0}}, data_next;
reg [STRB_WIDTH-1:0] strb_reg = {STRB_WIDTH{1'b0}}, strb_next;
reg [7:0] burst_reg = 8'd0, burst_next;
reg [2:0] burst_size_reg = 3'd0, burst_size_next;
reg [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
reg burst_active_reg = 1'b0, burst_active_next;
reg convert_burst_reg = 1'b0, convert_burst_next;
reg first_transfer_reg = 1'b0, first_transfer_next;
reg last_segment_reg = 1'b0, last_segment_next;
reg s_axi_awready_reg = 1'b0, s_axi_awready_next;
reg s_axi_wready_reg = 1'b0, s_axi_wready_next;
reg [AXI_ID_WIDTH-1:0] s_axi_bid_reg = {AXI_ID_WIDTH{1'b0}}, s_axi_bid_next;
reg [1:0] s_axi_bresp_reg = 2'd0, s_axi_bresp_next;
reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
reg [ADDR_WIDTH-1:0] m_axil_awaddr_reg = {ADDR_WIDTH{1'b0}}, m_axil_awaddr_next;
reg [2:0] m_axil_awprot_reg = 3'd0, m_axil_awprot_next;
reg m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
reg [AXIL_DATA_WIDTH-1:0] m_axil_wdata_reg = {AXIL_DATA_WIDTH{1'b0}}, m_axil_wdata_next;
reg [AXIL_STRB_WIDTH-1:0] m_axil_wstrb_reg = {AXIL_STRB_WIDTH{1'b0}}, m_axil_wstrb_next;
reg m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
reg m_axil_bready_reg = 1'b0, m_axil_bready_next;
assign s_axi_awready = s_axi_awready_reg;
assign s_axi_wready = s_axi_wready_reg;
assign s_axi_bid = s_axi_bid_reg;
assign s_axi_bresp = s_axi_bresp_reg;
assign s_axi_bvalid = s_axi_bvalid_reg;
assign m_axil_awaddr = m_axil_awaddr_reg;
//assign m_axil_awlen = m_axil_awlen_reg;
//assign m_axil_awsize = m_axil_awsize_reg;
//assign m_axil_awburst = m_axil_awburst_reg;
assign m_axil_awprot = m_axil_awprot_reg;
assign m_axil_awvalid = m_axil_awvalid_reg;
assign m_axil_wdata = m_axil_wdata_reg;
assign m_axil_wstrb = m_axil_wstrb_reg;
assign m_axil_wvalid = m_axil_wvalid_reg;
assign m_axil_bready = m_axil_bready_reg;
integer i;
always @* begin
state_next = STATE_IDLE;
id_next = id_reg;
addr_next = addr_reg;
data_next = data_reg;
strb_next = strb_reg;
burst_next = burst_reg;
burst_size_next = burst_size_reg;
master_burst_size_next = master_burst_size_reg;
burst_active_next = burst_active_reg;
convert_burst_next = convert_burst_reg;
first_transfer_next = first_transfer_reg;
last_segment_next = last_segment_reg;
s_axi_awready_next = 1'b0;
s_axi_wready_next = 1'b0;
s_axi_bid_next = s_axi_bid_reg;
s_axi_bresp_next = s_axi_bresp_reg;
s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_bready;
m_axil_awaddr_next = m_axil_awaddr_reg;
m_axil_awprot_next = m_axil_awprot_reg;
m_axil_awvalid_next = m_axil_awvalid_reg && !m_axil_awready;
m_axil_wdata_next = m_axil_wdata_reg;
m_axil_wstrb_next = m_axil_wstrb_reg;
m_axil_wvalid_next = m_axil_wvalid_reg && !m_axil_wready;
m_axil_bready_next = 1'b0;
if (SEGMENT_COUNT == 1) begin
// master output is same width; direct transfer with no splitting/merging
case (state_reg)
STATE_IDLE: begin
// idle state; wait for new burst
s_axi_awready_next = !m_axil_awvalid;
first_transfer_next = 1'b1;
if (s_axi_awready && s_axi_awvalid) begin
s_axi_awready_next = 1'b0;
id_next = s_axi_awid;
m_axil_awaddr_next = s_axi_awaddr;
addr_next = s_axi_awaddr;
burst_next = s_axi_awlen;
burst_size_next = s_axi_awsize;
burst_active_next = 1'b1;
m_axil_awprot_next = s_axi_awprot;
m_axil_awvalid_next = 1'b1;
s_axi_wready_next = !m_axil_wvalid;
state_next = STATE_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
// data state; transfer write data
s_axi_wready_next = !m_axil_wvalid;
if (s_axi_wready && s_axi_wvalid) begin
m_axil_wdata_next = s_axi_wdata;
m_axil_wstrb_next = s_axi_wstrb;
m_axil_wvalid_next = 1'b1;
burst_next = burst_reg - 1;
burst_active_next = burst_reg != 0;
addr_next = addr_reg + (1 << burst_size_reg);
s_axi_wready_next = 1'b0;
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
state_next = STATE_RESP;
end else begin
state_next = STATE_DATA;
end
end
STATE_RESP: begin
// resp state; transfer write response
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
if (m_axil_bready && m_axil_bvalid) begin
m_axil_bready_next = 1'b0;
s_axi_bid_next = id_reg;
first_transfer_next = 1'b0;
if (first_transfer_reg || m_axil_bresp != 0) begin
s_axi_bresp_next = m_axil_bresp;
end
if (burst_active_reg) begin
// burst on slave interface still active; start new AXI lite write
m_axil_awaddr_next = addr_reg;
m_axil_awvalid_next = 1'b1;
s_axi_wready_next = !m_axil_wvalid;
state_next = STATE_DATA;
end else begin
// burst on slave interface finished; return to idle
s_axi_bvalid_next = 1'b1;
s_axi_awready_next = !m_axil_awvalid;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_RESP;
end
end
endcase
end else if (EXPAND) begin
// master output is wider; merge writes
case (state_reg)
STATE_IDLE: begin
// idle state; wait for new burst
s_axi_awready_next = !m_axil_awvalid;
first_transfer_next = 1'b1;
data_next = {DATA_WIDTH{1'b0}};
strb_next = {STRB_WIDTH{1'b0}};
if (s_axi_awready && s_axi_awvalid) begin
s_axi_awready_next = 1'b0;
id_next = s_axi_awid;
m_axil_awaddr_next = s_axi_awaddr;
addr_next = s_axi_awaddr;
burst_next = s_axi_awlen;
burst_size_next = s_axi_awsize;
if (CONVERT_BURST && s_axi_awcache[1] && (CONVERT_NARROW_BURST || s_axi_awsize == AXI_BURST_SIZE)) begin
// merge writes
// require CONVERT_BURST and awcache[1] set
convert_burst_next = 1'b1;
master_burst_size_next = AXIL_BURST_SIZE;
state_next = STATE_DATA_2;
end else begin
// output narrow burst
convert_burst_next = 1'b0;
master_burst_size_next = s_axi_awsize;
state_next = STATE_DATA;
end
m_axil_awprot_next = s_axi_awprot;
m_axil_awvalid_next = 1'b1;
s_axi_wready_next = !m_axil_wvalid;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
// data state; transfer write data
s_axi_wready_next = !m_axil_wvalid || m_axil_wready;
if (s_axi_wready && s_axi_wvalid) begin
m_axil_wdata_next = {(AXIL_WORD_WIDTH/AXI_WORD_WIDTH){s_axi_wdata}};
m_axil_wstrb_next = s_axi_wstrb << (addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB] * AXI_STRB_WIDTH);
m_axil_wvalid_next = 1'b1;
burst_next = burst_reg - 1;
burst_active_next = burst_reg != 0;
addr_next = addr_reg + (1 << burst_size_reg);
s_axi_wready_next = 1'b0;
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
state_next = STATE_RESP;
end else begin
state_next = STATE_DATA;
end
end
STATE_DATA_2: begin
s_axi_wready_next = !m_axil_wvalid;
if (s_axi_wready && s_axi_wvalid) begin
if (CONVERT_NARROW_BURST) begin
for (i = 0; i < AXI_WORD_WIDTH; i = i + 1) begin
if (s_axi_wstrb[i]) begin
data_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_DATA_WIDTH+i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE] = s_axi_wdata[i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE];
strb_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_STRB_WIDTH+i] = 1'b1;
end
end
end else begin
data_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = s_axi_wdata;
strb_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_STRB_WIDTH +: SEGMENT_STRB_WIDTH] = s_axi_wstrb;
end
m_axil_wdata_next = data_next;
m_axil_wstrb_next = strb_next;
burst_next = burst_reg - 1;
burst_active_next = burst_reg != 0;
addr_next = addr_reg + (1 << burst_size_reg);
if (burst_reg == 0 || addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
data_next = {DATA_WIDTH{1'b0}};
strb_next = {STRB_WIDTH{1'b0}};
m_axil_wvalid_next = 1'b1;
s_axi_wready_next = 1'b0;
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
state_next = STATE_RESP;
end else begin
state_next = STATE_DATA_2;
end
end else begin
state_next = STATE_DATA_2;
end
end
STATE_RESP: begin
// resp state; transfer write response
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
if (m_axil_bready && m_axil_bvalid) begin
m_axil_bready_next = 1'b0;
s_axi_bid_next = id_reg;
first_transfer_next = 1'b0;
if (first_transfer_reg || m_axil_bresp != 0) begin
s_axi_bresp_next = m_axil_bresp;
end
if (burst_active_reg) begin
// burst on slave interface still active; start new AXI lite write
m_axil_awaddr_next = addr_reg;
m_axil_awvalid_next = 1'b1;
s_axi_wready_next = !m_axil_wvalid || m_axil_wready;
if (convert_burst_reg) begin
state_next = STATE_DATA_2;
end else begin
state_next = STATE_DATA;
end
end else begin
// burst on slave interface finished; return to idle
s_axi_bvalid_next = 1'b1;
s_axi_awready_next = !m_axil_awvalid;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_RESP;
end
end
endcase
end else begin
// master output is narrower; split writes, and possibly split burst
case (state_reg)
STATE_IDLE: begin
// idle state; wait for new burst
s_axi_awready_next = !m_axil_awvalid;
first_transfer_next = 1'b1;
if (s_axi_awready && s_axi_awvalid) begin
s_axi_awready_next = 1'b0;
id_next = s_axi_awid;
m_axil_awaddr_next = s_axi_awaddr;
addr_next = s_axi_awaddr;
burst_next = s_axi_awlen;
burst_size_next = s_axi_awsize;
burst_active_next = 1'b1;
if (s_axi_awsize > AXIL_BURST_SIZE) begin
// need to adjust burst size
master_burst_size_next = AXIL_BURST_SIZE;
end else begin
// pass through narrow (enough) burst
master_burst_size_next = s_axi_awsize;
end
m_axil_awprot_next = s_axi_awprot;
m_axil_awvalid_next = 1'b1;
s_axi_wready_next = !m_axil_wvalid;
state_next = STATE_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
s_axi_wready_next = !m_axil_wvalid;
if (s_axi_wready && s_axi_wvalid) begin
data_next = s_axi_wdata;
strb_next = s_axi_wstrb;
m_axil_wdata_next = s_axi_wdata >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_DATA_WIDTH);
m_axil_wstrb_next = s_axi_wstrb >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_STRB_WIDTH);
m_axil_wvalid_next = 1'b1;
burst_next = burst_reg - 1;
burst_active_next = burst_reg != 0;
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
last_segment_next = addr_next[burst_size_reg] != addr_reg[burst_size_reg];
s_axi_wready_next = 1'b0;
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
state_next = STATE_RESP;
end else begin
state_next = STATE_DATA;
end
end
STATE_DATA_2: begin
s_axi_wready_next = 1'b0;
if (!m_axil_wvalid || m_axil_wready) begin
m_axil_wdata_next = data_reg >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_DATA_WIDTH);
m_axil_wstrb_next = strb_reg >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_STRB_WIDTH);
m_axil_wvalid_next = 1'b1;
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
last_segment_next = addr_next[burst_size_reg] != addr_reg[burst_size_reg];
s_axi_wready_next = 1'b0;
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
state_next = STATE_RESP;
end else begin
state_next = STATE_DATA_2;
end
end
STATE_RESP: begin
// resp state; transfer write response
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
if (m_axil_bready && m_axil_bvalid) begin
first_transfer_next = 1'b0;
m_axil_awaddr_next = addr_reg;
m_axil_bready_next = 1'b0;
s_axi_bid_next = id_reg;
if (first_transfer_reg || m_axil_bresp != 0) begin
s_axi_bresp_next = m_axil_bresp;
end
if (burst_active_reg || !last_segment_reg) begin
// burst on slave interface still active; start new burst
m_axil_awvalid_next = 1'b1;
if (last_segment_reg) begin
s_axi_wready_next = !m_axil_wvalid;
state_next = STATE_DATA;
end else begin
s_axi_wready_next = 1'b0;
state_next = STATE_DATA_2;
end
end else begin
// burst on slave interface finished; return to idle
s_axi_bvalid_next = 1'b1;
s_axi_awready_next = !m_axil_awvalid;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_RESP;
end
end
endcase
end
end
always @(posedge clk) begin
state_reg <= state_next;
id_reg <= id_next;
addr_reg <= addr_next;
data_reg <= data_next;
strb_reg <= strb_next;
burst_reg <= burst_next;
burst_size_reg <= burst_size_next;
master_burst_size_reg <= master_burst_size_next;
burst_active_reg <= burst_active_next;
convert_burst_reg <= convert_burst_next;
first_transfer_reg <= first_transfer_next;
last_segment_reg <= last_segment_next;
s_axi_awready_reg <= s_axi_awready_next;
s_axi_wready_reg <= s_axi_wready_next;
s_axi_bid_reg <= s_axi_bid_next;
s_axi_bresp_reg <= s_axi_bresp_next;
s_axi_bvalid_reg <= s_axi_bvalid_next;
m_axil_awaddr_reg <= m_axil_awaddr_next;
m_axil_awprot_reg <= m_axil_awprot_next;
m_axil_awvalid_reg <= m_axil_awvalid_next;
m_axil_wdata_reg <= m_axil_wdata_next;
m_axil_wstrb_reg <= m_axil_wstrb_next;
m_axil_wvalid_reg <= m_axil_wvalid_next;
m_axil_bready_reg <= m_axil_bready_next;
if (rst) begin
state_reg <= STATE_IDLE;
s_axi_awready_reg <= 1'b0;
s_axi_wready_reg <= 1'b0;
s_axi_bvalid_reg <= 1'b0;
m_axil_awvalid_reg <= 1'b0;
m_axil_wvalid_reg <= 1'b0;
m_axil_bready_reg <= 1'b0;
end
end
endmodule
`resetall

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`timescale 1ns / 1ps
module my_bram0 #(
parameter DATA_WIDTH = 32, // 数据位宽，默认 32 bit
parameter ADDR_WIDTH = 10 // 地址位宽 10 bit，对应深度 1024
)(
// ======== Port A (Write Only) ========
input wire clka,
input wire ena,
input wire wea,
input wire [ADDR_WIDTH-1:0] addra,
input wire [DATA_WIDTH-1:0] dina,
// ======== Port B (Read Only) ========
input wire clkb,
input wire enb,
input wire [ADDR_WIDTH-1:0] addrb,
output reg [DATA_WIDTH-1:0] doutb
);
// 声明二维数组作为存储介质
// 使用 (* ram_style = "block" *) 强制 Vivado 综合器将其映射为 BRAM 资源
(* ram_style = "block" *) reg [DATA_WIDTH-1:0] ram [0:(1<<ADDR_WIDTH)-1];
//-------------------------------------------------------
// Port A: 同步写入逻辑
//-------------------------------------------------------
always @(posedge clka) begin
// ena 是整个端口的使能，wea 是具体的写使能标志
// 在你的例化中 wea 恒为 1'b1，所以实际由 ena 控制写入
if (ena) begin
if (wea) begin
ram[addra] <= dina;
end
end
end
//-------------------------------------------------------
// Port B: 同步读出逻辑
//-------------------------------------------------------
always @(posedge clkb) begin
if (enb) begin
doutb <= ram[addrb];
end
end
endmodule

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rtl/ip/cdma/snix_async_fifo.sv Normal file
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// ============================================================================
// snix_async_fifo.sv
//
// SystemVerilog implementation of an async FIFO. If targeting FPGAs, this
// implementation is intended to infer BRAM.
//
// Largely based on ZipCPU's async FIFO work:
// https://zipcpu.com/blog/2018/07/06/afifo.html
// ============================================================================
module snix_async_fifo #(parameter DATA_WIDTH = 8,
parameter FIFO_DEPTH = 4)
(input logic wclk,
input logic wrst_n,
input logic wr_en,
input logic [DATA_WIDTH-1:0] wdata,
output logic wfull,
input logic rclk,
input logic rrst_n,
input logic rd_en,
output logic [DATA_WIDTH-1:0] rdata,
output logic [$clog2(FIFO_DEPTH):0] rd_n_items,
output logic rempty);
localparam ADDR_W = $clog2(FIFO_DEPTH);
localparam NFF = 2;
logic [ADDR_W:0] rd_addr, next_rd_addr;
logic [ADDR_W:0] wr_addr, next_wr_addr;
logic [ADDR_W:0] rgray, wgray;
logic [ADDR_W:0] rd_wgray, wr_rgray, rd_wbin;// rd_n_items;
(* ASYNC_REG = "TRUE" *) logic [(ADDR_W+1)*(NFF-1)-1:0] rgray_cross, wgray_cross;
(* ram_style = "block" *) logic [DATA_WIDTH-1:0] mem [0:FIFO_DEPTH-1];
logic [DATA_WIDTH-1:0] lcl_rd_data;
logic lcl_read, lcl_rd_empty;
assign next_wr_addr = wr_addr + 1'b1;
always_ff @(posedge wclk or negedge wrst_n)
if(!wrst_n) begin
wr_addr <= (ADDR_W+1)'(0);
wgray <= (ADDR_W+1)'(0);
end
else if(wr_en && !wfull) begin
wr_addr <= next_wr_addr;
wgray <= next_wr_addr ^ (next_wr_addr>>1);
end
always_ff @(posedge rclk or negedge rrst_n)
if(!rrst_n) begin
rd_addr <= (ADDR_W+1)'(0);
rgray <= (ADDR_W+1)'(0);
end
else if(lcl_read && !lcl_rd_empty) begin
rd_addr <= next_rd_addr;
rgray <= next_rd_addr ^ (next_rd_addr>>1);
end
always_ff @(posedge wclk)
mem[wr_addr[ADDR_W-1:0]] <= wdata;
assign next_rd_addr = rd_addr + 1'b1;
assign lcl_rd_data = mem[rd_addr[ADDR_W-1:0]];
always_ff @(posedge wclk or negedge wrst_n)
if(!wrst_n) begin
wr_rgray <= (ADDR_W+1)'(0);
rgray_cross <= (ADDR_W+1)'(0);
end
else begin
{wr_rgray, rgray_cross} <= {rgray_cross, rgray};
end
always_ff @(posedge rclk or negedge rrst_n)
if(!rrst_n) begin
rd_wgray <= (ADDR_W+1)'(0);
wgray_cross <= (ADDR_W+1)'(0);
rd_n_items <= (ADDR_W+1)'(0);
end
else begin
{rd_wgray, wgray_cross} <= {wgray_cross, wgray};
rd_n_items <= (rd_wbin - rd_addr) & ((1 << (ADDR_W + 1)) - 1);
end
always_comb begin
rd_wbin[ADDR_W] = rd_wgray[ADDR_W];
for (int i = ADDR_W-1; i >= 0; i--) begin
rd_wbin[i] = rd_wbin[i+1] ^ rd_wgray[i];
end
end
assign wfull = wr_rgray == {~wgray[ADDR_W], wgray[ADDR_W-1:0]};
assign lcl_rd_empty = rd_wgray == rgray;
assign lcl_read = rempty || rd_en;
always_ff @(posedge rclk or negedge rrst_n)
if(!rrst_n) begin
rempty <= 1'b1;
end
else if(lcl_read) begin
rempty <= lcl_rd_empty;
end
always_ff @(posedge rclk)
if(lcl_read)
rdata <= lcl_rd_data;
endmodule: snix_async_fifo

219
rtl/ip/cdma/snix_axi_cdma.sv Normal file
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// ============================================================================
// snix_axi_cdma.sv
// Central DMA — memory-to-memory transfers via snix_axi_mm2mm
//
// Instantiates:
// snix_axi_cdma_csr — AXI-Lite register interface
// snix_axi_mm2mm — read-then-write AXI4 engine
//
// Software register map (see snix_axi_cdma_csr.sv for full detail):
// 0x00 CDMA_CTRL [0]=start [1]=stop [5:3]=size [13:6]=len
// 0x04 CDMA_NUM_BYTES [31:0]=transfer_len
// 0x08 CDMA_SRC_ADDR [31:0]=source base address
// 0x0C CDMA_DST_ADDR [31:0]=destination base address
// 0x10 STATUS [0]=done (sticky, read-only)
// ============================================================================
module snix_axi_cdma #(
parameter int ADDR_WIDTH = 32,
parameter int DATA_WIDTH = 64,
parameter int AXIL_ADDR_WIDTH = 32,
parameter int AXIL_DATA_WIDTH = 32,
parameter int ID_WIDTH = 4,
parameter int USER_WIDTH = 1)
(// Global signals
input logic clk,
input logic rst_n,
// AXI-Lite CSR interface
input logic [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
input logic s_axil_awvalid,
output logic s_axil_awready,
input logic [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
input logic [AXIL_DATA_WIDTH/8-1:0] s_axil_wstrb,
input logic s_axil_wvalid,
output logic s_axil_wready,
output logic [1:0] s_axil_bresp,
output logic s_axil_bvalid,
input logic s_axil_bready,
input logic [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
input logic s_axil_arvalid,
output logic s_axil_arready,
output logic [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
output logic [1:0] s_axil_rresp,
output logic s_axil_rvalid,
input logic s_axil_rready,
// AXI4 memory port — AW channel
output logic [ID_WIDTH-1:0] mm2mm_awid,
output logic [ADDR_WIDTH-1:0] mm2mm_awaddr,
output logic [7:0] mm2mm_awlen,
output logic [2:0] mm2mm_awsize,
output logic [1:0] mm2mm_awburst,
output logic mm2mm_awlock,
output logic [3:0] mm2mm_awcache,
output logic [2:0] mm2mm_awprot,
output logic [3:0] mm2mm_awqos,
output logic [USER_WIDTH-1:0] mm2mm_awuser,
output logic mm2mm_awvalid,
input logic mm2mm_awready,
// W channel
output logic [DATA_WIDTH-1:0] mm2mm_wdata,
output logic [DATA_WIDTH/8-1:0] mm2mm_wstrb,
output logic mm2mm_wlast,
output logic [USER_WIDTH-1:0] mm2mm_wuser,
output logic mm2mm_wvalid,
input logic mm2mm_wready,
// B channel
input logic [ID_WIDTH-1:0] mm2mm_bid,
input logic [1:0] mm2mm_bresp,
input logic [USER_WIDTH-1:0] mm2mm_buser,
input logic mm2mm_bvalid,
output logic mm2mm_bready,
// AR channel
output logic [ID_WIDTH-1:0] mm2mm_arid,
output logic [ADDR_WIDTH-1:0] mm2mm_araddr,
output logic [7:0] mm2mm_arlen,
output logic [2:0] mm2mm_arsize,
output logic [1:0] mm2mm_arburst,
output logic mm2mm_arlock,
output logic [3:0] mm2mm_arcache,
output logic [2:0] mm2mm_arprot,
output logic [3:0] mm2mm_arqos,
output logic [USER_WIDTH-1:0] mm2mm_aruser,
output logic mm2mm_arvalid,
input logic mm2mm_arready,
// R channel
input logic [ID_WIDTH-1:0] mm2mm_rid,
input logic [DATA_WIDTH-1:0] mm2mm_rdata,
input logic [1:0] mm2mm_rresp,
input logic mm2mm_rlast,
input logic [USER_WIDTH-1:0] mm2mm_ruser,
input logic mm2mm_rvalid,
output logic mm2mm_rready,
output logic dma_finish);
localparam int NUM_REGS = 8;
localparam int FIFO_DEPTH = 16;
localparam int CDMA_CTRL_IDX = 0;
localparam int CDMA_NUM_BYTES_IDX = 1;
localparam int CDMA_SRC_ADDR_IDX = 2;
localparam int CDMA_DST_ADDR_IDX = 3;
// Index 4 = STATUS — write-protected inside snix_axi_cdma_csr
logic [NUM_REGS-1:0][AXIL_DATA_WIDTH-1:0] config_status_reg;
logic [AXIL_DATA_WIDTH-1:0] read_status_reg;
// -------------------------------------------------------------------------
// Decode control registers
// -------------------------------------------------------------------------
logic ctrl_start, ctrl_stop;
logic [2:0] ctrl_size;
logic [7:0] ctrl_len;
logic [31:0] ctrl_transfer_len;
logic [ADDR_WIDTH-1:0] ctrl_src_addr, ctrl_dst_addr;
logic ctrl_done;
assign ctrl_start = config_status_reg[CDMA_CTRL_IDX][0];
assign ctrl_stop = config_status_reg[CDMA_CTRL_IDX][1];
assign ctrl_size = config_status_reg[CDMA_CTRL_IDX][5:3];
assign ctrl_len = config_status_reg[CDMA_CTRL_IDX][13:6];
assign ctrl_transfer_len = config_status_reg[CDMA_NUM_BYTES_IDX];
assign ctrl_src_addr = config_status_reg[CDMA_SRC_ADDR_IDX][ADDR_WIDTH-1:0];
assign ctrl_dst_addr = config_status_reg[CDMA_DST_ADDR_IDX][ADDR_WIDTH-1:0];
assign read_status_reg = {{(AXIL_DATA_WIDTH-1){1'b0}}, ctrl_done};
assign dma_finish = ctrl_done;
// -------------------------------------------------------------------------
// CSR
// -------------------------------------------------------------------------
snix_axi_cdma_csr #(
.DATA_WIDTH(AXIL_DATA_WIDTH),
.ADDR_WIDTH(AXIL_ADDR_WIDTH),
.NUM_REGS (NUM_REGS))
cdma_csr (
.clk (clk),
.rst_n (rst_n),
.s_axil_awaddr (s_axil_awaddr),
.s_axil_awvalid (s_axil_awvalid),
.s_axil_awready (s_axil_awready),
.s_axil_wdata (s_axil_wdata),
.s_axil_wstrb (s_axil_wstrb),
.s_axil_wvalid (s_axil_wvalid),
.s_axil_wready (s_axil_wready),
.s_axil_bresp (s_axil_bresp),
.s_axil_bvalid (s_axil_bvalid),
.s_axil_bready (s_axil_bready),
.s_axil_araddr (s_axil_araddr),
.s_axil_arvalid (s_axil_arvalid),
.s_axil_arready (s_axil_arready),
.s_axil_rdata (s_axil_rdata),
.s_axil_rresp (s_axil_rresp),
.s_axil_rvalid (s_axil_rvalid),
.s_axil_rready (s_axil_rready),
.read_status_reg (read_status_reg),
.config_status_reg (config_status_reg));
// -------------------------------------------------------------------------
// MM2MM engine
// -------------------------------------------------------------------------
snix_axi_mm2mm #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.ID_WIDTH (ID_WIDTH),
.USER_WIDTH(USER_WIDTH),
.FIFO_DEPTH(FIFO_DEPTH))
axi_mm2mm (
.clk (clk),
.rst_n (rst_n),
.ctrl_start (ctrl_start),
.ctrl_stop (ctrl_stop),
.ctrl_src_addr (ctrl_src_addr),
.ctrl_dst_addr (ctrl_dst_addr),
.ctrl_len (ctrl_len),
.ctrl_size (ctrl_size),
.ctrl_transfer_len(ctrl_transfer_len),
.ctrl_done (ctrl_done),
.mm2mm_awid (mm2mm_awid),
.mm2mm_awaddr (mm2mm_awaddr),
.mm2mm_awlen (mm2mm_awlen),
.mm2mm_awsize (mm2mm_awsize),
.mm2mm_awburst (mm2mm_awburst),
.mm2mm_awlock (mm2mm_awlock),
.mm2mm_awcache (mm2mm_awcache),
.mm2mm_awprot (mm2mm_awprot),
.mm2mm_awqos (mm2mm_awqos),
.mm2mm_awuser (mm2mm_awuser),
.mm2mm_awvalid (mm2mm_awvalid),
.mm2mm_awready (mm2mm_awready),
.mm2mm_wdata (mm2mm_wdata),
.mm2mm_wstrb (mm2mm_wstrb),
.mm2mm_wlast (mm2mm_wlast),
.mm2mm_wuser (mm2mm_wuser),
.mm2mm_wvalid (mm2mm_wvalid),
.mm2mm_wready (mm2mm_wready),
.mm2mm_bid (mm2mm_bid),
.mm2mm_bresp (mm2mm_bresp),
.mm2mm_buser (mm2mm_buser),
.mm2mm_bvalid (mm2mm_bvalid),
.mm2mm_bready (mm2mm_bready),
.mm2mm_arid (mm2mm_arid),
.mm2mm_araddr (mm2mm_araddr),
.mm2mm_arlen (mm2mm_arlen),
.mm2mm_arsize (mm2mm_arsize),
.mm2mm_arburst (mm2mm_arburst),
.mm2mm_arlock (mm2mm_arlock),
.mm2mm_arcache (mm2mm_arcache),
.mm2mm_arprot (mm2mm_arprot),
.mm2mm_arqos (mm2mm_arqos),
.mm2mm_aruser (mm2mm_aruser),
.mm2mm_arvalid (mm2mm_arvalid),
.mm2mm_arready (mm2mm_arready),
.mm2mm_rid (mm2mm_rid),
.mm2mm_rdata (mm2mm_rdata),
.mm2mm_rresp (mm2mm_rresp),
.mm2mm_rlast (mm2mm_rlast),
.mm2mm_ruser (mm2mm_ruser),
.mm2mm_rvalid (mm2mm_rvalid),
.mm2mm_rready (mm2mm_rready));
endmodule : snix_axi_cdma

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// ============================================================================
// snix_axi_cdma_csr.sv
// AXI-Lite CSR for snix_axi_cdma (memory-to-memory central DMA)
//
// Register Map (word-addressed, 32-bit registers):
//
// Offset Index Name Bits
// 0x00 0 CDMA_CTRL [0] = start (write-1 pulse)
// [1] = stop (write-1 pulse)
// [5:3] = size (AXI AxSIZE)
// [13:6] = len (AXI AxLEN)
// [31:14] = reserved
// 0x04 1 CDMA_NUM_BYTES [31:0] = transfer_len (byte count)
// 0x08 2 CDMA_SRC_ADDR [31:0] = source base address
// 0x0C 3 CDMA_DST_ADDR [31:0] = destination base address
// 0x10 4 STATUS (read-only) [0] = done (sticky; cleared on start)
// [31:1] = reserved
// 0x14– 5–7 Reserved
//
// Differences from snix_axi_dma_csr:
// - Single CTRL register (no separate WR/RD paths)
// - Separate SRC_ADDR and DST_ADDR registers
// - STATUS[0] is write-protected; hardware sets it, start clears it
// ============================================================================
module snix_axi_cdma_csr #(
parameter int DATA_WIDTH = 32,
parameter int ADDR_WIDTH = 4,
parameter int NUM_REGS = 8)
(input logic clk,
input logic rst_n,
// AXI-Lite interface
input logic [ADDR_WIDTH-1:0] s_axil_awaddr,
input logic s_axil_awvalid,
output logic s_axil_awready,
input logic [DATA_WIDTH-1:0] s_axil_wdata,
input logic [DATA_WIDTH/8-1:0] s_axil_wstrb,
input logic s_axil_wvalid,
output logic s_axil_wready,
output logic [1:0] s_axil_bresp,
output logic s_axil_bvalid,
input logic s_axil_bready,
input logic [ADDR_WIDTH-1:0] s_axil_araddr,
input logic s_axil_arvalid,
output logic s_axil_arready,
output logic [DATA_WIDTH-1:0] s_axil_rdata,
output logic [1:0] s_axil_rresp,
output logic s_axil_rvalid,
input logic s_axil_rready,
// Status from mm2mm engine: [0] = ctrl_done (single-cycle pulse)
input logic [DATA_WIDTH-1:0] read_status_reg,
// Register file
output logic [NUM_REGS-1:0][DATA_WIDTH-1:0] config_status_reg);
localparam int AXIL_DATA_WIDTH = DATA_WIDTH;
localparam int AXIL_ADDR_WIDTH = ADDR_WIDTH;
localparam int ADDRLSB = $clog2(AXIL_DATA_WIDTH / 8);
localparam int REG_INDEX_WIDTH = $clog2(NUM_REGS);
localparam int CDMA_CTRL_IDX = 0; // 0x00 used: pulse-clear start/stop bits
//localparam int CDMA_NUM_BYTES_IDX = 1; // 0x04 decoded in snix_axi_cdma top
//localparam int CDMA_SRC_ADDR_IDX = 2; // 0x08 decoded in snix_axi_cdma top
//localparam int CDMA_DST_ADDR_IDX = 3; // 0x0C decoded in snix_axi_cdma top
localparam int STATUS_IDX = 4; // 0x10 used: write-protect + done latch
// -------------------------------------------------------------------------
// AXI-Lite skid-buffer register slices (same topology as snix_axi_dma_csr)
// -------------------------------------------------------------------------
logic s_axil_awvalid_reg;
logic [AXIL_ADDR_WIDTH-ADDRLSB-1:0] s_axil_awaddr_reg;
logic s_axil_arvalid_reg;
logic [AXIL_ADDR_WIDTH-ADDRLSB-1:0] s_axil_araddr_reg;
logic s_axil_wvalid_reg;
logic [AXIL_DATA_WIDTH-1:0] s_axil_wdata_reg;
logic [AXIL_DATA_WIDTH/8-1:0] s_axil_wstrb_reg;
logic s_axil_write_ready, s_axil_read_ready;
logic [31:0] awaddr_index, araddr_index;
assign s_axil_write_ready = s_axil_awvalid_reg & s_axil_wvalid_reg &
(!s_axil_bvalid | s_axil_bready);
assign s_axil_read_ready = s_axil_arvalid_reg & (!s_axil_rvalid | s_axil_rready);
assign awaddr_index = {{(32-REG_INDEX_WIDTH){1'b0}}, s_axil_awaddr_reg[REG_INDEX_WIDTH-1:0]};
assign araddr_index = {{(32-REG_INDEX_WIDTH){1'b0}}, s_axil_araddr_reg[REG_INDEX_WIDTH-1:0]};
snix_register_slice #(.DATA_WIDTH(AXIL_ADDR_WIDTH - ADDRLSB)) reg_slice_u0 (
.clk (clk),
.rst_n (rst_n),
.s_axis_tdata (s_axil_awaddr[AXIL_ADDR_WIDTH-1:ADDRLSB]),
.s_axis_tvalid(s_axil_awvalid),
.s_axis_tready(s_axil_awready),
.m_axis_tdata (s_axil_awaddr_reg),
.m_axis_tvalid(s_axil_awvalid_reg),
.m_axis_tready(s_axil_write_ready));
snix_register_slice #(.DATA_WIDTH(AXIL_DATA_WIDTH + AXIL_DATA_WIDTH/8)) reg_slice_u1 (
.clk (clk),
.rst_n (rst_n),
.s_axis_tdata ({s_axil_wdata, s_axil_wstrb}),
.s_axis_tvalid(s_axil_wvalid),
.s_axis_tready(s_axil_wready),
.m_axis_tdata ({s_axil_wdata_reg, s_axil_wstrb_reg}),
.m_axis_tvalid(s_axil_wvalid_reg),
.m_axis_tready(s_axil_write_ready));
snix_register_slice #(.DATA_WIDTH(AXIL_ADDR_WIDTH - ADDRLSB)) reg_slice_u2 (
.clk (clk),
.rst_n (rst_n),
.s_axis_tdata (s_axil_araddr[AXIL_ADDR_WIDTH-1:ADDRLSB]),
.s_axis_tvalid(s_axil_arvalid),
.s_axis_tready(s_axil_arready),
.m_axis_tdata (s_axil_araddr_reg),
.m_axis_tvalid(s_axil_arvalid_reg),
.m_axis_tready(s_axil_read_ready));
// -------------------------------------------------------------------------
// B channel
// -------------------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) s_axil_bvalid <= 1'b0;
else if (s_axil_write_ready) s_axil_bvalid <= 1'b1;
else if (s_axil_bready) s_axil_bvalid <= 1'b0;
// -------------------------------------------------------------------------
// R channel
// -------------------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) s_axil_rvalid <= 1'b0;
else if (s_axil_read_ready) s_axil_rvalid <= 1'b1;
else if (s_axil_rready) s_axil_rvalid <= 1'b0;
// -------------------------------------------------------------------------
// Control / status signal aliases (combinatorial from register file)
// -------------------------------------------------------------------------
logic ctrl_start, ctrl_stop, ctrl_done;
assign ctrl_start = config_status_reg[CDMA_CTRL_IDX][0];
assign ctrl_stop = config_status_reg[CDMA_CTRL_IDX][1];
assign ctrl_done = read_status_reg[0];
// -------------------------------------------------------------------------
// Register file
//
// Write priority (highest to lowest within an always_ff block):
// 1. AXI-Lite write (byte-enable; STATUS_IDX is write-protected)
// 2. Pulse-clear: start[0] and stop[1] are single-cycle strobes
// 3. STATUS latch: done bit set by hardware, cleared when start fires
//
// Note on NBA priority: later assignments in program order win, so
// "config_status_reg <= config_status_reg" is safely overridden by
// the per-bit assignments that follow in the else branch.
// -------------------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
config_status_reg <= '0;
end else if (s_axil_write_ready &&
awaddr_index < NUM_REGS &&
awaddr_index != STATUS_IDX) begin // STATUS is read-only
for (int i = 0; i < AXIL_DATA_WIDTH/8; i++) begin
config_status_reg[awaddr_index][8*i +: 8] <=
s_axil_wstrb_reg[i] ? s_axil_wdata_reg[8*i +: 8]
: config_status_reg[awaddr_index][8*i +: 8];
end
end else begin
config_status_reg <= config_status_reg;
// Pulse-clear: start and stop are one-cycle strobes
if (ctrl_start) config_status_reg[CDMA_CTRL_IDX][0] <= 1'b0;
if (ctrl_stop) config_status_reg[CDMA_CTRL_IDX][1] <= 1'b0;
// STATUS[0]: cleared when a new transfer starts; set sticky on done
if (ctrl_start) config_status_reg[STATUS_IDX][0] <= 1'b0;
if (ctrl_done) config_status_reg[STATUS_IDX][0] <= 1'b1;
end
end
// -------------------------------------------------------------------------
// Read data mux
// -------------------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n)
s_axil_rdata <= '0;
else if (s_axil_read_ready && araddr_index < NUM_REGS)
s_axil_rdata <= config_status_reg[araddr_index];
end
assign s_axil_bresp = 2'b00;
assign s_axil_rresp = 2'b00;
endmodule : snix_axi_cdma_csr

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module snix_axi_mm2mm #(parameter int ADDR_WIDTH = 32,
parameter int DATA_WIDTH = 64,
parameter int ID_WIDTH = 4,
parameter int USER_WIDTH = 1,
parameter int FIFO_DEPTH = 16)
(// Global signals
input logic clk,
input logic rst_n,
// Control interface
input logic ctrl_start,
input logic ctrl_stop,
input logic [ADDR_WIDTH-1:0] ctrl_src_addr,
input logic [ADDR_WIDTH-1:0] ctrl_dst_addr,
input logic [7:0] ctrl_len,
input logic [2:0] ctrl_size,
input logic [31:0] ctrl_transfer_len,
output logic ctrl_done,
// AW Channel
output logic [ID_WIDTH-1:0] mm2mm_awid,
output logic [ADDR_WIDTH-1:0] mm2mm_awaddr,
output logic [7:0] mm2mm_awlen,
output logic [2:0] mm2mm_awsize,
output logic [1:0] mm2mm_awburst,
output logic mm2mm_awlock,
output logic [3:0] mm2mm_awcache,
output logic [2:0] mm2mm_awprot,
output logic [3:0] mm2mm_awqos,
output logic [USER_WIDTH-1:0] mm2mm_awuser,
output logic mm2mm_awvalid,
input logic mm2mm_awready,
// W Channel
output logic [DATA_WIDTH-1:0] mm2mm_wdata,
output logic [DATA_WIDTH/8-1:0] mm2mm_wstrb,
output logic mm2mm_wlast,
output logic [USER_WIDTH-1:0] mm2mm_wuser,
output logic mm2mm_wvalid,
input logic mm2mm_wready,
// B Channel
input logic [ID_WIDTH-1:0] mm2mm_bid,
input logic [1:0] mm2mm_bresp,
input logic [USER_WIDTH-1:0] mm2mm_buser,
input logic mm2mm_bvalid,
output logic mm2mm_bready,
// AR Channel
output logic [ID_WIDTH-1:0] mm2mm_arid,
output logic [ADDR_WIDTH-1:0] mm2mm_araddr,
output logic [7:0] mm2mm_arlen,
output logic [2:0] mm2mm_arsize,
output logic [1:0] mm2mm_arburst,
output logic mm2mm_arlock,
output logic [3:0] mm2mm_arcache,
output logic [2:0] mm2mm_arprot,
output logic [3:0] mm2mm_arqos,
output logic [USER_WIDTH-1:0] mm2mm_aruser,
output logic mm2mm_arvalid,
input logic mm2mm_arready,
// R Channel
input logic [ID_WIDTH-1:0] mm2mm_rid,
input logic [DATA_WIDTH-1:0] mm2mm_rdata,
input logic [1:0] mm2mm_rresp,
input logic mm2mm_rlast,
input logic [USER_WIDTH-1:0] mm2mm_ruser,
input logic mm2mm_rvalid,
output logic mm2mm_rready
);
// -------------------------------------------------------------------------
// Local parameters
// -------------------------------------------------------------------------
localparam int STRB_WIDTH = DATA_WIDTH / 8;
localparam int STRB_IDX_WIDTH = $clog2(STRB_WIDTH) + 1; // +1 to hold full-width value
// -------------------------------------------------------------------------
// Start / stop edge detection
// -------------------------------------------------------------------------
logic ctrl_start_r, wr_start_edge;
logic ctrl_stop_r, wr_stop_edge;
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) begin
ctrl_start_r <= 1'b0;
ctrl_stop_r <= 1'b0;
end else begin
ctrl_start_r <= ctrl_start;
ctrl_stop_r <= ctrl_stop;
end
assign wr_start_edge = ctrl_start & ~ctrl_start_r;
assign wr_stop_edge = ctrl_stop & ~ctrl_stop_r;
// -------------------------------------------------------------------------
// Abort latch — set on stop edge, cleared on start edge
// -------------------------------------------------------------------------
logic wr_abort;
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) wr_abort <= 1'b0;
else if (wr_stop_edge) wr_abort <= 1'b1;
else if (wr_start_edge) wr_abort <= 1'b0;
// -------------------------------------------------------------------------
// FSM
// -------------------------------------------------------------------------
typedef enum logic [2:0] {IDLE, PREP1, PREP2, AR, READ, AW, WRITE, WAIT_BRESP} state_t;
state_t state, next_state;
logic transfer_done;
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) state <= IDLE;
else state <= next_state;
always_comb begin
next_state = state; // default holds state; prevents latches
case (state)
IDLE: begin
next_state = (ctrl_start && !wr_abort) ? PREP1 : IDLE;
end
PREP1: begin
next_state = wr_abort ? IDLE : PREP2;
end
PREP2: begin
next_state = AR;
end
AR: begin
if (wr_abort)
next_state = IDLE;
else
next_state = (mm2mm_arvalid && mm2mm_arready) ? READ : AR;
end
READ: begin
next_state = (mm2mm_rvalid && mm2mm_rready && mm2mm_rlast) ? AW : READ;
end
AW: begin
if (wr_abort)
next_state = IDLE;
else
next_state = (mm2mm_awvalid && mm2mm_awready) ? WRITE : AW;
end
WRITE: begin
next_state = (mm2mm_wvalid && mm2mm_wready && mm2mm_wlast) ? WAIT_BRESP : WRITE;
end
WAIT_BRESP: begin
if (mm2mm_bvalid && mm2mm_bready) begin
if (wr_abort || transfer_done)
next_state = IDLE;
else
next_state = PREP1;
end
end
default: ;
endcase
end
// -------------------------------------------------------------------------
// 4K boundary & burst-length computation — pipelined across PREP1 / PREP2
//
// Identical two-stage pipeline to s2mm / mm2s. The src address is used
// for the 4K check; burst_actual_bytes is applied to both pointers so
// they stay in lock-step.
//
// PREP1 [Stage 1]: max_len, next_size, src_axi_addr (all regs)
// → next_bytes → cross_4k → bytes_to_4k
// → register bytes_to_4k_r
//
// PREP2 [Stage 2]: bytes_to_4k_r, pending_bytes, next_size (all regs)
// → num_bytes_comb → next_len_o
// → register next_arlen / next_awlen | burst_actual_bytes
// -------------------------------------------------------------------------
logic [7:0] max_len;
logic [2:0] next_size;
logic [ADDR_WIDTH-1:0] src_axi_addr;
logic [ADDR_WIDTH-1:0] dst_axi_addr;
logic [31:0] pending_bytes;
// Stage 1 wires
logic [14:0] next_bytes;
logic cross_4k;
logic [14:0] bytes_to_4k;
// Stage 1 → Stage 2 pipeline register
logic [14:0] bytes_to_4k_r;
// Stage 2 wires
logic [14:0] num_bytes_comb;
logic [7:0] next_len_o;
// Stage 1 combinatorial
assign next_bytes = compute_num_bytes(max_len, next_size);
assign cross_4k = ({1'b0, next_bytes} + {4'b0, src_axi_addr[11:0]}) >= 16'd4096;
assign bytes_to_4k = cross_4k ? (15'd4096 - {3'b0, src_axi_addr[11:0]}) : next_bytes;
// Stage 2 combinatorial
assign num_bytes_comb = ({{17{1'b0}}, bytes_to_4k_r} <= pending_bytes)
? bytes_to_4k_r
: pending_bytes[14:0];
assign next_len_o = compute_next_len(num_bytes_comb, next_size);
// -------------------------------------------------------------------------
// Transfer-state registers
// -------------------------------------------------------------------------
logic [31:0] transfer_len;
logic [31:0] copied_bytes;
logic [7:0] next_arlen;
logic [7:0] next_awlen;
logic [14:0] burst_actual_bytes;
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) begin
src_axi_addr <= '0;
dst_axi_addr <= '0;
next_arlen <= '0;
next_awlen <= '0;
max_len <= '0;
next_size <= '0;
copied_bytes <= '0;
transfer_len <= '0;
bytes_to_4k_r <= '0;
burst_actual_bytes <= '0;
end else if (wr_start_edge) begin
src_axi_addr <= ctrl_src_addr;
dst_axi_addr <= ctrl_dst_addr;
next_arlen <= ctrl_len;
next_awlen <= ctrl_len;
max_len <= ctrl_len;
next_size <= ctrl_size;
copied_bytes <= '0;
transfer_len <= ctrl_transfer_len;
burst_actual_bytes <= '0;
end else if (state == PREP1) begin
bytes_to_4k_r <= bytes_to_4k;
end else if (state == PREP2) begin
next_arlen <= next_len_o;
next_awlen <= next_len_o;
burst_actual_bytes <= num_bytes_comb;
end else if (state == AR && mm2mm_arready) begin
src_axi_addr <= src_axi_addr + {{(ADDR_WIDTH-15){1'b0}}, burst_actual_bytes};
end else if (state == AW && mm2mm_awready) begin
dst_axi_addr <= dst_axi_addr + {{(ADDR_WIDTH-15){1'b0}}, burst_actual_bytes};
copied_bytes <= copied_bytes + {17'b0, burst_actual_bytes};
end
// pending_bytes — decremented in AR state after burst_actual_bytes is registered.
// TIMING FIX: reg(burst_actual_bytes) → subtractor → reg(pending_bytes)
always_ff @(posedge clk or negedge rst_n)
if (!rst_n)
pending_bytes <= '0;
else if (wr_start_edge)
pending_bytes <= ctrl_transfer_len;
else if (state == AR && mm2mm_arready)
pending_bytes <= pending_bytes - {17'b0, burst_actual_bytes};
// -------------------------------------------------------------------------
// Transfer-done flag
// -------------------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n)
if (!rst_n)
transfer_done <= 1'b0;
else if (wr_start_edge || state == IDLE || state == AR ||
state == PREP1 || state == PREP2)
transfer_done <= 1'b0;
else
transfer_done <= (copied_bytes == transfer_len) && (copied_bytes != '0);
// -------------------------------------------------------------------------
// ctrl_done — single-cycle pulse when FSM transitions into IDLE
// -------------------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) ctrl_done <= 1'b0;
else ctrl_done <= (next_state == IDLE) && (state != IDLE);
// -------------------------------------------------------------------------
// Beat counter — drives wlast
// -------------------------------------------------------------------------
logic [7:0] beat_cnt;
always_ff @(posedge clk or negedge rst_n)
if (!rst_n)
beat_cnt <= '0;
else if (state == AW && mm2mm_awready)
beat_cnt <= '0;
else if (mm2mm_wvalid && mm2mm_wready)
beat_cnt <= beat_cnt + 1'b1;
// -------------------------------------------------------------------------
// Write strobe generation for partial last beat
//
// partial_strb_mask uses a per-bit comparator loop rather than a hardcoded
// case statement, making it correct for any DATA_WIDTH (including 1024-bit).
// Synthesises as a parallel comparator tree with no barrel shifter.
// -------------------------------------------------------------------------
logic [14:0] bytes_in_burst;
logic [STRB_WIDTH-1:0] wstrb_mask;
logic [STRB_IDX_WIDTH-1:0] valid_bytes;
always_ff @(posedge clk or negedge rst_n)
if (!rst_n)
bytes_in_burst <= '0;
else if (state == AW && mm2mm_awready)
bytes_in_burst <= burst_actual_bytes;
else if (mm2mm_wvalid && mm2mm_wready)
bytes_in_burst <= (bytes_in_burst > STRB_WIDTH[14:0])
? (bytes_in_burst - STRB_WIDTH[14:0])
: '0;
assign valid_bytes = (bytes_in_burst <= STRB_WIDTH[14:0])
? bytes_in_burst[STRB_IDX_WIDTH-1:0]
: STRB_WIDTH[STRB_IDX_WIDTH-1:0];
logic [STRB_WIDTH-1:0] partial_strb_mask;
always_comb begin
for (int i = 0; i < STRB_WIDTH; i++)
partial_strb_mask[i] = (i < valid_bytes);
end
always_comb begin
if (mm2mm_wlast && (bytes_in_burst < STRB_WIDTH[14:0]) && (bytes_in_burst != '0))
wstrb_mask = partial_strb_mask;
else if (bytes_in_burst == '0)
wstrb_mask = '0;
else
wstrb_mask = {STRB_WIDTH{1'b1}};
end
// -------------------------------------------------------------------------
// FIFO — bridges R channel (read path) to W channel (write path)
//
// R-channel data is accepted only in READ state to prevent beats arriving
// before READ is entered from being silently dropped (same fix as mm2s).
// The write side drains only in WRITE state for symmetric gating.
// -------------------------------------------------------------------------
logic [DATA_WIDTH-1:0] fifo_tdata;
logic fifo_tvalid;
logic fifo_tlast;
logic fifo_tuser;
logic fifo_s_tready;
assign mm2mm_rready = fifo_s_tready && (state == READ);
snix_axis_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.FIFO_DEPTH(FIFO_DEPTH)
) axis_fifo_u0 (
.clk (clk),
.rst_n (rst_n),
.s_axis_tdata (mm2mm_rdata),
.s_axis_tlast (mm2mm_rlast),
.s_axis_tuser (1'b0),
.s_axis_tvalid (mm2mm_rvalid && (state == READ)),
.s_axis_tready (fifo_s_tready),
.m_axis_tdata (fifo_tdata),
.m_axis_tlast (fifo_tlast),
.m_axis_tuser (fifo_tuser),
.m_axis_tvalid (fifo_tvalid),
.m_axis_tready (mm2mm_wready && (state == WRITE))
);
// -------------------------------------------------------------------------
// AXI output assignments — AR channel
// -------------------------------------------------------------------------
assign mm2mm_arvalid = (state == AR);
assign mm2mm_araddr = src_axi_addr;
assign mm2mm_arlen = next_arlen;
assign mm2mm_arsize = next_size;
assign mm2mm_arburst = 2'b01;
assign mm2mm_arlock = 1'b0;
assign mm2mm_arcache = 4'b0;
assign mm2mm_arprot = 3'b0;
assign mm2mm_arqos = 4'b0;
assign mm2mm_arid = '0;
assign mm2mm_aruser = '0;
// -------------------------------------------------------------------------
// AXI output assignments — AW channel
// -------------------------------------------------------------------------
assign mm2mm_awvalid = (state == AW);
assign mm2mm_awaddr = dst_axi_addr;
assign mm2mm_awlen = next_awlen;
assign mm2mm_awsize = next_size;
assign mm2mm_awburst = 2'b01;
assign mm2mm_awlock = 1'b0;
assign mm2mm_awcache = 4'b0;
assign mm2mm_awprot = 3'b0;
assign mm2mm_awqos = 4'b0;
assign mm2mm_awid = '0;
assign mm2mm_awuser = '0;
// -------------------------------------------------------------------------
// AXI output assignments — W channel
// -------------------------------------------------------------------------
generate
for (genvar i = 0; i < STRB_WIDTH; i++) begin : gen_wdata_mask
assign mm2mm_wdata[i*8 +: 8] = wstrb_mask[i] ? fifo_tdata[i*8 +: 8] : 8'h00;
end
endgenerate
assign mm2mm_wvalid = (state == WRITE) && fifo_tvalid;
assign mm2mm_wlast = (beat_cnt == next_awlen) && mm2mm_wvalid;
assign mm2mm_wstrb = wstrb_mask;
assign mm2mm_wuser = '0;
// -------------------------------------------------------------------------
// AXI output assignments — B channel
// -------------------------------------------------------------------------
assign mm2mm_bready = (state == WAIT_BRESP);
// -------------------------------------------------------------------------
// Functions (identical to s2mm / mm2s)
// -------------------------------------------------------------------------
// Returns total byte count for an AXI burst: (len+1) << size.
function automatic [14:0] compute_num_bytes(
input logic [7:0] len,
input logic [2:0] size
);
case (size)
3'b000: compute_num_bytes = {7'b0, len + 1'b1};
3'b001: compute_num_bytes = {6'b0, len + 1'b1, 1'b0};
3'b010: compute_num_bytes = {5'b0, len + 1'b1, 2'b0};
3'b011: compute_num_bytes = {4'b0, len + 1'b1, 3'b0};
3'b100: compute_num_bytes = {3'b0, len + 1'b1, 4'b0};
3'b101: compute_num_bytes = {2'b0, len + 1'b1, 5'b0};
3'b110: compute_num_bytes = {1'b0, len + 1'b1, 6'b0};
3'b111: compute_num_bytes = { len + 1'b1, 7'b0};
endcase
endfunction
// Returns arlen/awlen = ceil(bytes / beat_size) - 1.
function automatic [7:0] compute_next_len(
input logic [14:0] bytes_i,
input logic [2:0] size
);
logic [14:0] num_beats;
case (size)
3'b000: num_beats = bytes_i;
3'b001: num_beats = (bytes_i + 15'd1) >> 1;
3'b010: num_beats = (bytes_i + 15'd3) >> 2;
3'b011: num_beats = (bytes_i + 15'd7) >> 3;
3'b100: num_beats = (bytes_i + 15'd15) >> 4;
3'b101: num_beats = (bytes_i + 15'd31) >> 5;
3'b110: num_beats = (bytes_i + 15'd63) >> 6;
3'b111: num_beats = (bytes_i + 15'd127) >> 7;
endcase
if (num_beats == 15'd0)
compute_next_len = 8'd0;
else
compute_next_len = num_beats[7:0] - 8'd1;
endfunction
endmodule : snix_axi_mm2mm

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// ============================================================================
// snix_axil_cdma_mux.sv
// Multi-Channel AXI-Lite MUX Wrapper for snix_axi_mm2mm engine
//
// Register Map (per channel, offset 0x40):
// 0x00: READ_ADDR (Source Address)
// 0x04: WRITE_ADDR (Destination Address)
// 0x08: LENGTH (Transfer length in bytes)
// 0x0C: TAG (User tag, purely for software tracking)
// 0x10: CTRL (Write 1 to bit 0 to trigger)
// [5:3] = AXI AxSIZE (0=1B, 1=2B, 2=4B, 3=8B...)
// [13:6] = AXI AxLEN (0=1 beat, 15=16 beats...)
// 0x14: STATUS (Bit 0: Busy RO, Bit 1: Done W1C)
// ============================================================================
`timescale 1ns / 1ps
module snix_axil_cdma_mux #(
parameter int ADDR_WIDTH = 32,
parameter int DATA_WIDTH = 32, // Matches engine default
parameter int AXIL_ADDR_WIDTH = 32,
parameter int AXIL_DATA_WIDTH = 32,
parameter int ID_WIDTH = 4,
parameter int USER_WIDTH = 1,
parameter int PORTS = 8,
parameter int FIFO_DEPTH = 16
) (
input logic clk,
input logic rst_n,
// ==========================================
// AXI-Lite Slave Interface (CPU CSR Access)
// ==========================================
input logic [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
input logic s_axil_awvalid,
output logic s_axil_awready,
input logic [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
input logic [AXIL_DATA_WIDTH/8-1:0] s_axil_wstrb,
input logic s_axil_wvalid,
output logic s_axil_wready,
output logic [1:0] s_axil_bresp,
output logic s_axil_bvalid,
input logic s_axil_bready,
input logic [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
input logic s_axil_arvalid,
output logic s_axil_arready,
output logic [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
output logic [1:0] s_axil_rresp,
output logic s_axil_rvalid,
input logic s_axil_rready,
// ==========================================
// AXI4 Master Interface (To Crossbar/Memory)
// ==========================================
output logic [ID_WIDTH-1:0] mm2mm_awid,
output logic [ADDR_WIDTH-1:0] mm2mm_awaddr,
output logic [7:0] mm2mm_awlen,
output logic [2:0] mm2mm_awsize,
output logic [1:0] mm2mm_awburst,
output logic mm2mm_awlock,
output logic [3:0] mm2mm_awcache,
output logic [2:0] mm2mm_awprot,
output logic [3:0] mm2mm_awqos,
output logic [USER_WIDTH-1:0] mm2mm_awuser,
output logic mm2mm_awvalid,
input logic mm2mm_awready,
output logic [DATA_WIDTH-1:0] mm2mm_wdata,
output logic [DATA_WIDTH/8-1:0] mm2mm_wstrb,
output logic mm2mm_wlast,
output logic [USER_WIDTH-1:0] mm2mm_wuser,
output logic mm2mm_wvalid,
input logic mm2mm_wready,
input logic [ID_WIDTH-1:0] mm2mm_bid,
input logic [1:0] mm2mm_bresp,
input logic [USER_WIDTH-1:0] mm2mm_buser,
input logic mm2mm_bvalid,
output logic mm2mm_bready,
output logic [ID_WIDTH-1:0] mm2mm_arid,
output logic [ADDR_WIDTH-1:0] mm2mm_araddr,
output logic [7:0] mm2mm_arlen,
output logic [2:0] mm2mm_arsize,
output logic [1:0] mm2mm_arburst,
output logic mm2mm_arlock,
output logic [3:0] mm2mm_arcache,
output logic [2:0] mm2mm_arprot,
output logic [3:0] mm2mm_arqos,
output logic [USER_WIDTH-1:0] mm2mm_aruser,
output logic mm2mm_arvalid,
input logic mm2mm_arready,
input logic [ID_WIDTH-1:0] mm2mm_rid,
input logic [DATA_WIDTH-1:0] mm2mm_rdata,
input logic [1:0] mm2mm_rresp,
input logic mm2mm_rlast,
input logic [USER_WIDTH-1:0] mm2mm_ruser,
input logic mm2mm_rvalid,
output logic mm2mm_rready,
// Global Interrupt (OR'd from all channels)
output logic dma_finish
);
// ==========================================
// Local Parameters & Utilities
// ==========================================
localparam int CH_BITS = $clog2(PORTS);
// Function to safely apply WSTRB to 32-bit registers
function automatic logic [31:0] apply_wstrb(
input logic [31:0] old_val,
input logic [31:0] new_val,
input logic [3:0] wstrb
);
logic [31:0] res;
res[7:0] = wstrb[0] ? new_val[7:0] : old_val[7:0];
res[15:8] = wstrb[1] ? new_val[15:8] : old_val[15:8];
res[23:16] = wstrb[2] ? new_val[23:16] : old_val[23:16];
res[31:24] = wstrb[3] ? new_val[31:24] : old_val[31:24];
return res;
endfunction
// ==========================================
// Internal Registers (Per Channel)
// ==========================================
logic [ADDR_WIDTH-1:0] ch_src_addr [PORTS];
logic [ADDR_WIDTH-1:0] ch_dst_addr [PORTS];
logic [31:0] ch_len [PORTS];
logic [31:0] ch_tag [PORTS];
logic [31:0] ch_ctrl [PORTS];
logic [PORTS-1:0] ch_req; // Pending requests (Busy)
logic [PORTS-1:0] ch_done; // Completion flags
logic [PORTS-1:0] arb_set_done; // From Arbiter to CSR
// ==========================================
// Address Decoding (0x40 offset per channel)
// ==========================================
wire [CH_BITS-1:0] wr_ch = s_axil_awaddr[6 +: CH_BITS];
wire [5:0] wr_reg = s_axil_awaddr[5:0];
wire [CH_BITS-1:0] rd_ch = s_axil_araddr[6 +: CH_BITS];
wire [5:0] rd_reg = s_axil_araddr[5:0];
// ==========================================
// AXI-Lite Slave Logic (Robust Backpressure)
// ==========================================
assign s_axil_bresp = 2'b00;
assign s_axil_rresp = 2'b00;
// Write Path Handshake
always_ff @(posedge clk) begin
if (!rst_n) begin
s_axil_awready <= 1'b0;
s_axil_wready <= 1'b0;
end else begin
if (s_axil_awvalid && s_axil_wvalid && !s_axil_awready && (!s_axil_bvalid || s_axil_bready)) begin
s_axil_awready <= 1'b1;
s_axil_wready <= 1'b1;
end else begin
s_axil_awready <= 1'b0;
s_axil_wready <= 1'b0;
end
end
end
wire do_write = s_axil_awready && s_axil_awvalid && s_axil_wready && s_axil_wvalid;
always_ff @(posedge clk) begin
if (!rst_n) begin
s_axil_bvalid <= 1'b0;
end else begin
if (do_write) begin
s_axil_bvalid <= 1'b1;
end else if (s_axil_bready && s_axil_bvalid) begin
s_axil_bvalid <= 1'b0;
end
end
end
// Read Path Handshake
always_ff @(posedge clk) begin
if (!rst_n) begin
s_axil_arready <= 1'b0;
end else begin
if (s_axil_arvalid && !s_axil_arready && (!s_axil_rvalid || s_axil_rready)) begin
s_axil_arready <= 1'b1;
end else begin
s_axil_arready <= 1'b0;
end
end
end
wire do_read = s_axil_arready && s_axil_arvalid;
always_ff @(posedge clk) begin
if (!rst_n) begin
s_axil_rvalid <= 1'b0;
s_axil_rdata <= '0;
end else begin
if (do_read) begin
s_axil_rvalid <= 1'b1;
if (rd_ch < PORTS) begin
case (rd_reg)
6'h00: s_axil_rdata <= ch_src_addr[rd_ch];
6'h04: s_axil_rdata <= ch_dst_addr[rd_ch];
6'h08: s_axil_rdata <= ch_len[rd_ch];
6'h0C: s_axil_rdata <= ch_tag[rd_ch];
6'h10: s_axil_rdata <= ch_ctrl[rd_ch];
6'h14: s_axil_rdata <= {30'd0, ch_done[rd_ch], ch_req[rd_ch]};
default: s_axil_rdata <= 32'd0;
endcase
end else begin
s_axil_rdata <= 32'd0; // Out of bounds
end
end else if (s_axil_rready && s_axil_rvalid) begin
s_axil_rvalid <= 1'b0;
end
end
end
// ==========================================
// Register File Write Logic
// ==========================================
assign dma_finish = |ch_done;
always_ff @(posedge clk) begin
if (!rst_n) begin
ch_req <= '0;
ch_done <= '0;
for (int i=0; i<PORTS; i++) begin
ch_src_addr[i] <= '0; ch_dst_addr[i] <= '0;
ch_len[i] <= '0; ch_tag[i] <= '0; ch_ctrl[i] <= '0;
end
end else begin
// 1. Process Hardware Status Updates (Highest Priority for Done flag)
for (int i=0; i<PORTS; i++) begin
if (arb_set_done[i]) begin
ch_req[i] <= 1'b0;
ch_done[i] <= 1'b1;
end
end
// 2. Process CPU Writes
if (do_write && wr_ch < PORTS) begin
case (wr_reg)
6'h00: if (!ch_req[wr_ch]) ch_src_addr[wr_ch] <= apply_wstrb(ch_src_addr[wr_ch], s_axil_wdata, s_axil_wstrb);
6'h04: if (!ch_req[wr_ch]) ch_dst_addr[wr_ch] <= apply_wstrb(ch_dst_addr[wr_ch], s_axil_wdata, s_axil_wstrb);
6'h08: if (!ch_req[wr_ch]) ch_len[wr_ch] <= apply_wstrb(ch_len[wr_ch], s_axil_wdata, s_axil_wstrb);
6'h0C: if (!ch_req[wr_ch]) ch_tag[wr_ch] <= apply_wstrb(ch_tag[wr_ch], s_axil_wdata, s_axil_wstrb);
6'h10: begin
ch_ctrl[wr_ch] <= apply_wstrb(ch_ctrl[wr_ch], s_axil_wdata, s_axil_wstrb);
// Trigger Bit Processing
if (s_axil_wstrb[0] && s_axil_wdata[0]) begin
ch_req[wr_ch] <= 1'b1;
// Clean up done bit automatically upon new start
if (!arb_set_done[wr_ch]) ch_done[wr_ch] <= 1'b0;
end
end
6'h14: begin
// Software W1C for Done flag (Bit 1)
// ONLY clear if hardware is not setting it in the exact same cycle
if (s_axil_wstrb[0] && s_axil_wdata[1]) begin
if (!arb_set_done[wr_ch]) ch_done[wr_ch] <= 1'b0;
end
end
endcase
end
end
end
// ==========================================
// Round-Robin Arbiter & Engine Driver
// ==========================================
typedef enum logic [1:0] {IDLE, RUN} state_t;
state_t state;
logic [CH_BITS-1:0] cur_ch;
logic [CH_BITS-1:0] rr_ptr;
// Interfaces to Engine
logic engine_start;
logic [ADDR_WIDTH-1:0] engine_src;
logic [ADDR_WIDTH-1:0] engine_dst;
logic [31:0] engine_bytes;
logic [7:0] engine_len;
logic [2:0] engine_size;
logic engine_done;
// Dynamic routing to the engine based on current active channel
assign engine_src = ch_src_addr[cur_ch];
assign engine_dst = ch_dst_addr[cur_ch];
assign engine_bytes = ch_len[cur_ch];
assign engine_len = ch_ctrl[cur_ch][13:6];
assign engine_size = ch_ctrl[cur_ch][5:3];
always_ff @(posedge clk) begin
if (!rst_n) begin
state <= IDLE;
engine_start <= 1'b0;
rr_ptr <= '0;
cur_ch <= '0;
arb_set_done <= '0;
end else begin
arb_set_done <= '0;
engine_start <= 1'b0;
case (state)
IDLE: begin
for (int i = 0; i < PORTS; i++) begin
logic [CH_BITS:0] check_ch_ext;
logic [CH_BITS-1:0] check_ch;
// Calculate next channel safely avoiding modulo operators in loop
check_ch_ext = {1'b0, rr_ptr} + i[CH_BITS:0];
check_ch = (check_ch_ext >= PORTS) ? (check_ch_ext - PORTS) : check_ch_ext[CH_BITS-1:0];
if (ch_req[check_ch] && !arb_set_done[check_ch]) begin
cur_ch <= check_ch;
rr_ptr <= (check_ch == (PORTS - 1)) ? '0 : (check_ch + 1);
engine_start <= 1'b1;
state <= RUN;
break;
end
end
end
RUN: begin
if (engine_done) begin
arb_set_done[cur_ch] <= 1'b1;
state <= IDLE;
end
// Optional: Add a watchdog timeout counter here if dealing with untrusted PCIe/AXI endpoints
end
endcase
end
end
// ==========================================
// Instantiate The Original Core Engine
// ==========================================
snix_axi_mm2mm #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.ID_WIDTH (ID_WIDTH),
.USER_WIDTH(USER_WIDTH),
.FIFO_DEPTH(FIFO_DEPTH)
) u_core_engine (
.clk (clk),
.rst_n (rst_n),
.ctrl_start (engine_start),
.ctrl_stop (1'b0), // Tied off; can be wired if global abort is needed
.ctrl_src_addr (engine_src),
.ctrl_dst_addr (engine_dst),
.ctrl_len (engine_len),
.ctrl_size (engine_size),
.ctrl_transfer_len (engine_bytes),
.ctrl_done (engine_done),
// AXI4 Port Connections
.mm2mm_awid (mm2mm_awid), .mm2mm_awaddr (mm2mm_awaddr),
.mm2mm_awlen (mm2mm_awlen), .mm2mm_awsize (mm2mm_awsize),
.mm2mm_awburst(mm2mm_awburst),.mm2mm_awlock (mm2mm_awlock),
.mm2mm_awcache(mm2mm_awcache),.mm2mm_awprot (mm2mm_awprot),
.mm2mm_awqos (mm2mm_awqos), .mm2mm_awuser (mm2mm_awuser),
.mm2mm_awvalid(mm2mm_awvalid),.mm2mm_awready(mm2mm_awready),
.mm2mm_wdata (mm2mm_wdata), .mm2mm_wstrb (mm2mm_wstrb),
.mm2mm_wlast (mm2mm_wlast), .mm2mm_wuser (mm2mm_wuser),
.mm2mm_wvalid (mm2mm_wvalid), .mm2mm_wready (mm2mm_wready),
.mm2mm_bid (mm2mm_bid), .mm2mm_bresp (mm2mm_bresp),
.mm2mm_buser (mm2mm_buser), .mm2mm_bvalid (mm2mm_bvalid),
.mm2mm_bready (mm2mm_bready),
.mm2mm_arid (mm2mm_arid), .mm2mm_araddr (mm2mm_araddr),
.mm2mm_arlen (mm2mm_arlen), .mm2mm_arsize (mm2mm_arsize),
.mm2mm_arburst(mm2mm_arburst),.mm2mm_arlock (mm2mm_arlock),
.mm2mm_arcache(mm2mm_arcache),.mm2mm_arprot (mm2mm_arprot),
.mm2mm_arqos (mm2mm_arqos), .mm2mm_aruser (mm2mm_aruser),
.mm2mm_arvalid(mm2mm_arvalid),.mm2mm_arready(mm2mm_arready),
.mm2mm_rid (mm2mm_rid), .mm2mm_rdata (mm2mm_rdata),
.mm2mm_rresp (mm2mm_rresp), .mm2mm_rlast (mm2mm_rlast),
.mm2mm_ruser (mm2mm_ruser), .mm2mm_rvalid (mm2mm_rvalid),
.mm2mm_rready (mm2mm_rready)
);
endmodule

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// ============================================================================
// snix_axis_fifo.sv
//
// AXI4-Stream FIFO with two operating modes selected by FRAME_FIFO:
//
// FRAME_FIFO = 0 (default) — streaming / cut-through
// Output valid asserts as soon as any data enters the FIFO.
// Downstream can begin reading before the full packet arrives.
//
// FRAME_FIFO = 1 — store-and-forward
// Output valid is suppressed until the complete packet (through tlast)
// has been written into the FIFO. Guarantees the downstream never
// sees a stalled mid-packet transfer.
// ============================================================================
module snix_axis_fifo #(
parameter int DATA_WIDTH = 32,
parameter int USER_WIDTH = 1,
parameter int FIFO_DEPTH = 16,
parameter bit FRAME_FIFO = 0 // 0 = streaming, 1 = store-and-forward
) (
input logic clk,
input logic rst_n,
// AXI4-Stream slave (input)
input logic [DATA_WIDTH-1:0] s_axis_tdata,
input logic [USER_WIDTH-1:0] s_axis_tuser,
input logic s_axis_tvalid,
input logic s_axis_tlast,
output logic s_axis_tready,
// AXI4-Stream master (output)
output logic [DATA_WIDTH-1:0] m_axis_tdata,
output logic [USER_WIDTH-1:0] m_axis_tuser,
output logic m_axis_tvalid,
output logic m_axis_tlast,
input logic m_axis_tready
);
localparam int AWIDTH = $clog2(FIFO_DEPTH);
// Internal FIFO signals
logic [DATA_WIDTH-1:0] fifo_tdata;
logic [USER_WIDTH-1:0] fifo_tuser;
logic fifo_tlast;
logic wr_en, rd_en;
logic fifo_full, fifo_empty;
logic [AWIDTH:0] fill_cnt;
// Handshake strobes
assign s_axis_tready = ~fifo_full;
assign wr_en = s_axis_tvalid & s_axis_tready;
assign rd_en = m_axis_tvalid & m_axis_tready;
// Output mapping
assign m_axis_tdata = fifo_tdata;
assign m_axis_tuser = fifo_tuser;
assign m_axis_tlast = fifo_tlast;
// -------------------------------------------------------------------------
// Output valid generation
//
// FRAME_FIFO = 1 : store-and-forward FSM
// IDLE -> STREAM when tlast is written into the FIFO
// STREAM -> IDLE when tlast is read out of the FIFO
//
// FRAME_FIFO = 0 : cut-through, valid tracks fifo_empty directly
// -------------------------------------------------------------------------
generate
if (FRAME_FIFO) begin : gen_frame_mode
typedef enum logic { IDLE, STREAM } state_t;
state_t state, nxt;
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) state <= IDLE;
else state <= nxt;
always_comb begin
nxt = state;
case (state)
IDLE: if (wr_en && s_axis_tlast) nxt = STREAM;
STREAM: if (rd_en && fifo_tlast) nxt = IDLE;
endcase
end
assign m_axis_tvalid = ~fifo_empty & (state == STREAM);
end else begin : gen_stream_mode
assign m_axis_tvalid = ~fifo_empty;
end
endgenerate
// -------------------------------------------------------------------------
// Sync FIFO instance — packs {tdata, tuser, tlast} into one word
// -------------------------------------------------------------------------
snix_sync_fifo #(
.DATA_WIDTH (DATA_WIDTH + USER_WIDTH + 1),
.FIFO_DEPTH (FIFO_DEPTH)
) u_fifo (
.clk (clk),
.rst_n (rst_n),
.data_i ({s_axis_tdata, s_axis_tuser, s_axis_tlast}),
.wr_en (wr_en),
.rd_en (rd_en),
.data_o ({fifo_tdata, fifo_tuser, fifo_tlast}),
.fifo_full (fifo_full),
.fifo_empty (fifo_empty),
.fill_cnt (fill_cnt)
);
endmodule : snix_axis_fifo

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// ============================================================================
// snix_register_slice.sv
//
// Generic ready/valid register slice (skid buffer).
//
// Same architecture as snix_axis_register but without tuser/tlast —
// used internally by the DMA and CDMA engines for pipeline decoupling
// on raw data paths.
// ============================================================================
module snix_register_slice #(
parameter DATA_WIDTH = 32
) (
input logic clk,
input logic rst_n,
// Input interface
input logic [DATA_WIDTH-1:0] s_axis_tdata,
input logic s_axis_tvalid,
output logic s_axis_tready,
// Output interface
output logic [DATA_WIDTH-1:0] m_axis_tdata,
output logic m_axis_tvalid,
input logic m_axis_tready
);
// Skid register
logic skid_valid;
logic [DATA_WIDTH-1:0] skid_data;
wire s_hsk = s_axis_tvalid & s_axis_tready;
wire m_stall = m_axis_tvalid & ~m_axis_tready;
// -----------------------------------------------------------------
// Skid valid
// -----------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n)
if (!rst_n)
skid_valid <= 1'b0;
else if (s_hsk & m_stall)
skid_valid <= 1'b1;
else if (m_axis_tready)
skid_valid <= 1'b0;
// -----------------------------------------------------------------
// Skid data
// -----------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n)
if (!rst_n)
skid_data <= '0;
else if (s_hsk)
skid_data <= s_axis_tdata;
// Ready when skid is empty
assign s_axis_tready = ~skid_valid;
// -----------------------------------------------------------------
// Output valid
// -----------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n)
if (!rst_n)
m_axis_tvalid <= 1'b0;
else if (~m_axis_tvalid | m_axis_tready)
m_axis_tvalid <= s_axis_tvalid | skid_valid;
// -----------------------------------------------------------------
// Output data — skid has priority
// -----------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n)
if (!rst_n)
m_axis_tdata <= '0;
else if (~m_axis_tvalid | m_axis_tready) begin
if (skid_valid)
m_axis_tdata <= skid_data;
else if (s_axis_tvalid)
m_axis_tdata <= s_axis_tdata;
end
endmodule : snix_register_slice

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// ============================================================================
// snix_sync_fifo.sv
//
// Synchronous FIFO with first-word-fall-through (FWFT) bypass.
//
// Architecture:
// - Dual-pointer circular buffer with MSB wrap-bit for full detection
// - Write-through bypass path: when the FIFO is empty and a write arrives,
// data is forwarded directly to the output without a one-cycle read delay
// - Block-RAM inference hint for FPGA targets
// ============================================================================
module snix_sync_fifo #(
parameter int DATA_WIDTH = 32,
parameter int FIFO_DEPTH = 16
) (
input logic clk,
input logic rst_n,
// Write port
input logic [DATA_WIDTH-1:0] data_i,
input logic wr_en,
// Read port
input logic rd_en,
output logic [DATA_WIDTH-1:0] data_o,
// Status
output logic [$clog2(FIFO_DEPTH):0] fill_cnt,
output logic fifo_full,
output logic fifo_empty
);
localparam int AWIDTH = $clog2(FIFO_DEPTH);
// Storage
(* ram_style="block" *)
logic [DATA_WIDTH-1:0] mem [0:FIFO_DEPTH-1];
// Pointers — extra MSB for wrap-around detection
logic [AWIDTH:0] wptr, rptr;
// Bypass (FWFT) path
logic [DATA_WIDTH-1:0] fwd_data;
logic fwd_valid;
// Qualified strobes
wire do_wr = wr_en & ~fifo_full;
wire do_rd = rd_en & ~fifo_empty;
// -----------------------------------------------------------------
// Write pointer
// -----------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n)
if (!rst_n)
wptr <= '0;
else if (do_wr)
wptr <= wptr + 1'b1;
// -----------------------------------------------------------------
// Read pointer
// -----------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n)
if (!rst_n)
rptr <= '0;
else if (do_rd)
rptr <= rptr + 1'b1;
// -----------------------------------------------------------------
// Memory write
// -----------------------------------------------------------------
always_ff @(posedge clk)
if (do_wr)
mem[wptr[AWIDTH-1:0]] <= data_i;
// -----------------------------------------------------------------
// Memory read — pre-fetch next location for FWFT
// -----------------------------------------------------------------
logic [DATA_WIDTH-1:0] mem_rd;
always_ff @(posedge clk)
if (do_rd)
mem_rd <= mem[rptr[AWIDTH-1:0] + 1'b1];
// -----------------------------------------------------------------
// Fill counter and empty flag
// -----------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) begin
fifo_empty <= 1'b1;
fill_cnt <= '0;
end else begin
case ({do_wr, do_rd})
2'b10: begin
fill_cnt <= fill_cnt + 1'b1;
fifo_empty <= 1'b0;
end
2'b01: begin
fill_cnt <= fill_cnt - 1'b1;
fifo_empty <= (fill_cnt <= 1);
end
default: ;
endcase
end
// Full flag — MSB of fill counter
assign fifo_full = fill_cnt[AWIDTH];
// -----------------------------------------------------------------
// FWFT bypass — forward write data directly when FIFO is empty
// -----------------------------------------------------------------
always_ff @(posedge clk or negedge rst_n)
if (!rst_n)
fwd_valid <= 1'b0;
else if (fifo_empty || rd_en) begin
if (!wr_en)
fwd_valid <= 1'b0;
else if (fifo_empty || (rd_en && fill_cnt == 1))
fwd_valid <= 1'b1;
else
fwd_valid <= 1'b0;
end
always_ff @(posedge clk)
if (fifo_empty || rd_en)
fwd_data <= data_i;
// Output mux — bypass path has priority
assign data_o = fwd_valid ? fwd_data : mem_rd;
endmodule : snix_sync_fifo

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`define CONFREG_INT_ADDR 16'hf000 //1f20_f000
`define TIMER_ADDR 16'hf100 //1f20_f100
`define DIGITAL_ADDR 16'hf200 //1f20_f200
`define LED_ADDR 16'hf300 //1f20_f300
`define SWITCH_ADDR 16'hf400 //1f20_f400
`define SIMU_FLAG_ADDR 16'hf500 //1f20_f500
module confreg #(
parameter SIMULATION=1'b0
)
(
input aclk,
input aresetn,
input cpu_clk,
input cpu_resetn,
input [4 :0] s_awid,
input [31:0] s_awaddr,
input [7 :0] s_awlen,
input [2 :0] s_awsize,
input [1 :0] s_awburst,
input s_awlock,
input [3 :0] s_awcache,
input [2 :0] s_awprot,
input s_awvalid,
output s_awready,
input [4 :0] s_wid,
input [31:0] s_wdata,
input [3 :0] s_wstrb,
input s_wlast,
input s_wvalid,
output reg s_wready,
output [4 :0] s_bid,
output [1 :0] s_bresp,
output reg s_bvalid,
input s_bready,
input [4 :0] s_arid,
input [31:0] s_araddr,
input [7 :0] s_arlen,
input [2 :0] s_arsize,
input [1 :0] s_arburst,
input s_arlock,
input [3 :0] s_arcache,
input [2 :0] s_arprot,
input s_arvalid,
output s_arready,
output [4 :0] s_rid,
output reg [31:0] s_rdata,
output [1 :0] s_rresp,
output reg s_rlast,
output reg s_rvalid,
input s_rready,
output [15:0] led,
output [7:0] dpy0,
output [7:0] dpy1,
input [31:0] switch,
input [3 :0] touch_btn,
input uart0_int,
input dma_finish,
input fft_finish,
output confreg_int
);
wire [3:0] touch_btn_data;//按键中断信号，上升沿触发
reg [31:0] led_data;
wire [31:0] switch_data;
reg [31:0] simu_flag;
reg [31:0] confreg_int_en,confreg_int_edge,confreg_int_pol,confreg_int_clr,confreg_int_set;
wire [31:0] confreg_int_state;
reg [31:0] sys_timer,sys_timer_cmp;
reg sys_timer_en;
reg timer_int;//定时器中断信号，高电平触发
reg [31:0] digital_ctrl;
reg [31:0] digital_data;
reg busy,write,R_or_W;
wire ar_enter = s_arvalid & s_arready;
wire r_retire = s_rvalid & s_rready & s_rlast;
wire aw_enter = s_awvalid & s_awready;
wire w_enter = s_wvalid & s_wready & s_wlast;
wire b_retire = s_bvalid & s_bready;
assign s_arready = ~busy & (!R_or_W| !s_awvalid);
assign s_awready = ~busy & ( R_or_W| !s_arvalid);
always@(posedge aclk)
if(~aresetn) busy <= 1'b0;
else if(ar_enter|aw_enter) busy <= 1'b1;
else if(r_retire|b_retire) busy <= 1'b0;
reg [4 :0] buf_id;
reg [31:0] buf_addr;
reg [7 :0] buf_len;
reg [2 :0] buf_size;
reg [1 :0] buf_burst;
reg buf_lock;
reg [3 :0] buf_cache;
reg [2 :0] buf_prot;
always@(posedge aclk)
if(~aresetn) begin
R_or_W <= 1'b0;
buf_id <= 'b0;
buf_addr <= 'b0;
buf_len <= 'b0;
buf_size <= 'b0;
buf_burst <= 'b0;
buf_lock <= 'b0;
buf_cache <= 'b0;
buf_prot <= 'b0;
end
else
if(ar_enter | aw_enter) begin
R_or_W <= ar_enter;
buf_id <= ar_enter ? s_arid : s_awid ;
buf_addr <= ar_enter ? s_araddr : s_awaddr ;
buf_len <= ar_enter ? s_arlen : s_awlen ;
buf_size <= ar_enter ? s_arsize : s_awsize ;
buf_burst <= ar_enter ? s_arburst: s_awburst;
buf_lock <= ar_enter ? s_arlock : s_awlock ;
buf_cache <= ar_enter ? s_arcache: s_awcache;
buf_prot <= ar_enter ? s_arprot : s_awprot ;
end
always@(posedge aclk)
if(~aresetn) write <= 1'b0;
else if(aw_enter) write <= 1'b1;
else if(ar_enter) write <= 1'b0;
always@(posedge aclk)
if(~aresetn) s_wready <= 1'b0;
else if(aw_enter) s_wready <= 1'b1;
else if(w_enter & s_wlast) s_wready <= 1'b0;
wire [31:0] rdata_d = buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h0) ? confreg_int_en :
buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h4) ? confreg_int_edge :
buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h8) ? confreg_int_pol :
buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'hc) ? confreg_int_clr :
buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h10) ? confreg_int_set :
buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h14) ? confreg_int_state :
buf_addr[15:0] == (`TIMER_ADDR + 16'h0) ? sys_timer :
buf_addr[15:0] == (`TIMER_ADDR + 16'h4) ? sys_timer_cmp :
buf_addr[15:0] == (`TIMER_ADDR + 16'h8) ? sys_timer_en :
buf_addr[15:0] == (`DIGITAL_ADDR + 16'h0) ? digital_ctrl :
buf_addr[15:0] == (`DIGITAL_ADDR + 16'h4) ? digital_data :
buf_addr[15:0] == `LED_ADDR ? led_data :
buf_addr[15:0] == `SWITCH_ADDR ? switch_data :
buf_addr[15:0] == `SIMU_FLAG_ADDR ? simu_flag :
32'd0;
always@(posedge aclk)
if(~aresetn) begin
s_rdata <= 'b0;
s_rvalid <= 1'b0;
s_rlast <= 1'b0;
end
else if(busy & !write & !r_retire)
begin
s_rdata <= rdata_d;
s_rvalid <= 1'b1;
s_rlast <= 1'b1;
end
else if(r_retire)
begin
s_rvalid <= 1'b0;
end
always@(posedge aclk)
if(~aresetn) s_bvalid <= 1'b0;
else if(w_enter) s_bvalid <= 1'b1;
else if(b_retire) s_bvalid <= 1'b0;
assign s_rid = buf_id;
assign s_bid = buf_id;
assign s_bresp = 2'b0;
assign s_rresp = 2'b0;
//-------------------------------{touch_btn}begin----------------------------//
assign touch_btn_data = touch_btn;
// genvar i;
// generate for(i=0;i<4;i=i+1) begin: generate_btn_debounce
// key_debounce u_key_debounce(
// .sys_clk(aclk),
// .key(touch_btn[i]),
// .key_out(touch_btn_data[i])
// );
// end
// endgenerate
//--------------------------------{touch_btn}end-----------------------------//
//-------------------------------{timer}begin----------------------------//
wire write_timer_cmp = w_enter & (buf_addr[15:0]==`TIMER_ADDR+16'h4);
wire write_timer_en = w_enter & (buf_addr[15:0]==`TIMER_ADDR+16'h8);
always @(posedge aclk) begin
if(!aresetn) begin
sys_timer_cmp <= 32'h0;
end
else if (write_timer_cmp) begin
sys_timer_cmp <= s_wdata;
end
end
always @(posedge aclk) begin
if(!aresetn) begin
sys_timer_en <= 1'b0;
end
else if (write_timer_en) begin
sys_timer_en <= s_wdata[0];
end
end
always @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
sys_timer <= 32'h0;
timer_int <= 1'b0;
end
else if (sys_timer_en) begin
if (sys_timer >= sys_timer_cmp - 1) begin
sys_timer <= 32'h0;
timer_int <= 1'b1;
end else begin
sys_timer <= sys_timer + 1'b1;
end
end
else begin
sys_timer <= 32'h0;
timer_int <= 1'b0;
end
end
//--------------------------------{timer}end-----------------------------//
//--------------------------------{led}begin-----------------------------//
//led display
//led_data[31:0]
wire write_led = w_enter & (buf_addr[15:0]==`LED_ADDR);
assign led = led_data[15:0];
always @(posedge aclk)
begin
if(!aresetn)
begin
led_data <= 32'h0;
end
else if(write_led)
begin
led_data <= s_wdata[31:0];
end
end
//---------------------------------{led}end------------------------------//
//-------------------------------{switch}begin---------------------------//
//switch data
//switch_data[31:0]
assign switch_data = switch;
//--------------------------------{switch}end----------------------------//
//---------------------------{digital number}begin-----------------------//
wire write_digital_ctrl = w_enter & (buf_addr[15:0]==`DIGITAL_ADDR + 16'h0);
wire write_digital_data = w_enter & (buf_addr[15:0]==`DIGITAL_ADDR + 16'h4);
always @(posedge aclk) begin
if(!aresetn) begin
digital_ctrl <= 32'd0;
end
else if (write_digital_ctrl) begin
digital_ctrl <= s_wdata;
end
end
always @(posedge aclk) begin
if(!aresetn) begin
digital_data <= 32'd0;
end
else if (write_digital_data) begin
digital_data <= s_wdata;
end
end
wire [31:0] digital_data_in = digital_data;
digitaltube_controller u_digitaltube_controller (
.control_reg ( digital_ctrl ),
.clk ( aclk ),
.rst_n ( aresetn ),
.dpy0 ( dpy0 ),
.dpy1 ( dpy1 ),
.data_reg ( digital_data_in )
);
//----------------------------{digital number}end------------------------//
//--------------------------{simulation flag}begin-----------------------//
always @(posedge aclk)
begin
if(!aresetn) begin
simu_flag <= {32{SIMULATION}};
end
else begin
simu_flag <= {32{SIMULATION}};
end
end
//---------------------------{simulation flag}end------------------------//
//-------------------------------{int_ctrl}begin----------------------------//
//add your code
wire [31:0] int_in;
wire [31:0] int_out;
wire write_int_en = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h0));
wire write_int_edge = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h4));
wire write_int_pol = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h8));
wire write_int_clr = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'hc));
wire write_int_set = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h10));
always @(posedge aclk) begin
if (!aresetn) begin
confreg_int_en <= 32'h0;
confreg_int_edge <= 32'h0;
confreg_int_pol <= 32'h0;
end else begin
if (write_int_en) confreg_int_en <= s_wdata;
if (write_int_edge) confreg_int_edge <= s_wdata;
if (write_int_pol) confreg_int_pol <= s_wdata;
end
end
always @(posedge aclk) begin
if (!aresetn) begin
confreg_int_clr <= 32'h0;
confreg_int_set <= 32'h0;
end else begin
confreg_int_clr <= write_int_clr ? s_wdata : 32'h0;
confreg_int_set <= write_int_set ? s_wdata : 32'h0;
end
end
assign int_in = {24'b0, dma_finish, fft_finish, uart0_int, timer_int, touch_btn_data};
int_ctrl u_int_ctrl (
.clk (aclk),
.resetn (aresetn),
.int_en (confreg_int_en),
.int_edge (confreg_int_edge),
.int_pol (confreg_int_pol),
.int_in (int_in),
.int_clr (confreg_int_clr),
.int_set (confreg_int_set),
.int_out (int_out)
);
assign confreg_int_state = int_out;
// int_out 进行或操作，再经过延迟打拍处理
reg int_out_or_q1;
reg int_out_or_q2;
always @(posedge aclk) begin
if (!aresetn) begin
int_out_or_q1 <= 1'b0;
int_out_or_q2 <= 1'b0;
end else begin
int_out_or_q1 <= |int_out;
int_out_or_q2 <= int_out_or_q1;
end
end
assign confreg_int = int_out_or_q2;
//--------------------------------{int_ctrl}end-----------------------------//
endmodule

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module digitaltube_controller(
// 输入配置寄存器 默认 32 位
// [1:0] 控制右边的数码管 ：00：灭 01：仅显示数字 10：显示数字和小数点
// [3:2] 控制左边数码管
input wire [31:0] control_reg,
// 数据寄存器 [15:0]
// 0x0000_000X [3:0] 对应第一个灯的显示
// 0x0000_00X0 [7:4] 对应第二个灯的显示
inout wire [31:0] data_reg,
input wire clk,
input wire rst_n,
output wire [7:0] dpy0, // dpy0
output wire [7:0] dpy1 // dpy1
);
// 内部寄存器定义
reg [7:0] dpy0_reg;
reg [7:0] dpy1_reg;
assign dpy0 = dpy0_reg;
assign dpy1 = dpy1_reg;
reg [3:0] dpy0_data; // dpy0 显示内容（4 位，0-F）
reg [3:0] dpy1_data; // dpy1 显示内容（4 位，0-F）
// 数码管段码存储
reg [6:0] seg_code [0:15]; // 存储 0-F 的编码
// 初始化数码管段码
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
seg_code[0] <= 7'b1000000; // 0
seg_code[1] <= 7'b1110110; // 1
seg_code[2] <= 7'b0100001; // 2
seg_code[3] <= 7'b0100100; // 3
seg_code[4] <= 7'b0010110; // 4
seg_code[5] <= 7'b0001100; // 5
seg_code[6] <= 7'b0001000; // 6
seg_code[7] <= 7'b1100110; // 7
seg_code[8] <= 7'b0000000; // 8
seg_code[9] <= 7'b0000110; // 9
seg_code[10] <= 7'b0000010; // A
seg_code[11] <= 7'b0011000; // B
seg_code[12] <= 7'b1001001; // C
seg_code[13] <= 7'b0110000; // D
seg_code[14] <= 7'b0001001; // E
seg_code[15] <= 7'b0001011; // F
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dpy0_reg <= 8'b0000_0000;
end
else begin
// 解析数据寄存器中的显示内容
dpy0_data <= data_reg[3:0]; // dpy0 显示的内容
// 根据 control_reg 控制显示
case (control_reg[1:0])
2'b01: begin
dpy0_reg <= {~seg_code[dpy0_data], 1'b0}; // 显示 dpy0
end
2'b10: begin
dpy0_reg <= {~seg_code[dpy0_data], 1'b1}; // 显示 dpy0和小数点
end
default: begin
dpy0_reg <= 8'b0000_0000;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dpy1_reg <= 8'b0000_0000;
end
else begin
// 解析数据寄存器中的显示内容
dpy1_data <= data_reg[7:4]; // dpy0 显示的内容
// 根据 control_reg 控制显示
case (control_reg[3:2])
2'b01: begin
dpy1_reg <= {~seg_code[dpy1_data], 1'b0}; // 显示 dpy0
end
2'b10: begin
dpy1_reg <= {~seg_code[dpy1_data], 1'b1}; // 显示 dpy0和小数点
end
default: begin
dpy1_reg <= 8'b0000_0000;
end
endcase
end
end
endmodule

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module int_ctrl (
input wire clk,
input wire resetn,
input wire [31:0] int_en,
input wire [31:0] int_edge,
input wire [31:0] int_pol,
input wire [31:0] int_in,
input wire [31:0] int_clr,
input wire [31:0] int_set,
output wire [31:0] int_out
);
// 同步异步输入信号，防止亚稳态
reg [31:0] int_in_sync_d1;
reg [31:0] int_in_sync_d2;
reg [31:0] int_in_sync_d3; // 用于边沿检测
always @(posedge clk or negedge resetn) begin
if (!resetn) begin
int_in_sync_d1 <= 32'b0;
int_in_sync_d2 <= 32'b0;
int_in_sync_d3 <= 32'b0;
end else begin
int_in_sync_d1 <= int_in;
int_in_sync_d2 <= int_in_sync_d1;
int_in_sync_d3 <= int_in_sync_d2;
end
end
// 生成同步后的边沿信号
wire [31:0] rising_edge = int_in_sync_d2 & ~int_in_sync_d3;
wire [31:0] falling_edge = ~int_in_sync_d2 & int_in_sync_d3;
// 边沿触发状态寄存器
reg [31:0] edge_int_state;
integer i;
always @(posedge clk or negedge resetn) begin
if (!resetn) begin
edge_int_state <= 32'b0;
end else begin
for (i = 0; i < 32; i = i + 1) begin
// 硬件检测优先级通常建议高于软件清除，防止丢失极窄脉冲
if (int_edge[i]) begin
if ((int_pol[i] && rising_edge[i]) || (!int_pol[i] && falling_edge[i]))
edge_int_state[i] <= 1'b1;
else if (int_set[i])
edge_int_state[i] <= 1'b1;
else if (int_clr[i])
edge_int_state[i] <= 1'b0;
end
end
end
end
// 电平触发逻辑
wire [31:0] level_int_state = int_in_sync_d2 ^ ~int_pol;
// 最终输出
assign int_out = int_en & ((int_edge & edge_int_state) | (~int_edge & level_int_state));
endmodule

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module key_debounce(
input sys_clk, //外部时钟20M
input key, //外部按键输入
output wire key_out //按键消抖后的数据
);
//reg define
reg [31:0] delay_cnt; //延时计数
reg key_reg;
reg key_value = 1'b1;
//*****************************************************
//** main code
//*****************************************************
always @(posedge sys_clk ) begin
key_reg <= key;
if(key_reg != key) //一旦检测到按键状态发生变化(有按键被按下或释放)
delay_cnt <= 32'd400000; //给延时计数器重新装载初始值（计数时间为 20ms）
else if(key_reg == key) begin //在按键状态稳定时，计数器递减，开始 20ms 倒计时
if(delay_cnt > 32'd0)
delay_cnt <= delay_cnt - 1'b1;
else
delay_cnt <= delay_cnt;
end
end
always @(posedge sys_clk ) begin
if(delay_cnt == 32'd1) begin //当计数器递减到 1 时，说明按键稳定状态维持了 20ms
key_value <= key; //并寄存此时按键的值
end
else begin
key_value <= key_out;
end
end
assign key_out = key & key_value ;
endmodule

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//----------------------------------------------------------------------
// Butterfly: Add/Sub and Scaling
//----------------------------------------------------------------------
module Butterfly #(
parameter WIDTH = 16,
parameter RH = 0 // Round Half Up
)(
input signed [WIDTH-1:0] x0_re, // Input Data #0 (Real)
input signed [WIDTH-1:0] x0_im, // Input Data #0 (Imag)
input signed [WIDTH-1:0] x1_re, // Input Data #1 (Real)
input signed [WIDTH-1:0] x1_im, // Input Data #1 (Imag)
output signed [WIDTH-1:0] y0_re, // Output Data #0 (Real)
output signed [WIDTH-1:0] y0_im, // Output Data #0 (Imag)
output signed [WIDTH-1:0] y1_re, // Output Data #1 (Real)
output signed [WIDTH-1:0] y1_im // Output Data #1 (Imag)
);
wire signed [WIDTH:0] add_re, add_im, sub_re, sub_im;
// Add/Sub
assign add_re = x0_re + x1_re;
assign add_im = x0_im + x1_im;
assign sub_re = x0_re - x1_re;
assign sub_im = x0_im - x1_im;
// Scaling
assign y0_re = (add_re + RH) >>> 1;
assign y0_im = (add_im + RH) >>> 1;
assign y1_re = (sub_re + RH) >>> 1;
assign y1_im = (sub_im + RH) >>> 1;
endmodule

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//----------------------------------------------------------------------
// DelayBuffer: Generate Constant Delay
//----------------------------------------------------------------------
module DelayBuffer #(
parameter DEPTH = 32,
parameter WIDTH = 16
)(
input clock, // Master Clock
input [WIDTH-1:0] di_re, // Data Input (Real)
input [WIDTH-1:0] di_im, // Data Input (Imag)
output [WIDTH-1:0] do_re, // Data Output (Real)
output [WIDTH-1:0] do_im // Data Output (Imag)
);
reg [WIDTH-1:0] buf_re[0:DEPTH-1];
reg [WIDTH-1:0] buf_im[0:DEPTH-1];
integer n;
// Shift Buffer
always @(posedge clock) begin
for (n = DEPTH-1; n > 0; n = n - 1) begin
buf_re[n] <= buf_re[n-1];
buf_im[n] <= buf_im[n-1];
end
buf_re[0] <= di_re;
buf_im[0] <= di_im;
end
assign do_re = buf_re[DEPTH-1];
assign do_im = buf_im[DEPTH-1];
endmodule

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//----------------------------------------------------------------------
// FFT: 1024-Point FFT Using Radix-2^2 Single-Path Delay Feedback
//----------------------------------------------------------------------
module FFT #(
parameter WIDTH = 32
)(
input clock, // Master Clock
input reset, // Active High Asynchronous Reset
input di_en, // Input Data Enable
input [WIDTH-1:0] di_re, // Input Data (Real)
input [WIDTH-1:0] di_im, // Input Data (Imag)
output do_en, // Output Data Enable
output [WIDTH-1:0] do_re, // Output Data (Real)
output [WIDTH-1:0] do_im // Output Data (Imag)
);
//----------------------------------------------------------------------
// Data must be input consecutively in natural order.
// The result is scaled to 1/N and output in bit-reversed order.
//----------------------------------------------------------------------
wire su1_do_en;
wire[WIDTH-1:0] su1_do_re;
wire[WIDTH-1:0] su1_do_im;
wire su2_do_en;
wire[WIDTH-1:0] su2_do_re;
wire[WIDTH-1:0] su2_do_im;
wire su3_do_en;
wire[WIDTH-1:0] su3_do_re;
wire[WIDTH-1:0] su3_do_im;
wire su4_do_en;
wire[WIDTH-1:0] su4_do_re;
wire[WIDTH-1:0] su4_do_im;
SdfUnit #(.N(1024),.M(1024),.WIDTH(WIDTH)) SU1 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (di_en ), // i
.di_re (di_re ), // i
.di_im (di_im ), // i
.do_en (su1_do_en ), // o
.do_re (su1_do_re ), // o
.do_im (su1_do_im ) // o
);
SdfUnit #(.N(1024),.M(256),.WIDTH(WIDTH)) SU2 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (su1_do_en ), // i
.di_re (su1_do_re ), // i
.di_im (su1_do_im ), // i
.do_en (su2_do_en ), // o
.do_re (su2_do_re ), // o
.do_im (su2_do_im ) // o
);
SdfUnit #(.N(1024),.M(64),.WIDTH(WIDTH)) SU3 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (su2_do_en ), // i
.di_re (su2_do_re ), // i
.di_im (su2_do_im ), // i
.do_en (su3_do_en ), // o
.do_re (su3_do_re ), // o
.do_im (su3_do_im ) // o
);
SdfUnit #(.N(1024),.M(16),.WIDTH(WIDTH)) SU4 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (su3_do_en ), // i
.di_re (su3_do_re ), // i
.di_im (su3_do_im ), // i
.do_en (su4_do_en ), // o
.do_re (su4_do_re ), // o
.do_im (su4_do_im ) // o
);
SdfUnit #(.N(1024),.M(4),.WIDTH(WIDTH)) SU5 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (su4_do_en ), // i
.di_re (su4_do_re ), // i
.di_im (su4_do_im ), // i
.do_en (do_en ), // o
.do_re (do_re ), // o
.do_im (do_im ) // o
);
endmodule

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//----------------------------------------------------------------------
// Multiply: Complex Multiplier
//----------------------------------------------------------------------
module Multiply #(
parameter WIDTH = 16
)(
input signed [WIDTH-1:0] a_re,
input signed [WIDTH-1:0] a_im,
input signed [WIDTH-1:0] b_re,
input signed [WIDTH-1:0] b_im,
output signed [WIDTH-1:0] m_re,
output signed [WIDTH-1:0] m_im
);
wire signed [WIDTH*2-1:0] arbr, arbi, aibr, aibi;
wire signed [WIDTH-1:0] sc_arbr, sc_arbi, sc_aibr, sc_aibi;
// Signed Multiplication
assign arbr = a_re * b_re;
assign arbi = a_re * b_im;
assign aibr = a_im * b_re;
assign aibi = a_im * b_im;
// Scaling
assign sc_arbr = arbr >>> (WIDTH-1);
assign sc_arbi = arbi >>> (WIDTH-1);
assign sc_aibr = aibr >>> (WIDTH-1);
assign sc_aibi = aibi >>> (WIDTH-1);
// Sub/Add
// These sub/add may overflow if unnormalized data is input.
assign m_re = sc_arbr - sc_aibi;
assign m_im = sc_arbi + sc_aibr;
endmodule

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//----------------------------------------------------------------------
// SdfUnit: Radix-2^2 Single-Path Delay Feedback Unit for N-Point FFT
//----------------------------------------------------------------------
module SdfUnit #(
parameter N = 64, // Number of FFT Point
parameter M = 64, // Twiddle Resolution
parameter WIDTH = 16 // Data Bit Length
)(
input clock, // Master Clock
input reset, // Active High Asynchronous Reset
input di_en, // Input Data Enable
input [WIDTH-1:0] di_re, // Input Data (Real)
input [WIDTH-1:0] di_im, // Input Data (Imag)
output do_en, // Output Data Enable
output [WIDTH-1:0] do_re, // Output Data (Real)
output [WIDTH-1:0] do_im // Output Data (Imag)
);
// log2 constant function
function integer log2;
input integer x;
integer value;
begin
value = x-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
localparam LOG_N = log2(N); // Bit Length of N
localparam LOG_M = log2(M); // Bit Length of M
//----------------------------------------------------------------------
// Internal Regs and Nets
//----------------------------------------------------------------------
// 1st Butterfly
reg [LOG_N-1:0] di_count; // Input Data Count
wire bf1_bf; // Butterfly Add/Sub Enable
wire[WIDTH-1:0] bf1_x0_re; // Data #0 to Butterfly (Real)
wire[WIDTH-1:0] bf1_x0_im; // Data #0 to Butterfly (Imag)
wire[WIDTH-1:0] bf1_x1_re; // Data #1 to Butterfly (Real)
wire[WIDTH-1:0] bf1_x1_im; // Data #1 to Butterfly (Imag)
wire[WIDTH-1:0] bf1_y0_re; // Data #0 from Butterfly (Real)
wire[WIDTH-1:0] bf1_y0_im; // Data #0 from Butterfly (Imag)
wire[WIDTH-1:0] bf1_y1_re; // Data #1 from Butterfly (Real)
wire[WIDTH-1:0] bf1_y1_im; // Data #1 from Butterfly (Imag)
wire[WIDTH-1:0] db1_di_re; // Data to DelayBuffer (Real)
wire[WIDTH-1:0] db1_di_im; // Data to DelayBuffer (Imag)
wire[WIDTH-1:0] db1_do_re; // Data from DelayBuffer (Real)
wire[WIDTH-1:0] db1_do_im; // Data from DelayBuffer (Imag)
wire[WIDTH-1:0] bf1_sp_re; // Single-Path Data Output (Real)
wire[WIDTH-1:0] bf1_sp_im; // Single-Path Data Output (Imag)
reg bf1_sp_en; // Single-Path Data Enable
reg [LOG_N-1:0] bf1_count; // Single-Path Data Count
wire bf1_start; // Single-Path Output Trigger
wire bf1_end; // End of Single-Path Data
wire bf1_mj; // Twiddle (-j) Enable
reg [WIDTH-1:0] bf1_do_re; // 1st Butterfly Output Data (Real)
reg [WIDTH-1:0] bf1_do_im; // 1st Butterfly Output Data (Imag)
// 2nd Butterfly
reg bf2_bf; // Butterfly Add/Sub Enable
wire[WIDTH-1:0] bf2_x0_re; // Data #0 to Butterfly (Real)
wire[WIDTH-1:0] bf2_x0_im; // Data #0 to Butterfly (Imag)
wire[WIDTH-1:0] bf2_x1_re; // Data #1 to Butterfly (Real)
wire[WIDTH-1:0] bf2_x1_im; // Data #1 to Butterfly (Imag)
wire[WIDTH-1:0] bf2_y0_re; // Data #0 from Butterfly (Real)
wire[WIDTH-1:0] bf2_y0_im; // Data #0 from Butterfly (Imag)
wire[WIDTH-1:0] bf2_y1_re; // Data #1 from Butterfly (Real)
wire[WIDTH-1:0] bf2_y1_im; // Data #1 from Butterfly (Imag)
wire[WIDTH-1:0] db2_di_re; // Data to DelayBuffer (Real)
wire[WIDTH-1:0] db2_di_im; // Data to DelayBuffer (Imag)
wire[WIDTH-1:0] db2_do_re; // Data from DelayBuffer (Real)
wire[WIDTH-1:0] db2_do_im; // Data from DelayBuffer (Imag)
wire[WIDTH-1:0] bf2_sp_re; // Single-Path Data Output (Real)
wire[WIDTH-1:0] bf2_sp_im; // Single-Path Data Output (Imag)
reg bf2_sp_en; // Single-Path Data Enable
reg [LOG_N-1:0] bf2_count; // Single-Path Data Count
reg bf2_start; // Single-Path Output Trigger
wire bf2_end; // End of Single-Path Data
reg [WIDTH-1:0] bf2_do_re; // 2nd Butterfly Output Data (Real)
reg [WIDTH-1:0] bf2_do_im; // 2nd Butterfly Output Data (Imag)
reg bf2_do_en; // 2nd Butterfly Output Data Enable
// Multiplication
wire[1:0] tw_sel; // Twiddle Select (2n/n/3n)
wire[LOG_N-3:0] tw_num; // Twiddle Number (n)
wire[LOG_N-1:0] tw_addr; // Twiddle Table Address
wire[WIDTH-1:0] tw_re; // Twiddle Factor (Real)
wire[WIDTH-1:0] tw_im; // Twiddle Factor (Imag)
reg mu_en; // Multiplication Enable
wire[WIDTH-1:0] mu_a_re; // Multiplier Input (Real)
wire[WIDTH-1:0] mu_a_im; // Multiplier Input (Imag)
wire[WIDTH-1:0] mu_m_re; // Multiplier Output (Real)
wire[WIDTH-1:0] mu_m_im; // Multiplier Output (Imag)
reg [WIDTH-1:0] mu_do_re; // Multiplication Output Data (Real)
reg [WIDTH-1:0] mu_do_im; // Multiplication Output Data (Imag)
reg mu_do_en; // Multiplication Output Data Enable
//----------------------------------------------------------------------
// 1st Butterfly
//----------------------------------------------------------------------
always @(posedge clock or posedge reset) begin
if (reset) begin
di_count <= {LOG_N{1'b0}};
end else begin
di_count <= di_en ? (di_count + 1'b1) : {LOG_N{1'b0}};
end
end
assign bf1_bf = di_count[LOG_M-1];
// Set unknown value x for verification
assign bf1_x0_re = bf1_bf ? db1_do_re : {WIDTH{1'bx}};
assign bf1_x0_im = bf1_bf ? db1_do_im : {WIDTH{1'bx}};
assign bf1_x1_re = bf1_bf ? di_re : {WIDTH{1'bx}};
assign bf1_x1_im = bf1_bf ? di_im : {WIDTH{1'bx}};
Butterfly #(.WIDTH(WIDTH),.RH(0)) BF1 (
.x0_re (bf1_x0_re ), // i
.x0_im (bf1_x0_im ), // i
.x1_re (bf1_x1_re ), // i
.x1_im (bf1_x1_im ), // i
.y0_re (bf1_y0_re ), // o
.y0_im (bf1_y0_im ), // o
.y1_re (bf1_y1_re ), // o
.y1_im (bf1_y1_im ) // o
);
DelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 (
.clock (clock ), // i
.di_re (db1_di_re ), // i
.di_im (db1_di_im ), // i
.do_re (db1_do_re ), // o
.do_im (db1_do_im ) // o
);
assign db1_di_re = bf1_bf ? bf1_y1_re : di_re;
assign db1_di_im = bf1_bf ? bf1_y1_im : di_im;
assign bf1_sp_re = bf1_bf ? bf1_y0_re : bf1_mj ? db1_do_im : db1_do_re;
assign bf1_sp_im = bf1_bf ? bf1_y0_im : bf1_mj ? -db1_do_re : db1_do_im;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf1_sp_en <= 1'b0;
bf1_count <= {LOG_N{1'b0}};
end else begin
bf1_sp_en <= bf1_start ? 1'b1 : bf1_end ? 1'b0 : bf1_sp_en;
bf1_count <= bf1_sp_en ? (bf1_count + 1'b1) : {LOG_N{1'b0}};
end
end
assign bf1_start = (di_count == (2**(LOG_M-1)-1));
assign bf1_end = (bf1_count == (2**LOG_N-1));
assign bf1_mj = (bf1_count[LOG_M-1:LOG_M-2] == 2'd3);
always @(posedge clock) begin
bf1_do_re <= bf1_sp_re;
bf1_do_im <= bf1_sp_im;
end
//----------------------------------------------------------------------
// 2nd Butterfly
//----------------------------------------------------------------------
always @(posedge clock) begin
bf2_bf <= bf1_count[LOG_M-2];
end
// Set unknown value x for verification
assign bf2_x0_re = bf2_bf ? db2_do_re : {WIDTH{1'bx}};
assign bf2_x0_im = bf2_bf ? db2_do_im : {WIDTH{1'bx}};
assign bf2_x1_re = bf2_bf ? bf1_do_re : {WIDTH{1'bx}};
assign bf2_x1_im = bf2_bf ? bf1_do_im : {WIDTH{1'bx}};
// Negative bias occurs when RH=0 and positive bias occurs when RH=1.
// Using both alternately reduces the overall rounding error.
Butterfly #(.WIDTH(WIDTH),.RH(1)) BF2 (
.x0_re (bf2_x0_re ), // i
.x0_im (bf2_x0_im ), // i
.x1_re (bf2_x1_re ), // i
.x1_im (bf2_x1_im ), // i
.y0_re (bf2_y0_re ), // o
.y0_im (bf2_y0_im ), // o
.y1_re (bf2_y1_re ), // o
.y1_im (bf2_y1_im ) // o
);
DelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 (
.clock (clock ), // i
.di_re (db2_di_re ), // i
.di_im (db2_di_im ), // i
.do_re (db2_do_re ), // o
.do_im (db2_do_im ) // o
);
assign db2_di_re = bf2_bf ? bf2_y1_re : bf1_do_re;
assign db2_di_im = bf2_bf ? bf2_y1_im : bf1_do_im;
assign bf2_sp_re = bf2_bf ? bf2_y0_re : db2_do_re;
assign bf2_sp_im = bf2_bf ? bf2_y0_im : db2_do_im;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf2_sp_en <= 1'b0;
bf2_count <= {LOG_N{1'b0}};
end else begin
bf2_sp_en <= bf2_start ? 1'b1 : bf2_end ? 1'b0 : bf2_sp_en;
bf2_count <= bf2_sp_en ? (bf2_count + 1'b1) : {LOG_N{1'b0}};
end
end
always @(posedge clock) begin
bf2_start <= (bf1_count == (2**(LOG_M-2)-1)) & bf1_sp_en;
end
assign bf2_end = (bf2_count == (2**LOG_N-1));
always @(posedge clock) begin
bf2_do_re <= bf2_sp_re;
bf2_do_im <= bf2_sp_im;
end
always @(posedge clock or posedge reset) begin
if (reset) begin
bf2_do_en <= 1'b0;
end else begin
bf2_do_en <= bf2_sp_en;
end
end
//----------------------------------------------------------------------
// Multiplication
//----------------------------------------------------------------------
assign tw_sel[1] = bf2_count[LOG_M-2];
assign tw_sel[0] = bf2_count[LOG_M-1];
assign tw_num = bf2_count << (LOG_N-LOG_M);
assign tw_addr = tw_num * tw_sel;
Twiddle TW (
.clock (clock ), // i
.addr (tw_addr), // i
.tw_re (tw_re ), // o
.tw_im (tw_im ) // o
);
// Multiplication is bypassed when twiddle address is 0.
always @(posedge clock) begin
mu_en <= (tw_addr != {LOG_N{1'b0}});
end
// Set unknown value x for verification
assign mu_a_re = mu_en ? bf2_do_re : {WIDTH{1'bx}};
assign mu_a_im = mu_en ? bf2_do_im : {WIDTH{1'bx}};
Multiply #(.WIDTH(WIDTH)) MU (
.a_re (mu_a_re), // i
.a_im (mu_a_im), // i
.b_re (tw_re ), // i
.b_im (tw_im ), // i
.m_re (mu_m_re), // o
.m_im (mu_m_im) // o
);
always @(posedge clock) begin
mu_do_re <= mu_en ? mu_m_re : bf2_do_re;
mu_do_im <= mu_en ? mu_m_im : bf2_do_im;
end
always @(posedge clock or posedge reset) begin
if (reset) begin
mu_do_en <= 1'b0;
end else begin
mu_do_en <= bf2_do_en;
end
end
// No multiplication required at final stage
assign do_en = (LOG_M == 2) ? bf2_do_en : mu_do_en;
assign do_re = (LOG_M == 2) ? bf2_do_re : mu_do_re;
assign do_im = (LOG_M == 2) ? bf2_do_im : mu_do_im;
endmodule

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`define FFT_CSR_ADDR 16'hf000
`define FFT_IN_RE_BASE 16'h1000
`define FFT_IN_IM_BASE 16'h2000
`define FFT_OUT_RE_BASE 16'h3000
`define FFT_OUT_IM_BASE 16'h4000
module fft_controller #(
parameter FFT_LEN = 1024, // FFT处理长度
parameter BRAM_RD_LATENCY = 2 // 适配 BRAM 的读延迟 (通常 Block RAM 开启输出寄存器为 2)
)(
input aclk,
input aresetn,
// AXI Lite / AXI4 Wrapper ports
input [4 :0] s_awid,
input [31:0] s_awaddr,
input [7 :0] s_awlen,
input [2 :0] s_awsize,
input [1 :0] s_awburst,
input s_awlock,
input [3 :0] s_awcache,
input [2 :0] s_awprot,
input s_awvalid,
output reg s_awready,
input [4 :0] s_wid,
input [31:0] s_wdata,
input [3 :0] s_wstrb,
input s_wlast,
input s_wvalid,
output reg s_wready,
output [4 :0] s_bid,
output [1 :0] s_bresp,
output reg s_bvalid,
input s_bready,
input [4 :0] s_arid,
input [31:0] s_araddr,
input [7 :0] s_arlen,
input [2 :0] s_arsize,
input [1 :0] s_arburst,
input s_arlock,
input [3 :0] s_arcache,
input [2 :0] s_arprot,
input s_arvalid,
output reg s_arready,
output [4 :0] s_rid,
output reg [31:0] s_rdata,
output [1 :0] s_rresp,
output reg s_rlast,
output reg s_rvalid,
input s_rready,
output fft_finish
);
// AXI Burst 内部寄存器
reg [31:0] aw_addr_reg;
reg [1 :0] aw_burst_reg;
reg [4 :0] aw_id_reg;
reg [31:0] ar_addr_reg;
reg [7 :0] ar_len_reg;
reg [1 :0] ar_burst_reg;
reg [4 :0] ar_id_reg;
reg [7 :0] ar_cnt;
// 写通道状态机 (AW, W, B)
localparam W_IDLE = 2'd0;
localparam W_DATA = 2'd1;
localparam W_RESP = 2'd2;
reg [1:0] w_state;
always @(posedge aclk) begin
if (~aresetn) begin
w_state <= W_IDLE;
s_awready <= 1'b1;
s_wready <= 1'b0;
s_bvalid <= 1'b0;
aw_addr_reg <= 32'h0;
aw_burst_reg <= 2'h0;
aw_id_reg <= 5'h0;
end else begin
case (w_state)
W_IDLE: begin
s_awready <= 1'b1;
if (s_awvalid && s_awready) begin
s_awready <= 1'b0;
s_wready <= 1'b1;
aw_addr_reg <= s_awaddr;
aw_burst_reg <= s_awburst;
aw_id_reg <= s_awid;
w_state <= W_DATA;
end
end
W_DATA: begin
// 接收到有效写数据
if (s_wvalid && s_wready) begin
// INCR 模式下地址递增
if (aw_burst_reg == 2'b01) begin
aw_addr_reg <= aw_addr_reg + 4;
end
// 若是最后一拍，跳转到发送响应
if (s_wlast) begin
s_wready <= 1'b0;
s_bvalid <= 1'b1;
w_state <= W_RESP;
end
end
end
W_RESP: begin
if (s_bvalid && s_bready) begin
s_bvalid <= 1'b0;
s_awready <= 1'b1; // 准备接收下一次写请求
w_state <= W_IDLE;
end
end
default: w_state <= W_IDLE;
endcase
end
end
// 产生有效的写动作脉冲，用于触发 BRAM 写使能
wire w_active = (w_state == W_DATA) && s_wvalid && s_wready;
assign s_bid = aw_id_reg;
assign s_bresp = 2'b00;
// 读通道状态机(AR, R)
localparam R_IDLE = 2'd0;
localparam R_WAIT = 2'd1;
localparam R_DATA = 2'd2;
reg [1:0] r_state;
reg [3:0] r_wait_cnt;
always @(posedge aclk) begin
if (~aresetn) begin
r_state <= R_IDLE;
s_arready <= 1'b1;
s_rvalid <= 1'b0;
s_rlast <= 1'b0;
ar_addr_reg <= 32'h0;
ar_len_reg <= 8'h0;
ar_burst_reg <= 2'h0;
ar_id_reg <= 5'h0;
ar_cnt <= 8'h0;
r_wait_cnt <= 4'h0;
end else begin
case (r_state)
R_IDLE: begin
s_arready <= 1'b1;
if (s_arvalid && s_arready) begin
s_arready <= 1'b0;
ar_addr_reg <= s_araddr;
ar_len_reg <= s_arlen;
ar_burst_reg <= s_arburst;
ar_id_reg <= s_arid;
ar_cnt <= 8'h0;
r_wait_cnt <= BRAM_RD_LATENCY;
r_state <= R_WAIT; // 进入等待以拉取第一笔 BRAM 数据
end
end
R_WAIT: begin
// 等待 BRAM 固定潜伏期结束
if (r_wait_cnt <= 1) begin
s_rvalid <= 1'b1;
s_rlast <= (ar_cnt == ar_len_reg);
r_state <= R_DATA;
r_wait_cnt <= 4'h0;
end else begin
r_wait_cnt <= r_wait_cnt - 1;
end
end
R_DATA: begin
// 数据被总线成功读取
if (s_rvalid && s_rready) begin
if (ar_cnt == ar_len_reg) begin
// Burst 结束
s_rvalid <= 1'b0;
s_rlast <= 1'b0;
s_arready <= 1'b1;
r_state <= R_IDLE;
end else begin
// 准备读取下一拍数据
ar_cnt <= ar_cnt + 1;
// INCR 模式下地址递增
if (ar_burst_reg == 2'b01) begin
ar_addr_reg <= ar_addr_reg + 4;
end
s_rvalid <= 1'b0;
s_rlast <= 1'b0;
r_wait_cnt <= BRAM_RD_LATENCY;
r_state <= R_WAIT; // 再次进入等待状态
end
end
end
default: r_state <= R_IDLE;
endcase
end
end
assign s_rid = ar_id_reg;
assign s_rresp = 2'b00;
// 地址译码
wire hit_in_re = (aw_addr_reg[15:12] == 4'h1);
wire hit_in_im = (aw_addr_reg[15:12] == 4'h2);
wire hit_out_re = (ar_addr_reg[15:12] == 4'h3);
wire hit_out_im = (ar_addr_reg[15:12] == 4'h4);
// 寄存器控制
reg [3:0] fft_ctrl;
reg [3:0] fft_status;
wire [31:0] fft_csr = {24'h0, fft_ctrl, fft_status};
// 只有发生有效的写握手且地址对应 CSR 时，才写入控制寄存器
wire write_fft_csr = w_active && (aw_addr_reg[15:0] == `FFT_CSR_ADDR);
// 状态机
localparam IDLE = 2'd0;
localparam LOAD = 2'd1;
localparam WAIT_OUT = 2'd2;
localparam DONE = 2'd3;
reg [1:0] state, next_state;
reg [10:0] in_cnt;
reg [10:0] out_cnt;
wire do_en;
wire [31:0] do_re;
wire [31:0] do_im;
always @(posedge aclk) begin
if (~aresetn) state <= IDLE;
else state <= next_state;
end
always @(*) begin
case (state)
IDLE: if (fft_ctrl[0]) next_state = LOAD; else next_state = IDLE;
LOAD: if (in_cnt == FFT_LEN - 1) next_state = WAIT_OUT; else next_state = LOAD;
WAIT_OUT: if (do_en && out_cnt == FFT_LEN - 1) next_state = DONE; else next_state = WAIT_OUT;
DONE: next_state = IDLE;
default: next_state = IDLE;
endcase
end
always @(posedge aclk) begin
if (~aresetn) begin
in_cnt <= 0;
out_cnt <= 0;
end else if (state == IDLE) begin
in_cnt <= 0;
out_cnt <= 0;
end else begin
if (state == LOAD) in_cnt <= in_cnt + 1;
if (do_en) out_cnt <= out_cnt + 1;
end
end
// 更新寄存器与状态
always @(posedge aclk) begin
if (~aresetn) begin
fft_ctrl <= 4'h0;
fft_status <= 4'h0;
end else begin
if (write_fft_csr) begin
fft_ctrl <= s_wdata[7:4];
end else if (state != IDLE) begin
fft_ctrl[0] <= 1'b0;
end
fft_status[0] <= (state != IDLE && state != DONE);
if (write_fft_csr && s_wdata[4]) begin
fft_status[1] <= 1'b0;
end else if (state == DONE) begin
fft_status[1] <= 1'b1;
end
end
end
assign fft_finish = fft_status[1];
// BRAM 接口连线
wire [31:0] in_re_dout;
wire [31:0] in_im_dout;
wire [31:0] out_re_dout;
wire [31:0] out_im_dout;
my_bram0 u_in0(
.clka (aclk),
.ena (w_active && hit_in_re), // 由 burst写逻辑产生
.wea (1'b1),
.addra (aw_addr_reg[11:2]), // 取当前递增的突发写地址
.dina (s_wdata),
.clkb (aclk),
.enb (state == LOAD),
.addrb (in_cnt[9:0]),
.doutb (in_re_dout)
);
my_bram0 u_in1(
.clka (aclk),
.ena (w_active && hit_in_im),
.wea (1'b1),
.addra (aw_addr_reg[11:2]),
.dina (s_wdata),
.clkb (aclk),
.enb (state == LOAD),
.addrb (in_cnt[9:0]),
.doutb (in_im_dout)
);
// 对于输出 BRAM，采用原先的位反转（Bit-reverse）读取逻辑
wire [9:0] b_rd_addr = ar_addr_reg[11:2];
wire [9:0] bit_reversed_index = {
b_rd_addr[0], b_rd_addr[1], b_rd_addr[2], b_rd_addr[3], b_rd_addr[4],
b_rd_addr[5], b_rd_addr[6], b_rd_addr[7], b_rd_addr[8], b_rd_addr[9]
};
my_bram0 u_out0(
.clka (aclk),
.ena (do_en),
.wea (1'b1),
.addra (out_cnt[9:0]),
.dina (do_re),
.clkb (aclk),
.enb (r_state != R_IDLE), // 当处于读突发事务时始终使能 BRAM
.addrb (bit_reversed_index),
.doutb (out_re_dout)
);
my_bram0 u_out1(
.clka (aclk),
.ena (do_en),
.wea (1'b1),
.addra (out_cnt[9:0]),
.dina (do_im),
.clkb (aclk),
.enb (r_state != R_IDLE),
.addrb (bit_reversed_index),
.doutb (out_im_dout)
);
// 支持 1 到 N 拍的读延迟，让 di_en 严格对齐 BRAM 的吐出数据
reg [3:0] di_en_shift;
always @(posedge aclk) begin
if (~aresetn) di_en_shift <= 0;
else di_en_shift <= {di_en_shift[2:0], (state == LOAD)};
end
wire di_en_r = (BRAM_RD_LATENCY == 1) ? di_en_shift[0] :
(BRAM_RD_LATENCY == 2) ? di_en_shift[1] :
(BRAM_RD_LATENCY == 3) ? di_en_shift[2] : di_en_shift[3];
FFT #(
.WIDTH(32)
) u_FFT (
.clock (aclk),
.reset (~aresetn),
.di_en (di_en_r),
.di_re (in_re_dout),
.di_im (in_im_dout),
.do_en (do_en),
.do_re (do_re),
.do_im (do_im)
);
// 读取返回数据选择
wire [31:0] rdata_d =
(ar_addr_reg[15:0] == `FFT_CSR_ADDR) ? fft_csr :
hit_out_re ? out_re_dout :
hit_out_im ? out_im_dout :
32'h0;
always @(*) begin
s_rdata = rdata_d;
end
endmodule

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module matmul_axi_slave (
input clk,
input resetn,
input [4:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input s_axi_awvalid,
output s_axi_awready,
input [4:0] s_axi_wid,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output reg [4:0] s_axi_bid,
output [1:0] s_axi_bresp,
output reg s_axi_bvalid,
input s_axi_bready,
input [4:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input s_axi_arvalid,
output s_axi_arready,
output reg [4:0] s_axi_rid,
output reg [31:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output reg s_axi_rvalid,
input s_axi_rready
);
localparam ADDR_CTRL = 12'h000;
localparam ADDR_STATUS = 12'h004;
localparam ADDR_SRC_BASE = 12'h008;
localparam ADDR_DST_BASE = 12'h00c;
localparam ADDR_GROUP_NUM = 12'h010;
localparam ADDR_A_BASE = 12'h020;
localparam ADDR_B_BASE = 12'h060;
localparam ADDR_C_BASE = 12'h0a0;
reg [31:0] src_base;
reg [31:0] dst_base;
reg [31:0] group_num;
reg [31:0] a_data [0:15];
reg [31:0] b_data [0:15];
reg [65:0] c_data [0:15];
reg [31:0] awaddr_hold;
reg [4:0] awid_hold;
reg aw_hold_valid;
reg [31:0] wdata_hold;
reg [3:0] wstrb_hold;
reg w_hold_valid;
reg busy;
reg done;
reg error;
reg [3:0] calc_index;
wire write_fire;
wire start_fire;
wire [11:0] write_offset = awaddr_hold[11:0];
wire [11:0] read_offset = s_axi_araddr[11:0];
assign s_axi_awready = !aw_hold_valid;
assign s_axi_wready = !w_hold_valid;
assign s_axi_bresp = 2'b00;
assign s_axi_arready = !s_axi_rvalid;
assign s_axi_rresp = 2'b00;
assign s_axi_rlast = 1'b1;
assign write_fire = aw_hold_valid && w_hold_valid && !s_axi_bvalid;
assign start_fire = write_fire && (write_offset == ADDR_CTRL) && wdata_hold[0] && !busy;
function [31:0] apply_wstrb;
input [31:0] old_value;
input [31:0] new_value;
input [3:0] strobe;
begin
apply_wstrb = old_value;
if (strobe[0]) apply_wstrb[7:0] = new_value[7:0];
if (strobe[1]) apply_wstrb[15:8] = new_value[15:8];
if (strobe[2]) apply_wstrb[23:16] = new_value[23:16];
if (strobe[3]) apply_wstrb[31:24] = new_value[31:24];
end
endfunction
function [63:0] mul_u32_shift_add;
input [31:0] lhs;
input [31:0] rhs;
integer bit_index;
begin
mul_u32_shift_add = 64'b0;
for (bit_index = 0; bit_index < 32; bit_index = bit_index + 1) begin
if (rhs[bit_index]) begin
mul_u32_shift_add = mul_u32_shift_add + ({32'b0, lhs} << bit_index);
end
end
end
endfunction
function [65:0] calc_c_element;
input [3:0] index;
reg [1:0] row;
reg [1:0] col;
begin
row = index[3:2];
col = index[1:0];
calc_c_element = {2'b0, mul_u32_shift_add(a_data[{row, 2'd0}], b_data[{2'd0, col}])}
+ {2'b0, mul_u32_shift_add(a_data[{row, 2'd1}], b_data[{2'd1, col}])}
+ {2'b0, mul_u32_shift_add(a_data[{row, 2'd2}], b_data[{2'd2, col}])}
+ {2'b0, mul_u32_shift_add(a_data[{row, 2'd3}], b_data[{2'd3, col}])};
end
endfunction
function [31:0] c_read_word;
input [5:0] word_index;
begin
case (word_index)
6'd0: c_read_word = c_data[0][31:0];
6'd1: c_read_word = c_data[0][63:32];
6'd2: c_read_word = {30'b0, c_data[0][65:64]};
6'd3: c_read_word = c_data[1][31:0];
6'd4: c_read_word = c_data[1][63:32];
6'd5: c_read_word = {30'b0, c_data[1][65:64]};
6'd6: c_read_word = c_data[2][31:0];
6'd7: c_read_word = c_data[2][63:32];
6'd8: c_read_word = {30'b0, c_data[2][65:64]};
6'd9: c_read_word = c_data[3][31:0];
6'd10: c_read_word = c_data[3][63:32];
6'd11: c_read_word = {30'b0, c_data[3][65:64]};
6'd12: c_read_word = c_data[4][31:0];
6'd13: c_read_word = c_data[4][63:32];
6'd14: c_read_word = {30'b0, c_data[4][65:64]};
6'd15: c_read_word = c_data[5][31:0];
6'd16: c_read_word = c_data[5][63:32];
6'd17: c_read_word = {30'b0, c_data[5][65:64]};
6'd18: c_read_word = c_data[6][31:0];
6'd19: c_read_word = c_data[6][63:32];
6'd20: c_read_word = {30'b0, c_data[6][65:64]};
6'd21: c_read_word = c_data[7][31:0];
6'd22: c_read_word = c_data[7][63:32];
6'd23: c_read_word = {30'b0, c_data[7][65:64]};
6'd24: c_read_word = c_data[8][31:0];
6'd25: c_read_word = c_data[8][63:32];
6'd26: c_read_word = {30'b0, c_data[8][65:64]};
6'd27: c_read_word = c_data[9][31:0];
6'd28: c_read_word = c_data[9][63:32];
6'd29: c_read_word = {30'b0, c_data[9][65:64]};
6'd30: c_read_word = c_data[10][31:0];
6'd31: c_read_word = c_data[10][63:32];
6'd32: c_read_word = {30'b0, c_data[10][65:64]};
6'd33: c_read_word = c_data[11][31:0];
6'd34: c_read_word = c_data[11][63:32];
6'd35: c_read_word = {30'b0, c_data[11][65:64]};
6'd36: c_read_word = c_data[12][31:0];
6'd37: c_read_word = c_data[12][63:32];
6'd38: c_read_word = {30'b0, c_data[12][65:64]};
6'd39: c_read_word = c_data[13][31:0];
6'd40: c_read_word = c_data[13][63:32];
6'd41: c_read_word = {30'b0, c_data[13][65:64]};
6'd42: c_read_word = c_data[14][31:0];
6'd43: c_read_word = c_data[14][63:32];
6'd44: c_read_word = {30'b0, c_data[14][65:64]};
6'd45: c_read_word = c_data[15][31:0];
6'd46: c_read_word = c_data[15][63:32];
6'd47: c_read_word = {30'b0, c_data[15][65:64]};
default: c_read_word = 32'b0;
endcase
end
endfunction
integer i;
always @(posedge clk) begin
if (!resetn) begin
src_base <= 32'b0;
dst_base <= 32'b0;
group_num <= 32'd1;
awaddr_hold <= 32'b0;
awid_hold <= 5'b0;
aw_hold_valid <= 1'b0;
wdata_hold <= 32'b0;
wstrb_hold <= 4'b0;
w_hold_valid <= 1'b0;
s_axi_bid <= 5'b0;
s_axi_bvalid <= 1'b0;
s_axi_rid <= 5'b0;
s_axi_rdata <= 32'b0;
s_axi_rvalid <= 1'b0;
busy <= 1'b0;
done <= 1'b0;
error <= 1'b0;
calc_index <= 4'b0;
for (i = 0; i < 16; i = i + 1) begin
a_data[i] <= 32'b0;
b_data[i] <= 32'b0;
c_data[i] <= 66'b0;
end
end else begin
if (s_axi_awvalid && s_axi_awready) begin
awaddr_hold <= s_axi_awaddr;
awid_hold <= s_axi_awid;
aw_hold_valid <= 1'b1;
end
if (s_axi_wvalid && s_axi_wready) begin
wdata_hold <= s_axi_wdata;
wstrb_hold <= s_axi_wstrb;
w_hold_valid <= 1'b1;
end
if (s_axi_bvalid && s_axi_bready) begin
s_axi_bvalid <= 1'b0;
end
if (write_fire) begin
s_axi_bid <= awid_hold;
s_axi_bvalid <= 1'b1;
aw_hold_valid <= 1'b0;
w_hold_valid <= 1'b0;
if (write_offset == ADDR_SRC_BASE) begin
src_base <= apply_wstrb(src_base, wdata_hold, wstrb_hold);
end else if (write_offset == ADDR_DST_BASE) begin
dst_base <= apply_wstrb(dst_base, wdata_hold, wstrb_hold);
end else if (write_offset == ADDR_GROUP_NUM) begin
group_num <= apply_wstrb(group_num, wdata_hold, wstrb_hold);
end else if ((write_offset >= ADDR_A_BASE) && (write_offset < ADDR_B_BASE)) begin
a_data[(write_offset - ADDR_A_BASE) >> 2] <=
apply_wstrb(a_data[(write_offset - ADDR_A_BASE) >> 2], wdata_hold, wstrb_hold);
end else if ((write_offset >= ADDR_B_BASE) && (write_offset < ADDR_C_BASE)) begin
b_data[(write_offset - ADDR_B_BASE) >> 2] <=
apply_wstrb(b_data[(write_offset - ADDR_B_BASE) >> 2], wdata_hold, wstrb_hold);
end else if (write_offset == ADDR_STATUS) begin
if (wdata_hold[1]) done <= 1'b0;
if (wdata_hold[2]) error <= 1'b0;
end else if ((write_offset != ADDR_CTRL) && (write_offset < ADDR_C_BASE)) begin
error <= 1'b1;
end
end
if (s_axi_arvalid && s_axi_arready) begin
s_axi_rid <= s_axi_arid;
s_axi_rvalid <= 1'b1;
if (read_offset == ADDR_CTRL) begin
s_axi_rdata <= 32'b0;
end else if (read_offset == ADDR_STATUS) begin
s_axi_rdata <= {29'b0, error, done, busy};
end else if (read_offset == ADDR_SRC_BASE) begin
s_axi_rdata <= src_base;
end else if (read_offset == ADDR_DST_BASE) begin
s_axi_rdata <= dst_base;
end else if (read_offset == ADDR_GROUP_NUM) begin
s_axi_rdata <= group_num;
end else if ((read_offset >= ADDR_A_BASE) && (read_offset < ADDR_B_BASE)) begin
s_axi_rdata <= a_data[(read_offset - ADDR_A_BASE) >> 2];
end else if ((read_offset >= ADDR_B_BASE) && (read_offset < ADDR_C_BASE)) begin
s_axi_rdata <= b_data[(read_offset - ADDR_B_BASE) >> 2];
end else if ((read_offset >= ADDR_C_BASE) && (read_offset < (ADDR_C_BASE + 12'h0c0))) begin
s_axi_rdata <= c_read_word((read_offset - ADDR_C_BASE) >> 2);
end else begin
s_axi_rdata <= 32'b0;
end
end else if (s_axi_rvalid && s_axi_rready) begin
s_axi_rvalid <= 1'b0;
end
if (start_fire) begin
busy <= 1'b1;
done <= 1'b0;
error <= 1'b0;
calc_index <= 4'd0;
end else if (busy) begin
c_data[calc_index] <= calc_c_element(calc_index);
if (calc_index == 4'd15) begin
busy <= 1'b0;
done <= 1'b1;
calc_index <= 4'd0;
end else begin
calc_index <= calc_index + 4'd1;
end
end
end
end
endmodule

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木兰宽松许可证, 第2版
木兰宽松许可证， 第2版
2020年1月 http://license.coscl.org.cn/MulanPSL2
您对“软件”的复制、使用、修改及分发受木兰宽松许可证，第2版（“本许可证”）的如下条款的约束：
0. 定义
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6. 语言
“本许可证”以中英文双语表述，中英文版本具有同等法律效力。如果中英文版本存在任何冲突不一致，以中文版为准。
条款结束
如何将木兰宽松许可证，第2版，应用到您的软件
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2， 请您在软件包的一级目录下创建以“LICENSE”为名的文件，将整个许可证文本放入该文件中；
3， 请将如下声明文本放入每个源文件的头部注释中。
Copyright (c) [Year] [name of copyright holder]
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# openLA500
## 前言
openLA500是一款实现了龙芯架构32位精简版指令集（loongarch32r）的处理器核。其结构为单发射五级流水，分为取指、译码、执行、访存、写回五个流水级。并且含有两路组相连结构的指令和数据cache；32项tlb；以及简易的分支预测器。此外，处理器核对外为AXI接口，容易集成。
OpenLA500已经过流片验证，.13工艺下频率为100M，dhrystone，coremark分数分别为0.78 DMIPS/MHz(指令数有点高)，2.75 coremark/Mhz。软件方面，uboot、linux 5.14、ucore、rt-thread等常用工具及内核已完成对openLA500的适配。
详细设计报告见doc目录。

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`include "csr.h"
module addr_trans
#(
parameter TLBNUM = 32
)
(
input clk ,
input [ 9:0] asid ,
//trans mode
input inst_addr_trans_en ,
input data_addr_trans_en ,
//inst addr trans
input inst_fetch ,
input [31:0] inst_vaddr ,
input inst_dmw0_en ,
input inst_dmw1_en ,
output [ 7:0] inst_index ,
output [19:0] inst_tag ,
output [ 3:0] inst_offset ,
output inst_tlb_found ,
output inst_tlb_v ,
output inst_tlb_d ,
output [ 1:0] inst_tlb_mat ,
output [ 1:0] inst_tlb_plv ,
//data addr trans
input data_fetch ,
input [31:0] data_vaddr ,
input data_dmw0_en ,
input data_dmw1_en ,
input cacop_op_mode_di ,
output [ 7:0] data_index ,
output [19:0] data_tag ,
output [ 3:0] data_offset ,
output data_tlb_found ,
output [ 4:0] data_tlb_index ,
output data_tlb_v ,
output data_tlb_d ,
output [ 1:0] data_tlb_mat ,
output [ 1:0] data_tlb_plv ,
//tlbwi tlbwr tlb write
input tlbfill_en ,
input tlbwr_en ,
input [ 4:0] rand_index ,
input [31:0] tlbehi_in ,
input [31:0] tlbelo0_in ,
input [31:0] tlbelo1_in ,
input [31:0] tlbidx_in ,
input [ 5:0] ecode_in ,
//tlbr tlb read
output [31:0] tlbehi_out ,
output [31:0] tlbelo0_out ,
output [31:0] tlbelo1_out ,
output [31:0] tlbidx_out ,
output [ 9:0] asid_out ,
//invtlb
input invtlb_en ,
input [ 9:0] invtlb_asid ,
input [18:0] invtlb_vpn ,
input [ 4:0] invtlb_op ,
//from csr
input [31:0] csr_dmw0 ,
input [31:0] csr_dmw1 ,
input csr_da ,
input csr_pg
);
wire [18:0] s0_vppn ;
wire s0_odd_page ;
wire [ 5:0] s0_ps ;
wire [19:0] s0_ppn ;
wire [18:0] s1_vppn ;
wire s1_odd_page ;
wire [ 5:0] s1_ps ;
wire [19:0] s1_ppn ;
wire we ;
wire [ 4:0] w_index ;
wire [18:0] w_vppn ;
wire w_g ;
wire [ 5:0] w_ps ;
wire w_e ;
wire w_v0 ;
wire w_d0 ;
wire [ 1:0] w_mat0 ;
wire [ 1:0] w_plv0 ;
wire [19:0] w_ppn0 ;
wire w_v1 ;
wire w_d1 ;
wire [ 1:0] w_mat1 ;
wire [ 1:0] w_plv1 ;
wire [19:0] w_ppn1 ;
wire [ 4:0] r_index ;
wire [18:0] r_vppn ;
wire [ 9:0] r_asid ;
wire r_g ;
wire [ 5:0] r_ps ;
wire r_e ;
wire r_v0 ;
wire r_d0 ;
wire [ 1:0] r_mat0 ;
wire [ 1:0] r_plv0 ;
wire [19:0] r_ppn0 ;
wire r_v1 ;
wire r_d1 ;
wire [ 1:0] r_mat1 ;
wire [ 1:0] r_plv1 ;
wire [19:0] r_ppn1 ;
reg [31:0] inst_vaddr_buffer ;
reg [31:0] data_vaddr_buffer ;
wire [31:0] inst_paddr;
wire [31:0] data_paddr;
wire pg_mode;
wire da_mode;
always @(posedge clk) begin
if (inst_fetch) begin
inst_vaddr_buffer <= inst_vaddr;
end
if (data_fetch) begin
data_vaddr_buffer <= data_vaddr;
end
end
//trans search port sig
assign s0_vppn = inst_vaddr[31:13];
assign s0_odd_page = inst_vaddr[12];
assign s1_vppn = data_vaddr[31:13];
assign s1_odd_page = data_vaddr[12];
//trans write port sig
assign we = tlbfill_en || tlbwr_en;
assign w_index = ({5{tlbfill_en}} & rand_index) | ({5{tlbwr_en}} & tlbidx_in[`INDEX]);
assign w_vppn = tlbehi_in[`VPPN];
assign w_g = tlbelo0_in[`TLB_G] && tlbelo1_in[`TLB_G];
assign w_ps = tlbidx_in[`PS];
assign w_e = (ecode_in == 6'h3f) ? 1'b1 : !tlbidx_in[`NE];
assign w_v0 = tlbelo0_in[`TLB_V];
assign w_d0 = tlbelo0_in[`TLB_D];
assign w_plv0 = tlbelo0_in[`TLB_PLV];
assign w_mat0 = tlbelo0_in[`TLB_MAT];
assign w_ppn0 = tlbelo0_in[`TLB_PPN_EN];
assign w_v1 = tlbelo1_in[`TLB_V];
assign w_d1 = tlbelo1_in[`TLB_D];
assign w_plv1 = tlbelo1_in[`TLB_PLV];
assign w_mat1 = tlbelo1_in[`TLB_MAT];
assign w_ppn1 = tlbelo1_in[`TLB_PPN_EN];
//trans read port sig
assign r_index = tlbidx_in[`INDEX];
assign tlbehi_out = {r_vppn, 13'b0};
assign tlbelo0_out = {4'b0, r_ppn0, 1'b0, r_g, r_mat0, r_plv0, r_d0, r_v0};
assign tlbelo1_out = {4'b0, r_ppn1, 1'b0, r_g, r_mat1, r_plv1, r_d1, r_v1};
assign tlbidx_out = {!r_e, 1'b0, r_ps, 24'b0}; //note do not write index
assign asid_out = r_asid;
tlb_entry tlb_entry(
.clk (clk ),
// search port 0
.s0_fetch (inst_fetch ),
.s0_vppn (s0_vppn ),
.s0_odd_page (s0_odd_page ),
.s0_asid (asid ),
.s0_found (inst_tlb_found ),
.s0_index (),
.s0_ps (s0_ps ),
.s0_ppn (s0_ppn ),
.s0_v (inst_tlb_v ),
.s0_d (inst_tlb_d ),
.s0_mat (inst_tlb_mat ),
.s0_plv (inst_tlb_plv ),
// search port 1
.s1_fetch (data_fetch ),
.s1_vppn (s1_vppn ),
.s1_odd_page (s1_odd_page ),
.s1_asid (asid ),
.s1_found (data_tlb_found ),
.s1_index (data_tlb_index ),
.s1_ps (s1_ps ),
.s1_ppn (s1_ppn ),
.s1_v (data_tlb_v ),
.s1_d (data_tlb_d ),
.s1_mat (data_tlb_mat ),
.s1_plv (data_tlb_plv ),
// write port
.we (we ),
.w_index (w_index ),
.w_vppn (w_vppn ),
.w_asid (asid ),
.w_g (w_g ),
.w_ps (w_ps ),
.w_e (w_e ),
.w_v0 (w_v0 ),
.w_d0 (w_d0 ),
.w_plv0 (w_plv0 ),
.w_mat0 (w_mat0 ),
.w_ppn0 (w_ppn0 ),
.w_v1 (w_v1 ),
.w_d1 (w_d1 ),
.w_plv1 (w_plv1 ),
.w_mat1 (w_mat1 ),
.w_ppn1 (w_ppn1 ),
//read port
.r_index (r_index ),
.r_vppn (r_vppn ),
.r_asid (r_asid ),
.r_g (r_g ),
.r_ps (r_ps ),
.r_e (r_e ),
.r_v0 (r_v0 ),
.r_d0 (r_d0 ),
.r_mat0 (r_mat0 ),
.r_plv0 (r_plv0 ),
.r_ppn0 (r_ppn0 ),
.r_v1 (r_v1 ),
.r_d1 (r_d1 ),
.r_mat1 (r_mat1 ),
.r_plv1 (r_plv1 ),
.r_ppn1 (r_ppn1 ),
//invalid port
.inv_en (invtlb_en ),
.inv_op (invtlb_op ),
.inv_asid (invtlb_asid ),
.inv_vpn (invtlb_vpn )
);
assign pg_mode = !csr_da && csr_pg;
assign da_mode = csr_da && !csr_pg;
assign inst_paddr = (pg_mode && inst_dmw0_en) ? {csr_dmw0[`PSEG], inst_vaddr_buffer[28:0]} :
(pg_mode && inst_dmw1_en) ? {csr_dmw1[`PSEG], inst_vaddr_buffer[28:0]} : inst_vaddr_buffer;
assign inst_offset = inst_vaddr[3:0];
assign inst_index = inst_vaddr[11:4];
assign inst_tag = inst_addr_trans_en ? ((s0_ps == 6'd12) ? s0_ppn : {s0_ppn[19:10], inst_paddr[21:12]}) : inst_paddr[31:12];
assign data_paddr = (pg_mode && data_dmw0_en && !cacop_op_mode_di) ? {csr_dmw0[`PSEG], data_vaddr_buffer[28:0]} :
(pg_mode && data_dmw1_en && !cacop_op_mode_di) ? {csr_dmw1[`PSEG], data_vaddr_buffer[28:0]} : data_vaddr_buffer;
assign data_offset = data_vaddr[3:0];
assign data_index = data_vaddr[11:4];
assign data_tag = data_addr_trans_en ? ((s1_ps == 6'd12) ? s1_ppn : {s1_ppn[19:10], data_paddr[21:12]}) : data_paddr[31:12];
endmodule

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rtl/ip/open-la500/alu.v Normal file
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module alu(
input [13:0] alu_op,
input [31:0] alu_src1,
input [31:0] alu_src2,
output [31:0] alu_result
);
wire op_add;
wire op_sub;
wire op_slt;
wire op_sltu;
wire op_and;
wire op_nor;
wire op_or;
wire op_xor;
wire op_sll;
wire op_srl;
wire op_sra;
wire op_lui;
wire op_andn;
wire op_orn;
// control code decomposition
assign op_add = alu_op[ 0];
assign op_sub = alu_op[ 1];
assign op_slt = alu_op[ 2];
assign op_sltu = alu_op[ 3];
assign op_and = alu_op[ 4];
assign op_nor = alu_op[ 5];
assign op_or = alu_op[ 6];
assign op_xor = alu_op[ 7];
assign op_sll = alu_op[ 8];
assign op_srl = alu_op[ 9];
assign op_sra = alu_op[10];
assign op_lui = alu_op[11];
assign op_andn = alu_op[12];
assign op_orn = alu_op[13];
wire [31:0] add_sub_result;
wire [31:0] slt_result;
wire [31:0] sltu_result;
wire [31:0] and_result;
wire [31:0] nor_result;
wire [31:0] or_result;
wire [31:0] xor_result;
wire [31:0] lui_result;
wire [31:0] sll_result;
wire [63:0] sr64_result;
wire [31:0] sr_result;
wire [31:0] andn_result;
wire [31:0] orn_result;
// 32-bit adder
wire [31:0] adder_a;
wire [31:0] adder_b;
wire adder_cin;
wire [31:0] adder_result;
wire adder_cout;
assign adder_a = alu_src1;
assign adder_b = (op_sub | op_slt | op_sltu) ? ~alu_src2 : alu_src2; //src1 - src2 rj-rk
assign adder_cin = (op_sub | op_slt | op_sltu) ? 1'b1 : 1'b0;
assign {adder_cout, adder_result} = adder_a + adder_b + adder_cin;
// ADD, SUB result
assign add_sub_result = adder_result;
// SLT result
assign slt_result[31:1] = 31'b0; //rj < rk 1
assign slt_result[0] = (alu_src1[31] & ~alu_src2[31])
| ((alu_src1[31] ~^ alu_src2[31]) & adder_result[31]);
// SLTU result
assign sltu_result[31:1] = 31'b0;
assign sltu_result[0] = ~adder_cout;
// bitwise operation
assign and_result = alu_src1 & alu_src2;
assign andn_result= alu_src1 & ~alu_src2;
assign or_result = alu_src1 | alu_src2; //bug6 cycle
assign orn_result = alu_src1 | ~alu_src2;
assign nor_result = ~or_result;
assign xor_result = alu_src1 ^ alu_src2;
assign lui_result = alu_src2;
// SLL result
assign sll_result = alu_src1 << alu_src2[4:0]; //rj << i5
// SRL, SRA result
assign sr64_result = {{32{op_sra & alu_src1[31]}}, alu_src1[31:0]} >> alu_src2[4:0]; //rj >> i5
assign sr_result = sr64_result[31:0];
// final result mux
assign alu_result = ({32{op_add|op_sub}} & add_sub_result)
| ({32{op_slt }} & slt_result)
| ({32{op_sltu }} & sltu_result)
| ({32{op_and }} & and_result)
| ({32{op_andn }} & andn_result)
| ({32{op_nor }} & nor_result)
| ({32{op_or }} & or_result)
| ({32{op_orn }} & orn_result)
| ({32{op_xor }} & xor_result)
| ({32{op_lui }} & lui_result)
| ({32{op_sll }} & sll_result)
| ({32{op_srl|op_sra}} & sr_result); //bug7 srl and sra sign
endmodule

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module axi_bridge(
input clk,
input reset,
output reg[ 3:0] arid,
output reg[31:0] araddr,
output reg[ 7:0] arlen,
output reg[ 2:0] arsize,
output [ 1:0] arburst,
output [ 1:0] arlock,
output [ 3:0] arcache,
output [ 2:0] arprot,
output reg arvalid,
input arready,
input [ 3:0] rid,
input [31:0] rdata,
input [ 1:0] rresp,
input rlast,
input rvalid,
output reg rready,
output [ 3:0] awid,
output reg[31:0] awaddr,
output reg[ 7:0] awlen,
output reg[ 2:0] awsize,
output [ 1:0] awburst,
output [ 1:0] awlock,
output [ 3:0] awcache,
output [ 2:0] awprot,
output reg awvalid,
input awready,
output [ 3:0] wid,
output reg[31:0] wdata,
output reg[ 3:0] wstrb,
output reg wlast,
output reg wvalid,
input wready,
input [ 3:0] bid,
input [ 1:0] bresp,
input bvalid,
output reg bready,
//cache sign
input inst_rd_req ,
input [ 2:0] inst_rd_type ,
input [31:0] inst_rd_addr ,
output inst_rd_rdy ,
output inst_ret_valid ,
output inst_ret_last ,
output [31:0] inst_ret_data ,
input inst_wr_req ,
input [ 2:0] inst_wr_type ,
input [31:0] inst_wr_addr ,
input [ 3:0] inst_wr_wstrb ,
input [127:0] inst_wr_data ,
output inst_wr_rdy ,
input data_rd_req ,
input [ 2:0] data_rd_type ,
input [31:0] data_rd_addr ,
output data_rd_rdy ,
output data_ret_valid ,
output data_ret_last ,
output [31:0] data_ret_data ,
input data_wr_req ,
input [ 2:0] data_wr_type ,
input [31:0] data_wr_addr ,
input [ 3:0] data_wr_wstrb ,
input [127:0] data_wr_data ,
output data_wr_rdy ,
output write_buffer_empty
);
//fixed signal
assign arburst = 2'b1;
assign arlock = 2'b0;
assign arcache = 4'b0;
assign arprot = 3'b0;
assign awid = 4'b1;
assign awburst = 2'b1;
assign awlock = 2'b0;
assign awcache = 4'b0;
assign awprot = 3'b0;
assign wid = 4'b1;
assign inst_wr_rdy = 1'b1;
localparam read_requst_empty = 1'b0;
localparam read_requst_ready = 1'b1;
localparam read_respond_empty = 1'b0;
localparam read_respond_transfer = 1'b1;
localparam write_request_empty = 3'b000;
localparam write_addr_ready = 3'b001;
localparam write_data_ready = 3'b010;
localparam write_all_ready = 3'b011;
localparam write_data_transform = 3'b100;
localparam write_data_wait = 3'b101;
localparam write_wait_b = 3'b110;
reg read_requst_state;
reg read_respond_state;
reg [2:0] write_requst_state;
wire write_wait_enable;
wire rd_requst_state_is_empty;
wire rd_requst_can_receive;
assign rd_requst_state_is_empty = read_requst_state == read_requst_empty;
wire data_rd_cache_line;
wire inst_rd_cache_line;
wire [ 2:0] data_real_rd_size;
wire [ 7:0] data_real_rd_len ;
wire [ 2:0] inst_real_rd_size;
wire [ 7:0] inst_real_rd_len ;
wire data_wr_cache_line;
wire [ 2:0] data_real_wr_size;
wire [ 7:0] data_real_wr_len ;
reg [127:0] write_buffer_data;
reg [ 2:0] write_buffer_num;
wire write_buffer_last;
assign write_buffer_empty = (write_buffer_num == 3'b0) && !write_wait_enable;
assign rd_requst_can_receive = rd_requst_state_is_empty && !(write_wait_enable && !(bvalid && bready));
assign data_rd_rdy = rd_requst_can_receive;
assign inst_rd_rdy = !data_rd_req && rd_requst_can_receive;
//read type must be cache line
assign data_rd_cache_line = data_rd_type == 3'b100 ;
assign data_real_rd_size = data_rd_cache_line ? 3'b10 : data_rd_type;
assign data_real_rd_len = data_rd_cache_line ? 8'b11 : 8'b0 ;
assign inst_rd_cache_line = inst_rd_type == 3'b100 ;
assign inst_real_rd_size = inst_rd_cache_line ? 3'b10 : inst_rd_type;
assign inst_real_rd_len = inst_rd_cache_line ? 8'b11 : 8'b0 ;
//write size can be special
assign data_wr_cache_line = data_wr_type == 3'b100;
assign data_real_wr_size = data_wr_cache_line ? 3'b10 : data_wr_type;
assign data_real_wr_len = data_wr_cache_line ? 8'b11 : 8'b0 ;
assign inst_ret_valid = !rid[0] && rvalid;
assign inst_ret_last = !rid[0] && rlast;
assign inst_ret_data = rdata; //this signal needed buffer???
assign data_ret_valid = rid[0] && rvalid;
assign data_ret_last = rid[0] && rlast;
assign data_ret_data = rdata;
assign data_wr_rdy = (write_requst_state == write_request_empty);
assign write_buffer_last = write_buffer_num == 3'b1;
always @(posedge clk) begin
if (reset) begin
read_requst_state <= read_requst_empty;
arvalid <= 1'b0;
end
else case (read_requst_state)
read_requst_empty: begin
if (data_rd_req) begin
if (write_wait_enable) begin
if (bvalid && bready) begin //when wait write back, stop send read request. easiest way.
read_requst_state <= read_requst_ready;
arid <= 4'b1;
araddr <= data_rd_addr;
arsize <= data_real_rd_size;
arlen <= data_real_rd_len;
arvalid <= 1'b1;
end
end
else begin
read_requst_state <= read_requst_ready;
arid <= 4'b1;
araddr <= data_rd_addr;
arsize <= data_real_rd_size;
arlen <= data_real_rd_len;
arvalid <= 1'b1;
end
end
else if (inst_rd_req) begin
if (write_wait_enable) begin
if (bvalid && bready) begin
read_requst_state <= read_requst_ready;
arid <= 4'b0;
araddr <= inst_rd_addr;
arsize <= inst_real_rd_size;
arlen <= inst_real_rd_len;
arvalid <= 1'b1;
end
end
else begin
read_requst_state <= read_requst_ready;
arid <= 4'b0;
araddr <= inst_rd_addr;
arsize <= inst_real_rd_size;
arlen <= inst_real_rd_len;
arvalid <= 1'b1;
end
end
end
read_requst_ready: begin
if (arready && arid[0]) begin
read_requst_state <= read_requst_empty;
arvalid <= 1'b0;
end
else if (arready && !arid[0]) begin
read_requst_state <= read_requst_empty;
arvalid <= 1'b0;
end
end
endcase
end
always @(posedge clk) begin
if (reset) begin
read_respond_state <= read_respond_empty;
rready <= 1'b1;
end
else case (read_respond_state)
read_respond_empty: begin
if (rvalid && rready) begin
read_respond_state <= read_respond_transfer;
end
end
read_respond_transfer: begin
if (rlast && rvalid) begin
read_respond_state <= read_respond_empty;
end
end
endcase
end
always @(posedge clk) begin
if (reset) begin
write_requst_state <= write_request_empty;
awvalid <= 1'b0;
wvalid <= 1'b0;
wlast <= 1'b0;
bready <= 1'b0;
write_buffer_num <= 3'b0;
write_buffer_data <= 128'b0;
end
else case (write_requst_state)
write_request_empty: begin
if (data_wr_req) begin
write_requst_state <= write_data_wait;
//end
awaddr <= data_wr_addr;
awsize <= data_real_wr_size;
awlen <= data_real_wr_len;
awvalid <= 1'b1;
wdata <= data_wr_data[31:0]; //from write 128 bit buffer
wstrb <= data_wr_wstrb;
write_buffer_data <= {32'b0, data_wr_data[127:32]};
if (data_wr_type == 3'b100) begin
write_buffer_num <= 3'b011;
end
else begin
write_buffer_num <= 3'b0;
wlast <= 1'b1;
end
end
end
write_data_wait: begin
if (awready) begin
write_requst_state <= write_data_transform;
awvalid <= 1'b0;
wvalid <= 1'b1;
end
end
write_data_transform: begin
if (wready) begin
if (wlast) begin
write_requst_state <= write_wait_b;
wvalid <= 1'b0;
wlast <= 1'b0;
bready <= 1'b1;
end
else begin
if (write_buffer_last) begin
wlast <= 1'b1;
end
write_requst_state <= write_data_transform;
wdata <= write_buffer_data[31:0];
wvalid <= 1'b1;
write_buffer_data <= {32'b0, write_buffer_data[127:32]};
write_buffer_num <= write_buffer_num - 3'b1;
end
end
end
write_wait_b: begin
if (bvalid && bready) begin
write_requst_state <= write_request_empty;
bready <= 1'b0;
end
end
default: begin
write_requst_state <= write_request_empty;
end
endcase
end
assign write_wait_enable = ~(write_requst_state == write_request_empty);
endmodule

238
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module btb
#(
parameter BTBNUM = 32,
parameter RASNUM = 16
)
(
input clk ,
input reset ,
//from/to if
input [31:0] fetch_pc ,
input fetch_en ,
output [31:0] ret_pc ,
output taken ,
output ret_en ,
output [ 4:0] ret_index ,
//from id
input operate_en ,
input [31:0] operate_pc ,
input [ 4:0] operate_index ,
input pop_ras ,
input push_ras ,
input add_entry ,
input delete_entry ,
input pre_error ,
input pre_right ,
input target_error ,
input right_orien ,
input [31:0] right_target
);
/*
* btb_pc record all branch inst pc except jirl
* ras_pc only record jirl pc
*/
reg [29:0] btb_pc [BTBNUM-1:0];
reg [29:0] btb_target [BTBNUM-1:0];
reg [ 1:0] btb_counter [BTBNUM-1:0];
reg [BTBNUM-1:0] btb_valid;
reg [29:0] ras_pc [RASNUM-1:0];
reg [RASNUM-1:0] ras_valid;
reg [31:0] fetch_pc_r;
reg fetch_en_r;
//reg [BTBNUM-1:0] jirl_flag;
reg [29:0] ras [7:0];
reg [ 3:0] ras_ptr;
wire [29:0] ras_top;
wire ras_full;
wire ras_empty;
wire [31:0] btb_match_rd;
wire [15:0] ras_match_rd;
wire btb_match;
wire ras_match;
wire [29:0] btb_match_target;
wire [ 1:0] btb_match_counter;
wire [ 4:0] btb_match_index;
wire [ 4:0] btb_random_index;
wire [ 3:0] ras_match_index;
wire [ 3:0] ras_random_index;
wire btb_all_entry_valid;
wire [4:0] btb_select_one_invalid_entry;
wire [4:0] btb_add_entry_index;
reg [4:0] btb_add_entry_index_r;
wire [31:0] btb_add_entry_dec;
wire ras_all_entry_valid;
wire [3:0] ras_select_one_invalid_entry;
wire [3:0] ras_add_entry_index;
wire [31:0] btb_untaken_entry;
reg [31:0] btb_untaken_entry_r;
wire [31:0] btb_untaken_entry_t;
reg btb_add_entry_r;
wire [4:0] btb_sel_one_untaken_entry;
wire btb_has_one_untaken_entry;
reg [5:0] fcsr;
always @(posedge clk) begin
if (reset)
fetch_en_r <= 1'b0;
else
fetch_en_r <= fetch_en;
if (fetch_en)
fetch_pc_r <= fetch_pc;
end
always @(posedge clk) begin
btb_untaken_entry_r <= btb_untaken_entry;
btb_add_entry_r <= operate_en && !pop_ras && add_entry;
btb_add_entry_index_r <= btb_add_entry_index;
end
//untaken entry list cal at previous clock
assign btb_untaken_entry_t = btb_untaken_entry_r & ({32{!btb_add_entry_r}} | ~btb_add_entry_dec);
assign btb_has_one_untaken_entry = |btb_untaken_entry_t;
decoder_5_32 dec_btb_add_entry (.in(btb_add_entry_index_r), .out(btb_add_entry_dec));
one_valid_32 sel_one_untaken_entry (.in(btb_untaken_entry_t), .out_en(btb_sel_one_untaken_entry));
//assign btb_random_index = (btb_match && (fcsr[4:0] == btb_match_index)) ? (fcsr[4:0]+1'b1) : fcsr[4:0];
//untaken entry can exit first, make no difference, except lose history infor.
assign btb_add_entry_index = !btb_all_entry_valid ? btb_select_one_invalid_entry :
btb_has_one_untaken_entry ? btb_sel_one_untaken_entry :
fcsr[4:0] ;
assign btb_all_entry_valid = &btb_valid;
one_valid_32 sel_one_btb_entry (.in(~btb_valid), .out_en(btb_select_one_invalid_entry));
//assign ras_random_index = (ras_match && (fcsr[3:0] == ras_match_index)) ? (fcsr[3:0]+1'b1) : fcsr[3:0];
assign ras_add_entry_index = ras_all_entry_valid ? fcsr[3:0] : ras_select_one_invalid_entry;
assign ras_all_entry_valid = &ras_valid;
one_valid_16 sel_one_ras_entry (.in(~ras_valid), .out_en(ras_select_one_invalid_entry));
always @(posedge clk) begin
if (reset) begin
btb_valid <= 32'b0;
ras_valid <= 16'b0;
end
else if (operate_en && !pop_ras) begin
if (add_entry) begin
btb_valid[btb_add_entry_index] <= 1'b1;
btb_pc[btb_add_entry_index] <= operate_pc[31:2];
btb_target[btb_add_entry_index] <= right_target[31:2];
btb_counter[btb_add_entry_index] <= 2'b10;
end
else if (target_error) begin
btb_target[operate_index] <= right_target[31:2];
btb_counter[operate_index] <= 2'b10;
end
else if (pre_error || pre_right) begin
if (right_orien) begin
if (btb_counter[operate_index] != 2'b11) begin
btb_counter[operate_index] <= btb_counter[operate_index] + 2'b1;
end
end
else begin
if (btb_counter[operate_index] != 2'b00) begin
btb_counter[operate_index] <= btb_counter[operate_index] - 2'b1;
end
end
end
end
else if (operate_en && pop_ras) begin
if (add_entry) begin
ras_valid[ras_add_entry_index] <= 1'b1;
ras_pc[ras_add_entry_index] <= operate_pc[31:2];
end
end
end
genvar i;
generate
for (i = 0; i < BTBNUM; i = i + 1)
begin: btb_match_com
assign btb_match_rd[i] = fetch_en_r && ((fetch_pc_r[31:2] == btb_pc[i]) && btb_valid[i]);
end
endgenerate
generate
for (i = 0; i < RASNUM; i = i + 1)
begin: ras_match_com
assign ras_match_rd[i] = fetch_en_r && ((fetch_pc_r[31:2] == ras_pc[i]) && ras_valid[i]);
end
endgenerate
generate
for (i = 0; i < BTBNUM; i = i + 1)
begin: sel_untaken_entry
assign btb_untaken_entry[i] = btb_valid[i] && ~|btb_counter[i];
end
endgenerate
assign btb_match = |btb_match_rd;
assign ras_match = |ras_match_rd && !ras_empty;
assign ras_top = ras[ras_ptr - 4'b1]; //ras modify may before inst fetch
encoder_32_5 encode_btb_match (.in(btb_match_rd), .out(btb_match_index));
encoder_16_4 encode_ras_match (.in(ras_match_rd), .out(ras_match_index));
assign btb_match_target = btb_target[btb_match_index];
assign btb_match_counter = btb_counter[btb_match_index];
assign ret_pc = {32{ras_match}} & {ras_top, 2'b0} |
{32{btb_match}} & {btb_match_target, 2'b0};
assign ret_en = btb_match || ras_match;
assign taken = btb_match && btb_match_counter[1] || ras_match;
assign ret_index = {5{btb_match}} & {btb_match_index} |
{5{ras_match}} & {1'b0,ras_match_index};
assign ras_full = ras_ptr[3];
assign ras_empty = (ras_ptr == 4'd0);
always @(posedge clk) begin
if (reset) begin
ras_ptr <= 4'b0;
end
else if (operate_en) begin
if (push_ras && !ras_full) begin
ras[ras_ptr] <= operate_pc[31:2] + 30'b1;
ras_ptr <= ras_ptr + 4'b1;
end
else if (pop_ras && !ras_empty) begin
ras_ptr <= ras_ptr - 4'b1;
end
end
end
always @(posedge clk) begin
if (reset) begin
fcsr <= 6'b100010;
end
else begin
fcsr[0] <= fcsr[5];
fcsr[1] <= fcsr[0];
fcsr[2] <= fcsr[1];
fcsr[3] <= fcsr[2] ^ fcsr[5];
fcsr[4] <= fcsr[3] ^ fcsr[5];
fcsr[5] <= fcsr[4];
end
end
endmodule

73
rtl/ip/open-la500/csr.h Normal file
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//CRMD
`define PLV 1:0
`define IE 2
`define DA 3
`define PG 4
`define DATF 6:5
`define DATM 8:7
//PRMD
`define PPLV 1:0
`define PIE 2
//ECTL
`define LIE 12:0
`define LIE_1 9:0
`define LIE_2 12:11
//ESTAT
`define IS 12:0
`define ECODE 21:16
`define ESUBCODE 30:22
//TLBIDX
`define INDEX 4:0
`define PS 29:24
`define NE 31
//TLBEHI
`define VPPN 31:13
//TLBELO
`define TLB_V 0
`define TLB_D 1
`define TLB_PLV 3:2
`define TLB_MAT 5:4
`define TLB_G 6
`define TLB_PPN 31:8
`define TLB_PPN_EN 27:8 //todo
//ASID
`define TLB_ASID 9:0
//CPUID
`define COREID 8:0
//LLBCTL
`define ROLLB 0
`define WCLLB 1
`define KLO 2
//TCFG
`define EN 0
`define PERIODIC 1
`define INITVAL 31:2
//TICLR
`define CLR 0
//TLBRENTRY
`define TLBRENTRY_PA 31:6
//DMW
`define PLV0 0
`define PLV3 3
`define DMW_MAT 5:4
`define PSEG 27:25
`define VSEG 31:29
//PGDL PGDH PGD
`define BASE 31:12
`define ECODE_INT 6'h0
`define ECODE_PIL 6'h1
`define ECODE_PIS 6'h2
`define ECODE_PIF 6'h3
`define ECODE_PME 6'h4
`define ECODE_PPI 6'h7
`define ECODE_ADEF 6'h8
`define ECODE_ALE 6'h9
`define ECODE_SYS 6'hb
`define ECODE_BRK 6'hc
`define ECODE_INE 6'hd
`define ECODE_IPE 6'he
`define ECODE_FPD 6'hf
`define ECODE_TLBR 6'h3f
`define ESUBCODE_ADEF 9'h0

856
rtl/ip/open-la500/csr.v Normal file
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`include "mycpu.h"
`include "csr.h"
module csr
#(
parameter TLBNUM = 32
)
(
input clk ,
input reset ,
//from to ds
input [13:0] rd_addr ,
output [31:0] rd_data ,
//timer 64
output [63:0] timer_64_out ,
output [31:0] tid_out ,
//from ws
input csr_wr_en ,
input [13:0] wr_addr ,
input [31:0] wr_data ,
//interrupt
input [ 7:0] interrupt ,
output has_int ,
//from ws
input excp_flush ,
input ertn_flush ,
input [31:0] era_in ,
input [ 8:0] esubcode_in ,
input [ 5:0] ecode_in ,
input va_error_in ,
input [31:0] bad_va_in ,
input tlbsrch_en ,
input tlbsrch_found ,
input [ 4:0] tlbsrch_index ,
input excp_tlbrefill,
input excp_tlb ,
input [18:0] excp_tlb_vppn,
//from ws llbit
input llbit_in ,
input llbit_set_in ,
input [27:0] lladdr_in ,
input lladdr_set_in,
//to es
output llbit_out ,
output [18:0] vppn_out ,
//to ms
output [27:0] lladdr_out ,
//to fs
output [31:0] eentry_out ,
output [31:0] era_out ,
output [31:0] tlbrentry_out,
output disable_cache_out,
//to addr trans
output [ 9:0] asid_out ,
output [ 4:0] rand_index ,
output [31:0] tlbehi_out ,
output [31:0] tlbelo0_out ,
output [31:0] tlbelo1_out ,
output [31:0] tlbidx_out ,
output pg_out ,
output da_out ,
output [31:0] dmw0_out ,
output [31:0] dmw1_out ,
output [ 1:0] datf_out ,
output [ 1:0] datm_out ,
output [ 5:0] ecode_out ,
//from addr trans
input tlbrd_en ,
input [31:0] tlbehi_in ,
input [31:0] tlbelo0_in ,
input [31:0] tlbelo1_in ,
input [31:0] tlbidx_in ,
input [ 9:0] asid_in ,
//general use
output [ 1:0] plv_out
// csr regs for diff
`ifdef DIFFTEST_EN
,
output [31:0] csr_crmd_diff,
output [31:0] csr_prmd_diff,
output [31:0] csr_ectl_diff,
output [31:0] csr_estat_diff,
output [31:0] csr_era_diff,
output [31:0] csr_badv_diff,
output [31:0] csr_eentry_diff,
output [31:0] csr_tlbidx_diff,
output [31:0] csr_tlbehi_diff,
output [31:0] csr_tlbelo0_diff,
output [31:0] csr_tlbelo1_diff,
output [31:0] csr_asid_diff,
output [31:0] csr_save0_diff,
output [31:0] csr_save1_diff,
output [31:0] csr_save2_diff,
output [31:0] csr_save3_diff,
output [31:0] csr_tid_diff,
output [31:0] csr_tcfg_diff,
output [31:0] csr_tval_diff,
output [31:0] csr_ticlr_diff,
output [31:0] csr_llbctl_diff,
output [31:0] csr_tlbrentry_diff,
output [31:0] csr_dmw0_diff,
output [31:0] csr_dmw1_diff,
output [31:0] csr_pgdl_diff,
output [31:0] csr_pgdh_diff
`endif
);
localparam CRMD = 14'h0;
localparam PRMD = 14'h1;
localparam ECTL = 14'h4;
localparam ESTAT = 14'h5;
localparam ERA = 14'h6;
localparam BADV = 14'h7;
localparam EENTRY = 14'hc;
localparam TLBIDX= 14'h10;
localparam TLBEHI= 14'h11;
localparam TLBELO0=14'h12;
localparam TLBELO1=14'h13;
localparam ASID = 14'h18;
localparam PGDL = 14'h19;
localparam PGDH = 14'h1a;
localparam PGD = 14'h1b;
localparam CPUID = 14'h20;
localparam SAVE0 = 14'h30;
localparam SAVE1 = 14'h31;
localparam SAVE2 = 14'h32;
localparam SAVE3 = 14'h33;
localparam TID = 14'h40;
localparam TCFG = 14'h41;
localparam TVAL = 14'h42;
localparam CNTC = 14'h43;
localparam TICLR = 14'h44;
localparam LLBCTL= 14'h60;
localparam TLBRENTRY = 14'h88;
localparam DMW0 = 14'h180;
localparam DMW1 = 14'h181;
localparam BRK = 14'h100;
localparam DISABLE_CACHE = 14'h101;
localparam CPUCFG_1 = 14'hb1;
localparam CPUCFG_2 = 14'hb2;
localparam CPUCFG_10 = 14'hc0;
localparam CPUCFG_11 = 14'hc1;
localparam CPUCFG_12 = 14'hc2;
localparam CPUCFG_13 = 14'hc3;
wire crmd_wen = csr_wr_en & (wr_addr == CRMD);
wire prmd_wen = csr_wr_en & (wr_addr == PRMD);
wire ectl_wen = csr_wr_en & (wr_addr == ECTL);
wire estat_wen = csr_wr_en & (wr_addr == ESTAT);
wire era_wen = csr_wr_en & (wr_addr == ERA);
wire badv_wen = csr_wr_en & (wr_addr == BADV);
wire eentry_wen = csr_wr_en & (wr_addr == EENTRY);
wire tlbidx_wen = csr_wr_en & (wr_addr == TLBIDX);
wire tlbehi_wen = csr_wr_en & (wr_addr == TLBEHI);
wire tlbelo0_wen= csr_wr_en & (wr_addr == TLBELO0);
wire tlbelo1_wen= csr_wr_en & (wr_addr == TLBELO1);
wire asid_wen = csr_wr_en & (wr_addr == ASID);
wire pgdl_wen = csr_wr_en & (wr_addr == PGDL);
wire pgdh_wen = csr_wr_en & (wr_addr == PGDH);
wire pgd_wen = csr_wr_en & (wr_addr == PGD);
wire cpuid_wen = csr_wr_en & (wr_addr == CPUID);
wire save0_wen = csr_wr_en & (wr_addr == SAVE0);
wire save1_wen = csr_wr_en & (wr_addr == SAVE1);
wire save2_wen = csr_wr_en & (wr_addr == SAVE2);
wire save3_wen = csr_wr_en & (wr_addr == SAVE3);
wire tid_wen = csr_wr_en & (wr_addr == TID);
wire tcfg_wen = csr_wr_en & (wr_addr == TCFG);
wire tval_wen = csr_wr_en & (wr_addr == TVAL);
wire cntc_wen = csr_wr_en & (wr_addr == CNTC);
wire ticlr_wen = csr_wr_en & (wr_addr == TICLR);
wire llbctl_wen = csr_wr_en & (wr_addr == LLBCTL);
wire tlbrentry_wen = csr_wr_en & (wr_addr == TLBRENTRY);
wire DMW0_wen = csr_wr_en & (wr_addr == DMW0);
wire DMW1_wen = csr_wr_en & (wr_addr == DMW1);
wire BRK_wen = csr_wr_en & (wr_addr == BRK);
wire disable_cache_wen = csr_wr_en & (wr_addr == DISABLE_CACHE);
reg [31:0] csr_crmd;
reg [31:0] csr_prmd;
reg [31:0] csr_ectl;
reg [31:0] csr_estat;
reg [31:0] csr_era;
reg [31:0] csr_badv;
reg [31:0] csr_eentry;
reg [31:0] csr_tlbidx;
reg [31:0] csr_tlbehi;
reg [31:0] csr_tlbelo0;
reg [31:0] csr_tlbelo1;
reg [31:0] csr_asid;
reg [31:0] csr_cpuid;
reg [31:0] csr_save0;
reg [31:0] csr_save1;
reg [31:0] csr_save2;
reg [31:0] csr_save3;
reg [31:0] csr_tid;
reg [31:0] csr_tcfg;
reg [31:0] csr_tval;
reg [31:0] csr_cntc;
reg [31:0] csr_ticlr;
reg [31:0] csr_llbctl;
reg [31:0] csr_tlbrentry;
reg [31:0] csr_dmw0;
reg [31:0] csr_dmw1;
reg [31:0] csr_pgdl;
reg [31:0] csr_pgdh;
reg [31:0] csr_brk;
reg [31:0] csr_disable_cache;
reg [31:0] csr_cpucfg1;
reg [31:0] csr_cpucfg2;
reg [31:0] csr_cpucfg10;
reg [31:0] csr_cpucfg11;
reg [31:0] csr_cpucfg12;
reg [31:0] csr_cpucfg13;
wire [31:0] csr_pgd;
reg timer_en;
reg [63:0] timer_64;
reg llbit;
reg [27:0] lladdr;
wire tlbrd_valid_wr_en;
wire tlbrd_invalid_wr_en;
wire eret_tlbrefill_excp;
wire no_forward;
assign csr_pgd = csr_badv[31] ? csr_pgdh : csr_pgdl;
assign eret_tlbrefill_excp = csr_estat[`ECODE] == 6'h3f;
assign tlbrd_valid_wr_en = tlbrd_en && !tlbidx_in[`NE];
assign tlbrd_invalid_wr_en = tlbrd_en && tlbidx_in[`NE];
assign has_int = ((csr_ectl[`LIE] & csr_estat[`IS]) != 13'b0) & csr_crmd[`IE];
assign eentry_out = csr_eentry;
assign era_out = csr_era;
assign timer_64_out = timer_64 + {{32{csr_cntc[31]}}, csr_cntc};
assign tid_out = csr_tid;
assign llbit_out = llbit;
assign lladdr_out = lladdr;
assign asid_out = csr_asid[`TLB_ASID];
assign vppn_out = (csr_wr_en && wr_addr == TLBEHI) ? wr_data[`VPPN] : csr_tlbehi[`VPPN];
assign tlbehi_out = csr_tlbehi;
assign tlbelo0_out = csr_tlbelo0;
assign tlbelo1_out = csr_tlbelo1;
assign tlbidx_out = csr_tlbidx;
assign rand_index = timer_64[4:0];
assign disable_cache_out = csr_disable_cache[0];
//forward to if stage
assign no_forward = !excp_tlbrefill && !(eret_tlbrefill_excp && ertn_flush) && !crmd_wen;
assign pg_out = excp_tlbrefill & 1'b0 |
(eret_tlbrefill_excp && ertn_flush) & 1'b1 |
crmd_wen & wr_data[`PG] |
no_forward & csr_crmd[`PG];
assign da_out = excp_tlbrefill & 1'b1 |
(eret_tlbrefill_excp && ertn_flush) & 1'b0 |
crmd_wen & wr_data[`DA] |
no_forward & csr_crmd[`DA];
assign dmw0_out = DMW0_wen ? wr_data : csr_dmw0;
assign dmw1_out = DMW1_wen ? wr_data : csr_dmw1;
assign plv_out = {2{excp_flush}} & 2'b0 |
{2{ertn_flush}} & csr_prmd[`PPLV] |
{2{crmd_wen }} & wr_data[`PLV] |
{2{!excp_flush && !ertn_flush && !crmd_wen}} & csr_crmd[`PLV];
assign tlbrentry_out= csr_tlbrentry;
assign datf_out = csr_crmd[`DATF];
assign datm_out = csr_crmd[`DATM];
assign ecode_out = csr_estat[`ECODE];
assign rd_data = {32{rd_addr == CRMD }} & csr_crmd |
{32{rd_addr == PRMD }} & csr_prmd |
{32{rd_addr == ECTL }} & csr_ectl |
{32{rd_addr == ESTAT }} & csr_estat |
{32{rd_addr == ERA }} & csr_era |
{32{rd_addr == BADV }} & csr_badv |
{32{rd_addr == EENTRY}} & csr_eentry |
{32{rd_addr == TLBIDX}} & csr_tlbidx |
{32{rd_addr == TLBEHI}} & csr_tlbehi |
{32{rd_addr == TLBELO0}} & csr_tlbelo0 |
{32{rd_addr == TLBELO1}} & csr_tlbelo1 |
{32{rd_addr == ASID }} & csr_asid |
{32{rd_addr == PGDL }} & csr_pgdl |
{32{rd_addr == PGDH }} & csr_pgdh |
{32{rd_addr == PGD }} & csr_pgd |
{32{rd_addr == CPUID }} & csr_cpuid |
{32{rd_addr == SAVE0 }} & csr_save0 |
{32{rd_addr == SAVE1 }} & csr_save1 |
{32{rd_addr == SAVE2 }} & csr_save2 |
{32{rd_addr == SAVE3 }} & csr_save3 |
{32{rd_addr == TID }} & csr_tid |
{32{rd_addr == TCFG }} & csr_tcfg |
{32{rd_addr == CNTC }} & csr_cntc |
{32{rd_addr == TICLR }} & csr_ticlr |
{32{rd_addr == LLBCTL}} & {csr_llbctl[31:1], llbit} |
{32{rd_addr == TVAL }} & csr_tval |
{32{rd_addr == TLBRENTRY}} & csr_tlbrentry |
{32{rd_addr == DMW0}} & csr_dmw0 |
{32{rd_addr == DMW1}} & csr_dmw1 |
{32{rd_addr == CPUCFG_1 }} & csr_cpucfg1 |
{32{rd_addr == CPUCFG_2 }} & csr_cpucfg2 |
{32{rd_addr == CPUCFG_10 }} & csr_cpucfg10 |
{32{rd_addr == CPUCFG_11 }} & csr_cpucfg11 |
{32{rd_addr == CPUCFG_12 }} & csr_cpucfg12 |
{32{rd_addr == CPUCFG_13 }} & csr_cpucfg13 ;
//crmd
always @(posedge clk) begin
if (reset) begin
csr_crmd[ `PLV] <= 2'b0;
csr_crmd[ `IE] <= 1'b0;
csr_crmd[ `DA] <= 1'b1;
csr_crmd[ `PG] <= 1'b0;
csr_crmd[`DATF] <= 2'b0;
csr_crmd[`DATM] <= 2'b0;
csr_crmd[31: 9] <= 23'b0;
end
else if (excp_flush) begin
csr_crmd[ `PLV] <= 2'b0;
csr_crmd[ `IE] <= 1'b0;
if (excp_tlbrefill) begin
csr_crmd [`DA] <= 1'b1;
csr_crmd [`PG] <= 1'b0;
end
end
else if (ertn_flush) begin
csr_crmd[ `PLV] <= csr_prmd[`PPLV];
csr_crmd[ `IE] <= csr_prmd[`PIE ];
if (eret_tlbrefill_excp) begin
csr_crmd[`DA] <= 1'b0;
csr_crmd[`PG] <= 1'b1;
end
end
else if (crmd_wen) begin
csr_crmd[ `PLV] <= wr_data[ `PLV];
csr_crmd[ `IE] <= wr_data[ `IE];
csr_crmd[ `DA] <= wr_data[ `DA];
csr_crmd[ `PG] <= wr_data[ `PG];
csr_crmd[`DATF] <= wr_data[`DATF];
csr_crmd[`DATM] <= wr_data[`DATM];
end
end
//prmd
always @(posedge clk) begin
if (reset) begin
csr_prmd[31:3] <= 29'b0;
end
else if (excp_flush) begin
csr_prmd[`PPLV] <= csr_crmd[`PLV];
csr_prmd[ `PIE] <= csr_crmd[`IE ];
end
else if (prmd_wen) begin
csr_prmd[`PPLV] <= wr_data[`PPLV];
csr_prmd[ `PIE] <= wr_data[ `PIE];
end
end
//ectl
always @(posedge clk) begin
if (reset) begin
csr_ectl <= 32'b0;
end
else if (ectl_wen) begin
csr_ectl[ `LIE_1] <= wr_data[ `LIE_1];
csr_ectl[ `LIE_2] <= wr_data[ `LIE_2];
end
end
//estat
always @(posedge clk) begin
if (reset) begin
csr_estat[ 1: 0] <= 2'b0;
csr_estat[10] <= 1'b0;
csr_estat[12] <= 1'b0;
csr_estat[15:13] <= 3'b0;
csr_estat[31] <= 1'b0;
csr_estat[21:16] <= 6'b0;
timer_en <= 1'b0;
end
else begin
if (ticlr_wen && wr_data[`CLR]) begin
csr_estat[11] <= 1'b0;
end
else if (tcfg_wen) begin
timer_en <= wr_data[`EN];
end
else if (timer_en && (csr_tval == 32'b0)) begin
csr_estat[11] <= 1'b1;
timer_en <= csr_tcfg[`PERIODIC];
end
csr_estat[9:2] <= interrupt;
if (excp_flush) begin
csr_estat[ `ECODE] <= ecode_in;
csr_estat[`ESUBCODE] <= esubcode_in;
end
else if (estat_wen) begin
csr_estat[ 1:0] <= wr_data[ 1:0];
end
end
end
//era
always @(posedge clk) begin
if (excp_flush) begin
csr_era <= era_in;
end
else if (era_wen) begin
csr_era <= wr_data;
end
end
//badv
always @(posedge clk) begin
if (badv_wen) begin
csr_badv <= wr_data;
end
else if (va_error_in) begin
csr_badv <= bad_va_in;
end
end
//eentry
always @(posedge clk) begin
if (reset) begin
csr_eentry[5:0] <= 6'b0;
end
else if (eentry_wen) begin
csr_eentry[31:6] <= wr_data[31:6];
end
end
//tlbidx
always @(posedge clk) begin
if (reset) begin
csr_tlbidx[23: 5] <= 19'b0;
csr_tlbidx[30] <= 1'b0;
csr_tlbidx[`INDEX]<= 5'b0;
end
else if (tlbidx_wen) begin
csr_tlbidx[$clog2(TLBNUM)-1:0] <= wr_data[$clog2(TLBNUM)-1:0];
csr_tlbidx[`PS] <= wr_data[`PS];
csr_tlbidx[`NE] <= wr_data[`NE];
end
else if (tlbsrch_en) begin
if (tlbsrch_found) begin
csr_tlbidx[`INDEX] <= tlbsrch_index;
csr_tlbidx[`NE] <= 1'b0;
end
else begin
csr_tlbidx[`NE] <= 1'b1;
end
end
else if (tlbrd_valid_wr_en) begin
csr_tlbidx[`PS] <= tlbidx_in[`PS];
csr_tlbidx[`NE] <= tlbidx_in[`NE];
end
else if (tlbrd_invalid_wr_en) begin
csr_tlbidx[`PS] <= 6'b0;
csr_tlbidx[`NE] <= tlbidx_in[`NE];
end
end
//tlbehi
always @(posedge clk) begin
if (reset) begin
csr_tlbehi[12:0] <= 13'b0;
end
else if (tlbehi_wen) begin
csr_tlbehi[`VPPN] <= wr_data[`VPPN];
end
else if (tlbrd_valid_wr_en) begin
csr_tlbehi[`VPPN] <= tlbehi_in[`VPPN];
end
else if (tlbrd_invalid_wr_en) begin
csr_tlbehi[`VPPN] <= 19'b0;
end
else if (excp_tlb) begin
csr_tlbehi[`VPPN] <= excp_tlb_vppn;
end
end
//tlbelo0
always @(posedge clk) begin
if (reset) begin
csr_tlbelo0[7] <= 1'b0;
end
else if (tlbelo0_wen) begin
csr_tlbelo0[`TLB_V] <= wr_data[`TLB_V];
csr_tlbelo0[`TLB_D] <= wr_data[`TLB_D];
csr_tlbelo0[`TLB_PLV] <= wr_data[`TLB_PLV];
csr_tlbelo0[`TLB_MAT] <= wr_data[`TLB_MAT];
csr_tlbelo0[`TLB_G] <= wr_data[`TLB_G];
csr_tlbelo0[`TLB_PPN_EN] <= wr_data[`TLB_PPN_EN];
end
else if (tlbrd_valid_wr_en) begin
csr_tlbelo0[`TLB_V] <= tlbelo0_in[`TLB_V];
csr_tlbelo0[`TLB_D] <= tlbelo0_in[`TLB_D];
csr_tlbelo0[`TLB_PLV] <= tlbelo0_in[`TLB_PLV];
csr_tlbelo0[`TLB_MAT] <= tlbelo0_in[`TLB_MAT];
csr_tlbelo0[`TLB_G] <= tlbelo0_in[`TLB_G];
csr_tlbelo0[`TLB_PPN_EN] <= tlbelo0_in[`TLB_PPN_EN];
end
else if (tlbrd_invalid_wr_en) begin
csr_tlbelo0[`TLB_V] <= 1'b0;
csr_tlbelo0[`TLB_D] <= 1'b0;
csr_tlbelo0[`TLB_PLV] <= 2'b0;
csr_tlbelo0[`TLB_MAT] <= 2'b0;
csr_tlbelo0[`TLB_G] <= 1'b0;
csr_tlbelo0[`TLB_PPN_EN] <= 20'b0;
end
end
//tlbelo1
always @(posedge clk) begin
if (reset) begin
csr_tlbelo1[7] <= 1'b0;
end
else if (tlbelo1_wen) begin
csr_tlbelo1[`TLB_V] <= wr_data[`TLB_V];
csr_tlbelo1[`TLB_D] <= wr_data[`TLB_D];
csr_tlbelo1[`TLB_PLV] <= wr_data[`TLB_PLV];
csr_tlbelo1[`TLB_MAT] <= wr_data[`TLB_MAT];
csr_tlbelo1[`TLB_G] <= wr_data[`TLB_G];
csr_tlbelo1[`TLB_PPN_EN] <= wr_data[`TLB_PPN_EN];
end
else if (tlbrd_valid_wr_en) begin
csr_tlbelo1[`TLB_V] <= tlbelo1_in[`TLB_V];
csr_tlbelo1[`TLB_D] <= tlbelo1_in[`TLB_D];
csr_tlbelo1[`TLB_PLV] <= tlbelo1_in[`TLB_PLV];
csr_tlbelo1[`TLB_MAT] <= tlbelo1_in[`TLB_MAT];
csr_tlbelo1[`TLB_G] <= tlbelo1_in[`TLB_G];
csr_tlbelo1[`TLB_PPN_EN] <= tlbelo1_in[`TLB_PPN_EN];
end
else if (tlbrd_invalid_wr_en) begin
csr_tlbelo1[`TLB_V] <= 1'b0;
csr_tlbelo1[`TLB_D] <= 1'b0;
csr_tlbelo1[`TLB_PLV] <= 2'b0;
csr_tlbelo1[`TLB_MAT] <= 2'b0;
csr_tlbelo1[`TLB_G] <= 1'b0;
csr_tlbelo1[`TLB_PPN_EN] <= 20'b0;
end
end
//asid
always @(posedge clk) begin
if (reset) begin
csr_asid[31:10] <= 22'h280; //ASIDBITS = 10
end
else if (asid_wen) begin
csr_asid[`TLB_ASID] <= wr_data[`TLB_ASID];
end
else if (tlbrd_valid_wr_en) begin
csr_asid[`TLB_ASID] <= asid_in;
end
else if (tlbrd_invalid_wr_en) begin
csr_asid[`TLB_ASID] <= 10'b0;
end
end
//TLBRENTRY
always @(posedge clk) begin
if (reset) begin
csr_tlbrentry[5:0] <= 6'b0;
end
else if (tlbrentry_wen) begin
csr_tlbrentry[`TLBRENTRY_PA] <= wr_data[`TLBRENTRY_PA];
end
end
//dmw0
always @(posedge clk) begin
if (reset) begin
csr_dmw0[ 2:1] <= 2'b0;
csr_dmw0[24:6] <= 19'b0;
csr_dmw0[28] <= 1'b0;
end
else if (DMW0_wen) begin
csr_dmw0[`PLV0] <= wr_data[`PLV0];
csr_dmw0[`PLV3] <= wr_data[`PLV3];
csr_dmw0[`DMW_MAT] <= wr_data[`DMW_MAT];
csr_dmw0[`PSEG] <= wr_data[`PSEG];
csr_dmw0[`VSEG] <= wr_data[`VSEG];
end
end
//dmw1
always @(posedge clk) begin
if (reset) begin
csr_dmw1[ 2:1] <= 2'b0;
csr_dmw1[24:6] <= 19'b0;
csr_dmw1[28] <= 1'b0;
end
else if (DMW1_wen) begin
csr_dmw1[`PLV0] <= wr_data[`PLV0];
csr_dmw1[`PLV3] <= wr_data[`PLV3];
csr_dmw1[`DMW_MAT] <= wr_data[`DMW_MAT];
csr_dmw1[`PSEG] <= wr_data[`PSEG];
csr_dmw1[`VSEG] <= wr_data[`VSEG];
end
end
//cpuid
always @(posedge clk) begin
if (reset) begin
csr_cpuid <= 32'b0;
end
end
//save0
always @(posedge clk) begin
if (save0_wen) begin
csr_save0 <= wr_data;
end
end
//save1
always @(posedge clk) begin
if (save1_wen) begin
csr_save1 <= wr_data;
end
end
//save2
always @(posedge clk) begin
if (save2_wen) begin
csr_save2 <= wr_data;
end
end
//save3
always @(posedge clk) begin
if (save3_wen) begin
csr_save3 <= wr_data;
end
end
//tid
always @(posedge clk) begin
if (reset) begin
csr_tid <= 32'b0;
end
else if (tid_wen) begin
csr_tid <= wr_data;
end
end
//tcfg
always @(posedge clk) begin
if (reset) begin
csr_tcfg[`EN] <= 1'b0;
end
else if (tcfg_wen) begin
csr_tcfg[ `EN] <= wr_data[ `EN];
csr_tcfg[`PERIODIC] <= wr_data[`PERIODIC];
csr_tcfg[ `INITVAL] <= wr_data[ `INITVAL];
end
end
//cntc
always @(posedge clk) begin
if (reset) begin
csr_cntc <= 32'b0;
end
else if (cntc_wen) begin
csr_cntc <= wr_data;
end
end
//tval
always @(posedge clk) begin
if (tcfg_wen) begin
csr_tval <= {wr_data[ `INITVAL], 2'b0};
end
else if (timer_en) begin
if (csr_tval != 32'b0) begin
csr_tval <= csr_tval - 32'b1;
end
else if (csr_tval == 32'b0) begin
csr_tval <= csr_tcfg[`PERIODIC] ? {csr_tcfg[`INITVAL], 2'b0} : 32'hffffffff;
end
end
end
//ticlr
always @(posedge clk) begin
if (reset) begin
csr_ticlr <= 32'b0;
end
end
//llbctl
always @(posedge clk) begin
if (reset) begin
csr_llbctl[`KLO] <= 1'b0;
csr_llbctl[31:3] <= 29'b0;
csr_llbctl[`WCLLB] <= 1'b0;
llbit <= 1'b0;
end
else if (ertn_flush) begin
if (csr_llbctl[`KLO]) begin
csr_llbctl[`KLO] <= 1'b0;
end
else begin
llbit <= 1'b0;
end
end
else if (llbctl_wen) begin
csr_llbctl[ `KLO] <= wr_data[ `KLO];
if (wr_data[`WCLLB] == 1'b1) begin
llbit <= 1'b0;
end
end
else if (llbit_set_in) begin
llbit <= llbit_in;
end
end
always @(posedge clk) begin
if (reset) begin
lladdr <= 28'b0;
end
else if (lladdr_set_in) begin
lladdr <= lladdr_in;
end
end
//timer_64
always @(posedge clk) begin
if (reset) begin
timer_64 <= 64'b0;
end
else begin
timer_64 <= timer_64 + 1'b1;
end
end
//pgdl
always @(posedge clk) begin
if (pgdl_wen) begin
csr_pgdl[`BASE] <= wr_data[`BASE];
end
end
//pgdh
always @(posedge clk) begin
if (pgdh_wen) begin
csr_pgdh[`BASE] <= wr_data[`BASE];
end
end
//use for break in chipscope in software
always @(posedge clk) begin
if (reset) begin
csr_brk <= 32'b0;
end
if (BRK_wen) begin
csr_brk <= wr_data;
end
end
//use for disable cache or enable cache
always @(posedge clk) begin
if (reset) begin
csr_disable_cache <= 32'b0;
end
if (disable_cache_wen) begin
csr_disable_cache <= wr_data;
end
end
//cpucfg1
always @(posedge clk) begin
if (reset) begin
csr_cpucfg1 <= 32'h1f1f4;
end
end
//cpucfg2
always @(posedge clk) begin
if (reset) begin
csr_cpucfg2 <= 32'h0;
end
end
//cpucfg10
always @(posedge clk) begin
if (reset) begin
csr_cpucfg10 <= 32'h5;
end
end
//cpucfg11
always @(posedge clk) begin
if (reset) begin
csr_cpucfg11 <= 32'h04080001;
end
end
//cpucfg12
always @(posedge clk) begin
if (reset) begin
csr_cpucfg12 <= 32'h04080001;
end
end
//cpucfg13
always @(posedge clk) begin
if (reset) begin
csr_cpucfg13 <= 32'h0;
end
end
// difftest
`ifdef DIFFTEST_EN
assign csr_crmd_diff = csr_crmd;
assign csr_prmd_diff = csr_prmd;
assign csr_ectl_diff = csr_ectl;
assign csr_estat_diff = csr_estat;
assign csr_era_diff = csr_era;
assign csr_badv_diff = csr_badv;
assign csr_eentry_diff = csr_eentry;
assign csr_tlbidx_diff = csr_tlbidx;
assign csr_tlbehi_diff = csr_tlbehi;
assign csr_tlbelo0_diff = csr_tlbelo0;
assign csr_tlbelo1_diff = csr_tlbelo1;
assign csr_asid_diff = csr_asid;
assign csr_save0_diff = csr_save0;
assign csr_save1_diff = csr_save1;
assign csr_save2_diff = csr_save2;
assign csr_save3_diff = csr_save3;
assign csr_tid_diff = csr_tid;
assign csr_tcfg_diff = csr_tcfg;
assign csr_tval_diff = csr_tval;
assign csr_ticlr_diff = csr_ticlr;
assign csr_llbctl_diff = {csr_llbctl[31:1], llbit};
assign csr_tlbrentry_diff = csr_tlbrentry;
assign csr_dmw0_diff = csr_dmw0;
assign csr_dmw1_diff = csr_dmw1;
assign csr_pgdl_diff = csr_pgdl;
assign csr_pgdh_diff = csr_pgdh;
`endif
endmodule

651
rtl/ip/open-la500/dcache.v Normal file
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module dcache
(
input clk ,
input reset ,
//to from cpu
input valid ,
input op , //cache inst treat as load, op is zero
input [ 2:0] size ,
input [ 7:0] index ,
input [19:0] tag ,
input [ 3:0] offset ,
input [ 3:0] wstrb ,
input [31:0] wdata ,
output addr_ok ,
output data_ok ,
output [31:0] rdata ,
input uncache_en ,
input dcacop_op_en ,
input [ 1:0] cacop_op_mode,
input [ 4:0] preld_hint ,
input preld_en ,
input tlb_excp_cancel_req,
input sc_cancel_req,
output dcache_empty ,
//to from axi
output rd_req ,
output [ 2:0] rd_type ,
output [31:0] rd_addr ,
input rd_rdy ,
input ret_valid ,
input ret_last ,
input [31:0] ret_data ,
output reg wr_req ,
output [ 2:0] wr_type ,
output [31:0] wr_addr ,
output [ 3:0] wr_wstrb ,
output [127:0] wr_data ,
input wr_rdy ,
//to perf_counter
output cache_miss
);
reg [1:0] way_d_reg [255:0];
wire request_uncache_en ;
reg request_buffer_op ;
reg request_buffer_preld ;
reg [ 2:0] request_buffer_size ;
reg [ 7:0] request_buffer_index ;
reg [19:0] request_buffer_tag ;
reg [ 3:0] request_buffer_offset ;
reg [ 3:0] request_buffer_wstrb ;
reg [31:0] request_buffer_wdata ;
reg request_buffer_uncache_en ;
reg request_buffer_dcacop ;
reg [ 1:0] request_buffer_cacop_op_mode;
reg [ 1:0] miss_buffer_replace_way ;
reg [ 1:0] miss_buffer_ret_num ;
wire [ 1:0] ret_num_add_one ;
reg [ 7:0] write_buffer_index ;
reg [ 3:0] write_buffer_wstrb ;
reg [31:0] write_buffer_wdata ;
reg [ 1:0] write_buffer_way ;
reg [ 3:0] write_buffer_offset ;
wire [ 7:0] way_bank_addra [1:0][3:0];
wire [31:0] way_bank_dina [1:0][3:0];
wire [31:0] way_bank_douta [1:0][3:0];
wire way_bank_ena [1:0][3:0];
wire [ 3:0] way_bank_wea [1:0][3:0];
wire [ 7:0] way_tagv_addra [1:0];
wire [20:0] way_tagv_dina [1:0];
wire [20:0] way_tagv_douta [1:0];
wire way_tagv_ena [1:0];
wire way_tagv_wea [1:0];
wire wr_match_way_bank[1:0][3:0];
wire [ 1:0] way_d ;
wire [ 1:0] way_hit ;
wire cache_hit ;
wire [31:0] way_load_word [1:0];
wire [127:0] way_data [1:0];
wire [31:0] load_res ;
wire [127:0] replace_data ;
wire replace_d ;
wire replace_v ;
wire [19:0] replace_tag ;
wire [ 1:0] random_val ;
wire [ 3:0] chosen_way ;
wire [ 1:0] replace_way ;
wire [ 1:0] invalid_way ;
wire has_invalid_way ;
wire [ 1:0] rand_repl_way ;
wire [ 3:0] cacop_chose_way ;
wire main_idle2lookup ;
wire main_lookup2lookup;
wire main_state_is_idle ;
wire main_state_is_lookup ;
wire main_state_is_miss ;
wire main_state_is_replace;
wire main_state_is_refill ;
wire write_state_is_idle;
wire write_state_is_full;
wire uncache_wr ;
reg uncache_wr_buffer;
wire [ 2:0] uncache_wr_type;
wire [ 1:0] way_wr_en;
wire [31:0] refill_data;
wire [31:0] write_in;
wire cacop_op_mode0;
wire cacop_op_mode1;
wire cacop_op_mode2;
wire cacop_op_mode2_hit_wr;
reg cacop_op_mode2_hit_wr_buffer;
wire preld_st_en;
wire preld_ld_en;
wire preld_ld_st_en;
wire req_or_inst_valid;
reg [1:0] lookup_way_hit_buffer;
localparam main_idle = 5'b00001;
localparam main_lookup = 5'b00010;
localparam main_miss = 5'b00100;
localparam main_replace = 5'b01000;
localparam main_refill = 5'b10000;
localparam write_buffer_idle = 1'b0;
localparam write_buffer_write = 1'b1;
genvar i,j;
reg [4:0] main_state;
reg write_buffer_state;
reg rd_req_buffer;
// wire invalid_way;
wire cancel_req = tlb_excp_cancel_req || sc_cancel_req;
//state machine
//main loop
always @(posedge clk) begin
if (reset) begin
main_state <= main_idle;
request_buffer_op <= 1'b0;
request_buffer_preld <= 1'b0;
request_buffer_size <= 3'b0;
request_buffer_index <= 8'b0;
request_buffer_tag <= 20'b0;
request_buffer_offset <= 4'b0;
request_buffer_wstrb <= 4'b0;
request_buffer_wdata <= 32'b0;
request_buffer_uncache_en <= 1'b0;
request_buffer_cacop_op_mode <= 2'b0;
request_buffer_dcacop <= 1'b0;
miss_buffer_replace_way <= 2'b0;
wr_req <= 1'b0;
end
else case (main_state)
main_idle: begin
if (req_or_inst_valid && main_idle2lookup) begin
main_state <= main_lookup;
request_buffer_op <= op ;
request_buffer_preld <= preld_en ;
request_buffer_size <= size ;
request_buffer_index <= index ;
request_buffer_offset <= offset ;
request_buffer_wstrb <= wstrb ;
request_buffer_wdata <= wdata ;
request_buffer_cacop_op_mode <= cacop_op_mode ;
request_buffer_dcacop <= dcacop_op_en ;
end
end
main_lookup: begin
if (req_or_inst_valid && main_lookup2lookup) begin
main_state <= main_lookup;
request_buffer_op <= op ;
request_buffer_preld <= preld_en ;
request_buffer_size <= size ;
request_buffer_index <= index ;
request_buffer_offset <= offset ;
request_buffer_wstrb <= wstrb ;
request_buffer_wdata <= wdata ;
request_buffer_cacop_op_mode <= cacop_op_mode ;
request_buffer_dcacop <= dcacop_op_en ;
end
else if (cancel_req) begin
main_state <= main_idle;
end
else if (!cache_hit) begin
//uncache wr --> wr_req 1
//uncache rd, cacop(code==0) --> wr_req 0
//cacop(code==1, 2), cache st, cache ld --> wr_req (dirty && valid)
if (uncache_wr || ((replace_d && replace_v) && (!request_uncache_en || cacop_op_mode2_hit_wr) && !cacop_op_mode0))
main_state <= main_miss;
else
main_state <= main_replace;
request_buffer_tag <= tag;
request_buffer_uncache_en <= request_uncache_en;
uncache_wr_buffer <= uncache_wr;
miss_buffer_replace_way <= replace_way;
cacop_op_mode2_hit_wr_buffer <= cacop_op_mode2_hit_wr;
end
else begin
main_state <= main_idle;
end
end
main_miss: begin
if (wr_rdy) begin
main_state <= main_replace;
wr_req <= 1'b1;
end
end
main_replace: begin
if (rd_rdy) begin
main_state <= main_refill;
miss_buffer_ret_num <= 2'b0; //when get ret data, it will be sent to cpu directly.
end
wr_req <= 1'b0;
end
main_refill: begin
if ((ret_valid && ret_last) || !rd_req_buffer) begin //when rd_req is not set, go to next state directly
main_state <= main_idle;
end
else begin
if (ret_valid) begin
miss_buffer_ret_num <= ret_num_add_one;
end
end
end
default: begin
main_state <= main_idle;
end
endcase
end
//hit write state
always @(posedge clk) begin
if (reset) begin
write_buffer_state <= write_buffer_idle;
write_buffer_index <= 8'b0;
write_buffer_wstrb <= 4'b0;
write_buffer_wdata <= 32'b0;
write_buffer_offset <= 4'b0;
write_buffer_way <= 2'b0;
end
else case (write_buffer_state)
write_buffer_idle: begin
if (main_state_is_lookup && cache_hit && request_buffer_op && !cancel_req) begin
write_buffer_state <= write_buffer_write;
write_buffer_index <= request_buffer_index;
write_buffer_wstrb <= request_buffer_wstrb;
write_buffer_wdata <= request_buffer_wdata;
write_buffer_offset <= request_buffer_offset;
write_buffer_way <= way_hit;
end
end
write_buffer_write: begin
if (main_state_is_lookup && cache_hit && request_buffer_op && !cancel_req) begin
write_buffer_state <= write_buffer_write;
write_buffer_index <= request_buffer_index;
write_buffer_wstrb <= request_buffer_wstrb;
write_buffer_wdata <= request_buffer_wdata;
write_buffer_offset <= request_buffer_offset;
write_buffer_way <= way_hit;
end
else begin
write_buffer_state <= write_buffer_idle;
end
end
endcase
end
/*====================================main state idle=======================================*/
assign req_or_inst_valid = valid || dcacop_op_en || preld_en;
//state change condition, write hit cache block write do not conflict with lookup read and cacop
assign main_idle2lookup = !(write_state_is_full && ((write_buffer_offset[3:2] == offset[3:2]) || dcacop_op_en));
assign dcache_empty = main_state_is_idle;
//addr_ok logic
/*===================================main state lookup======================================*/
//tag compare
generate for(i=0;i<2;i=i+1) begin:gen_way_hit
assign way_hit[i] = way_tagv_douta[i][0] && (tag == way_tagv_douta[i][20:1]); //this signal will not maintain
end endgenerate
assign cache_hit = |way_hit && !(uncache_en || cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2); //uncache road reuse
//when cache inst op mode2 no hit, main state machine will still go a round. implement easy.
assign main_lookup2lookup = !(write_state_is_full && ((write_buffer_offset[3:2] == offset[3:2]) || dcacop_op_en)) &&
!(request_buffer_op && !op && ((request_buffer_offset[3:2] == offset[3:2]) || dcacop_op_en)) &&
cache_hit;
assign addr_ok = (main_state_is_idle && main_idle2lookup) || (main_state_is_lookup && main_lookup2lookup); //request can be get
//data select
generate for(i=0;i<2;i=i+1) begin:gen_way_data
assign way_data[i] = {way_bank_douta[i][3],way_bank_douta[i][2],way_bank_douta[i][1],way_bank_douta[i][0]};
assign way_load_word[i] = way_data[i][request_buffer_offset[3:2]*32 +: 32];
end endgenerate
assign load_res = {32{way_hit[0]}} & way_load_word[0] |
{32{way_hit[1]}} & way_load_word[1] ;
assign request_uncache_en = (uncache_en && !request_buffer_dcacop);
assign uncache_wr = request_uncache_en && request_buffer_op && !cacop_op_mode1 && !cacop_op_mode2_hit_wr;
//data_ok logic
decoder_2_4 dec_rand_way (.in({1'b0,random_val[0]}),.out(chosen_way));
one_valid_n #(2) sel_one_invalid (.in(~{way_tagv_douta[1][0],way_tagv_douta[0][0]}),.out(invalid_way),.nozero(has_invalid_way));
assign rand_repl_way = has_invalid_way ? invalid_way : chosen_way[1:0]; //chose invalid way first.
decoder_2_4 dec_cacop_way (.in({1'b0,request_buffer_offset[0]}),.out(cacop_chose_way));
assign replace_way = {2{cacop_op_mode0 || cacop_op_mode1}} & cacop_chose_way[1:0] |
{2{cacop_op_mode2}} & way_hit |
{2{!request_buffer_dcacop}} & rand_repl_way;
assign way_d = way_d_reg[request_buffer_index] |
{2{(write_buffer_index==request_buffer_index)&&write_state_is_full}}&write_buffer_way;
assign replace_d = |(replace_way & way_d);
assign replace_v = |(replace_way & {way_tagv_douta[1][0],way_tagv_douta[0][0]});
/*====================================main state miss=======================================*/
assign replace_tag = {20{miss_buffer_replace_way[0]}} & way_tagv_douta[0][20:1] |
{20{miss_buffer_replace_way[1]}} & way_tagv_douta[1][20:1] ;
assign replace_data = {128{miss_buffer_replace_way[0]}} & way_data[0] |
{128{miss_buffer_replace_way[1]}} & way_data[1] ;
assign wr_type = uncache_wr_buffer ? uncache_wr_type : 3'b100; //replace cache line
assign wr_addr = uncache_wr_buffer ? {request_buffer_tag, request_buffer_index, request_buffer_offset} :
{replace_tag, request_buffer_index, 4'b0};
assign wr_data = uncache_wr_buffer ? {96'b0, request_buffer_wdata} : replace_data;
assign wr_wstrb = uncache_wr_buffer ? request_buffer_wstrb : 4'hf;
//assign wr_req = main_state_is_miss;
/*==================================main state replace======================================*/
assign uncache_wr_type = request_buffer_size;
assign rd_req = main_state_is_replace && !(uncache_wr_buffer || cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2);
assign rd_type = request_buffer_uncache_en ? request_buffer_size : 3'b100;
assign rd_addr = request_buffer_uncache_en ? {request_buffer_tag, request_buffer_index, request_buffer_offset} : {request_buffer_tag, request_buffer_index, 4'b0};
/*===================================main state refill======================================*/
//write process will not block pipeline
//preld ins will not block pipeline ps:preld is not real mem inst, this operation is controled in pipeline
assign data_ok = ((main_state_is_lookup && (cache_hit || request_buffer_op || cancel_req)) ||
(main_state_is_refill && (!request_buffer_op && (ret_valid && ((miss_buffer_ret_num == request_buffer_offset[3:2]) || request_buffer_uncache_en))))) &&
!(request_buffer_preld || request_buffer_dcacop); //when rd_req is not set, set data_ok directly.
//rdate connect with ret_data dirctly. maintain one clock only
assign write_in = {(request_buffer_wstrb[3] ? request_buffer_wdata[31:24] : ret_data[31:24]),
(request_buffer_wstrb[2] ? request_buffer_wdata[23:16] : ret_data[23:16]),
(request_buffer_wstrb[1] ? request_buffer_wdata[15: 8] : ret_data[15: 8]),
(request_buffer_wstrb[0] ? request_buffer_wdata[ 7: 0] : ret_data[ 7: 0])};
assign refill_data = (request_buffer_op && (request_buffer_offset[3:2] == miss_buffer_ret_num)) ? write_in : ret_data;
assign way_wr_en = miss_buffer_replace_way & {2{ret_valid}}; //when rd_req is not set, ret_valid and ret_last will not be set. block will not be wr also.
assign cache_miss = main_state_is_refill && ret_last && !(request_buffer_uncache_en || request_buffer_dcacop || request_buffer_preld);
//add one
assign ret_num_add_one[0] = miss_buffer_ret_num[0] ^ 1'b1;
assign ret_num_add_one[1] = miss_buffer_ret_num[1] ^ miss_buffer_ret_num[0];
always @(posedge clk) begin
if (reset) begin
rd_req_buffer <= 1'b0;
end
else if (rd_req) begin
rd_req_buffer <= 1'b1;
end
else if (main_state_is_refill && (ret_valid && ret_last)) begin
rd_req_buffer <= 1'b0;
end
end
/*==========================================================================================*/
//refill or write state update dirty reg
always @(posedge clk) begin
if (main_state_is_refill && ((ret_valid && ret_last) || !rd_req_buffer) && (!(request_buffer_uncache_en || cacop_op_mode0))) begin
way_d_reg[request_buffer_index][0] <= miss_buffer_replace_way[0] ? request_buffer_op : way_d_reg[request_buffer_index][0];
way_d_reg[request_buffer_index][1] <= miss_buffer_replace_way[1] ? request_buffer_op : way_d_reg[request_buffer_index][1];
end
else if (write_state_is_full) begin
way_d_reg[write_buffer_index] <= way_d_reg[write_buffer_index] | write_buffer_way;
end
end
//cache ins control signal
assign cacop_op_mode0 = request_buffer_dcacop && (request_buffer_cacop_op_mode == 2'b00);
assign cacop_op_mode1 = request_buffer_dcacop && ((request_buffer_cacop_op_mode == 2'b01) || (request_buffer_cacop_op_mode == 2'b11));
assign cacop_op_mode2 = request_buffer_dcacop && (request_buffer_cacop_op_mode == 2'b10);
assign cacop_op_mode2_hit_wr = cacop_op_mode2 && |way_hit;
//output
assign rdata = {32{main_state_is_lookup}} & load_res |
{32{main_state_is_refill}} & ret_data ;
generate
for(i=0;i<2;i=i+1) begin:gen_data_way
for(j=0;j<4;j=j+1) begin:gen_data_bank
/*===============================bank addra logic==============================*/
assign wr_match_way_bank[i][j] = write_state_is_full && (write_buffer_way[i] && (write_buffer_offset[3:2] == j[1:0]));
assign way_bank_addra[i][j] = wr_match_way_bank[i][j] ? write_buffer_index : ({8{addr_ok}} & index | /*lookup*/
{8{!addr_ok}} & request_buffer_index);
/*===============================bank we logic=================================*/
assign way_bank_wea[i][j] = {4{wr_match_way_bank[i][j]}} & write_buffer_wstrb |
{4{main_state_is_refill && (way_wr_en[i] && (miss_buffer_ret_num == j[1:0]))}} & 4'hf;
/*===============================bank dina logic=================================*/
assign way_bank_dina[i][j] = {32{write_state_is_full}} & write_buffer_wdata |
{32{main_state_is_refill}} & refill_data ;
/*===============================bank ena logic=================================*/
assign way_bank_ena[i][j] = (!(request_buffer_uncache_en || cacop_op_mode0)) || main_state_is_idle || main_state_is_lookup;
end
end
endgenerate
generate
for(i=0;i<2;i=i+1) begin:gen_tagv_way
/*===============================tagv addra logic=================================*/
assign way_tagv_addra[i] = {8{addr_ok }} & index |
{8{!addr_ok}} & request_buffer_index ;
/*===============================tagv ena logic=================================*/
assign way_tagv_ena[i] = (!request_buffer_uncache_en) || main_state_is_idle || main_state_is_lookup;
/*===============================tagv wea logic=================================*/
assign way_tagv_wea[i] = miss_buffer_replace_way[i] && main_state_is_refill &&
((ret_valid && ret_last) || cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2_hit_wr_buffer); //write at least 4B
/*===============================tagv dina logic=================================*/
assign way_tagv_dina[i] = (cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2_hit_wr_buffer) ? 21'b0 : {request_buffer_tag, 1'b1};
end
endgenerate
/*==============================================================================*/
generate
for(i=0;i<2;i=i+1) begin:data_ram_way
for(j=0;j<4;j=j+1) begin:data_ram_bank
data_bank_sram u(
.addra (way_bank_addra[i][j]),
.clka (clk ),
.dina (way_bank_dina[i][j] ),
.douta (way_bank_douta[i][j]),
.ena (way_bank_ena[i][j] ),
.wea (way_bank_wea[i][j] )
);
end
end
endgenerate
generate
for(i=0;i<2;i=i+1) begin:tagv_ram_way
//[20:1] tag [0:0] v
tagv_sram u(
.addra (way_tagv_addra[i]),
.clka (clk ),
.dina (way_tagv_dina[i] ),
.douta (way_tagv_douta[i]),
.ena (way_tagv_ena[i] ),
.wea (way_tagv_wea[i] )
);
end
endgenerate
lfsr lfsr(
.clk (clk ),
.reset (reset ),
.random_val (random_val )
);
assign main_state_is_idle = main_state == main_idle ;
assign main_state_is_lookup = main_state == main_lookup ;
assign main_state_is_miss = main_state == main_miss ;
assign main_state_is_replace = main_state == main_replace;
assign main_state_is_refill = main_state == main_refill ;
assign write_state_is_idle = (write_buffer_state == write_buffer_idle) ;
assign write_state_is_full = (write_buffer_state == write_buffer_write);
endmodule
`ifdef SIMU
module data_bank_sram
#(
parameter WIDTH = 32 ,
parameter DEPTH = 256
)
(
input [ 7:0] addra ,
input clka ,
input [31:0] dina ,
output [31:0] douta ,
input ena ,
input [ 3:0] wea
);
reg [31:0] mem_reg [255:0];
reg [31:0] output_buffer;
always @(posedge clka) begin
if (ena) begin
if (wea) begin
if (wea[0]) begin
mem_reg[addra][ 7: 0] <= dina[ 7: 0];
end
if (wea[1]) begin
mem_reg[addra][15: 8] <= dina[15: 8];
end
if (wea[2]) begin
mem_reg[addra][23:16] <= dina[23:16];
end
if (wea[3]) begin
mem_reg[addra][31:24] <= dina[31:24];
end
end
else begin
output_buffer <= mem_reg[addra];
end
end
end
assign douta = output_buffer;
endmodule
module tagv_sram
#(
parameter WIDTH = 21 ,
parameter DEPTH = 256
)
(
input [ 7:0] addra ,
input clka ,
input [20:0] dina ,
output [20:0] douta ,
input ena ,
input wea
);
reg [20:0] mem_reg [255:0];
reg [20:0] output_buffer;
always @(posedge clka) begin
if (ena) begin
if (wea) begin
mem_reg[addra] <= dina;
end
else begin
output_buffer <= mem_reg[addra];
end
end
end
assign douta = output_buffer;
endmodule
`endif
module lfsr
(
input clk ,
input reset ,
output [1:0] random_val
);
reg [7:0] r_lfsr;
always @(posedge clk) begin
if (reset) begin
r_lfsr <= 8'b1;
end
else begin
r_lfsr[0] <= r_lfsr[7];
r_lfsr[1] <= r_lfsr[0];
r_lfsr[2] <= r_lfsr[1];
r_lfsr[3] <= r_lfsr[2];
r_lfsr[4] <= r_lfsr[3] ^ r_lfsr[7];
r_lfsr[5] <= r_lfsr[4] ^ r_lfsr[7];
r_lfsr[6] <= r_lfsr[5] ^ r_lfsr[7];
r_lfsr[7] <= r_lfsr[6];
end
end
assign random_val = r_lfsr[7:6];
endmodule

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//x/y //执行需要34个周期
module div(
input div_clk, reset,
input div,
input div_signed,
input [31:0] x, y,
output [31:0] s, r,
output complete
);
reg [32:0] UnsignS;
reg [32:0] UnsignR;
reg [32:0] tmp_r;
reg [7:0] count;
wire [32:0] tmp_d;
wire [32:0] result_r;
wire [32:0] UnsignX, UnsignY;
reg div_signed_buffer;
reg x_31_buffer;
reg y_31_buffer;
wire real_div_signed;
wire real_x_31;
wire real_y_31;
wire complete_delay;
wire real_complete;
assign complete_delay = (count == 8'hf0);
assign real_complete = complete_delay || complete;
always @(posedge div_clk) begin
if (reset) begin
div_signed_buffer <= 1'b0;
x_31_buffer <= 1'b0;
y_31_buffer <= 1'b0;
end
else if (div) begin
div_signed_buffer <= div_signed; //when div inst go to ms, div_signed will be changed. so buffer it.
x_31_buffer <= x[31];
y_31_buffer <= y[31];
end
end
assign real_div_signed = real_complete ? div_signed_buffer : div_signed;
assign real_x_31 = real_complete ? x_31_buffer : x[31];
assign real_y_31 = real_complete ? y_31_buffer : y[31];
assign UnsignX = {1'b0, (real_div_signed ? (x[31] ? (~x + 32'b1) : x) : x)}; //取绝对值并扩展至33位
assign UnsignY = {1'b0, (real_div_signed ? (y[31] ? (~y + 32'b1) : y) : y)};
always @(posedge div_clk) begin //33位除法计算
if (reset) begin
count <= 8'd32;
tmp_r <= 33'b0;
UnsignS <= 33'b0;
UnsignR <= 33'b0;
end
else if (~div || complete_delay) begin
count <= 8'd32; //计算33次
tmp_r <= 33'b0;
end
else if (~(count[7])) begin
if (tmp_d[32]) begin //tmp_d为负数
UnsignS <= {UnsignS[31:0], 1'b0};
tmp_r <= result_r;
end
else begin
UnsignS <= {UnsignS[31:0], 1'b1};
tmp_r <= tmp_d;
end
count <= count - 8'd1;
end
else begin
UnsignR <= tmp_r;
count <= 8'hf0; //complete signal only maintain one clock
end
end
assign complete = (count == 8'hff);//chenji
assign result_r = {tmp_r[31:0], UnsignX[count]};
assign tmp_d = result_r - UnsignY;
wire [32:0] TmpS, TmpR;
assign TmpS = (real_div_signed ? ((real_x_31 == real_y_31) ? UnsignS : ~(UnsignS - 1)) : UnsignS); //去绝对值并截位
assign TmpR = (real_div_signed ? (real_x_31 ? ~(UnsignR - 1) : UnsignR) : UnsignR);
assign s = TmpS[31:0];
assign r = TmpR[31:0];
endmodule
//表达式的符号关系
//x[31] y[31] s[31] r[31]
// 0 0 0 0
// 0 1 1 0
// 1 0 1 1
// 1 1 0 1

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# LaCC 接口
LaCC(Loongarch32R Custom Coprocessor Interface) 接口是 Open-LA500 用于扩展自定义指令的接口。
# 指令格式
![](./picture/lacc_inst.png)
| 域 | 描述 |
| ------ | --------------------------------------------------- |
| opcode | 固定为1100,用于确定当前指令 |
| command| 用于编码多个自定义指令，将发送至lacc接口 |
| imm | 额外的立即数 |
| rj | 第一个寄存器的编码 |
| rk | 第二个寄存器的编码 |
| rd | 目的寄存器编码，当目的寄存器不为0时会写回寄存器堆中 |
# 接口定义
> 方向为协处理器视角
| 通道 | 方向 | 宽度 | 信号名 | 描述 |
| -------- | ------ | ------------- | --------------- | ------------------------------------------------------------ |
| 全局 | input | 1 | lacc_flush | 当处理器触发异常或分支预测失败时将该信号置位 |
| 请求 | input | 1 | lacc_req_valid | 处理器核发送请求 |
| 请求 | input | LACC_OP_WIDTH | lacc_req_command| 指令中的command域 |
| 请求 | input | 7 | lacc_req_imm | 指令中的imm域 |
| 请求 | input | 32 | lacc_req_rj | 第一个寄存器的值 |
| 请求 | input | 32 | lacc_req_rk | 第二个寄存器的值 |
| 回复 | output | 1 | lacc_rsp_valid | 指令完成信号，处理器将继续执行 |
| 回复 | output | 32 | lacc_rsp_rdat | 写回寄存器的数据 |
| 访存请求 | output | 1 | lacc_data_valid | 向dcache发送的访存请求信号 |
| 访存请求 | input | 1 | lacc_data_ready | dcache当前是否可以接受请求 |
| 访存请求 | output | 32 | lacc_data_addr | 访存地址 |
| 访存请求 | output | 1 | lacc_data_read | 是否为读请求 |
| 访存请求 | output | 32 | lacc_data_wdata | 写入数据 |
| 访存请求 | output | 2 | lacc_data_size | 访存数据大小 <br>2'b00: byte<br>2'b01: half<br>2'b10: word |
| 访存回复 | input | 1 | lacc_drsp_valid | dcache发送的回复信号<br>写请求将会在第二周期接收到该回复<br>读请求将会在dcache成功后接收 |
| 访存回复 | input | 32 | lacc_drsp_data | 访存得到的数据 |
# 运行流程
1. 在解码阶段解析 lacc 指令，并将 op 和 imm 发送给执行阶段
2. 在执行阶段`lacc_req_valid`为1，lacc接口将接受 lacc 指令并暂停，直到`lacc_rsp_valid`为高才会将指令发送给下一级
3. 如果需要访存，可以将 `lacc_data_valid` 置高并设置访存地址及大小等信息。当`lacc_data_valid`和`lacc_data_ready`同时为高则当前请求成功发送至dcache。
4. 当指令执行完成之后将`lacc_rsp_valid`置高，指令将从 exe 级继续执行
lacc读请求时序,读取地址为0x1C0FFF38，读取数据为0x00000000
![](./picture/lacc_read.png)
lacc写请求时序，写入地址为0x1C0FFEE8,写入数据为0x70A3A52B
![](./picture/lacc_write.png)
# 自定义指令
添加自定义指令只需两步：
1. 修改`mycpu.h`中的`LACC_OP_SIZE`为自定义指令数量（若`LACC_OP_SIZE`为1需要修改`LACC_OP_WIDTH`为1），并且取消`HAS_LACC`的注释
2. 在`lacc_core.v`中删除示例`lacc_demo`，写入自定指令代码
# demo
demo实现了从两个地址载入向量，点乘之后再存入缓存中的功能，代码位于`lacc_demo.v`中。
## 指令
| 指令 | op | rj | rk | 描述 |
| -------- | ---- | ----- | ----- | ----------------------------------------------- |
| op_cfg | 1 | size | waddr | 设置写回地址及向量长度 |
| op_lmadd | 0 | addr1 | addr2 | 设置需要计算的两个内存地址，对位相加再存入waddr |
## 状态机
| 状态 | 说明 | 转换条件 | 下一状态 |
| --------- | --------------- | ----------------------------------------- | --------- |
| IDLE | | lacc_req_valid & op_lmadd | REQ_ADDR1 |
| REQ_ADDR1 | 访问addr1的数据 | data_hsk(访问addr1数据) | REQ_ADDR2 |
| REQ_ADDR2 | 访问addr2的数据 | data_hsk(访问addr2数据) | FINAL |
| FINAL | 计算结果并写回 | data_hsk & req_size_nz(写入数据且size!=0) | REQ_ADDR1 |
| FINAL | | data_hsk & ~req_size_nz | IDLE |
data_hsk即`lacc_data_valid & lacc_data_ready`，表明当前访存请求发送成功。
**数据控制**
使用buffer_valid信号表示第一个地址的数据是否被接收。wdata_valid表示写回数据准备完成
当`buffer_valid & lacc_drsp_valid`为高时说明第二个地址的数据已经返回，在该周期计算`buffer_data+lacc_drsp_rdata`并写入wdata
# 修改编译器
我们可以使用".word xxxxxxx"的格式在汇编中添加自定义指令。但是这种方式阅读不够友好，并且不利于操作数读写，例如
```c
asm volatile (
"move $r5, %[addr]\n\t"
"move $r6, %[para]\n\t"
".word 0xc00018a0\n\t"
::[addr]"r"(addr),[para]"r"(para)
:"$r5", "$r6"
);
```
**修改编译器**
我们可以修改binutils使得编译器可以识别自定义指令。
- 下载loongarch toolchain: https://gitee.com/loongson-edu/la32r-toolchains/tree/master
- 进入src/la32r_binutils/opcodes,打开loongarch-opc.c,在`loongarch_fix_opcodes`结构体中添加
```c
{0xc0000000, 0xf0000000, "lacc", "u22:6,r0:5,r5:5,r10:5,u15:7", 0, 0, 0, 0}
```
- 根据toolchina的README编译，并将bin目录添加到path中
自定义指令的格式为:
```
lacc command, rd, rj, rk, imm
```
上例可以修改为：
```c
asm volatile (
"lacc 0x0, $r0, %[addr], %[para], 0x0\n\t"
::[addr]"r"(addr), [para]"r"(para)
);
```

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# 分支预测
分支预测即根据分支历史，提前预测指令跳转方向及跳转目标。分支预测器种类繁多，例如BTB（Branch Target Buffer）、BHT（Branch History Table）、RAS（Return Address Stack）等，但适用于五级流水的其实并不多。如设计概述中所介绍的，五级流水中，pfs级发出取指请求，fs级取回指令，ds级开始译码，并明确跳转指令的所有信息。也就表示分支预测只有一拍的空间可以利用，且无预译码，可依据的信息只有pc，跳转方向及跳转目标都只能靠猜。适用的实际上仅有BTB。不过对于较为特殊的jirl指令，即寄存器跳转，若直接采用BTB的机制，会使得命中率极低。因此，在BTB的基础上进行改造，由CAM表记录jirl指令的pc，并由RAS机制预测其跳转目标。
----
接下来介绍分支预测器的具体实现，分为两点：分支预测器的内部实现；分支预测器同流水线的交互。
## 分支预测器设计
分支预测器的逻辑可以分为两个部分，由PC进行预测跳转目标及跳转方向的预测部分；根据指令译码结果与分支预测器预测结果的比较，对分支预测器历史信息进行修正的修正部分。
### 预测部分
首先来看模块的接口。
- fetch_pc：取指pc
- fetch_en：取指使能
- ret_en：预测结果使能
- ret_pc：预测跳转目标
- taken：预测跳转方向
- ret_index：指示当前预测结果的对应项，用于修正
btb表有32项，包含四个内容：
- btb_pc：30位，用于和取指pc匹配
- btb_target：30位，存放跳转目标
- btb_counter：2位，由最高位指示跳转方向
- btb_valid：1位，当前项是否有效
对于jirl指令的预测逻辑由两部分组成，16项的CAM表以及8项的RAS。
CAM表包含两个内容：
- ras_pc：30位，用于和取指pc匹配
- ras_valid：1位，当前项是否有效
RAS简单来说就是一个栈。存储30位的跳转目标，由ras_ptr指示栈顶。
明确表项内容后，来看预测逻辑。fetch_en以及fetch_pc进入分支预测器时，首先缓存一拍。单看分支预测器，缓存插在什么位置其实都可以，只要有一拍的延迟即可，但考虑到赋值nextpc即fetch_pc的路径非常长，因此将缓存插在靠前的位置。缓存后的信号为fetch_en_r及fetch_pc_r，将其与两个CAM的PC部分，btb_pc和ras_pc进行匹配。该项有效且pc匹配则表示命中。命中项记录在btb_match_rd和ras_match_rd中。
两个表中有一项命中，则置起ret_en。若命中在btb CAM表中，ret_pc取对应项的btb_target即可，若命中在ras CAM表中，则取ras栈顶的跳转目标。理论上btb_match_rd和ras_match_rd为one-hot且只会命中在一个表中，因此不必使用优先级逻辑。ret_index同理，而taken在btb_match时，需要看对应项btb_counter最高位，而ras_match时，直接置为1。预测阶段不会对分支预测器的历史信息进行任何修正。
### 修正部分
在ds译码级，汇总分支预测信息以及译码得到的正确分支跳转信息。
预测信息同上：
- ds_btb_target
- ds_btb_index
- ds_btb_taken
- ds_btb_en
正确的分支跳转信息如下：
- br_to_btb：表示当前指令是否为分支预测器所覆盖的跳转指令，当前结构的分支预测器覆盖所有跳转指令。
- br_taken：跳转方向
- br_target：跳转目标
译码级根据以上信息，稍加分析并传递至分支预测器，传递信息包括：
- operate_en：分支预测器修正操作使能。注意该信号需要在ds_ready_go、es_allowin和ds_valid为1时置起且无例外。只有ds当拍允许流动至下一级时才能发出修正操作。对于ds_ready_go，因为流水线中指令寄存器的依赖有可能导致ds阻塞，阻塞时指令所得到的寄存器值是错误的，即译码得到的分支跳转信息也是错误的。而es_allowin的介入使其操作使能仅维持一拍，避免重复操作。
- operate_pc：修正操作针对的分支指令的pc
- operate_index：修正操作针对的CAM表项
- pop_ras：为jirl指令时置起
- push_ras：为bl指令时置起
- add_entry：当前指令为分支指令但预测器未进行预测时置起。这里与上了一个额外条件br_taken，因为当pc在分支预测器中未命中时，顺序指令，也算是预测为untaken。br_taken不为1时，并不需要在预测器中建项
- delete_entry：当前指令不为分支指令但预测器进行预测时置起。这种情况出现的概率极低，只有在自修改代码中，可以不用考虑
- pre_error：当前指令为分支指令且预测器进行预测，但跳转目标不一致时置起
- pre_right：当前指令为分支指令且预测器进行预测，且跳转目标一致时置起
- target_error：当前指令为分支指令且预测器进行预测，且跳转目标一致，但跳转目标不一致时置起
- right_orien：正确的跳转方向
- right_target：正确的跳转目标
分支预测器会根据以上信息进行修正，首先由pop_ras即是否为jirl指令区分当前操作的是BTB部分还是RAS部分，针对BTB部分，操作类型包括：
- 建项：add_entry置起时。使能指定项，并填入operate_pc和right_target，以及初始化btb_counter为2'b10。对于填入项即index的选择，若BTB CAM表中还留有未使能项，则选择其中一项。若所有项都有效则选择btb_counter为2'b00的一项，即大概率不跳转的预测项，因为未在btb中命中的pc即预测为不跳转，两者效果是相同的，只不过该pc若下一次为跳转，则会重新建项，相当于将其btb_counter由2'b00直接转为2'b10，很有可能导致下一次的预测出错。但是这种情况出现的概率肯定比替换掉其他btb_counter的值导致下一次预测错的概率低。若所有项都有效且btb_counter都不为2'b00，则随机选择一项。
- 修正跳转目标：target_error置起时。重新填入right_target，并初始化btb_counter为2'b10。
- 修正跳转方向：pre_error或者pre_right置起时。根据right_orien调整btb_counter，若正确的分支方向为taken则累加，若为untaken则递减。
针对RAS部分，操作类型包括：
- 建项：add_entry置起时。使能指定项，填入operate_pc即可。相当于预测pc的分支类型。index的选择同BTB部分。
- 进栈：当push_ras置起且当前RAS非满时，存入当前pc的下一条指令，并将指针上移。即当前为bl函数跳转指令，其返回地址为bl的下一条指令。RAS指针指向的是空项。
- 出栈：当pop_ras置起且当前RAS非空时，指针直接下移一项即可。
## 分支预测器与流水线交互逻辑
首先简单介绍取指逻辑，该部分内容会在后续逐步展开。来看几个关键信号，inst_valid指示当前取指pc是否有效，该信号直接送往icache等待接收。inst_valid主要看fs_allowin信号，即pfs指令允许向后流动时，其取指pc即为有效，能够避免相同pc取指请求的重复发出。nextpc即为取指pc，当前仅关注其最为常规的pc来源seq_pc，顺序取指pc。当inst_valid为1时，并不代表取指请求即刻便能发出，还需要等待icache空闲，由inst_addr_ok表示（取指请求的其他去向tlb、btb不需要等待）。当inst_valid && inst_addr_ok为1，取指请求发出，pfs_ready_go置起，pfs向fs流动。
fetch_en和fetch_pc发送至分支预测器后，下一拍得到预测结果（btb_en/btb_ret_pc/btb_taken）。当btb_en && btb_taken为1时，fetch_btb_target置起，分支跳转，将nextpc纠正至btb_ret_pc。这段逻辑中有一点需要注意，分支预测器返回的结果仅维持一拍，但pfs并不一定能够向后流动，因此需要缓存分支预测器的返回结果，避免信息丢失。分支预测器的返回结果缓存在btb_lock_buffer中，由btb_lock_en指示缓存是否有效。缓存条件即为分支返回结果且pfs无法向后流动（btb_en && !pfs_ready_go），缓存释放条件为下一次取指重新发起。而nextpc的维护以及fs向ds传递分支预测结果时都将采用btb_ret_pc_t、btb_ret_pc_t、btb_ret_pc_t、btb_ret_pc_t信号，由分支预测器返回信息和缓存的信息相或得到，两者同一时刻仅有一个有效。
译码级，根据译码和分支预测的结果，能够知道下一条指令取指的方向是否正确。取指级有两个方面的工作需要完成：修正分支预测的历史信息；若预测错误则需纠正取指方向。此处主要讲述第二方面的内容。若译码级检测到分支预测错误，则会置起btb_pre_error_flush信号，由该信号修正取指方向，该工作可继续细分为两个内容
- 取消掉下一条进入译码级的指令，及错误预测导致错误取指的指令
两种情况需要考虑：
- 当该分支指令向后流动的那一拍，即（btb_pre_error_flush && es_allowin）为1时，若下一拍下一条指令紧接着进入译码级，则可直接取消。不过可以用更粗犷的方法，即下一拍的ds_valid直接为0，无需识别是否有指令进入。
- 同样的条件，若下一拍无指令进入，即当拍fs_to_ds_valid为0，则置起branch_slot_cancel触发器。该触发器为1时，会等待下一条指令进入，当检测fs_to_ds_valid为1时，将其取消，并恢复branch_slot_cancel至0。
- 纠正nextpc。当译码级发现分支预测错误，会将正确的跳转目标（btb_pre_error_flush_target）和使能信号（btb_pre_error_flush）通过br_bus传递至取指阶段，修正nextpc。
需要考虑两个问题：
- 当nextpc修正信息向前传递时，pfs并不一定处于能够取指的状态，例如inst_addr_ok不为1。此时若译码级不阻塞，且pfs不将修正信息存入buffer，会导致信息丢失。
- 译码级会记录分支预测错误，并取消掉错误预测的分支指令的下一条指令。若pfs在取完预测错误的分支指令后始终处于阻塞状态，之后直接被修正至正确的跳转方向，则会导致正确的指令被取消掉。
针对上述两个问题，可在pfs中构建一个状态机解决。br_target_inst_req_state表示状态。当发现预测错误后，根据流水线状态，进入不同的状态。
- !fs_valid && !inst_addr_ok：预测错误分支指令取出后未进行任何取指，因为fs级为空，inst_addr_ok从未置起。且当前也不处于可取指的状态。进入br_target_inst_req_wait_slot状态。
- !inst_addr_ok && fs_valid：已有一条错误取指的指令在fs中，但pfs并不处于能够取指的状态。进入br_target_inst_req_wait_br_target状态。
- inst_addr_ok && !fs_valid：预测错误分支指令取出后未进行任何取指，当前处于可取指的状态，但当前的指令会在译码级取消。进入br_target_inst_req_wait_br_target状态。
br_target_inst_req_wait_slot状态会待取指请求发出后切换至br_target_inst_req_wait_br_target状态，该状态便会将nextpc修正至存储btb_pre_error_flush_target的pc buffer（br_target_inst_req_buffer）。当取指请求再次发出后，状态切换至空状态br_target_inst_req_empty。
构建状态机后，还需要注意一个问题。也许pfs处于即刻能够发出取指请求的状态。可粗略的判断fs级是否有指令，便改变next_pc同时置起inst_valid，即使当前无法取指(inst_addr_ok为0)也没有关系。

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# 前言
OpenLA500（齐物）是一款实现了`龙芯架构32位精简版指令集（LoongArch32 Reduced）`的处理器核。OpenLA500的架构为经典的单发射静态五级流水，配备两路组相连的指令/数据Cache，32项全相连的tlb实现虚实地址映射，以及BTB及RAS实现分支预测。基本按照国科大体系结构实验课程逐步设计得到。FPGA运行频率为50M。
OpenLA500经过全面验证，已处于稳定状态。并于2023年龙芯全流程平台项目中，在SMIC 180um工艺下流片。
以下将从8个方面介绍OpenLA500的设计细节。
- [设计概述](./设计概述.md)：基于顶层框图，介绍各级流水的划分和各级流水之间的交互，以及流水线与其他模块的交互。
- [分支预测](./分支预测.md)：BTB及RAS两个分支预测器的具体设计，以及在流水线中的工作原理。
- [流水线的发射部分]()：流水线发射阶段（译码级）操作数准备、前递网络、阻塞控制的设计。
- [流水线的执行部分]()：alu、mul、div运算部件在流水线中的实现。
- [MMU]()：虚实地址映射逻辑，tlb维护。
- [例外实现]()：流水线中例外的判断及处理。
- [访存子系统]()：指令/数据Cache及AXI总线接口的实现。
- [调试部分]()：UART在线调试系统与OpenLA500的交互逻辑。

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# 设计概述
![系统框图](./picture/框图.svg)
系统框图展示了OpenLA500处理器核的内部结构。指令的执行始终按照取指、译码、执行、访存、写回的顺序进行。各级流水会存储指令执行的中间状态，在完成当前阶段的操作后，将结果存入下一级流水，进行下一个阶段的操作。
## 执行流程
处理器核内维护`nextpc`信号，表示取指地址。待取指开始时，`fetch_pc`会发往`icache`、`tlb`、`btb`进行不同的工作，以及存入触发器。在下一拍即`fs_stage`取指级,`btb`完成分支预测，将结果直接送往`nextpc`，更改其取指方向。以及由`fetch_pc`以及`tlb`虚实地址翻译的结果，在`icache`指令缓存中得到`inst`指令码，并存入触发器。下一级`ds_stage`译码级在拿到指令码后，便交给`decoder`进行译码。译码后可以得到具体的操作码`op`，以及寄存器号，并可借此在`regfile`寄存器堆或者`csr`控制寄存器中索引到寄存器值`rf_data`。`es_stage`执行级在得到操作码及操作数后，便可送至`alu`运算部件进行简单运算，以及送往`div`除法部件、`mul`乘法部件进行多拍较复杂的运算。此外，由`alu`可以得到访存地址，并发至`tlb`及`dcache`数据缓存完成访存请求的处理，基本同`icache`。在`mem_stage`访存级，可得到访存、乘除法的运算结果，并由`op`选择最终的运算结果`final_res`，并存入触发器。`wb_stage`写回级便会将最终运算结果写回到`regfile`及`csr`。对于`i/dcache`，若取指/访存请求缺失，便会发送请求至`axi_bridge`并通过标准的`AXI3`总线协议与外界通信。
---
流水级的各阶段需要与其他不同的模块进行交互，确认其任务是否完成。以下针对流水级及各模块进行介绍：
## 取指阶段
### `pfs`
该级流水的主要功能是维护`nextpc`，也就是流水线取指的虚地址。其实从更为严谨的角度来看`pfs`并不应该单独称为一级流水，因为`nextpc`为`wire`类型，或者说`pfs`在正常的执行流程中不会缓存信号，当拍便可获得取指方向。实际上`pfs`为各级能够影响取指地址的流水级的衍生。`nextpc`的维护逻辑可以说是五级流水中最为复杂的一部分，因为`icache`并不是时刻处于就绪的状态，由`inst_addr_ok`信号指示其是否就绪。因此，对于某些特殊情况下出现的转顺即逝的信息，比如流水线刷新等，需要构建状态机缓存信息。待取指方向确认，且`icache`就绪，`pfs`会置起`fetch_en`，紧接着`btb`、`icache`、`tlb`便会接收`pfs`发出的`fetch_pc`，开始相应的操作。
### `btb`
分支预测器，根据`PC`直接预测其跳转地址。32项`btb`组织为`CAM`表的形式，由`PC`查询。此外，还包括一个`ras`，组织为一个8项的栈，存储函数调用过程中的返回地址。`btb`分支预测的结果会在下一拍返回，若预测正确则可消除下一拍产生于`fs`级流水的空泡，预测错误不会造成任何性能损失。
### `icache`
指令缓存，两路组相连的结构。`fetch_pc`进入`icache`后，首先根据由`fetch_pc`拆解而来的`index`部分，索引出两路的`cache`行。其次再根据`tag`部分与`tlb`翻译得到的物理页号是否相等判断是否有命中项。若命中，下一拍返回`inst_rdata`，若未命中，则进入`icache`处理`miss`请求的状态机，`inst_addr_ok`拉低。等待`miss`请求处理完毕后再接收新的取指请求。替换策略为随机替换。
### `tlb`
组织为32项`CAM`表的形式，指令和数据共用，需要两个查询端口。通过`fetch_pc`的虚页号查询是否存在命中项，命中则返回物理页号。若未命中，则会标记该指令存在`tlb`缺失例外，并进入例外处理程序。待对应`tlb`项在页表中找到并由软件填入`tlb`后，重新执行该指令。
### `fs`
`fs`取值级便是真正意义上的第一级流水。`fs`级接收`icache`返回的指令码`inst_rdata`，由`inst_data_ok`指示指令码是否就绪。若`icache miss`，`fs`级便会阻塞。额外需要注意一点，`tlb`的读取有一拍的延迟，因为32项的CAM表会有较长的逻辑。因此`tlb`的读取结果是在`fs`级得到，也就表示`tlb`相关的例外判断是在`fs`级完成，而取指请求是在`pfs`级发出。所以`fs`级需要具备中止上一拍`pfs`级发往`icache`的取指请求的能力，体现在`tlb_excp_cancel_req`信号中，`dcache`同理。
## 译码阶段
### `ds`
译码级，其功能便是将指令码解析为对应的操作码，并根据寄存器号，从`regfile`中取出寄存器值。不过寄存器的最新值可能还未被写入到`regfile`中，因为后续流水线中的指令正在执行，结果未获得或者未写回，而当前指令可能依赖于这些指令的结果。因此译码级与后续流水线构建了前递路径（`es_to_ds_forward_bus/ms_to_ds_forward_bus`），用于前递未写回的结果，或者通知`ds`级结果未获取，需要阻塞。此外，经过译码，已知晓该指令是否为跳转指令，以及是否跳转。也就可以识别分支预测器的预测结果是否正确，`ds`级便可通过`br_bus`对取指方向进行修正，以及更新分支预测器的历史信息。`btb`的预测包括两个方面，该`PC`是否为跳转指令；识别为跳转指令时是否跳转。`ds`级需要鉴别并对分支预测器执行特定的更新操作。
## 执行阶段
### `es`
执行级，根据译码得到的操作码，送往`alu`、`mul`、`div`进行特定类型的运算。`alu`用于处理较简单的运算，比如加减、移位运算。`mul`为华莱士树实现的乘法部件，拆为两级。`div`为常规的迭代除法部件，需要34个周期得到结果。此外，若为访存指令，执行级便可通过加减运算得到访存地址。同`pfs`等待`dcache`准备就绪，即`data_addr_ok`置起，`es`便可发出`data_fetch`以及`data_addr`，由`tlb`进行虚实地址映射以及`dcache`取回数据。不过需要注意若当前指令或者后续流水线中的指令存在例外，需要及时中止`data_fetch`的置起。
## 访存阶段
### `dcache`
数据缓存，在`icache`的基础上新增了处理写请求的能力。每个`cache`行新增一个`dirty`位，用于标识该`cache`行是否为脏，在被替换时判断是否需要写回。此外，写请求在命中的情况下，相较于读请求，需要额外的一拍将数据写入到`ram`中。这额外一拍的延迟可以通过构建写请求状态机节省。待确认写请求命中后，进入状态机，使得`dcache`可以继续接收新的请求。不过需要注意规避读写请求同时出现在单端口的`ram`上。
### `ms`
访存级，等待`dcache`数据返回，由`data_data_ok`指示`data_rdata`是否有效。`ms`级同`fs`级，需要由`tlb_excp_cancel_req`信号取消掉上一拍`es`发往`dcache`的访存请求。写请求不同于读请求需要等待接收数据，待请求发出后，不管命不命中，可继续向后流动。
## 写回阶段
### `ws`
写回级，此时指令已执行完毕，并得到`result`，需根据执行结果修改处理器状态，包括两个方面：写通用寄存器`regfile`以及状态寄存器`csr`；根据指令触发的例外类型，修改`csr`寄存器，以及清空流水线并调整取指方向至例外入口。
---
## 流水级间交互
最理想的情况下，同一时刻五个阶段都处于工作的状态，也就表示同一时刻在处理五条指令。此时，处理器核在通过流水线切分得到较高频率时，带宽仍然保持为1指令/拍。但在实际情况下，如前文所述，并不会如此，各级流水总是会出现阻塞的情况。因此，流水级之间需要交互，避免一级流水的操作还未完成便被上一级覆盖。
流水级之间的交互逻辑中，需要维护以下关键信号：
- `stage_valid`：由触发器维护，表示当前流水级是否在处理指令。
- `stage_ready_go`：表示流水级是否需要被阻塞。
- `stage_allowin`：表示当前流水级是否允许上一级流水进入，该信号传递至上一级，与上一级流水交互，两种情况下该信号置起，当前流水无正在处理的指令；或者当前流水级中的指令已处理完毕且下一级流水允许进入。该信号会由最后一级流水向前传递，只要某一流水级阻塞，其`stage_allowin`拉低，同一时刻，前面所有流水级的`stage_allowin`都会拉低（假设所有流水级中都有指令在处理）。
- `stage_to_nextstage_valid`：表示当前流水级中是否有处理完毕的指令，该信号传递至下一级，与下一级流水交互。下一级流水在收到高电平信号时，且其下一级流水的`stage_allowin`为高电平，则会在下一拍置起下一级流水的`stage_valid`，实现流水级间指令的流动。`stage_to_nextstage_bus`总线信号中传递缓存信号，会随着`stage_to_nextstage_valid`流动。

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`include "mycpu.h"
`include "csr.h"
module exe_stage(
input clk ,
input reset ,
//allowin
input ms_allowin ,
output es_allowin ,
//from ds
input ds_to_es_valid ,
input [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus ,
//to ms
output es_to_ms_valid ,
output [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus ,
//to ds forward path
output [`ES_TO_DS_FORWARD_BUS -1:0] es_to_ds_forward_bus,
output es_to_ds_valid ,
//div_mul
output es_div_enable ,
output es_mul_div_sign ,
output [31:0] es_rj_value ,
output [31:0] es_rkd_value ,
input div_complete ,
`ifdef HAS_LACC
output es_lacc_req,
output [`LACC_OP_WIDTH-1:0] es_lacc_command,
input lacc_req_ready,
input lacc_data_valid,
input lacc_data_read,
input [31: 0] lacc_data_addr,
input [31: 0] lacc_data_wdata,
input [1: 0] lacc_data_size,
input lacc_rsp_valid,
input [31: 0] lacc_rsp_rdat,
output [6: 0] lacc_req_imm,
output lacc_flush,
input data_data_ok,
output lacc_drsp_valid,
`endif
//exception
input excp_flush ,
input ertn_flush ,
input refetch_flush ,
input icacop_flush ,
//idle
input idle_flush ,
//tlb/cache ins
output tlb_inst_stall ,
//cache ins
output icacop_op_en ,
output dcacop_op_en ,
output [ 1:0] cacop_op_mode ,
//from icache
input icache_unbusy ,
//preld ins
output [ 4:0] preld_hint ,
output preld_en ,
// data cache interface
output data_valid ,
output data_op ,
output [ 2:0] data_size ,
output [ 3:0] data_wstrb ,
output [31:0] data_wdata ,
input data_addr_ok ,
//from csr
input [18:0] csr_vppn ,
//to addr trans
output [31:0] data_addr ,
output data_fetch ,
//from ms
input ms_wr_tlbehi ,
input ms_flush
);
reg es_valid ;
wire es_ready_go ;
wire [31:0] error_va ;
reg [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus_r;
wire [13:0] es_alu_op ;
wire es_src1_is_pc ;
wire es_src2_is_imm ;
wire es_src2_is_4 ;
wire es_gr_we ;
wire es_store_op ;
wire [ 4:0] es_dest ;
wire [31:0] es_imm ;
wire [31:0] es_pc ;
wire [ 3:0] es_mul_div_op ;
wire [ 1:0] es_mem_size ;
wire [31:0] es_csr_data ;
wire [13:0] es_csr_idx ;
wire [31:0] es_csr_result ;
wire [31:0] csr_mask_result;
wire es_res_from_csr;
wire es_csr_we ;
wire es_csr_mask ;
wire es_excp ;
wire excp ;
wire [ 8:0] es_excp_num ;
wire [ 9:0] excp_num ;
wire es_ertn ;
wire es_mul_enable ;
wire div_stall ;
wire es_ll_w ;
wire es_sc_w ;
wire es_tlbsrch ;
wire es_tlbwr ;
wire es_tlbfill ;
wire es_tlbrd ;
wire es_refetch ;
wire es_invtlb ;
wire [ 9:0] es_invtlb_asid ;
wire [18:0] es_invtlb_vpn ;
wire es_cacop ;
wire es_preld ;
wire es_br_inst ;
wire es_icache_miss ;
wire es_idle ;
wire es_load_op ;
wire dep_need_stall ;
wire forward_enable ;
wire dest_zero ;
wire excp_ale ;
wire es_flush_sign ;
wire [ 3:0] wr_byte_en ;
wire access_mem ;
wire es_mem_sign_exted;
wire [ 1:0] sram_addr_low2bit;
wire tlbsrch_stall ;
wire [31:0] pv_addr ;
wire [ 4:0] cacop_op ;
wire dcache_req_or_inst_en;
wire icacop_inst ;
wire icacop_inst_stall;
wire dcacop_inst ;
wire preld_inst ;
wire es_br_pre_error ;
wire es_br_pre ;
// difftest
wire [31:0] es_inst ;
wire [63:0] es_timer_64 ;
wire es_cnt_inst ;
wire [ 7:0] es_inst_ld_en ;
wire [ 7:0] es_inst_st_en ;
wire es_csr_rstat_en ;
wire [2: 0] data_size_pre;
`ifdef HAS_LACC
wire lacc_stall;
wire [3: 0] lacc_data_mask, lacc_data_byte, lacc_data_half;
wire es_lacc_req_pre;
`endif
assign {
`ifdef HAS_LACC
es_lacc_command,
es_lacc_req_pre,
`endif
es_csr_rstat_en , //349:349 for difftest
es_inst_st_en , //348:341 for difftest
es_inst_ld_en , //340:333 for difftst
es_cnt_inst , //332:332 for difftest
es_timer_64 , //331:268 for difftest
es_inst , //236:267 for difftest
es_idle , //235:235
es_br_pre_error , //234:234
es_br_pre , //233:233
es_icache_miss , //232:232
es_br_inst , //231:231
es_preld , //230:230
es_cacop , //229:229
es_mem_sign_exted, //228:228
es_invtlb , //227:227
es_tlbrd , //226:226
es_refetch , //225:225
es_tlbfill , //224:224
es_tlbwr , //223:223
es_tlbsrch , //222:222
es_sc_w , //221:221
es_ll_w , //220:220
es_excp_num , //219:211
es_csr_mask , //210:210
es_csr_we , //209:209
es_csr_idx , //208:195
es_res_from_csr , //194:194
es_csr_data , //193:162
es_ertn , //161:161
es_excp , //160:160
es_mem_size , //159:158
es_mul_div_op , //157:154
es_mul_div_sign , //153:153
es_alu_op , //152:139
es_load_op , //138:138
es_src1_is_pc , //137:137
es_src2_is_imm , //136:136
es_src2_is_4 , //135:135
es_gr_we , //134:134
es_store_op , //133:133
es_dest , //132:128
es_imm , //127:96
es_rj_value , //95 :64
es_rkd_value , //63 :32
es_pc //31 :0
} = ds_to_es_bus_r;
wire [31:0] es_alu_src1 ;
wire [31:0] es_alu_src2 ;
wire [31:0] es_alu_result ;
wire [31:0] exe_result ;
assign es_to_ms_bus = {es_csr_data , //424:393 for difftest
es_csr_rstat_en , //392:392 for difftest
data_wdata , //391:360 for difftest
es_inst_st_en , //359:352 for difftest
data_addr , //351:320 for difftest
es_inst_ld_en , //319:312 for difftest
es_cnt_inst , //311:311 for difftest
es_timer_64 , //310:247 for difftest
es_inst , //246:215 for difftest
error_va , //214:183
es_idle , //182:182
es_cacop , //181:181
preld_inst , //180:180
es_br_pre_error , //179:179
es_br_pre , //178:178
es_icache_miss , //177:177
es_br_inst , //176:176
icacop_op_en , //175:175
es_mem_sign_exted, //174:174 //only add this, not used.
es_invtlb_vpn , //173:155
es_invtlb_asid , //154:145
es_invtlb , //144:144
es_tlbrd , //143:143
es_refetch , //142:142
es_tlbfill , //141:141
es_tlbwr , //140:140
es_tlbsrch , //139:139
es_store_op , //138:138
es_sc_w , //137:137
es_ll_w , //136:136
excp_num , //135:126
es_csr_we , //125:125
es_csr_idx , //124:111
es_csr_result , //110:79
es_ertn , //78:78
excp , //77:77
es_mem_size , //76:75
es_mul_div_op , //74:71
es_load_op , //70:70
es_gr_we , //69:69
es_dest , //68:64
exe_result , //63:32
es_pc //31:0
};
assign es_to_ds_valid = es_valid;
assign access_mem = es_load_op || es_store_op;
assign es_flush_sign = excp_flush || ertn_flush || refetch_flush || icacop_flush || idle_flush;
assign icacop_inst_stall = icacop_op_en && !icache_unbusy;
assign es_ready_go = (!div_stall &&
`ifdef HAS_LACC
!lacc_stall &&
`endif
((dcache_req_or_inst_en && data_addr_ok) || !(access_mem || dcacop_inst || preld_inst)) && !tlbsrch_stall && !icacop_inst_stall) || excp;
assign es_allowin = !es_valid || es_ready_go && ms_allowin;
assign es_to_ms_valid = es_valid && es_ready_go;
always @(posedge clk) begin
if (reset || es_flush_sign) begin
es_valid <= 1'b0;
end
else if (es_allowin) begin
es_valid <= ds_to_es_valid;
end
if (ds_to_es_valid && es_allowin) begin
ds_to_es_bus_r <= ds_to_es_bus;
end
end
assign es_alu_src1 = es_src1_is_pc ? es_pc : es_rj_value;
assign es_alu_src2 = (es_src2_is_imm) ? es_imm :
(es_src2_is_4) ? 32'd4 : es_rkd_value;
assign es_div_enable = (es_mul_div_op[2] | es_mul_div_op[3]) & es_valid;
assign es_mul_enable = es_mul_div_op[0] | es_mul_div_op[1];
assign div_stall = es_div_enable & ~div_complete;
`ifdef HAS_LACC
assign lacc_stall = es_lacc_req & ~lacc_rsp_valid;
assign es_lacc_req = es_lacc_req_pre & es_valid;
assign lacc_req_imm = es_imm[11: 5];
assign lacc_drsp_valid = es_lacc_req & data_data_ok;
`endif
alu u_alu(
.alu_op (es_alu_op ),
.alu_src1 (es_alu_src1 ), //bug3 es_alu_src2
.alu_src2 (es_alu_src2 ),
.alu_result (es_alu_result)
);
assign exe_result = `ifdef HAS_LACC
es_lacc_req ? lacc_rsp_rdat :
`endif
es_res_from_csr ? es_csr_data : es_alu_result;
//forward path
assign dest_zero = (es_dest == 5'b0);
assign forward_enable = es_gr_we & ~dest_zero & es_valid;
assign dep_need_stall = es_load_op | es_div_enable | es_mul_enable;
assign es_to_ds_forward_bus = {dep_need_stall , //38:38
forward_enable , //37:37
es_dest , //36:32
exe_result //31:0
};
assign tlb_inst_stall = (es_tlbsrch || es_tlbrd) && es_valid;
//csr mask
assign csr_mask_result = (es_rj_value & es_rkd_value) | (~es_rj_value & es_csr_data);
assign es_csr_result = es_csr_mask ? csr_mask_result : es_rkd_value;
assign error_va = pv_addr;
//exception
assign excp_ale = access_mem & ((es_mem_size[0] & 1'b0) |
(es_mem_size[1] & es_alu_result[0]) |
(!es_mem_size & (es_alu_result[0] | es_alu_result[1]))) ;
assign excp = es_excp || excp_ale;
assign excp_num = {excp_ale, es_excp_num};
assign sram_addr_low2bit = {es_alu_result[1], es_alu_result[0]};
//mem_size[0] byte size [1] halfword size
assign dcache_req_or_inst_en = es_valid && !excp && ms_allowin && !es_flush_sign && !ms_flush;
`ifdef HAS_LACC
assign data_valid = access_mem && dcache_req_or_inst_en || lacc_data_valid;
assign data_op = lacc_data_valid ? !lacc_data_read :
es_store_op && !es_cacop && !es_preld;
decoder_2_4 decoder_lacc_size (lacc_data_addr[1: 0], lacc_data_byte);
assign lacc_data_half[0] = ~(|lacc_data_addr);
assign lacc_data_half[1] = ~lacc_data_addr[1];
assign lacc_data_half[2] = ^lacc_data_addr;
assign lacc_data_half[3] = lacc_data_addr[1];
assign lacc_data_mask = lacc_data_size == 2'b00 ? lacc_data_byte :
lacc_data_size == 2'b01 ? lacc_data_half : 4'b1111;
assign data_wstrb = lacc_data_valid ? lacc_data_mask : wr_byte_en;
assign data_size = lacc_data_valid ? lacc_data_size : data_size_pre;
assign data_addr = lacc_data_valid ? lacc_data_addr :
es_tlbsrch ? {csr_vppn, 13'b0} : pv_addr;
`else
assign data_valid = access_mem && dcache_req_or_inst_en;
assign data_op = es_store_op && !es_cacop && !es_preld;
assign data_wstrb = wr_byte_en;
assign data_size = data_size_pre;
assign data_addr = es_tlbsrch ? {csr_vppn, 13'b0} : pv_addr;
`endif
wire [3:0] es_stb_wen = { sram_addr_low2bit==2'b11 ,
sram_addr_low2bit==2'b10 ,
sram_addr_low2bit==2'b01 ,
sram_addr_low2bit==2'b00} ;
wire [3:0] es_sth_wen = { sram_addr_low2bit==2'b10 ,
sram_addr_low2bit==2'b10 ,
sram_addr_low2bit==2'b00 ,
sram_addr_low2bit==2'b00} ;
wire [31:0] es_stb_cont = { {8{es_stb_wen[3]}} & es_rkd_value[7:0] ,
{8{es_stb_wen[2]}} & es_rkd_value[7:0] ,
{8{es_stb_wen[1]}} & es_rkd_value[7:0] ,
{8{es_stb_wen[0]}} & es_rkd_value[7:0]};
wire [31:0] es_sth_cont = { {16{es_sth_wen[3]}} & es_rkd_value[15:0] ,
{16{es_sth_wen[0]}} & es_rkd_value[15:0]};
assign {wr_byte_en, data_size_pre} = ({7{es_mem_size[0]}} & {es_stb_wen, 3'b00}) |
({7{es_mem_size[1]}} & {es_sth_wen, 3'b01}) |
({7{!es_mem_size }} & {4'b1111 , 3'b10}) ;
//assign data_wdata = es_rkd_value;
assign data_wdata =
`ifdef HAS_LACC
lacc_data_valid ? lacc_data_wdata :
`endif
({32{es_mem_size[0]}} & es_stb_cont ) |
({32{es_mem_size[1]}} & es_sth_cont ) |
({32{!es_mem_size }} & es_rkd_value) ;
assign tlbsrch_stall = es_tlbsrch && ms_wr_tlbehi;
//invtlb
assign es_invtlb_asid = es_rj_value[9:0];
assign es_invtlb_vpn = es_rkd_value[31:13];
assign pv_addr = es_alu_result;
//cache ins
assign cacop_op = es_dest;
assign icacop_inst = es_cacop && (cacop_op[2:0] == 3'b0);
assign icacop_op_en = icacop_inst && dcache_req_or_inst_en;
assign dcacop_inst = es_cacop && (cacop_op[2:0] == 3'b1);
assign dcacop_op_en = dcacop_inst && dcache_req_or_inst_en;
assign cacop_op_mode = cacop_op[4:3];
//preld ins
assign preld_hint = es_dest;
assign preld_inst = es_preld && ((preld_hint == 5'd0) || (preld_hint == 5'd8))/* && !data_uncache_en*/; //preld must have bug
assign preld_en = preld_inst && dcache_req_or_inst_en;
assign data_fetch = (data_valid || dcacop_inst || preld_en) && data_addr_ok || ((icacop_inst || es_tlbsrch) && es_ready_go && ms_allowin)
`ifdef HAS_LACC
|| lacc_data_valid
`endif
;
endmodule

410
rtl/ip/open-la500/icache.v Normal file
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@@ -0,0 +1,410 @@
module icache
(
input clk ,
input reset ,
//to from cpu
input valid ,
input op ,
input [ 7:0] index ,
input [19:0] tag ,
input [ 3:0] offset ,
input [ 3:0] wstrb ,
input [31:0] wdata ,
output addr_ok ,
output data_ok ,
output [31:0] rdata ,
input uncache_en ,
input icacop_op_en ,
input [ 1:0] cacop_op_mode ,
input [ 7:0] cacop_op_addr_index , //this signal from mem stage's va
input [19:0] cacop_op_addr_tag ,
input [ 3:0] cacop_op_addr_offset,
output icache_unbusy,
input tlb_excp_cancel_req,
//to from axi
output rd_req ,
output [ 2:0] rd_type ,
output [31:0] rd_addr ,
input rd_rdy ,
input ret_valid ,
input ret_last ,
input [31:0] ret_data ,
output reg wr_req ,
output [ 2:0] wr_type ,
output [31:0] wr_addr ,
output [ 3:0] wr_wstrb ,
output [127:0] wr_data ,
input wr_rdy ,
//to perf_counter
output cache_miss
);
reg request_buffer_op ;
reg [ 7:0] request_buffer_index ;
reg [19:0] request_buffer_tag ;
reg [ 3:0] request_buffer_offset ;
reg [ 3:0] request_buffer_wstrb ;
reg [31:0] request_buffer_wdata ;
reg request_buffer_uncache_en ;
reg request_buffer_icacop ;
reg [ 1:0] request_buffer_cacop_op_mode;
reg [ 1:0] miss_buffer_replace_way ;
reg [ 1:0] miss_buffer_ret_num ;
wire [ 1:0] ret_num_add_one ;
wire [ 7:0] way_bank_addra [1:0][3:0];
wire [31:0] way_bank_dina [1:0][3:0];
wire [31:0] way_bank_douta [1:0][3:0];
wire way_bank_ena [1:0][3:0];
wire [ 3:0] way_bank_wea [1:0][3:0];
wire [ 7:0] way_tagv_addra [1:0];
wire [20:0] way_tagv_dina [1:0];
wire [20:0] way_tagv_douta [1:0];
wire way_tagv_ena [1:0];
wire way_tagv_wea [1:0];
wire [ 1:0] way_hit ;
wire cache_hit ;
wire [ 31:0] way_load_word [1:0];
wire [127:0] way_data [1:0];
wire [31:0] load_res ;
wire main_idle2lookup ;
wire main_lookup2lookup;
wire main_state_is_idle ;
wire main_state_is_lookup ;
wire main_state_is_replace;
wire main_state_is_refill ;
wire [1:0] way_wr_en;
wire [31:0] refill_data;
wire cacop_op_mode0;
wire cacop_op_mode1;
wire cacop_op_mode2;
wire [1:0] random_val;
wire [3:0] chosen_way;
wire [1:0] replace_way;
wire [1:0] invalid_way;
wire has_invalid_way;
wire [1:0] rand_repl_way;
wire [3:0] cacop_chose_way;
wire cacop_op_mode2_hit_wr;
wire cacop_op_mode2_no_hit;
reg [ 1:0] lookup_way_hit_buffer;
wire [ 3:0] real_offset;
wire [19:0] real_tag ;
wire [ 7:0] real_index ;
wire req_or_inst_valid ;
localparam main_idle = 5'b00001;
localparam main_lookup = 5'b00010;
localparam main_replace = 5'b01000;
localparam main_refill = 5'b10000;
localparam write_buffer_idle = 1'b0;
localparam write_buffer_write = 1'b1;
reg [4:0] main_state;
reg rd_req_buffer;
genvar i,j;
//state machine
//main loop
always @(posedge clk) begin
if (reset) begin
main_state <= main_idle;
request_buffer_op <= 1'b0;
request_buffer_index <= 8'b0;
request_buffer_tag <= 20'b0;
request_buffer_offset <= 4'b0;
request_buffer_wstrb <= 4'b0;
request_buffer_wdata <= 32'b0;
request_buffer_uncache_en <= 1'b0;
request_buffer_cacop_op_mode <= 2'b0;
request_buffer_icacop <= 1'b0;
miss_buffer_replace_way <= 2'b0;
wr_req <= 1'b0;
end
else case (main_state)
main_idle: begin
if (req_or_inst_valid && main_idle2lookup) begin
main_state <= main_lookup;
request_buffer_op <= op ;
request_buffer_index <= real_index ;
request_buffer_offset <= real_offset;
request_buffer_wstrb <= wstrb;
request_buffer_wdata <= wdata;
request_buffer_cacop_op_mode <= cacop_op_mode;
request_buffer_icacop <= icacop_op_en ;
end
end
main_lookup: begin
if (req_or_inst_valid && main_lookup2lookup) begin
main_state <= main_lookup;
request_buffer_op <= op ;
request_buffer_index <= real_index ;
request_buffer_offset <= real_offset;
request_buffer_wstrb <= wstrb;
request_buffer_wdata <= wdata;
request_buffer_cacop_op_mode <= cacop_op_mode;
request_buffer_icacop <= icacop_op_en ;
end
else if (tlb_excp_cancel_req) begin
main_state <= main_idle;
end
else if (!cache_hit) begin
main_state <= main_replace;
request_buffer_tag <= real_tag;
request_buffer_uncache_en <= (uncache_en && !request_buffer_icacop);
miss_buffer_replace_way <= replace_way;
end
else begin
main_state <= main_idle;
end
end
main_replace: begin
if (rd_rdy) begin
main_state <= main_refill;
miss_buffer_ret_num <= 2'b0; //when get ret data, it will be sent to cpu directly.
end
end
main_refill: begin
if ((ret_valid && ret_last) || !rd_req_buffer) begin //when rd_req is not set, go to next state directly
main_state <= main_idle;
end
else begin
if (ret_valid) begin
miss_buffer_ret_num <= ret_num_add_one;
end
end
end
default: begin
main_state <= main_idle;
end
endcase
end
assign real_offset = icacop_op_en ? cacop_op_addr_offset : offset;
assign real_index = icacop_op_en ? cacop_op_addr_index : index ;
assign real_tag = request_buffer_icacop ? cacop_op_addr_tag : tag ;
/*====================================main state idle=======================================*/
assign req_or_inst_valid = valid || icacop_op_en;
assign main_idle2lookup = 1'b1;
assign icache_unbusy = main_state_is_idle;
//addr_ok logic
/*===================================main state lookup======================================*/
//tag compare
generate for(i=0;i<2;i=i+1) begin:gen_way_hit
assign way_hit[i] = way_tagv_douta[i][0] && (real_tag == way_tagv_douta[i][20:1]); //this signal will not maintain
end endgenerate
assign cache_hit = |way_hit && !(uncache_en || cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2); //uncache road reuse
//when cache inst op mode2 no hit, main state machine will still go a round. implement easy.
assign main_lookup2lookup = cache_hit;
assign addr_ok = ((main_state_is_idle && main_idle2lookup) || (main_state_is_lookup && main_lookup2lookup)) && !icacop_op_en; //request can be get
//data select
generate for(i=0;i<2;i=i+1) begin: gen_data
assign way_data[i] = {way_bank_douta[i][3],way_bank_douta[i][2],way_bank_douta[i][1],way_bank_douta[i][0]};
assign way_load_word[i] = way_data[i][request_buffer_offset[3:2]*32 +: 32];
end endgenerate
assign load_res = {32{way_hit[0]}} & way_load_word[0] |
{32{way_hit[1]}} & way_load_word[1] ;
//data_ok logic
/*====================================main state miss=======================================*/
decoder_2_4 dec_rand_way (.in({1'b0,random_val[0]}),.out(chosen_way));
one_valid_n #(2) sel_one_invalid (.in(~{way_tagv_douta[1][0],way_tagv_douta[0][0]}),.out(invalid_way),.nozero(has_invalid_way));
assign rand_repl_way = has_invalid_way ? invalid_way : chosen_way[1:0]; //chose invalid way first.
decoder_2_4 dec_cacop_way (.in({1'b0,request_buffer_offset[0]}),.out(cacop_chose_way));
assign replace_way = {2{cacop_op_mode0 || cacop_op_mode1}} & cacop_chose_way[1:0] |
{2{cacop_op_mode2}} & way_hit |
{2{!request_buffer_icacop}} & rand_repl_way;
/*==================================main state replace======================================*/
assign rd_req = main_state_is_replace && !(cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2);
/*===================================main state refill======================================*/
assign rd_type = request_buffer_uncache_en ? 3'b10 : 3'b100;
assign rd_addr = request_buffer_uncache_en ? {request_buffer_tag, request_buffer_index, request_buffer_offset} : {request_buffer_tag, request_buffer_index, 4'b0};
//write process will not block pipeline
assign data_ok = (main_state_is_lookup && (cache_hit || tlb_excp_cancel_req)) ||
(main_state_is_refill && ((ret_valid && ((miss_buffer_ret_num == request_buffer_offset[3:2]) || request_buffer_uncache_en))/* || !rd_req_buffer*/)) &&
!request_buffer_icacop; //when rd_req is not set, set data_ok directly.
//rdate connect with ret_data dirctly. maintain one clock only
assign refill_data = ret_data;
assign way_wr_en = miss_buffer_replace_way & {2{ret_valid}}; //when rd_req is not set, ret_valid and ret_last will not be set. block will not be wr also.
assign cache_miss = main_state_is_refill && ret_last && !(request_buffer_uncache_en || request_buffer_icacop);
//add one
assign ret_num_add_one[0] = miss_buffer_ret_num[0] ^ 1'b1;
assign ret_num_add_one[1] = miss_buffer_ret_num[1] ^ miss_buffer_ret_num[0];
always @(posedge clk) begin
if (reset) begin
rd_req_buffer <= 1'b0;
end
else if (rd_req) begin
rd_req_buffer <= 1'b1;
end
else if (main_state_is_refill && (ret_valid && ret_last)) begin
rd_req_buffer <= 1'b0;
end
end
/*==========================================================================================*/
//cache ins control signal
assign cacop_op_mode0 = request_buffer_icacop && (request_buffer_cacop_op_mode == 2'b00);
assign cacop_op_mode1 = request_buffer_icacop && ((request_buffer_cacop_op_mode == 2'b01) || (request_buffer_cacop_op_mode == 2'b11));
assign cacop_op_mode2 = request_buffer_icacop && (request_buffer_cacop_op_mode == 2'b10);
assign cacop_op_mode2_hit_wr = cacop_op_mode2 && |lookup_way_hit_buffer;
assign cacop_op_mode2_no_hit = cacop_op_mode2 && ~|lookup_way_hit_buffer;
always @(posedge clk) begin
if (reset) begin
lookup_way_hit_buffer <= 2'b0;
end
else if (cacop_op_mode2 && main_state_is_lookup) begin
lookup_way_hit_buffer <= way_hit;
end
end
//output
assign rdata = {32{main_state_is_lookup}} & load_res |
{32{main_state_is_refill}} & ret_data ;
generate
for(i=0;i<2;i=i+1) begin:gen_data_way
for(j=0;j<4;j=j+1) begin:gen_data_bank
/*===============================bank addra logic==============================*/
assign way_bank_addra[i][j] = {8{addr_ok}} & real_index | /*lookup*/
{8{!addr_ok}} & request_buffer_index ;
/*===============================bank we logic=================================*/
assign way_bank_wea[i][j] = {4{main_state_is_refill &&
(way_wr_en[i] && (miss_buffer_ret_num == j[1:0]))}} & 4'hf;
/*===============================bank dina logic=================================*/
assign way_bank_dina[i][j] = {32{main_state_is_refill}} & refill_data;
/*===============================bank ena logic=================================*/
assign way_bank_ena[i][j] = (!(request_buffer_uncache_en || cacop_op_mode0)) || main_state_is_idle || main_state_is_lookup;
end
end
endgenerate
generate
for(i=0;i<2;i=i+1) begin:gen_tagv_way
/*===============================tagv addra logic=================================*/
assign way_tagv_addra[i] = {8{addr_ok || (icacop_op_en &&
(main_state_is_idle || main_state_is_lookup))}} & real_index |
{8{main_state_is_replace || main_state_is_refill}} & request_buffer_index ;
//{8{(main_state_is_miss && wr_rdy) ||
/*===============================tagv ena logic=================================*/
assign way_tagv_ena[i] = (!request_buffer_uncache_en) || main_state_is_idle || main_state_is_lookup;
/*===============================tagv wea logic=================================*/
assign way_tagv_wea[i] = miss_buffer_replace_way[i] && main_state_is_refill &&
((ret_valid && ret_last) || cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2_hit_wr); //wirte at last 4B
/*===============================tagv dina logic=================================*/
assign way_tagv_dina[i] = (cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2_hit_wr) ? 21'b0 : {request_buffer_tag, 1'b1};
end
endgenerate
/*==============================================================================*/
generate
for(i=0;i<2;i=i+1) begin:data_ram_way
for(j=0;j<4;j=j+1) begin:data_ram_bank
data_bank_sram u(
.addra (way_bank_addra[i][j]) ,
.clka (clk ) ,
.dina (way_bank_dina[i][j] ) ,
.douta (way_bank_douta[i][j]) ,
.ena (way_bank_ena[i][j] ) ,
.wea (way_bank_wea[i][j] )
);
end
end
endgenerate
generate
for(i=0;i<2;i=i+1) begin:tagv_ram_way
//[20:1] tag [0:0] v
tagv_sram u(
.addra (way_tagv_addra[i]) ,
.clka (clk ) ,
.dina (way_tagv_dina[i] ) ,
.douta (way_tagv_douta[i]) ,
.ena (way_tagv_ena[i] ) ,
.wea (way_tagv_wea[i] )
);
end
endgenerate
lfsr lfsr(
.clk (clk ) ,
.reset (reset ) ,
.random_val (random_val )
);
assign main_state_is_idle = main_state == main_idle ;
assign main_state_is_lookup = main_state == main_lookup ;
assign main_state_is_replace = main_state == main_replace;
assign main_state_is_refill = main_state == main_refill ;
endmodule

1005
rtl/ip/open-la500/id_stage.v Normal file
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`include "mycpu.h"
`include "csr.h"
module if_stage(
input clk ,
input reset ,
//allwoin
input ds_allowin ,
//brbus
input [`BR_BUS_WD -1:0] br_bus ,
//to ds
output fs_to_ds_valid ,
output [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus ,
//exception
input excp_flush ,
input ertn_flush ,
input refetch_flush ,
input icacop_flush ,
input [31:0] ws_pc ,
input [31:0] csr_eentry ,
input [31:0] csr_era ,
input excp_tlbrefill ,
input [31:0] csr_tlbrentry ,
input has_int ,
//idle
input idle_flush ,
// inst cache interface
output inst_valid ,
output inst_op ,
output [ 3:0] inst_wstrb ,
output [31:0] inst_wdata ,
input inst_addr_ok ,
input inst_data_ok ,
input icache_miss ,
input [31:0] inst_rdata ,
output inst_uncache_en ,
output tlb_excp_cancel_req,
//from csr
input csr_pg ,
input csr_da ,
input [31:0] csr_dmw0 ,
input [31:0] csr_dmw1 ,
input [ 1:0] csr_plv ,
input [ 1:0] csr_datf ,
input disable_cache ,
//to btb
output [31:0] fetch_pc ,
output fetch_en ,
input [31:0] btb_ret_pc ,
input btb_taken ,
input btb_en ,
input [ 4:0] btb_index ,
//to addr trans
output [31:0] inst_addr ,
output inst_addr_trans_en,
output dmw0_en ,
output dmw1_en ,
//tlb
input inst_tlb_found ,
input inst_tlb_v ,
input inst_tlb_d ,
input [ 1:0] inst_tlb_mat ,
input [ 1:0] inst_tlb_plv
);
reg fs_valid;
wire fs_ready_go;
wire fs_allowin;
wire to_fs_valid;
wire pfs_ready_go;
wire [31:0] seq_pc;
wire [31:0] nextpc;
wire pfs_excp_adef;
wire fs_excp_tlbr;
wire fs_excp_pif;
wire fs_excp_ppi;
reg fs_excp;
reg fs_excp_num;
wire excp;
wire [3:0] excp_num;
wire pfs_excp;
wire pfs_excp_num;
wire flush_sign;
reg [31:0] inst_rd_buff;
reg inst_buff_enable;
wire da_mode;
wire pg_mode;
wire btb_pre_error_flush;
wire [31:0] btb_pre_error_flush_target;
wire flush_inst_delay;
wire flush_inst_go_dirt;
wire fetch_btb_target;
reg idle_lock;
wire tlb_excp_lock_pc;
wire [31:0] btb_ret_pc_t;
wire [ 4:0] btb_index_t;
wire btb_taken_t;
wire btb_en_t;
wire [31:0] excp_entry;
wire [31:0] inst_flush_pc;
assign {btb_pre_error_flush,
btb_pre_error_flush_target } = br_bus;
wire [31:0] fs_inst;
reg [31:0] fs_pc;
reg [37:0] btb_lock_buffer;
reg btb_lock_en;
assign fs_to_ds_bus = {btb_ret_pc_t, //108:77
btb_index_t, //76:72
btb_taken_t, //71:71
btb_en_t, //70:70
icache_miss, //69:69
excp, //68:68
excp_num, //67:64
fs_inst, //63:32
fs_pc //31:0
};
assign flush_sign = ertn_flush || excp_flush || refetch_flush || icacop_flush || idle_flush;
assign flush_inst_delay = flush_sign && !inst_addr_ok || idle_flush;
assign flush_inst_go_dirt = flush_sign && inst_addr_ok && !idle_flush;
//flush state machine
reg [31:0] flush_inst_req_buffer;
reg flush_inst_req_state;
localparam flush_inst_req_empty = 1'b0;
localparam flush_inst_req_full = 1'b1;
always @(posedge clk) begin
if (reset) begin
flush_inst_req_state <= flush_inst_req_empty;
end
else case (flush_inst_req_state)
flush_inst_req_empty: begin
if(flush_inst_delay) begin
flush_inst_req_buffer <= nextpc;
flush_inst_req_state <= flush_inst_req_full;
end
end
flush_inst_req_full: begin
if(pfs_ready_go) begin
flush_inst_req_state <= flush_inst_req_empty;
end
else if (flush_sign) begin
flush_inst_req_buffer <= nextpc;
end
end
endcase
end
assign fetch_btb_target = (btb_taken && btb_en) || (btb_lock_en && btb_lock_buffer[37]);
/*
* idle lock
* when idle inst commit, stop inst fetch until interrupted
*/
always @(posedge clk) begin
if (reset) begin
idle_lock <= 1'b0;
end
else if (idle_flush && !has_int) begin
idle_lock <= 1'b1;
end
else if (has_int) begin
idle_lock <= 1'b0;
end
end
/*
* br state machine
* when btb pre error, id stage will cancel one inst. so need confirm useless
* inst (will be canceled) is generated.
*/
reg [31:0] br_target_inst_req_buffer;
reg [ 2:0] br_target_inst_req_state;
localparam br_target_inst_req_empty = 3'b001;
localparam br_target_inst_req_wait_slot = 3'b010;
localparam br_target_inst_req_wait_br_target = 3'b100;
always @(posedge clk) begin
if (reset) begin
br_target_inst_req_state <= br_target_inst_req_empty;
end
else case (br_target_inst_req_state)
br_target_inst_req_empty: begin
if (flush_sign) begin
br_target_inst_req_state <= br_target_inst_req_empty;
end
else if(btb_pre_error_flush && !fs_valid && !inst_addr_ok) begin
br_target_inst_req_state <= br_target_inst_req_wait_slot;
br_target_inst_req_buffer <= btb_pre_error_flush_target;
end
else if(btb_pre_error_flush && !inst_addr_ok && fs_valid || btb_pre_error_flush && inst_addr_ok && !fs_valid) begin
br_target_inst_req_state <= br_target_inst_req_wait_br_target;
br_target_inst_req_buffer <= btb_pre_error_flush_target;
end
end
br_target_inst_req_wait_slot: begin
if(flush_sign) begin
br_target_inst_req_state <= br_target_inst_req_empty;
end
else if(pfs_ready_go) begin
br_target_inst_req_state <= br_target_inst_req_wait_br_target;
end
end
br_target_inst_req_wait_br_target: begin
if(pfs_ready_go || flush_sign) begin
br_target_inst_req_state <= br_target_inst_req_empty;
end
end
default: begin
br_target_inst_req_state <= br_target_inst_req_empty;
end
endcase
end
/*
* btb lock
* btb ret only maintain one clock
* when pfs not ready go, should buffer btb ret
*/
always @(posedge clk) begin
if (reset || flush_sign || fetch_en)
btb_lock_en <= 1'b0;
else if (btb_en && !pfs_ready_go) begin
btb_lock_en <= 1'b1;
btb_lock_buffer <= {btb_taken, btb_index, btb_ret_pc};
end
end
assign btb_ret_pc_t = {32{btb_lock_en}} & btb_lock_buffer[31:0] | btb_ret_pc;
assign btb_index_t = {5{btb_lock_en}} & btb_lock_buffer[36:32] | btb_index;
assign btb_taken_t = btb_lock_en && btb_lock_buffer[37] || btb_taken;
assign btb_en_t = btb_lock_en || btb_en;
// pre-IF stage
assign pfs_ready_go = (inst_valid || pfs_excp) && inst_addr_ok;
assign to_fs_valid = ~reset && pfs_ready_go;
assign seq_pc = fs_pc + 32'h4;
assign excp_entry = {32{excp_tlbrefill}} & csr_tlbrentry |
{32{!excp_tlbrefill}} & csr_eentry ;
assign inst_flush_pc = {32{ertn_flush}} & csr_era |
{32{refetch_flush || icacop_flush || idle_flush}} & (ws_pc + 32'h4) ;
assign nextpc = (flush_inst_req_state == flush_inst_req_full) ? flush_inst_req_buffer :
excp_flush ? excp_entry :
(ertn_flush || refetch_flush || icacop_flush || idle_flush) ? inst_flush_pc :
(br_target_inst_req_state == br_target_inst_req_wait_br_target) ? br_target_inst_req_buffer :
btb_pre_error_flush && fs_valid ? btb_pre_error_flush_target:
fetch_btb_target ? btb_ret_pc_t :
seq_pc ;
/*
*when encounter tlb excp, stop inst fetch until excp_flush. avoid fetch useless inst.
*but should not lock when btb state machine or flush state machine is work.
*/
assign tlb_excp_lock_pc = tlb_excp_cancel_req && br_target_inst_req_state != br_target_inst_req_wait_br_target && flush_inst_req_state != flush_inst_req_full;
//when flush_sign meet icache_busy 1, flush_sign's inst valid should not set immediately
assign inst_valid = (fs_allowin && !pfs_excp && !tlb_excp_lock_pc || flush_sign || btb_pre_error_flush) && !(idle_flush || idle_lock);
assign inst_op = 1'b0;
assign inst_wstrb = 4'h0;
assign inst_addr = nextpc; //nextpc
assign inst_wdata = 32'b0;
assign fs_inst = (inst_buff_enable) ? inst_rd_buff : inst_rdata;
//inst read buffer use for stall situation
always @(posedge clk) begin
if (reset || (fs_ready_go && ds_allowin) || flush_sign) begin
inst_buff_enable <= 1'b0;
end
else if ((inst_data_ok) && !ds_allowin) begin
inst_rd_buff <= inst_rdata;
inst_buff_enable <= 1'b1;
end
end
//exception
assign pfs_excp_adef = (nextpc[0] || nextpc[1]); //word align
//tlb
assign fs_excp_tlbr = !inst_tlb_found && inst_addr_trans_en;
assign fs_excp_pif = !inst_tlb_v && inst_addr_trans_en;
assign fs_excp_ppi = (csr_plv > inst_tlb_plv) && inst_addr_trans_en;
assign tlb_excp_cancel_req = fs_excp_tlbr || fs_excp_pif || fs_excp_ppi;
assign pfs_excp = pfs_excp_adef;
assign pfs_excp_num = {pfs_excp_adef};
assign excp = fs_excp || fs_excp_tlbr || fs_excp_pif || fs_excp_ppi ;
assign excp_num = {fs_excp_ppi, fs_excp_pif, fs_excp_tlbr, fs_excp_num};
//addr trans
assign inst_addr_trans_en = pg_mode && !dmw0_en && !dmw1_en;
//addr dmw trans //TOT
assign dmw0_en = ((csr_dmw0[`PLV0] && csr_plv == 2'd0) || (csr_dmw0[`PLV3] && csr_plv == 2'd3)) && (fs_pc[31:29] == csr_dmw0[`VSEG]) && pg_mode;
assign dmw1_en = ((csr_dmw1[`PLV0] && csr_plv == 2'd0) || (csr_dmw1[`PLV3] && csr_plv == 2'd3)) && (fs_pc[31:29] == csr_dmw1[`VSEG]) && pg_mode;
//uncache judgement
assign da_mode = csr_da && !csr_pg;
assign pg_mode = csr_pg && !csr_da;
assign inst_uncache_en = (da_mode && (csr_datf == 2'b0)) ||
(dmw0_en && (csr_dmw0[`DMW_MAT] == 2'b0)) ||
(dmw1_en && (csr_dmw1[`DMW_MAT] == 2'b0)) ||
(inst_addr_trans_en && (inst_tlb_mat == 2'b0)) ||
disable_cache;
//assign inst_uncache_en = 1'b1; //used for debug
// IF stage
assign fs_ready_go = inst_data_ok || inst_buff_enable || excp;
assign fs_allowin = !fs_valid || fs_ready_go && ds_allowin;
assign fs_to_ds_valid = fs_valid && fs_ready_go;
always @(posedge clk) begin
if (reset || flush_inst_delay) begin
fs_valid <= 1'b0;
end
else if (fs_allowin) begin
fs_valid <= to_fs_valid;
end
if (reset) begin
fs_pc <= 32'h1bfffffc; //trick: to make nextpc be 0x1c000000 during reset
fs_excp <= 1'b0;
fs_excp_num <= 4'b0;
end
else if (to_fs_valid && (fs_allowin || flush_inst_go_dirt)) begin
fs_pc <= nextpc;
fs_excp <= pfs_excp;
fs_excp_num <= pfs_excp_num;
end
end
//go btb and tlb
assign fetch_pc = nextpc;
assign fetch_en = inst_valid && inst_addr_ok;
endmodule

53
rtl/ip/open-la500/lacc_core.v Normal file
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`include "mycpu.h"
`include "csr.h"
`ifdef HAS_LACC
module lacc_core(
input clk,
input reset,
input lacc_flush,
input lacc_req_valid,
input [`LACC_OP_WIDTH-1: 0] lacc_req_command,
input [6: 0] lacc_req_imm,
input [31: 0] lacc_req_rj,
input [31: 0] lacc_req_rk,
output lacc_rsp_valid,
output [31: 0] lacc_rsp_rdat,
// wreq will also send valid sign
output lacc_data_valid,
input lacc_data_ready,
output [31: 0] lacc_data_addr,
output lacc_data_read,
output [31: 0] lacc_data_wdata,
output [1: 0] lacc_data_size,
input lacc_drsp_valid,
input [31: 0] lacc_drsp_rdata
);
lacc_demo demo(
.clk(clk),
.reset(reset),
.lacc_flush (lacc_flush),
.lacc_req_valid (lacc_req_valid),
.lacc_req_command(lacc_req_command),
.lacc_req_imm (lacc_req_imm),
.lacc_req_rj (lacc_req_rj),
.lacc_req_rk (lacc_req_rk),
.lacc_rsp_valid (lacc_rsp_valid),
.lacc_rsp_rdat (lacc_rsp_rdat),
.lacc_data_valid(lacc_data_valid),
.lacc_data_ready(lacc_data_ready),
.lacc_data_addr (lacc_data_addr),
.lacc_data_read (lacc_data_read),
.lacc_data_wdata(lacc_data_wdata),
.lacc_data_size (lacc_data_size),
.lacc_drsp_valid(lacc_drsp_valid),
.lacc_drsp_rdata(lacc_drsp_rdata)
);
endmodule
`endif

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module lacc_demo(
input clk,
input reset,
input lacc_flush,
input lacc_req_valid,
input [`LACC_OP_WIDTH-1: 0] lacc_req_command,
input [6: 0] lacc_req_imm,
input [31: 0] lacc_req_rj,
input [31: 0] lacc_req_rk,
output lacc_rsp_valid,
output [31: 0] lacc_rsp_rdat,
output lacc_data_valid,
input lacc_data_ready,
output [31: 0] lacc_data_addr,
output lacc_data_read,
output [31: 0] lacc_data_wdata,
output [1: 0] lacc_data_size,
input lacc_drsp_valid,
input [31: 0] lacc_drsp_rdata
);
wire op_lmadd;
wire op_cfg;
reg [31: 0] req_addr1, req_addr2, waddr;
reg [6: 0] req_size;
wire [31: 0] nxt_req_addr1, nxt_req_addr2, req_addr1_n4, req_addr2_n4;
wire [31: 0] nxt_waddr, waddr_n4;
wire [6: 0] nxt_req_size, req_size_p1;
wire req_addr1_en, req_addr2_en, req_size_en, waddr_en;
wire req_size_nz = |req_size;
reg [31: 0] conv_data;
wire [31: 0] add_data;
/*********************************
* func:
* rj and rk are addr
* read from rj and rk and add them
* write back to waddr
* then write add res to rd
**********************************/
assign op_lmadd = lacc_req_command == 0;
// rj is size of read, rk is waddr
assign op_cfg = lacc_req_command == 1;
parameter FSM_WIDTH = 2;
parameter IDLE = 'b0;
parameter REQ_ADDR1 = 'b1;
parameter REQ_ADDR2 = 'd2;
parameter FINAL = 'd3;
reg [FSM_WIDTH-1: 0] state_r;
wire [FSM_WIDTH-1: 0] state_n;
wire [FSM_WIDTH-1: 0] state_final_n;
wire state_idle = state_r == IDLE;
wire state_req_addr1 = state_r == REQ_ADDR1;
wire state_req_addr2 = state_r == REQ_ADDR2;
wire state_final = state_r == FINAL;
wire data_hsk = lacc_data_valid & lacc_data_ready;
wire idle_exit = state_idle & lacc_req_valid & op_lmadd & req_size_nz;
wire req_addr1_exit = state_req_addr1 & data_hsk;
wire req_addr2_exit = state_req_addr2 & data_hsk;
wire final_exit = state_final & data_hsk;
wire exit2idle = final_exit & ~req_size_nz;
assign state_final_n = ~req_size_nz ? IDLE : REQ_ADDR1;
wire state_en = idle_exit | req_addr1_exit | req_addr2_exit | final_exit;
assign state_n = {FSM_WIDTH{idle_exit}} & REQ_ADDR1 |
{FSM_WIDTH{req_addr1_exit}} & REQ_ADDR2 |
{FSM_WIDTH{req_addr2_exit}} & FINAL |
{FSM_WIDTH{final_exit}} & state_final_n;
assign req_addr1_en = state_idle & lacc_req_valid & op_lmadd | req_addr1_exit;
assign req_addr2_en = state_idle & lacc_req_valid & op_lmadd | req_addr2_exit;
assign req_size_en = lacc_req_valid & op_cfg | req_addr2_exit;
assign waddr_en = lacc_req_valid & op_cfg | final_exit;
assign req_addr1_n4 = req_addr1 + 4;
assign req_addr2_n4 = req_addr2 + 4;
assign req_size_p1 = req_size - 1;
assign waddr_n4 = waddr + 4;
assign nxt_req_addr1 = {32{lacc_req_valid & state_idle & op_lmadd}} & lacc_req_rj |
{32{req_addr1_exit}} & req_addr1_n4;
assign nxt_req_addr2 = {32{lacc_req_valid & state_idle & op_lmadd}} & lacc_req_rk |
{32{req_addr2_exit}} & req_addr2_n4;
assign nxt_req_size = {7{lacc_req_valid & op_cfg}} & lacc_req_rj |
{7{req_addr2_exit}} & req_size_p1;
assign nxt_waddr = {32{lacc_req_valid & op_cfg}} & lacc_req_rk |
{32{final_exit}} & waddr_n4;
reg data_req;
wire data_req_en;
wire nxt_data_req;
assign data_req_en = idle_exit | req_addr1_exit | req_addr2_exit | final_exit;
assign nxt_data_req = ~exit2idle & ~req_addr2_exit;
reg buffer_valid, wdata_valid, wdata_valid_n;
reg [31: 0] buffer_data;
reg [31: 0] buffer_wdata;
always @(posedge clk)begin
if(req_addr1_en) req_addr1 <= nxt_req_addr1;
if(req_addr2_en) req_addr2 <= nxt_req_addr2;
if(waddr_en) waddr <= nxt_waddr;
if(~buffer_valid) buffer_data <= lacc_drsp_rdata;
if(buffer_valid & lacc_drsp_valid) begin
buffer_wdata <= lacc_drsp_rdata + buffer_data;
end
wdata_valid_n <= wdata_valid;
if(reset | lacc_flush)begin
req_size <= 7'b0;
state_r <= IDLE;
data_req <= 1'b0;
buffer_valid <= 1'b0;
wdata_valid <= 1'b0;
end
else begin
if(req_size_en) req_size <= nxt_req_size;
if(state_en) state_r <= state_n;
if(data_req_en) data_req <= nxt_data_req;
if(final_exit) buffer_valid <= 1'b0;
else if(lacc_drsp_valid & ~wdata_valid_n) buffer_valid <= 1'b1;
if(final_exit) wdata_valid <= 1'b0;
else if(buffer_valid & lacc_drsp_valid) wdata_valid <= 1'b1;
end
end
assign lacc_data_valid = data_req | wdata_valid;
assign lacc_data_read = ~wdata_valid;
assign lacc_data_addr = {32{state_req_addr1}} & req_addr1 |
{32{state_req_addr2}} & req_addr2 |
{32{state_final}} & waddr;
assign lacc_data_size = 2'b10;
assign lacc_data_wdata = buffer_wdata;
assign add_data = conv_data + lacc_drsp_rdata;
always @(posedge clk)begin
if(idle_exit)begin
conv_data <= 0;
end
else begin
if(lacc_drsp_valid)begin
conv_data <= add_data;
end
end
end
assign lacc_rsp_valid = exit2idle | lacc_req_valid & state_idle & ((op_lmadd & ~req_size_nz) | op_cfg);
assign lacc_rsp_rdat = conv_data;
endmodule

368
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`include "mycpu.h"
`include "csr.h"
module mem_stage(
input clk ,
input reset ,
//allowin
input ws_allowin ,
output ms_allowin ,
//from es
input es_to_ms_valid,
input [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus ,
//to ws
output ms_to_ws_valid,
output [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus ,
//to ds forward path
output [`MS_TO_DS_FORWARD_BUS-1:0] ms_to_ds_forward_bus,
output ms_to_ds_valid,
//div mul
input [31:0] div_result ,
input [31:0] mod_result ,
input [63:0] mul_result ,
//exception
input excp_flush ,
input ertn_flush ,
input refetch_flush ,
input icacop_flush ,
//idle
input idle_flush ,
//tlb ins
output tlb_inst_stall,
//to es
output ms_wr_tlbehi ,
output ms_flush ,
//from cache
input data_data_ok ,
input dcache_miss ,
input [31:0] data_rdata ,
//to cache
output data_uncache_en,
output tlb_excp_cancel_req,
output sc_cancel_req ,
//from csr
input csr_pg ,
input csr_da ,
input [31:0] csr_dmw0 ,
input [31:0] csr_dmw1 ,
input [ 1:0] csr_plv ,
input [ 1:0] csr_datm ,
input disable_cache ,
input [27:0] lladdr ,
// from addr trans for difftest
input [ 7:0] data_index_diff ,
input [19:0] data_tag_diff ,
input [ 3:0] data_offset_diff ,
//to addr trans
output data_addr_trans_en,
output dmw0_en ,
output dmw1_en ,
output cacop_op_mode_di ,
//tlb
input data_tlb_found ,
input [ 4:0] data_tlb_index ,
input data_tlb_v ,
input data_tlb_d ,
input [ 1:0] data_tlb_mat ,
input [ 1:0] data_tlb_plv ,
input [19:0] data_tlb_ppn
);
reg ms_valid;
wire ms_ready_go;
wire dep_need_stall;
reg [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus_r;
wire [ 3:0] ms_mul_div_op;
wire [ 1:0] sram_addr_low2bit;
wire [ 1:0] ms_mem_size;
wire ms_load_op;
wire ms_gr_we;
wire [ 4:0] ms_dest;
wire [31:0] ms_exe_result;
wire [31:0] ms_pc;
wire ms_excp;
wire [ 9:0] ms_excp_num;
wire ms_ertn;
wire [31:0] ms_csr_result;
wire [13:0] ms_csr_idx;
wire ms_csr_we;
wire ms_ll_w;
wire ms_sc_w;
wire ms_store_op;
wire ms_tlbsrch;
wire ms_tlbfill;
wire ms_tlbwr;
wire ms_tlbrd;
wire ms_refetch;
wire ms_invtlb;
wire [ 9:0] ms_invtlb_asid;
wire [18:0] ms_invtlb_vpn;
wire ms_mem_sign_exted;
wire ms_icacop_op_en;
wire ms_br_inst;
wire ms_icache_miss;
wire ms_br_pre;
wire ms_br_pre_error;
wire ms_preld_inst;
wire ms_cacop;
wire ms_idle;
wire [31:0] ms_error_va;
// difftest
wire ms_cnt_inst ;
wire [63:0] ms_timer_64 ;
wire [31:0] ms_inst ;
wire [ 7:0] ms_inst_ld_en ;
wire [31:0] ms_ld_paddr ;
wire [31:0] ms_ld_vaddr ;
wire [ 7:0] ms_inst_st_en ;
wire [31:0] ms_st_data ;
wire ms_csr_rstat_en ;
wire [31:0] ms_csr_data ;
assign {ms_csr_data , //424:393 for difftest
ms_csr_rstat_en , //392:392 for difftest
ms_st_data , //391:360 for difftest
ms_inst_st_en , //359:352 for difftest
ms_ld_vaddr , //351:320 for difftest
ms_inst_ld_en , //319:312 for difftest
ms_cnt_inst , //311:311 for difftest
ms_timer_64 , //310:247 for difftest
ms_inst , //246:215 for difftest
ms_error_va , //214:183
ms_idle , //182:182
ms_cacop , //181:181
ms_preld_inst , //180:180
ms_br_pre_error , //179:179
ms_br_pre , //178:178
ms_icache_miss , //177:177
ms_br_inst , //176:176
ms_icacop_op_en , //175:175
ms_mem_sign_exted, //174:174
ms_invtlb_vpn , //173:155
ms_invtlb_asid , //154:145
ms_invtlb , //144:144
ms_tlbrd , //143:143
ms_refetch , //142:142
ms_tlbfill , //141:141
ms_tlbwr , //140:140
ms_tlbsrch , //139:139
ms_store_op , //138:138
ms_sc_w , //137:137
ms_ll_w , //136:136
ms_excp_num , //135:126
ms_csr_we , //125:125
ms_csr_idx , //124:111
ms_csr_result , //110:79
ms_ertn , //78:78
ms_excp , //77:77
ms_mem_size , //76:75
ms_mul_div_op , //74:71
ms_load_op , //70:70
ms_gr_we , //69:69
ms_dest , //68:64
ms_exe_result , //63:32
ms_pc //31:0
} = es_to_ms_bus_r;
wire [31:0] mem_result;
wire [31:0] ms_final_result;
wire flush_sign;
wire [31:0] ms_rdata;
reg [31:0] data_rd_buff;
reg data_buff_enable;
wire access_mem;
wire [ 4:0] cacop_op;
wire [ 1:0] cacop_op_mode;
wire forward_enable;
wire dest_zero;
wire [31:0] paddr;
wire [15:0] excp_num;
wire excp;
wire excp_tlbr;
wire excp_pil ;
wire excp_pis ;
wire excp_pme ;
wire excp_ppi ;
wire da_mode ;
wire pg_mode ;
wire sc_addr_eq;
assign ms_to_ws_bus = {ms_csr_data , //492:461 for difftest
ms_csr_rstat_en, //460:460 for difftest
ms_st_data , //459:428 for difftest
ms_inst_st_en , //427:420 for difftest
ms_ld_vaddr , //419:388 for difftest
ms_ld_paddr , //387:356 for difftest
ms_inst_ld_en , //355:348 for difftest
ms_cnt_inst , //347:347 for difftest
ms_timer_64 , //346:283 for difftest
ms_inst , //282:251 for difftest
data_uncache_en, //250:250
paddr , //249:218
ms_idle , //217:217
ms_br_pre_error, //216:216
ms_br_pre , //215:215
dcache_miss , //214:214
access_mem , //213:213
ms_icache_miss , //212:212
ms_br_inst , //211:211
ms_icacop_op_en, //210:210
ms_invtlb_vpn , //209:191
ms_invtlb_asid , //190:181
ms_invtlb , //180:180
ms_tlbrd , //179:179
ms_refetch , //178:178
ms_tlbfill , //177:177
ms_tlbwr , //176:176
data_tlb_index , //175:171
data_tlb_found , //170:170
ms_tlbsrch , //169:169
ms_error_va , //168:137
ms_sc_w , //136:136
ms_ll_w , //135:135
excp_num , //134:119
ms_csr_we , //118:118
ms_csr_idx , //117:104
ms_csr_result , //103:72
ms_ertn , //71:71
excp , //70:70
ms_gr_we , //69:69
ms_dest , //68:64
ms_final_result, //63:32
ms_pc //31:0
};
assign ms_to_ds_valid = ms_valid;
//cache inst need wait data_data_ok signal
assign ms_ready_go = (data_data_ok || data_buff_enable) || !access_mem || excp || sc_cancel_req;
assign ms_allowin = !ms_valid || ms_ready_go && ws_allowin;
assign ms_to_ws_valid = ms_valid && ms_ready_go;
always @(posedge clk) begin
if (reset || flush_sign) begin
ms_valid <= 1'b0;
end
else if (ms_allowin) begin
ms_valid <= es_to_ms_valid;
end
if (es_to_ms_valid && ms_allowin) begin
es_to_ms_bus_r <= es_to_ms_bus;
end
end
assign access_mem = ms_store_op || ms_load_op;
assign flush_sign = excp_flush || ertn_flush || refetch_flush || icacop_flush || idle_flush;
assign ms_rdata = data_buff_enable ? data_rd_buff : data_rdata;
assign sram_addr_low2bit = {ms_exe_result[1], ms_exe_result[0]};
wire [7:0] mem_byteLoaded = ({8{sram_addr_low2bit==2'b00}} & ms_rdata[ 7: 0]) |
({8{sram_addr_low2bit==2'b01}} & ms_rdata[15: 8]) |
({8{sram_addr_low2bit==2'b10}} & ms_rdata[23:16]) |
({8{sram_addr_low2bit==2'b11}} & ms_rdata[31:24]) ;
wire [15:0] mem_halfLoaded = ({16{sram_addr_low2bit==2'b00}} & ms_rdata[15: 0]) |
({16{sram_addr_low2bit==2'b10}} & ms_rdata[31:16]) ;
assign mem_result = ({32{ms_mem_size[0] && ms_mem_sign_exted}} & {{24{mem_byteLoaded[ 7]}}, mem_byteLoaded}) |
({32{ms_mem_size[0] && ~ms_mem_sign_exted}} & { 24'b0 , mem_byteLoaded}) |
({32{ms_mem_size[1] && ms_mem_sign_exted}} & {{16{mem_halfLoaded[15]}}, mem_halfLoaded}) |
({32{ms_mem_size[1] && ~ms_mem_sign_exted}} & { 16'b0 , mem_halfLoaded}) |
({32{!ms_mem_size}} & ms_rdata ) ;
assign ms_final_result = ({32{ms_load_op }} & mem_result ) |
({32{ms_mul_div_op[0]}} & mul_result[31:0] ) |
({32{ms_mul_div_op[1]}} & mul_result[63:32]) |
({32{ms_mul_div_op[2]}} & div_result ) |
({32{ms_mul_div_op[3]}} & mod_result ) |
({32{!ms_mul_div_op && !ms_load_op}} & (ms_exe_result&{32{!sc_cancel_req}}));
assign dest_zero = (ms_dest == 5'b0);
assign forward_enable = ms_gr_we & ~dest_zero & ms_valid;
assign dep_need_stall = ms_load_op && !ms_to_ws_valid;
assign ms_to_ds_forward_bus = {dep_need_stall, //38:38
forward_enable, //37:37
ms_dest , //36:32
ms_final_result //31:0
};
//addr trans
assign pg_mode = !csr_da && csr_pg;
//uncache judgement
assign da_mode = csr_da && !csr_pg;
assign data_addr_trans_en = pg_mode && !dmw0_en && !dmw1_en && !cacop_op_mode_di;
assign paddr = {data_tlb_ppn, ms_error_va[11:0]};
assign sc_addr_eq = (lladdr == paddr[31:4]);
assign sc_cancel_req = (!sc_addr_eq||data_uncache_en) && ms_sc_w && access_mem;
//addr dmw trans
assign dmw0_en = ((csr_dmw0[`PLV0] && csr_plv == 2'd0) || (csr_dmw0[`PLV3] && csr_plv == 2'd3)) && (ms_error_va[31:29] == csr_dmw0[`VSEG]) && pg_mode;
assign dmw1_en = ((csr_dmw1[`PLV0] && csr_plv == 2'd0) || (csr_dmw1[`PLV3] && csr_plv == 2'd3)) && (ms_error_va[31:29] == csr_dmw1[`VSEG]) && pg_mode;
assign excp = excp_tlbr || excp_pil || excp_pis || excp_ppi || excp_pme || ms_excp;
assign excp_num = {excp_pil, excp_pis, excp_ppi, excp_pme, excp_tlbr, 1'b0, ms_excp_num};
//tlb exception //preld should not generate these excp
assign excp_tlbr = (access_mem || ms_cacop) && !data_tlb_found && data_addr_trans_en;
assign excp_pil = (ms_load_op || ms_cacop) && !data_tlb_v && data_addr_trans_en; //cache will generate pil exception??
assign excp_pis = ms_store_op && !data_tlb_v && data_addr_trans_en;
assign excp_ppi = access_mem && data_tlb_v && (csr_plv > data_tlb_plv) && data_addr_trans_en;
assign excp_pme = ms_store_op && data_tlb_v && (csr_plv <= data_tlb_plv) && !data_tlb_d && data_addr_trans_en;
assign tlb_excp_cancel_req = excp_tlbr || excp_pil || excp_pis || excp_ppi || excp_pme;
assign data_uncache_en = (da_mode && (csr_datm == 2'b0)) ||
(dmw0_en && (csr_dmw0[`DMW_MAT] == 2'b0)) ||
(dmw1_en && (csr_dmw1[`DMW_MAT] == 2'b0)) ||
(data_addr_trans_en && (data_tlb_mat == 2'b0)) ||
disable_cache;
assign ms_flush = (excp | ms_ertn | (ms_csr_we | (ms_ll_w | ms_sc_w) & !excp) | ms_refetch | ms_idle) & ms_valid;
assign tlb_inst_stall = (ms_tlbsrch || ms_tlbrd) && ms_valid;
always @(posedge clk) begin
if (reset || (ms_ready_go && ws_allowin) || flush_sign) begin
data_rd_buff <= 32'b0;
data_buff_enable <= 1'b0;
end
else if (data_data_ok && !ws_allowin) begin
data_rd_buff <= data_rdata;
data_buff_enable <= 1'b1;
end
end
assign ms_wr_tlbehi = ms_csr_we && (ms_csr_idx == 14'h11) && ms_valid; //stall es tlbsrch
assign cacop_op = ms_dest;
assign cacop_op_mode = cacop_op[4:3];
assign cacop_op_mode_di = ms_cacop && ((cacop_op_mode == 2'b0) || (cacop_op_mode == 2'b1));
reg [ 7:0] tmp_data_index ;
reg [ 3:0] tmp_data_offset ;
always @(posedge clk) begin
tmp_data_index <= data_index_diff;
tmp_data_offset <= data_offset_diff;
end
assign ms_ld_paddr = {data_tag_diff, tmp_data_index, tmp_data_offset};
endmodule

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module YDecoder(
input yc, yb, ya, //c -> i+1; b -> i; a -> i-1
output negx, x, neg2x, _2x
);
assign negx = (yc & yb & ~ya) | (yc & ~yb & ya);
assign x = (~yc & ~yb & ya) | (~yc & yb & ~ya);
assign neg2x = (yc & ~yb & ~ya);
assign _2x = (~yc & yb & ya);
endmodule
module BoothBase(
input negx, x, neg2x, _2x,
input InX,
input PosLastX, NegLastX,
output PosNextX, NegNextX,
output OutX
);
assign OutX = (negx & ~InX) | (x & InX) | (neg2x & NegLastX) | (_2x & PosLastX);
assign PosNextX = InX;
assign NegNextX = ~InX;
endmodule
module BoothInterBase(
input [2:0] y,
input [63:0] InX,
output [63:0] OutX,
output Carry
);
wire negx, x, neg2x, _2x;
wire [1:0] CarrySig [64:0];
YDecoder uu(.yc(y[2]), .yb(y[1]), .ya(y[0]), .negx(negx), .x(x), .neg2x(neg2x), ._2x(_2x));
BoothBase fir(.negx(negx), .x(x), .neg2x(neg2x), ._2x(_2x), .InX(InX[0]), .PosLastX(1'b0), .NegLastX(1'b1), .PosNextX(CarrySig[1][0]), .NegNextX(CarrySig[1][1]), .OutX(OutX[0]));
generate
genvar i;
for (i=1; i<64; i=i+1) begin: gfor
BoothBase ui(
.negx(negx),
.x(x),
.neg2x(neg2x),
._2x(_2x),
.InX(InX[i]),
.PosLastX(CarrySig[i][0]),
.NegLastX(CarrySig[i][1]),
.PosNextX(CarrySig[i+1][0]),
.NegNextX(CarrySig[i+1][1]),
.OutX(OutX[i])
);
end
endgenerate
assign Carry = negx || neg2x;
endmodule
module addr(
input A, B, C,
output Carry, S
);
assign S = ~A & ~B & C | ~A & B & ~C | A & ~B & ~C | A & B & C;
assign Carry = A & B | A & C | B & C;
endmodule
module WallaceTreeBase(
input [16:0] InData,
input [13:0] CIn,
output [13:0] COut,
output C, S
);
//first stage
wire [4:0] FirSig;
addr first1(.A(InData[4]), .B(InData[3]), .C(InData[2]), .Carry(COut[0]), .S(FirSig[0]));
addr first2(.A(InData[7]), .B(InData[6]), .C(InData[5]), .Carry(COut[1]), .S(FirSig[1]));
addr first3(.A(InData[10]), .B(InData[9]), .C(InData[8]), .Carry(COut[2]), .S(FirSig[2]));
addr first4(.A(InData[13]), .B(InData[12]), .C(InData[11]), .Carry(COut[3]), .S(FirSig[3]));
addr first5(.A(InData[16]), .B(InData[15]), .C(InData[14]), .Carry(COut[4]), .S(FirSig[4]));
//second stage
wire [3:0] SecSig;
addr second1(.A(CIn[2]), .B(CIn[1]), .C(CIn[0]), .Carry(COut[5]), .S(SecSig[0]));
addr second2(.A(InData[0]), .B(CIn[4]), .C(CIn[3]), .Carry(COut[6]), .S(SecSig[1]));
addr second3(.A(FirSig[1]), .B(FirSig[0]), .C(InData[1]), .Carry(COut[7]), .S(SecSig[2]));
addr second4(.A(FirSig[4]), .B(FirSig[3]), .C(FirSig[2]), .Carry(COut[8]), .S(SecSig[3]));
//third stage
wire [1:0] ThiSig;
addr third1(.A(SecSig[0]), .B(CIn[6]), .C(CIn[5]), .Carry(COut[9]), .S(ThiSig[0]));
addr third2(.A(SecSig[3]), .B(SecSig[2]), .C(SecSig[1]), .Carry(COut[10]), .S(ThiSig[1]));
//fourth stage
wire [1:0] ForSig;
addr fourth1(.A(CIn[9]), .B(CIn[8]), .C(CIn[7]), .Carry(COut[11]), .S(ForSig[0]));
addr fourth2(.A(ThiSig[1]), .B(ThiSig[0]), .C(CIn[10]), .Carry(COut[12]), .S(ForSig[1]));
//fifth stage
wire FifSig;
addr fifth1(.A(ForSig[1]), .B(ForSig[0]), .C(CIn[11]), .Carry(COut[13]), .S(FifSig));
//sixth stage
addr sixth1(.A(FifSig), .B(CIn[13]), .C(CIn[12]), .Carry(C), .S(S));
endmodule
//-------------------------------------------------------------------------------------------------------------------
module mul(
input mul_clk, reset,
input mul_signed,
input [31:0] x, y, //x扩展至64位 y扩展至33位 区别有无符号
output [63:0] result
);
wire [63:0] CalX;
wire [32:0] CalY;
assign CalX = mul_signed ? {{32{x[31]}}, x} : {32'b0, x};
assign CalY = mul_signed ? {y[31], y} : {1'b0, y};
//booth
wire [16:0] Carry; //booth计算得到的进位
wire [63:0] BoothRes [16:0]; //booth的计算结果
BoothInterBase fir(.y({CalY[1], CalY[0], 1'b0}), .InX(CalX), .OutX(BoothRes[0]), .Carry(Carry[0]));
generate
genvar i;
for (i=2; i<32; i=i+2) begin: boothfor
BoothInterBase ai(
.y(CalY[i+1:i-1]),
.InX(CalX<<i),
.OutX(BoothRes[i>>1]),
.Carry(Carry[i>>1])
);
end
endgenerate
BoothInterBase las(.y({CalY[32], CalY[32], CalY[31]}), .InX(CalX<<32), .OutX(BoothRes[16]), .Carry(Carry[16]));
reg [16:0] SecStageCarry;
reg [63:0] SecStageBoothRes [16:0];
integer p;
always @(posedge mul_clk) begin
if (~reset) begin
SecStageCarry <= Carry;
for(p=0; p<17; p=p+1) begin
SecStageBoothRes[p] <= BoothRes[p];
end
end
end
//wallace
wire [13:0] WallaceInter [64:0];
wire [63:0] COut, SOut;
WallaceTreeBase firs(
.InData({SecStageBoothRes[0][0], SecStageBoothRes[1][0], SecStageBoothRes[2][0], SecStageBoothRes[3][0], SecStageBoothRes[4][0], SecStageBoothRes[5][0], SecStageBoothRes[6][0],
SecStageBoothRes[7][0], SecStageBoothRes[8][0], SecStageBoothRes[9][0], SecStageBoothRes[10][0], SecStageBoothRes[11][0], SecStageBoothRes[12][0], SecStageBoothRes[13][0], SecStageBoothRes[14][0],
SecStageBoothRes[15][0], SecStageBoothRes[16][0]}),
.CIn(SecStageCarry[13:0]),
.COut(WallaceInter[1]),
.C(COut[0]),
.S(SOut[0])
);
generate
genvar n;
for (n=1; n<64; n=n+1) begin: wallacefor
WallaceTreeBase bi(
.InData({SecStageBoothRes[0][n], SecStageBoothRes[1][n], SecStageBoothRes[2][n], SecStageBoothRes[3][n], SecStageBoothRes[4][n], SecStageBoothRes[5][n], SecStageBoothRes[6][n],
SecStageBoothRes[7][n], SecStageBoothRes[8][n], SecStageBoothRes[9][n], SecStageBoothRes[10][n], SecStageBoothRes[11][n], SecStageBoothRes[12][n], SecStageBoothRes[13][n], SecStageBoothRes[14][n],
SecStageBoothRes[15][n], SecStageBoothRes[16][n]}),
.CIn(WallaceInter[n]),
.COut(WallaceInter[n+1]),
.C(COut[n]),
.S(SOut[n])
);
end
endgenerate
//64bit add
assign result = SOut + {COut[62:0], SecStageCarry[14]} + SecStageCarry[15];
endmodule

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rtl/ip/open-la500/mycpu.h Normal file
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`ifndef MYCPU_H
`define MYCPU_H
// `define BR_BUS_WD 33 //bug5 32->33
// `define FS_TO_DS_BUS_WD 109
// `define DS_TO_ES_BUS_WD 236
// `define ES_TO_MS_BUS_WD 215
// `define MS_TO_WS_BUS_WD 218
// `define WS_TO_RF_BUS_WD 38
// `define ES_TO_DS_FORWARD_BUS 39
// `define MS_TO_DS_FORWARD_BUS 39
// `define HAS_LACC
`define LACC_OP_SIZE 3
`define LACC_OP_WIDTH $clog2(`LACC_OP_SIZE)
`define BR_BUS_WD 33 //bug5 32->33
`define FS_TO_DS_BUS_WD 109
`define DS_TO_ES_BUS_WD (350 \
`ifdef HAS_LACC \
+`LACC_OP_WIDTH+1 \
`endif \
)
`define ES_TO_MS_BUS_WD 425
`define MS_TO_WS_BUS_WD 493
`define WS_TO_RF_BUS_WD 38
`define ES_TO_DS_FORWARD_BUS 39
`define MS_TO_DS_FORWARD_BUS 39
`endif
//`define SIMU

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module perf_counter (
input clk ,
input reset ,
input dcache_miss ,
input icache_miss ,
input commit_inst ,
input br_inst ,
input mem_inst ,
input br_pre ,
input br_pre_error
);
reg[31:0] dcache_miss_counter;
reg[31:0] icache_miss_counter;
reg[31:0] commit_inst_counter;
reg[31:0] br_inst_counter;
reg[31:0] mem_inst_counter;
reg[31:0] br_pre_counter;
reg[31:0] br_pre_error_counter;
always @(posedge clk) begin
if (reset) begin
dcache_miss_counter <= 32'b0;
icache_miss_counter <= 32'b0;
commit_inst_counter <= 32'b0;
br_inst_counter <= 32'b0;
mem_inst_counter <= 32'b0;
br_pre_counter <= 32'b0;
br_pre_error_counter <= 32'b0;
end
else begin
if (dcache_miss) begin
dcache_miss_counter <= dcache_miss_counter + 32'b1;
end
if (icache_miss) begin
icache_miss_counter <= icache_miss_counter + 32'b1;
end
if (commit_inst) begin
commit_inst_counter <= commit_inst_counter + 32'b1;
end
if (br_inst) begin
br_inst_counter <= br_inst_counter + 32'b1;
end
if (mem_inst) begin
mem_inst_counter <= mem_inst_counter + 32'b1;
end
if (br_pre) begin
br_pre_counter <= br_pre_counter + 32'b1;
end
if (br_pre_error) begin
br_pre_error_counter <= br_pre_error_counter + 32'b1;
end
end
end
endmodule

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module regfile(
input clk,
// READ PORT 1
input [ 4:0] raddr1,
output [31:0] rdata1,
// READ PORT 2
input [ 4:0] raddr2,
output [31:0] rdata2,
// WRITE PORT
input we, //write enable, HIGH valid
input [ 4:0] waddr,
input [31:0] wdata
`ifdef DIFFTEST_EN
,
output [31:0] rf_o [31:0] // difftest
`endif
);
reg [31:0] rf[31:0];
//WRITE
always @(posedge clk) begin
if (we) rf[waddr]<= wdata;
end
//READ OUT 1
assign rdata1 = (raddr1==5'b0) ? 32'b0 :
((raddr1==waddr) && we) ? wdata :
rf[raddr1];
//READ OUT 2
assign rdata2 = (raddr2==5'b0) ? 32'b0 :
((raddr2==waddr) && we) ? wdata :
rf[raddr2];
// difftest
`ifdef DIFFTEST_EN
assign rf_o = rf;
`endif
endmodule

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module tlb_entry
#(
parameter TLBNUM = 32
)
(
input clk,
// search port 0
input s0_fetch ,
input [18:0] s0_vppn ,
input s0_odd_page ,
input [ 9:0] s0_asid ,
output s0_found ,
output [ 4:0] s0_index ,
output [ 5:0] s0_ps ,
output [19:0] s0_ppn ,
output s0_v ,
output s0_d ,
output [ 1:0] s0_mat ,
output [ 1:0] s0_plv ,
//search port 1
input s1_fetch ,
input [18:0] s1_vppn ,
input s1_odd_page ,
input [ 9:0] s1_asid ,
output s1_found ,
output [ 4:0] s1_index ,
output [ 5:0] s1_ps ,
output [19:0] s1_ppn ,
output s1_v ,
output s1_d ,
output [ 1:0] s1_mat ,
output [ 1:0] s1_plv ,
// write port
input we ,
input [$clog2(TLBNUM)-1:0] w_index ,
input [18:0] w_vppn ,
input [ 9:0] w_asid ,
input w_g ,
input [ 5:0] w_ps ,
input w_e ,
input w_v0 ,
input w_d0 ,
input [ 1:0] w_mat0 ,
input [ 1:0] w_plv0 ,
input [19:0] w_ppn0 ,
input w_v1 ,
input w_d1 ,
input [ 1:0] w_mat1 ,
input [ 1:0] w_plv1 ,
input [19:0] w_ppn1 ,
// read port
input [$clog2(TLBNUM)-1:0] r_index ,
output [18:0] r_vppn ,
output [ 9:0] r_asid ,
output r_g ,
output [ 5:0] r_ps ,
output r_e ,
output r_v0 ,
output r_d0 ,
output [ 1:0] r_mat0 ,
output [ 1:0] r_plv0 ,
output [19:0] r_ppn0 ,
output r_v1 ,
output r_d1 ,
output [ 1:0] r_mat1 ,
output [ 1:0] r_plv1 ,
output [19:0] r_ppn1 ,
// invalid port
input inv_en ,
input [ 4:0] inv_op ,
input [ 9:0] inv_asid ,
input [18:0] inv_vpn
);
reg [18:0] tlb_vppn [TLBNUM-1:0];
reg tlb_e [TLBNUM-1:0];
reg [ 9:0] tlb_asid [TLBNUM-1:0];
reg tlb_g [TLBNUM-1:0];
reg [ 5:0] tlb_ps [TLBNUM-1:0];
reg [19:0] tlb_ppn0 [TLBNUM-1:0];
reg [ 1:0] tlb_plv0 [TLBNUM-1:0];
reg [ 1:0] tlb_mat0 [TLBNUM-1:0];
reg tlb_d0 [TLBNUM-1:0];
reg tlb_v0 [TLBNUM-1:0];
reg [19:0] tlb_ppn1 [TLBNUM-1:0];
reg [ 1:0] tlb_plv1 [TLBNUM-1:0];
reg [ 1:0] tlb_mat1 [TLBNUM-1:0];
reg tlb_d1 [TLBNUM-1:0];
reg tlb_v1 [TLBNUM-1:0];
reg s0_fetch_r ;
reg [18:0] s0_vppn_r ;
reg s0_odd_page_r;
reg [ 9:0] s0_asid_r ;
reg s1_fetch_r ;
reg [18:0] s1_vppn_r ;
reg s1_odd_page_r;
reg [ 9:0] s1_asid_r ;
wire [TLBNUM-1:0] match0;
wire [TLBNUM-1:0] match1;
wire [$clog2(TLBNUM)-1:0] match0_en;
wire [$clog2(TLBNUM)-1:0] match1_en;
wire [TLBNUM-1:0] s0_odd_page_buffer;
wire [TLBNUM-1:0] s1_odd_page_buffer;
always @(posedge clk) begin
s0_fetch_r <= s0_fetch;
if (s0_fetch) begin
s0_vppn_r <= s0_vppn;
s0_odd_page_r <= s0_odd_page;
s0_asid_r <= s0_asid;
end
s1_fetch_r <= s1_fetch;
if (s1_fetch) begin
s1_vppn_r <= s1_vppn;
s1_odd_page_r <= s1_odd_page;
s1_asid_r <= s1_asid;
end
end
genvar i;
generate
for (i = 0; i < TLBNUM; i = i + 1)
begin: match
assign s0_odd_page_buffer[i] = (tlb_ps[i] == 6'd12) ? s0_odd_page_r : s0_vppn_r[8];
assign match0[i] = tlb_e[i] && ((tlb_ps[i] == 6'd12) ? s0_vppn_r == tlb_vppn[i] : s0_vppn_r[18: 9] == tlb_vppn[i][18: 9]) && ((s0_asid_r == tlb_asid[i]) || tlb_g[i]);
assign s1_odd_page_buffer[i] = (tlb_ps[i] == 6'd12) ? s1_odd_page_r : s1_vppn_r[8];
assign match1[i] = tlb_e[i] && ((tlb_ps[i] == 6'd12) ? s1_vppn_r == tlb_vppn[i] : s1_vppn_r[18: 9] == tlb_vppn[i][18: 9]) && ((s1_asid_r == tlb_asid[i]) || tlb_g[i]);
end
endgenerate
encoder_32_5 en_match0 (.in({{(32-TLBNUM){1'b0}},match0}), .out(match0_en));
encoder_32_5 en_match1 (.in({{(32-TLBNUM){1'b0}},match1}), .out(match1_en));
assign s0_found = |match0;
assign s0_index = {{(5-$clog2(TLBNUM)){1'b0}},match0_en};
assign s0_ps = tlb_ps[match0_en];
assign s0_ppn = s0_odd_page_buffer[match0_en] ? tlb_ppn1[match0_en] : tlb_ppn0[match0_en];
assign s0_v = s0_odd_page_buffer[match0_en] ? tlb_v1[match0_en] : tlb_v0[match0_en] ;
assign s0_d = s0_odd_page_buffer[match0_en] ? tlb_d1[match0_en] : tlb_d0[match0_en] ;
assign s0_mat = s0_odd_page_buffer[match0_en] ? tlb_mat1[match0_en] : tlb_mat0[match0_en];
assign s0_plv = s0_odd_page_buffer[match0_en] ? tlb_plv1[match0_en] : tlb_plv0[match0_en];
assign s1_found = |match1;
assign s1_index = {{(5-$clog2(TLBNUM)){1'b0}},match1_en};
assign s1_ps = tlb_ps[match1_en];
assign s1_ppn = s1_odd_page_buffer[match1_en] ? tlb_ppn1[match1_en] : tlb_ppn0[match1_en];
assign s1_v = s1_odd_page_buffer[match1_en] ? tlb_v1[match1_en] : tlb_v0[match1_en] ;
assign s1_d = s1_odd_page_buffer[match1_en] ? tlb_d1[match1_en] : tlb_d0[match1_en] ;
assign s1_mat = s1_odd_page_buffer[match1_en] ? tlb_mat1[match1_en] : tlb_mat0[match1_en];
assign s1_plv = s1_odd_page_buffer[match1_en] ? tlb_plv1[match1_en] : tlb_plv0[match1_en];
always @(posedge clk) begin
if (we) begin
tlb_vppn [w_index] <= w_vppn;
tlb_asid [w_index] <= w_asid;
tlb_g [w_index] <= w_g;
tlb_ps [w_index] <= w_ps;
tlb_ppn0 [w_index] <= w_ppn0;
tlb_plv0 [w_index] <= w_plv0;
tlb_mat0 [w_index] <= w_mat0;
tlb_d0 [w_index] <= w_d0;
tlb_v0 [w_index] <= w_v0;
tlb_ppn1 [w_index] <= w_ppn1;
tlb_plv1 [w_index] <= w_plv1;
tlb_mat1 [w_index] <= w_mat1;
tlb_d1 [w_index] <= w_d1;
tlb_v1 [w_index] <= w_v1;
end
end
assign r_vppn = tlb_vppn [r_index];
assign r_asid = tlb_asid [r_index];
assign r_g = tlb_g [r_index];
assign r_ps = tlb_ps [r_index];
assign r_e = tlb_e [r_index];
assign r_v0 = tlb_v0 [r_index];
assign r_d0 = tlb_d0 [r_index];
assign r_mat0 = tlb_mat0 [r_index];
assign r_plv0 = tlb_plv0 [r_index];
assign r_ppn0 = tlb_ppn0 [r_index];
assign r_v1 = tlb_v1 [r_index];
assign r_d1 = tlb_d1 [r_index];
assign r_mat1 = tlb_mat1 [r_index];
assign r_plv1 = tlb_plv1 [r_index];
assign r_ppn1 = tlb_ppn1 [r_index];
//tlb entry invalid
generate
for (i = 0; i < TLBNUM; i = i + 1)
begin: invalid_tlb_entry
always @(posedge clk) begin
if (we && (w_index == i)) begin
tlb_e[i] <= w_e;
end
else if (inv_en) begin
if (inv_op == 5'd0 || inv_op == 5'd1) begin
tlb_e[i] <= 1'b0;
end
else if (inv_op == 5'd2) begin
if (tlb_g[i]) begin
tlb_e[i] <= 1'b0;
end
end
else if (inv_op == 5'd3) begin
if (!tlb_g[i]) begin
tlb_e[i] <= 1'b0;
end
end
else if (inv_op == 5'd4) begin
if (!tlb_g[i] && (tlb_asid[i] == inv_asid)) begin
tlb_e[i] <= 1'b0;
end
end
else if (inv_op == 5'd5) begin
if (!tlb_g[i] && (tlb_asid[i] == inv_asid) &&
((tlb_ps[i] == 6'd12) ? (tlb_vppn[i] == inv_vpn) : (tlb_vppn[i][18:9] == inv_vpn[18:9]))) begin
tlb_e[i] <= 1'b0;
end
end
else if (inv_op == 5'd6) begin
if ((tlb_g[i] || (tlb_asid[i] == inv_asid)) &&
((tlb_ps[i] == 6'd12) ? (tlb_vppn[i] == inv_vpn) : (tlb_vppn[i][18:9] == inv_vpn[18:9]))) begin
tlb_e[i] <= 1'b0;
end
end
end
end
end
endgenerate
endmodule

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module decoder_2_4(
input [ 1:0] in,
output [ 3:0] out
);
genvar i;
generate for (i=0; i<4; i=i+1) begin : gen_for_dec_2_4
assign out[i] = (in == i);
end endgenerate
endmodule
module encoder_4_2(
input [3:0] in,
output [1:0] out
);
assign out = {2{in[0]}} & 2'd0 |
{2{in[1]}} & 2'd1 |
{2{in[2]}} & 2'd2 |
{2{in[3]}} & 2'd3 ;
endmodule
module decoder_4_16(
input [ 3:0] in,
output [15:0] out
);
genvar i;
generate for (i=0; i<16; i=i+1) begin : gen_for_dec_4_16
assign out[i] = (in == i);
end endgenerate
endmodule
module encoder_16_4(
input [15:0] in,
output [ 3:0] out
);
wire [1:0] out_0, out_1, out_2, out_3;
encoder_4_2 one (.in(in[ 3: 0]), .out(out_0));
encoder_4_2 two (.in(in[ 7: 4]), .out(out_1));
encoder_4_2 thr (.in(in[11: 8]), .out(out_2));
encoder_4_2 fou (.in(in[15:12]), .out(out_3));
assign out = {4{|in[ 3: 0]}} & {2'd0, out_0} |
{4{|in[ 7: 4]}} & {2'd1, out_1} |
{4{|in[11: 8]}} & {2'd2, out_2} |
{4{|in[15:12]}} & {2'd3, out_3} ;
endmodule
module decoder_5_32(
input [ 4:0] in,
output [31:0] out
);
genvar i;
generate for (i=0; i<32; i=i+1) begin : gen_for_dec_5_32
assign out[i] = (in == i);
end endgenerate
endmodule
module encoder_32_5(
input [31:0] in,
output [ 4:0] out
);
wire [3:0] out_0, out_1;
encoder_16_4 one (.in(in[15: 0]), .out(out_0));
encoder_16_4 two (.in(in[31:16]), .out(out_1));
assign out = {5{|in[15: 0]}} & {1'd0, out_0} |
{5{|in[31:16]}} & {1'd1, out_1} ;
endmodule
module decoder_6_64(
input [ 5:0] in,
output [63:0] out
);
genvar i;
generate
for (i=0; i<64; i=i+1)
begin : gen_for_dec_6_64 //bug7
assign out[i] = (in == i);
end
endgenerate
endmodule
module one_valid_n #(
parameter n = 16
)(
input [n-1:0] in,
output [n-1:0] out,
output nozero
);
wire [n-1:0] one_in;
assign one_in[0] = in[0];
genvar i;
generate
for (i=1; i<n; i=i+1)
begin: sel_one
assign one_in[i] = in[i] && ~|in[i-1:0];
end
endgenerate
assign out = one_in;
assign nozero = |out;
endmodule
module one_valid_16 (
input [15:0] in,
output [ 3:0] out_en
);
wire [15:0] one_in;
assign one_in[0] = in[0];
genvar i;
generate
for (i=1; i<16; i=i+1)
begin: sel_one
assign one_in[i] = in[i] && ~|in[i-1:0];
end
endgenerate
encoder_16_4 coder (.in(one_in), .out(out_en));
endmodule
module one_valid_32 (
input [31:0] in,
output [ 4:0] out_en
);
wire [31:0] one_in;
assign one_in[0] = in[0];
genvar i;
generate
for (i=1; i<32; i=i+1)
begin: sel_one
assign one_in[i] = in[i] && ~|in[i-1:0];
end
endgenerate
encoder_32_5 coder (.in(one_in), .out(out_en));
endmodule

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`include "mycpu.h"
`include "csr.h"
module wb_stage(
input clk ,
input reset ,
//allowin
output ws_allowin ,
//from ms
input ms_to_ws_valid ,
input [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus ,
//to rf: for write back
output [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus ,
//to ds
output ws_to_ds_valid ,
//exception
output [31:0] csr_era ,
output [ 8:0] csr_esubcode ,
output [ 5:0] csr_ecode ,
output excp_flush ,
output ertn_flush ,
output refetch_flush ,
output icacop_flush ,
output csr_wr_en ,
output [13:0] wr_csr_addr ,
output [31:0] wr_csr_data ,
output va_error ,
output [31:0] bad_va ,
output excp_tlbrefill ,
output excp_tlb ,
output [18:0] excp_tlb_vppn ,
//idle
output idle_flush ,
//llbit
output ws_llbit_set ,
output ws_llbit ,
output ws_lladdr_set ,
output [27:0] ws_lladdr ,
//tlb ins
output tlb_inst_stall ,
output tlbsrch_en ,
output tlbsrch_found ,
output [ 4:0] tlbsrch_index ,
output tlbfill_en ,
output tlbwr_en ,
output tlbrd_en ,
output invtlb_en ,
output [ 9:0] invtlb_asid ,
output [18:0] invtlb_vpn ,
output [ 4:0] invtlb_op ,
//to perf_counter
output real_valid ,
output real_br_inst ,
output real_icache_miss ,
output real_dcache_miss ,
output real_mem_inst ,
output real_br_pre ,
output real_br_pre_error ,
//debug
output debug_ws_valid ,
input debug_break_point ,
//trace debug interface
output [31:0] debug_wb_pc ,
output [ 3:0] debug_wb_rf_wen ,
output [ 4:0] debug_wb_rf_wnum ,
output [31:0] debug_wb_rf_wdata ,
output [31:0] debug_wb_inst
// difftest
`ifdef DIFFTEST_EN
,
output ws_valid_diff ,
output ws_cnt_inst_diff ,
output [63:0] ws_timer_64_diff ,
output [ 7:0] ws_inst_ld_en_diff ,
output [31:0] ws_ld_paddr_diff ,
output [31:0] ws_ld_vaddr_diff ,
output [ 7:0] ws_inst_st_en_diff ,
output [31:0] ws_st_paddr_diff ,
output [31:0] ws_st_vaddr_diff ,
output [31:0] ws_st_data_diff ,
output ws_csr_rstat_en_diff ,
output [31:0] ws_csr_data_diff
`endif
);
reg ws_valid;
wire ws_ready_go;
wire flush_sign;
reg [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus_r;
wire ws_gr_we;
wire ws_excp;
wire [15:0] ws_excp_num;
wire ws_ertn;
wire [ 4:0] ws_dest;
wire [31:0] ws_final_result;
wire [31:0] ws_pc;
wire [31:0] ws_csr_result;
wire [13:0] ws_csr_idx;
wire ws_csr_we;
wire ws_ll_w;
wire ws_sc_w;
wire [31:0] ws_error_va;
wire ws_tlbsrch;
wire ws_tlbfill;
wire ws_tlbwr;
wire ws_tlbrd;
wire ws_refetch;
wire ws_invtlb;
wire ws_icacop_op_en;
wire ws_br_inst;
wire ws_icache_miss;
wire ws_access_mem;
wire ws_dcache_miss;
wire ws_br_pre;
wire ws_br_pre_error;
wire ws_idle;
wire [31:0] ws_paddr;
wire ws_data_uc;
// difftest
wire [31:0] ws_inst ;
wire ws_cnt_inst ;
wire [63:0] ws_timer_64 ;
wire [ 7:0] ws_inst_ld_en ;
wire [31:0] ws_ld_paddr ;
wire [31:0] ws_ld_vaddr ;
wire [ 7:0] ws_inst_st_en ;
wire [31:0] ws_st_data ;
wire ws_csr_rstat_en ;
wire [31:0] ws_csr_data ;
assign {ws_csr_data , //492:461 for difftest
ws_csr_rstat_en, //460:460 for difftest
ws_st_data , //459:428 for difftest
ws_inst_st_en , //427:420 for difftest
ws_ld_vaddr , //419:388 for difftest
ws_ld_paddr , //387:356 for difftest
ws_inst_ld_en , //355:348 for difftest
ws_cnt_inst , //347:347 for difftest
ws_timer_64 , //346:283 for difftest
ws_inst , //282:251 for difftest
ws_data_uc , //250:250
ws_paddr , //249:218
ws_idle , //217:217
ws_br_pre_error, //216:216
ws_br_pre , //215:215
ws_dcache_miss , //214:214
ws_access_mem , //213:213
ws_icache_miss , //212:212
ws_br_inst , //211:211
ws_icacop_op_en, //210:210
invtlb_vpn , //209:191
invtlb_asid , //190:181
ws_invtlb , //180:180
ws_tlbrd , //179:179
ws_refetch , //178:178
ws_tlbfill , //177:177
ws_tlbwr , //176:176
tlbsrch_index , //175:171
tlbsrch_found , //170:170
ws_tlbsrch , //169:169
ws_error_va , //168:137
ws_sc_w , //136:136
ws_ll_w , //135:135
ws_excp_num , //134:119
ws_csr_we , //118:118
ws_csr_idx , //117:104
ws_csr_result , //103:72
ws_ertn , //71:71
ws_excp , //70:70
ws_gr_we , //69:69
ws_dest , //68:64
ws_final_result, //63:32
ws_pc //31:0
} = ms_to_ws_bus_r;
assign ws_to_ds_valid = ws_valid;
assign flush_sign = excp_flush || ertn_flush || refetch_flush || icacop_flush || idle_flush;
wire rf_we;
wire [4 :0] rf_waddr;
wire [31:0] rf_wdata;
assign ws_to_rf_bus = {rf_we , //37:37
rf_waddr, //36:32
rf_wdata //31:0
};
assign ws_ready_go = ~debug_break_point;
assign ws_allowin = !ws_valid || ws_ready_go;
always @(posedge clk) begin
if (reset || flush_sign) begin
ws_valid <= 1'b0;
end
else if (ws_allowin) begin
ws_valid <= ms_to_ws_valid;
end
if (ms_to_ws_valid && ws_allowin) begin
ms_to_ws_bus_r <= ms_to_ws_bus;
end
end
assign real_br_inst = ws_br_inst && real_valid;
assign real_icache_miss = ws_icache_miss && real_valid;
assign real_dcache_miss = ws_dcache_miss && real_valid;
assign real_mem_inst = ws_access_mem && real_valid;
assign real_br_pre = ws_br_pre && real_valid;
assign real_br_pre_error = ws_br_pre_error && real_valid;
assign real_valid = ws_valid & ~ws_excp; //ws valid and no exception
assign rf_we = ws_gr_we & real_valid;
assign rf_waddr = ws_dest;
assign rf_wdata = ws_final_result;
assign excp_flush = ws_excp & ws_valid;
assign ertn_flush = ws_ertn & real_valid;
assign refetch_flush = (ws_csr_we || ((ws_ll_w || ws_sc_w) && !ws_excp) || ws_refetch) && ws_valid;
assign csr_era = ws_pc;
assign csr_wr_en = ws_csr_we && real_valid;
assign wr_csr_addr = ws_csr_idx;
assign wr_csr_data = ws_csr_result;
assign icacop_flush = ws_icacop_op_en && ws_valid;
assign idle_flush = ws_idle && real_valid;
assign tlb_inst_stall = (ws_tlbsrch || ws_tlbrd) && ws_valid;
//tlb ins
assign {tlbsrch_en ,
tlbwr_en ,
tlbfill_en ,
tlbrd_en ,
invtlb_en } = {ws_tlbsrch ,
ws_tlbwr ,
ws_tlbfill ,
ws_tlbrd ,
ws_invtlb } & {5{real_valid}};
//llbit
assign ws_llbit_set = (ws_ll_w | ws_sc_w) & real_valid;
assign ws_llbit = ((ws_ll_w&&!ws_data_uc) & 1'b1) | (ws_sc_w & 1'b0);
assign ws_lladdr_set = ws_ll_w && !ws_data_uc && real_valid;
assign ws_lladdr = ws_paddr[31:4];
/*
excp_num[0] int
[1] adef
[2] tlbr |inst tlb exceptions
[3] pif |
[4] ppi |
[5] syscall
[6] brk
[7] ine
[8] ipe
[9] ale
[10] <null>
[11] tlbr |
[12] pme |data tlb exceptions
[13] ppi |
[14] pis |
[15] pil |
*/
//exception have piority, onle one exception is valid
assign {csr_ecode,
va_error,
bad_va,
csr_esubcode,
excp_tlbrefill,
excp_tlb,
excp_tlb_vppn} = ws_excp_num[ 0] ? {`ECODE_INT , 1'b0 , 32'b0 , 9'b0 , 1'b0 , 1'b0 , 19'b0 } :
ws_excp_num[ 1] ? {`ECODE_ADEF, ws_valid, ws_pc , `ESUBCODE_ADEF, 1'b0 , 1'b0 , 19'b0 } :
ws_excp_num[ 2] ? {`ECODE_TLBR, ws_valid, ws_pc , 9'b0 , ws_valid, ws_valid, ws_pc[31:13] } :
ws_excp_num[ 3] ? {`ECODE_PIF , ws_valid, ws_pc , 9'b0 , 1'b0 , ws_valid, ws_pc[31:13] } :
ws_excp_num[ 4] ? {`ECODE_PPI , ws_valid, ws_pc , 9'b0 , 1'b0 , ws_valid, ws_pc[31:13] } :
ws_excp_num[ 5] ? {`ECODE_SYS , 1'b0 , 32'b0 , 9'b0 , 1'b0 , 1'b0 , 19'b0 } :
ws_excp_num[ 6] ? {`ECODE_BRK , 1'b0 , 32'b0 , 9'b0 , 1'b0 , 1'b0 , 19'b0 } :
ws_excp_num[ 7] ? {`ECODE_INE , 1'b0 , 32'b0 , 9'b0 , 1'b0 , 1'b0 , 19'b0 } :
ws_excp_num[ 8] ? {`ECODE_IPE , 1'b0 , 32'b0 , 9'b0 , 1'b0 , 1'b0 , 19'b0 } : //close ipe excp now
ws_excp_num[ 9] ? {`ECODE_ALE , ws_valid, ws_error_va, 9'b0 , 1'b0 , 1'b0 , 19'b0 } :
ws_excp_num[11] ? {`ECODE_TLBR, ws_valid, ws_error_va, 9'b0 , ws_valid, ws_valid, ws_error_va[31:13]} :
ws_excp_num[12] ? {`ECODE_PME , ws_valid, ws_error_va, 9'b0 , 1'b0 , ws_valid, ws_error_va[31:13]} :
ws_excp_num[13] ? {`ECODE_PPI , ws_valid, ws_error_va, 9'b0 , 1'b0 , ws_valid, ws_error_va[31:13]} :
ws_excp_num[14] ? {`ECODE_PIS , ws_valid, ws_error_va, 9'b0 , 1'b0 , ws_valid, ws_error_va[31:13]} :
ws_excp_num[15] ? {`ECODE_PIL , ws_valid, ws_error_va, 9'b0 , 1'b0 , ws_valid, ws_error_va[31:13]} :
69'b0;
//invtlb ins
assign invtlb_op = ws_dest;
// debug info generate
assign debug_wb_pc = ws_pc;
assign debug_wb_rf_wen = {4{rf_we}};
assign debug_wb_rf_wnum = ws_dest;
assign debug_wb_rf_wdata = ws_final_result;
assign debug_wb_inst = ws_inst;
assign debug_ws_valid = ws_valid;
`ifdef DIFFTEST_EN
assign ws_valid_diff = real_valid ;
assign ws_timer_64_diff = ws_timer_64 ;
assign ws_cnt_inst_diff = ws_cnt_inst ;
assign ws_inst_ld_en_diff = ws_inst_ld_en ;
assign ws_ld_paddr_diff = ws_ld_paddr ;
assign ws_ld_vaddr_diff = ws_ld_vaddr ;
assign ws_inst_st_en_diff = ws_inst_st_en ;
assign ws_st_paddr_diff = ws_ld_paddr_diff ;
assign ws_st_vaddr_diff = ws_ld_vaddr_diff ;
assign ws_st_data_diff = ws_st_data ;
assign ws_csr_rstat_en_diff = ws_csr_rstat_en ;
assign ws_csr_data_diff = ws_csr_data ;
`endif
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
module axi_wrap_ram_dp #(
parameter Init_File = "none"
)
(
input aclk,
input aresetn,
//ar
input [4 :0] axi_arid ,
input [31:0] axi_araddr ,
input [7 :0] axi_arlen ,
input [2 :0] axi_arsize ,
input [1 :0] axi_arburst,
input [1 :0] axi_arlock ,
input [3 :0] axi_arcache,
input [2 :0] axi_arprot ,
input axi_arvalid,
output axi_arready,
//r
output [4 :0] axi_rid ,
output [31:0] axi_rdata ,
output [1 :0] axi_rresp ,
output axi_rlast ,
output axi_rvalid ,
input axi_rready ,
//aw
input [4 :0] axi_awid ,
input [31:0] axi_awaddr ,
input [7 :0] axi_awlen ,
input [2 :0] axi_awsize ,
input [1 :0] axi_awburst,
input [1 :0] axi_awlock ,
input [3 :0] axi_awcache,
input [2 :0] axi_awprot ,
input axi_awvalid,
output axi_awready,
//w
input [31:0] axi_wdata ,
input [3 :0] axi_wstrb ,
input axi_wlast ,
input axi_wvalid ,
output axi_wready ,
//b
output [4 :0] axi_bid ,
output [1 :0] axi_bresp ,
output axi_bvalid ,
input axi_bready
);
//ram axi
//ar
wire [4 :0] ram_arid ;
wire [31:0] ram_araddr ;
wire [7 :0] ram_arlen ;
wire [2 :0] ram_arsize ;
wire [1 :0] ram_arburst;
wire [1 :0] ram_arlock ;
wire [3 :0] ram_arcache;
wire [2 :0] ram_arprot ;
wire ram_arvalid;
wire ram_arready;
//r
wire [4 :0] ram_rid ;
wire [31:0] ram_rdata ;
wire [1 :0] ram_rresp ;
wire ram_rlast ;
wire ram_rvalid ;
wire ram_rready ;
//aw
wire [4 :0] ram_awid ;
wire [31:0] ram_awaddr ;
wire [7 :0] ram_awlen ;
wire [2 :0] ram_awsize ;
wire [1 :0] ram_awburst;
wire [1 :0] ram_awlock ;
wire [3 :0] ram_awcache;
wire [2 :0] ram_awprot ;
wire ram_awvalid;
wire ram_awready;
//w
wire [31:0] ram_wdata ;
wire [3 :0] ram_wstrb ;
wire ram_wlast ;
wire ram_wvalid ;
wire ram_wready ;
//b
wire [4 :0] ram_bid ;
wire [1 :0] ram_bresp ;
wire ram_bvalid ;
wire ram_bready ;
//sram signal
wire [31:0] fpga_sram_raddr;
wire [31:0] fpga_sram_rdata;
wire fpga_sram_ren;
wire [31:0] fpga_sram_waddr;
wire [31:0] fpga_sram_wdata;
wire [3:0] fpga_sram_wen;
//ar
assign ram_arid = axi_arid ;
assign ram_araddr = axi_araddr ;
assign ram_arlen = axi_arlen ;
assign ram_arsize = axi_arsize ;
assign ram_arburst = axi_arburst;
assign ram_arlock = axi_arlock ;
assign ram_arcache = axi_arcache;
assign ram_arprot = axi_arprot ;
assign ram_arvalid = axi_arvalid;
assign axi_arready = ram_arready;
//r
assign axi_rid = axi_rvalid ? ram_rid : 5'd0 ;
assign axi_rdata = axi_rvalid ? ram_rdata : 32'd0 ;
assign axi_rresp = axi_rvalid ? ram_rresp : 2'd0 ;
assign axi_rlast = axi_rvalid ? ram_rlast : 1'd0 ;
assign axi_rvalid = ram_rvalid;
assign ram_rready = axi_rready;
//aw
assign ram_awid = axi_awid ;
assign ram_awaddr = axi_awaddr ;
assign ram_awlen = axi_awlen ;
assign ram_awsize = axi_awsize ;
assign ram_awburst = axi_awburst;
assign ram_awlock = axi_awlock ;
assign ram_awcache = axi_awcache;
assign ram_awprot = axi_awprot ;
assign ram_awvalid = axi_awvalid;
assign axi_awready = ram_awready;
//w
assign ram_wdata = axi_wdata ;
assign ram_wstrb = axi_wstrb ;
assign ram_wlast = axi_wlast ;
assign ram_wvalid = axi_wvalid ;
assign axi_wready = ram_wready ;
//b
assign axi_bid = axi_bvalid ? ram_bid : 5'd0 ;
assign axi_bresp = axi_bvalid ? ram_bresp : 2'd0 ;
assign axi_bvalid = ram_bvalid ;
assign ram_bready = axi_bready ;
axi2sram_dp #(
.BUS_WIDTH ( 32 ),
.DATA_WIDTH ( 32 ),
.CPU_WIDTH ( 32 ))
u_axi2sram_dp (
.aclk ( aclk ),
.aresetn ( aresetn ),
.m_araddr ( ram_araddr ),
.m_arburst ( ram_arburst ),
.m_arcache ( 4'h0 ),
.m_arid ( ram_arid ),
.m_arlen ( ram_arlen ),
.m_arlock ( 2'h0 ),
.m_arprot ( 3'h0 ),
.m_arsize ( ram_arsize ),
.m_arvalid ( ram_arvalid ),
.m_arready ( ram_arready ),
.m_rready ( ram_rready ),
.m_rdata ( ram_rdata ),
.m_rid ( ram_rid ),
.m_rlast ( ram_rlast ),
.m_rresp ( ram_rresp ),
.m_rvalid ( ram_rvalid ),
.m_awaddr ( ram_awaddr ),
.m_awburst ( ram_awburst ),
.m_awcache ( 4'h0 ),
.m_awid ( ram_awid ),
.m_awlen ( ram_awlen ),
.m_awlock ( 2'h0 ),
.m_awprot ( 3'h0 ),
.m_awsize ( ram_awsize ),
.m_awvalid ( ram_awvalid ),
.m_awready ( ram_awready ),
.m_wdata ( ram_wdata ),
.m_wlast ( ram_wlast ),
.m_wstrb ( ram_wstrb ),
.m_wvalid ( ram_wvalid ),
.m_wready ( ram_wready ),
.m_bready ( ram_bready ),
.m_bid ( ram_bid ),
.m_bresp ( ram_bresp ),
.m_bvalid ( ram_bvalid ),
.ram_raddr ( fpga_sram_raddr ),
.ram_ren ( fpga_sram_ren ),
.ram_waddr ( fpga_sram_waddr ),
.ram_wdata ( fpga_sram_wdata ),
.ram_wen ( fpga_sram_wen ),
.ram_rdata ( fpga_sram_rdata )
);
//1MByte SRAM
fpga_sram_dp #(
.AW ( 18 ),
.Init_File (Init_File)
)u_fpga_sram (
.CLK ( aclk ),
.ram_raddr ( fpga_sram_raddr[19:2] ),
.ram_ren ( fpga_sram_ren ),
.ram_rdata ( fpga_sram_rdata ),
.ram_waddr ( fpga_sram_waddr[19:2] ),
.ram_wdata ( fpga_sram_wdata ),
.ram_wen ( fpga_sram_wen )
);
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
module axi_wrap_ram_sp #(
parameter Init_File = "none"
)
(
input aclk,
input aresetn,
//ar
input [4 :0] axi_arid ,
input [31:0] axi_araddr ,
input [7 :0] axi_arlen ,
input [2 :0] axi_arsize ,
input [1 :0] axi_arburst,
input [1 :0] axi_arlock ,
input [3 :0] axi_arcache,
input [2 :0] axi_arprot ,
input axi_arvalid,
output axi_arready,
//r
output [4 :0] axi_rid ,
output [31:0] axi_rdata ,
output [1 :0] axi_rresp ,
output axi_rlast ,
output axi_rvalid ,
input axi_rready ,
//aw
input [4 :0] axi_awid ,
input [31:0] axi_awaddr ,
input [7 :0] axi_awlen ,
input [2 :0] axi_awsize ,
input [1 :0] axi_awburst,
input [1 :0] axi_awlock ,
input [3 :0] axi_awcache,
input [2 :0] axi_awprot ,
input axi_awvalid,
output axi_awready,
//w
input [31:0] axi_wdata ,
input [3 :0] axi_wstrb ,
input axi_wlast ,
input axi_wvalid ,
output axi_wready ,
//b
output [4 :0] axi_bid ,
output [1 :0] axi_bresp ,
output axi_bvalid ,
input axi_bready
);
//ram axi
//ar
wire [4 :0] ram_arid ;
wire [31:0] ram_araddr ;
wire [7 :0] ram_arlen ;
wire [2 :0] ram_arsize ;
wire [1 :0] ram_arburst;
wire [1 :0] ram_arlock ;
wire [3 :0] ram_arcache;
wire [2 :0] ram_arprot ;
wire ram_arvalid;
wire ram_arready;
//r
wire [4 :0] ram_rid ;
wire [31:0] ram_rdata ;
wire [1 :0] ram_rresp ;
wire ram_rlast ;
wire ram_rvalid ;
wire ram_rready ;
//aw
wire [4 :0] ram_awid ;
wire [31:0] ram_awaddr ;
wire [7 :0] ram_awlen ;
wire [2 :0] ram_awsize ;
wire [1 :0] ram_awburst;
wire [1 :0] ram_awlock ;
wire [3 :0] ram_awcache;
wire [2 :0] ram_awprot ;
wire ram_awvalid;
wire ram_awready;
//w
wire [31:0] ram_wdata ;
wire [3 :0] ram_wstrb ;
wire ram_wlast ;
wire ram_wvalid ;
wire ram_wready ;
//b
wire [4 :0] ram_bid ;
wire [1 :0] ram_bresp ;
wire ram_bvalid ;
wire ram_bready ;
//sram signal
wire [31:0] fpga_sram_addr;
wire fpga_sram_cs;
wire fpga_sram_we;
wire [3:0] fpga_sram_be;
wire [31:0] fpga_sram_wdata;
wire [31:0] fpga_sram_rdata;
//ar
assign ram_arid = axi_arid ;
assign ram_araddr = axi_araddr ;
assign ram_arlen = axi_arlen ;
assign ram_arsize = axi_arsize ;
assign ram_arburst = axi_arburst;
assign ram_arlock = axi_arlock ;
assign ram_arcache = axi_arcache;
assign ram_arprot = axi_arprot ;
assign ram_arvalid = axi_arvalid;
assign axi_arready = ram_arready;
//r
assign axi_rid = axi_rvalid ? ram_rid : 5'd0 ;
assign axi_rdata = axi_rvalid ? ram_rdata : 32'd0 ;
assign axi_rresp = axi_rvalid ? ram_rresp : 2'd0 ;
assign axi_rlast = axi_rvalid ? ram_rlast : 1'd0 ;
assign axi_rvalid = ram_rvalid;
assign ram_rready = axi_rready;
//aw
assign ram_awid = axi_awid ;
assign ram_awaddr = axi_awaddr ;
assign ram_awlen = axi_awlen ;
assign ram_awsize = axi_awsize ;
assign ram_awburst = axi_awburst;
assign ram_awlock = axi_awlock ;
assign ram_awcache = axi_awcache;
assign ram_awprot = axi_awprot ;
assign ram_awvalid = axi_awvalid;
assign axi_awready = ram_awready;
//w
assign ram_wdata = axi_wdata ;
assign ram_wstrb = axi_wstrb ;
assign ram_wlast = axi_wlast ;
assign ram_wvalid = axi_wvalid ;
assign axi_wready = ram_wready ;
//b
assign axi_bid = axi_bvalid ? ram_bid : 5'd0 ;
assign axi_bresp = axi_bvalid ? ram_bresp : 2'd0 ;
assign axi_bvalid = ram_bvalid ;
assign ram_bready = axi_bready ;
axi2sram_sp #(
.AXI_ID_WIDTH ( 5 ),
.AXI_ADDR_WIDTH ( 32 ),
.AXI_DATA_WIDTH ( 32 ))
u_axi_sram_sp (
.clk ( aclk ),
.resetn ( aresetn ),
.s_araddr ( ram_araddr ),
.s_arburst ( ram_arburst ),
.s_arcache ( ram_arcache ),
.s_arid ( ram_arid ),
.s_arlen ( ram_arlen ),
.s_arlock ( ram_arlock ),
.s_arprot ( ram_arprot ),
.s_arsize ( ram_arsize ),
.s_arvalid ( ram_arvalid ),
.s_awaddr ( ram_awaddr ),
.s_awburst ( ram_awburst ),
.s_awcache ( ram_awcache ),
.s_awid ( ram_awid ),
.s_awlen ( ram_awlen ),
.s_awlock ( ram_awlock ),
.s_awprot ( ram_awprot ),
.s_awsize ( ram_awsize ),
.s_awvalid ( ram_awvalid ),
.s_bready ( ram_bready ),
.s_rready ( ram_rready ),
.s_wdata ( ram_wdata ),
.s_wlast ( ram_wlast ),
.s_wstrb ( ram_wstrb ),
.s_wvalid ( ram_wvalid ),
.s_arready ( ram_arready ),
.s_awready ( ram_awready ),
.s_bid ( ram_bid ),
.s_bresp ( ram_bresp ),
.s_bvalid ( ram_bvalid ),
.s_rdata ( ram_rdata ),
.s_rid ( ram_rid ),
.s_rlast ( ram_rlast ),
.s_rresp ( ram_rresp ),
.s_rvalid ( ram_rvalid ),
.s_wready ( ram_wready ),
.req_o ( fpga_sram_cs ),
.we_o ( fpga_sram_we ),
.addr_o ( fpga_sram_addr ),
.be_o ( fpga_sram_be ),
.data_o ( fpga_sram_wdata ),
.data_i ( fpga_sram_rdata )
);
wire [3:0] fpga_sram_wren = {4{fpga_sram_we}} & fpga_sram_be;
//1MByte SRAM
fpga_sram_sp #(
.AW ( 18 ),
.Init_File (Init_File)
)u_fpga_sram (
.CLK ( aclk ),
.ADDR ( fpga_sram_addr[19:2] ),
.WDATA ( fpga_sram_wdata ),
.WREN ( fpga_sram_wren ),
.CS ( fpga_sram_cs ),
.RDATA ( fpga_sram_rdata )
);
endmodule

259
rtl/ip/ram_wrap/axi_wrap_ram_sp_external.v Normal file
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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
module axi_wrap_ram_sp_external (
input aclk,
input aresetn,
//ar
input [4 :0] axi_arid ,
input [31:0] axi_araddr ,
input [7 :0] axi_arlen ,
input [2 :0] axi_arsize ,
input [1 :0] axi_arburst,
input axi_arlock ,
input [3 :0] axi_arcache,
input [2 :0] axi_arprot ,
input axi_arvalid,
output axi_arready,
//r
output [4 :0] axi_rid ,
output [31:0] axi_rdata ,
output [1 :0] axi_rresp ,
output axi_rlast ,
output axi_rvalid ,
input axi_rready ,
//aw
input [4 :0] axi_awid ,
input [31:0] axi_awaddr ,
input [7 :0] axi_awlen ,
input [2 :0] axi_awsize ,
input [1 :0] axi_awburst,
input axi_awlock ,
input [3 :0] axi_awcache,
input [2 :0] axi_awprot ,
input axi_awvalid,
output axi_awready,
//w
input [31:0] axi_wdata ,
input [3 :0] axi_wstrb ,
input axi_wlast ,
input axi_wvalid ,
output axi_wready ,
//b
output [4 :0] axi_bid ,
output [1 :0] axi_bresp ,
output axi_bvalid ,
input axi_bready ,
//BaseRAM信号
inout [31:0] base_ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享
output [19:0] base_ram_addr, //BaseRAM地址
output [ 3:0] base_ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0
output base_ram_ce_n, //BaseRAM片选，低有效
output base_ram_oe_n, //BaseRAM读使能，低有效
output base_ram_we_n, //BaseRAM写使能，低有效
//ExtRAM信号
inout [31:0] ext_ram_data, //ExtRAM数据
output [19:0] ext_ram_addr, //ExtRAM地址
output [ 3:0] ext_ram_be_n, //ExtRAM字节使能，低有效。如果不使用字节使能，请保持为0
output ext_ram_ce_n, //ExtRAM片选，低有效
output ext_ram_oe_n, //ExtRAM读使能，低有效
output ext_ram_we_n //ExtRAM写使能，低有效
);
//ram axi
//ar
wire [4 :0] ram_arid ;
wire [31:0] ram_araddr ;
wire [7 :0] ram_arlen ;
wire [2 :0] ram_arsize ;
wire [1 :0] ram_arburst;
wire ram_arlock ;
wire [3 :0] ram_arcache;
wire [2 :0] ram_arprot ;
wire ram_arvalid;
wire ram_arready;
//r
wire [4 :0] ram_rid ;
wire [31:0] ram_rdata ;
wire [1 :0] ram_rresp ;
wire ram_rlast ;
wire ram_rvalid ;
wire ram_rready ;
//aw
wire [4 :0] ram_awid ;
wire [31:0] ram_awaddr ;
wire [7 :0] ram_awlen ;
wire [2 :0] ram_awsize ;
wire [1 :0] ram_awburst;
wire ram_awlock ;
wire [3 :0] ram_awcache;
wire [2 :0] ram_awprot ;
wire ram_awvalid;
wire ram_awready;
//w
wire [31:0] ram_wdata ;
wire [3 :0] ram_wstrb ;
wire ram_wlast ;
wire ram_wvalid ;
wire ram_wready ;
//b
wire [4 :0] ram_bid ;
wire [1 :0] ram_bresp ;
wire ram_bvalid ;
wire ram_bready ;
//sram signal
wire [31:0] soc_sram_addr;
wire soc_sram_cs;
wire soc_sram_we;
wire [3:0] soc_sram_be;
wire [31:0] soc_sram_wdata;
wire [31:0] soc_sram_rdata;
//ar
assign ram_arid = axi_arid ;
assign ram_araddr = axi_araddr ;
assign ram_arlen = axi_arlen ;
assign ram_arsize = axi_arsize ;
assign ram_arburst = axi_arburst;
assign ram_arlock = axi_arlock ;
assign ram_arcache = axi_arcache;
assign ram_arprot = axi_arprot ;
assign ram_arvalid = axi_arvalid;
assign axi_arready = ram_arready;
//r
assign axi_rid = axi_rvalid ? ram_rid : 5'd0 ;
assign axi_rdata = axi_rvalid ? ram_rdata : 32'd0 ;
assign axi_rresp = axi_rvalid ? ram_rresp : 2'd0 ;
assign axi_rlast = axi_rvalid ? ram_rlast : 1'd0 ;
assign axi_rvalid = ram_rvalid;
assign ram_rready = axi_rready;
//aw
assign ram_awid = axi_awid ;
assign ram_awaddr = axi_awaddr ;
assign ram_awlen = axi_awlen ;
assign ram_awsize = axi_awsize ;
assign ram_awburst = axi_awburst;
assign ram_awlock = axi_awlock ;
assign ram_awcache = axi_awcache;
assign ram_awprot = axi_awprot ;
assign ram_awvalid = axi_awvalid;
assign axi_awready = ram_awready;
//w
assign ram_wdata = axi_wdata ;
assign ram_wstrb = axi_wstrb ;
assign ram_wlast = axi_wlast ;
assign ram_wvalid = axi_wvalid ;
assign axi_wready = ram_wready ;
//b
assign axi_bid = axi_bvalid ? ram_bid : 5'd0 ;
assign axi_bresp = axi_bvalid ? ram_bresp : 2'd0 ;
assign axi_bvalid = ram_bvalid ;
assign ram_bready = axi_bready ;
axi2sram_sp_external #(
.AXI_ID_WIDTH ( 5 ),
.AXI_ADDR_WIDTH ( 32 ),
.AXI_DATA_WIDTH ( 32 ))
u_axi_sram_sp (
.clk ( aclk ),
.resetn ( aresetn ),
.s_araddr ( ram_araddr ),
.s_arburst ( ram_arburst ),
.s_arcache ( ram_arcache ),
.s_arid ( ram_arid ),
.s_arlen ( ram_arlen ),
.s_arlock ( ram_arlock ),
.s_arprot ( ram_arprot ),
.s_arsize ( ram_arsize ),
.s_arvalid ( ram_arvalid ),
.s_awaddr ( ram_awaddr ),
.s_awburst ( ram_awburst ),
.s_awcache ( ram_awcache ),
.s_awid ( ram_awid ),
.s_awlen ( ram_awlen ),
.s_awlock ( ram_awlock ),
.s_awprot ( ram_awprot ),
.s_awsize ( ram_awsize ),
.s_awvalid ( ram_awvalid ),
.s_bready ( ram_bready ),
.s_rready ( ram_rready ),
.s_wdata ( ram_wdata ),
.s_wlast ( ram_wlast ),
.s_wstrb ( ram_wstrb ),
.s_wvalid ( ram_wvalid ),
.s_arready ( ram_arready ),
.s_awready ( ram_awready ),
.s_bid ( ram_bid ),
.s_bresp ( ram_bresp ),
.s_bvalid ( ram_bvalid ),
.s_rdata ( ram_rdata ),
.s_rid ( ram_rid ),
.s_rlast ( ram_rlast ),
.s_rresp ( ram_rresp ),
.s_rvalid ( ram_rvalid ),
.s_wready ( ram_wready ),
.req_o ( soc_sram_cs ),
.we_o ( soc_sram_we ),
.addr_o ( soc_sram_addr ),
.be_o ( soc_sram_be ),
.data_o ( soc_sram_wdata ),
.data_i ( soc_sram_rdata )
);
wire choose_sram = soc_sram_addr[22];//1:ExtRAM 0:BaseRAM
wire [3:0] be_out = soc_sram_we ? soc_sram_be : 4'b1111;
assign base_ram_addr = soc_sram_addr[21:2];
assign base_ram_be_n = choose_sram ? 4'b1111 : ~be_out;
assign base_ram_ce_n = ~(soc_sram_cs & (~choose_sram));
assign base_ram_oe_n = soc_sram_we | choose_sram;
assign base_ram_we_n = ~(soc_sram_we & (~choose_sram));
assign base_ram_data = ((~choose_sram) & soc_sram_cs & soc_sram_we) ? soc_sram_wdata : 32'hzzzzzzzz;
assign ext_ram_addr = soc_sram_addr[21:2];
assign ext_ram_be_n = choose_sram ? ~be_out : 4'b1111;
assign ext_ram_ce_n = choose_sram ? ~soc_sram_cs : 1'b1;
assign ext_ram_oe_n = choose_sram ? soc_sram_we : 1'b1;
assign ext_ram_we_n = choose_sram ? ~soc_sram_we : 1'b1;
assign ext_ram_data = ((choose_sram) & soc_sram_cs & soc_sram_we) ? soc_sram_wdata : 32'hzzzzzzzz;
assign soc_sram_rdata = choose_sram ? ext_ram_data : base_ram_data;
endmodule

85
rtl/ip/ram_wrap/cache_sram.v Normal file
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`include "config.h"
module data_bank_sram (
input [ 7:0] addra ,
input clka ,
input [31:0] dina ,
output [31:0] douta ,
input ena ,
input [ 3:0] wea
);
`ifdef USE_CACHE
localparam V_STYLE = "block";
localparam P_STYLE = (V_STYLE == "ultra") ? "uram" :
(V_STYLE == "distributed") ? "select_ram" :
"block_ram";
(*ram_style = V_STYLE*) reg [31:0] mem_reg [255:0]/*synthesis syn_ramstyle=P_STYLE*/;
reg [31:0] output_buffer;
always @(posedge clka) begin
if (ena) begin
if (wea) begin
if (wea[0]) begin
mem_reg[addra][ 7: 0] <= dina[ 7: 0];
end
if (wea[1]) begin
mem_reg[addra][15: 8] <= dina[15: 8];
end
if (wea[2]) begin
mem_reg[addra][23:16] <= dina[23:16];
end
if (wea[3]) begin
mem_reg[addra][31:24] <= dina[31:24];
end
end
else begin
output_buffer <= mem_reg[addra];
end
end
end
assign douta = output_buffer;
`else
assign douta = 32'h0;
`endif
endmodule
module tagv_sram (
input [ 7:0] addra ,
input clka ,
input [20:0] dina ,
output [20:0] douta ,
input ena ,
input wea
);
`ifdef USE_CACHE
localparam V_STYLE = "block";
localparam P_STYLE = (V_STYLE == "ultra") ? "uram" :
(V_STYLE == "distributed") ? "select_ram" :
"block_ram";
(*ram_style = V_STYLE*) reg [20:0] mem_reg [255:0]/*synthesis syn_ramstyle=P_STYLE*/;
reg [20:0] output_buffer;
always @(posedge clka) begin
if (ena) begin
if (wea) begin
mem_reg[addra] <= dina;
end
else begin
output_buffer <= mem_reg[addra];
end
end
end
assign douta = output_buffer;
`else
assign douta = 21'h0;
`endif
endmodule

53
rtl/ip/ram_wrap/fpga_sram_dp.v Normal file
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module fpga_sram_dp #(
parameter AW = 16,
parameter Init_File = "none"
)
(
input wire CLK,
input wire [AW-1:0] ram_raddr,
output wire [31 :0] ram_rdata,
input wire ram_ren ,
input wire [AW-1:0] ram_waddr,
input wire [31 :0] ram_wdata,
input wire [3 :0] ram_wen
);
localparam AWT = ((1<<(AW-0))-1);
localparam V_STYLE = "block";
localparam P_STYLE = (V_STYLE == "ultra") ? "uram" :
(V_STYLE == "distributed") ? "select_ram" :
"block_ram";
(*ram_style = V_STYLE*)reg [31:0] BRAM [AWT:0]/*synthesis syn_ramstyle=P_STYLE*/;
initial begin
if(Init_File != "none") begin
$readmemb(Init_File,BRAM);
end
end
reg [AW-1:0] addr_q1;
always@(posedge CLK) begin
if(ram_wen[0]) BRAM[ram_waddr][7:0] <= ram_wdata[7:0];
end
always@(posedge CLK) begin
if(ram_wen[1]) BRAM[ram_waddr][15:8] <= ram_wdata[15:8];
end
always@(posedge CLK) begin
if(ram_wen[2]) BRAM[ram_waddr][23:16] <= ram_wdata[23:16];
end
always@(posedge CLK) begin
if(ram_wen[3]) BRAM[ram_waddr][31:24] <= ram_wdata[31:24];
end
always @ (posedge CLK) begin
if(ram_ren)
addr_q1 <= ram_raddr;
end
assign ram_rdata = BRAM[addr_q1];
endmodule

54
rtl/ip/ram_wrap/fpga_sram_sp.v Normal file
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module fpga_sram_sp #(
parameter AW = 16,
parameter Init_File = "none"
)
(
input wire CLK,
input wire [AW-1:0] ADDR,
input wire [31:0] WDATA,
input wire [3:0] WREN,
input wire CS,
output wire [31:0] RDATA
);
localparam AWT = ((1<<(AW-0))-1);
localparam V_STYLE = "block";
localparam P_STYLE = (V_STYLE == "ultra") ? "uram" :
(V_STYLE == "distributed") ? "select_ram" :
"block_ram";
(*ram_style = V_STYLE*)reg [31:0] BRAM [AWT:0]/*synthesis syn_ramstyle=P_STYLE*/;
initial begin
if(Init_File != "none") begin
$readmemb(Init_File,BRAM);
end
end
reg [AW-1:0] addr_q1;
wire [3:0] write_enable;
assign write_enable[3:0] = WREN[3:0] & {4{CS}};
always@(posedge CLK) begin
if(write_enable[0]) BRAM[ADDR][7:0] <= WDATA[7:0];
end
always@(posedge CLK) begin
if(write_enable[1]) BRAM[ADDR][15:8] <= WDATA[15:8];
end
always@(posedge CLK) begin
if(write_enable[2]) BRAM[ADDR][23:16] <= WDATA[23:16];
end
always@(posedge CLK) begin
if(write_enable[3]) BRAM[ADDR][31:24] <= WDATA[31:24];
end
always @ (posedge CLK) begin
if(CS && !(|WREN))
addr_q1 <= ADDR[AW-1:0];
end
assign RDATA = BRAM[addr_q1];
endmodule

18
rtl/ip/rst_sync/rst_sync.v Normal file
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module rst_sync(
input clk,
input rst_n_in,
output rst_n_out
);
reg [1:0] delay;
always @(posedge clk or negedge rst_n_in) begin
if(~rst_n_in) begin
delay <= 2'b00;
end
else begin
delay <= {delay[0],1'b1};
end
end
assign rst_n_out = delay[1];
endmodule

1684
rtl/soc_top.v Normal file
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10004
sdk/axi_ram.mif Normal file
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BIN
sdk/hello_world.bin Executable file
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82
sdk/software/bsp/common.mk Normal file
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LA32R_GCC := loongarch32r-linux-gnusf-gcc
LA32R_AS := loongarch32r-linux-gnusf-as
LA32R_GXX := loongarch32r-linux-gnusf-g++
LA32R_OBJDUMP := loongarch32r-linux-gnusf-objdump
LA32R_GDB := loongarch32r-linux-gnusf-gdb
LA32R_AR := loongarch32r-linux-gnusf-ar
LA32R_OBJCOPY := loongarch32r-linux-gnusf-objcopy
LA32R_READELF := loongarch32r-linux-gnusf-readelf
.PHONY: all
all: $(TARGET)
#TODO: 根据Cache实际情况调整has_cache宏，以在start.S中生成正确的Cache初始化代码
CFLAGS += -Dhas_cache=1
CFLAGS += -Dcache_index_depth=0x100 -Dcache_offset_width=0x4 -Dcache_way=2
CFLAGS += -ffunction-sections -fdata-sections
CFLAGS += -nostartfiles -nostdlib -nostdinc -static -fno-builtin
CFLAGS += -DCLOCKS_PER_SEC=CORE_CLOCKS_PER_SEC -D_CLOCKS_PER_SEC_=CORE_CLOCKS_PER_SEC
CFLAGS += -DUSE_CPU_CLOCK_COUNT
#若使用 newlib , 将下面的 -lsemihost 替换为 -lgloss
LDFLAGS += -T $(LINKER_SCRIPT) \
-Wl,--gc-sections -Wl,--check-sections \
-lc -lm -lg -lsemihost -lgcc -L$(PICOLIBC_DIR)/lib
LINKER_SCRIPT := $(COMMON_DIR)/env/script.lds
ASM_SRCS += $(COMMON_DIR)/env/start.S
ifeq ($(TARGET), RTThread_Nano)
else
ASM_SRCS += $(COMMON_DIR)/env/trap_handler.S
endif
C_SRCS += $(COMMON_DIR)/drivers/confreg_time.c
C_SRCS += $(COMMON_DIR)/drivers/core_time.c
C_SRCS += $(COMMON_DIR)/drivers/common_func.c
C_SRCS += $(COMMON_DIR)/drivers/dvi.c \
$(COMMON_DIR)/drivers/led.c \
$(COMMON_DIR)/drivers/seg7.c
INCLUDES += -I./ \
-I$(COMMON_DIR)/include \
-I$(PICOLIBC_DIR)/include \
-I$(GCC_DIR)/lib/gcc/loongarch32r-linux-gnusf/8.3.0/include \
-I$(GCC_DIR)/lib/gcc/loongarch32r-linux-gnusf/8.3.0/include-fixed
ASM_OBJS := $(ASM_SRCS:.S=.o)
C_OBJS := $(C_SRCS:.c=.o)
LINK_OBJS += $(ASM_OBJS) $(C_OBJS)
LINK_DEPS += $(LINKER_SCRIPT)
CLEAN_OBJS += $(OBJDIR)/$(TARGET).elf $(LINK_OBJS) $(OBJDIR)/$(TARGET).s $(OBJDIR)/$(TARGET).bin $(OBJDIR)/convert $(OBJDIR)/axi_ram.coe $(OBJDIR)/axi_ram.mif $(OBJDIR)/rom.vlog
$(TARGET): $(LINK_OBJS) $(LINK_DEPS) convert Makefile
$(LA32R_GCC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $(OBJDIR)/$@.elf $(LDFLAGS)
$(LA32R_OBJCOPY) -O binary $(OBJDIR)/$@.elf $(OBJDIR)/$@.bin
$(LA32R_OBJDUMP) --disassemble-all -S $(OBJDIR)/$@.elf > $(OBJDIR)/$@.s
$(OBJDIR)/convert $@.bin $(OBJDIR)/
cp ./$(OBJDIR)/axi_ram.mif $(COMMON_DIR)/../../
cp ./$(OBJDIR)/axi_ram.mif $(LA32RSOC_WINDOWS_HOME)/sdk
cp ./$(OBJDIR)/$@.bin $(COMMON_DIR)/../../
cp ./$(OBJDIR)/$@.bin $(LA32RSOC_WINDOWS_HOME)/sdk
rm -f $(LINK_OBJS)
rm -f $(OBJDIR)/convert
$(ASM_OBJS): %.o: %.S
$(LA32R_GCC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
$(C_OBJS): %.o: %.c
$(LA32R_GCC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
convert: $(COMMON_DIR)/env/convert.c
mkdir -p $(OBJDIR)/
gcc -o $(OBJDIR)/convert $(COMMON_DIR)/env/convert.c
.PHONY: clean
clean:
rm -f $(CLEAN_OBJS)

20
sdk/software/bsp/drivers/common_func.c Normal file
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#include "common_func.h"
void RegWrite(unsigned int addr,unsigned int var)
{
*((volatile unsigned int *)(addr)) = var;
}
unsigned int RegRead(unsigned int addr)
{
return (*((volatile unsigned int *)(addr)));
}
//memcpy 32bit
void SaveMemory(unsigned int *DestAddr, unsigned int *SrcAddr, unsigned int Size)
{
unsigned int i;
for (i = 0; i < Size; i += 1)
*(U32*)(DestAddr + i) = SrcAddr[i];
}

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