From fbc993b8464757abc3b135d171cb3f24c1fcc33f Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Tue, 23 Jun 2026 01:22:45 +0800 Subject: [PATCH] Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC --- .gitignore | 53 + doc/2026集创赛龙芯中科杯初赛.pdf | Bin 0 -> 2206412 bytes doc/matmul_ip_spec.md | 137 + fpga/check_dsp.py | 59 + fpga/create_project.tcl | 24 + fpga/generate_bit.tcl | 26 + fpga/run-linter.py | 288 + fpga/run_impl.tcl | 32 + rtl/config.h | 94 + rtl/ip/APB_UART/URT/raminfr.v | 62 + rtl/ip/APB_UART/URT/uart_defines.h | 119 + rtl/ip/APB_UART/URT/uart_receiver.v | 288 + rtl/ip/APB_UART/URT/uart_regs.v | 711 ++ rtl/ip/APB_UART/URT/uart_rfifo.v | 193 + rtl/ip/APB_UART/URT/uart_sync_flops.v | 76 + rtl/ip/APB_UART/URT/uart_tfifo.v | 129 + rtl/ip/APB_UART/URT/uart_top.v | 107 + rtl/ip/APB_UART/URT/uart_transmitter.v | 281 + rtl/ip/APB_UART/apb_mux2.v | 206 + rtl/ip/APB_UART/axi2apb.v | 674 ++ rtl/ip/APB_UART/axi_uart_controller.v | 356 + rtl/ip/Bus_interconnects/AxiCrossbar_2x8.v | 6331 ++++++++++ rtl/ip/Bus_interconnects/Axi_CDC.v | 1608 +++ rtl/ip/Bus_interconnects/axi2sram_dp.v | 520 + rtl/ip/Bus_interconnects/axi2sram_sp.v | 350 + .../Bus_interconnects/axi2sram_sp_external.v | 380 + rtl/ip/DVI/axi_dvi.v | 258 + rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v | 224 + rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl | 170 + rtl/ip/PLL_2019_2/clk_pll_stub.v | 23 + rtl/ip/PLL_2019_2/clk_pll_stub.vhdl | 32 + rtl/ip/axi_axil_adapter/axi_axil_adapter.v | 223 + rtl/ip/axi_axil_adapter/axi_axil_adapter_rd.v | 507 + rtl/ip/axi_axil_adapter/axi_axil_adapter_wr.v | 570 + rtl/ip/bram0/my_bram0.v | 47 + rtl/ip/cdma/snix_async_fifo.sv | 112 + rtl/ip/cdma/snix_axi_cdma.sv | 219 + rtl/ip/cdma/snix_axi_cdma_csr.sv | 192 + rtl/ip/cdma/snix_axi_mm2mm.sv | 455 + rtl/ip/cdma/snix_axil_cdma_mux.sv | 381 + rtl/ip/cdma/snix_axis_fifo.sv | 113 + rtl/ip/cdma/snix_register_slice.sv | 79 + rtl/ip/cdma/snix_sync_fifo.sv | 130 + rtl/ip/confreg/confreg.v | 421 + rtl/ip/confreg/digitaltube_controller.v | 101 + rtl/ip/confreg/int_ctrl.v | 61 + rtl/ip/confreg/key_debounce.v | 40 + rtl/ip/fft/Butterfly.v | 32 + rtl/ip/fft/DelayBuffer.v | 32 + rtl/ip/fft/FFT1024_32B.v | 89 + rtl/ip/fft/Multiply.v | 35 + rtl/ip/fft/SdfUnit.v | 277 + rtl/ip/fft/Twiddle1024_32B.v | 1064 ++ rtl/ip/fft/axi_fft_wrapper.v | 383 + rtl/ip/matmul/matmul_axi_slave.v | 303 + rtl/ip/open-la500/LICENSE | 127 + rtl/ip/open-la500/README.md | 7 + rtl/ip/open-la500/addr_trans.v | 250 + rtl/ip/open-la500/alu.v | 109 + rtl/ip/open-la500/axi_bridge.v | 317 + rtl/ip/open-la500/btb.v | 238 + rtl/ip/open-la500/csr.h | 73 + rtl/ip/open-la500/csr.v | 856 ++ rtl/ip/open-la500/dcache.v | 651 + rtl/ip/open-la500/div.v | 99 + rtl/ip/open-la500/doc/lacc接口.md | 135 + rtl/ip/open-la500/doc/picture/lacc_inst.png | Bin 0 -> 2925 bytes rtl/ip/open-la500/doc/picture/lacc_read.png | Bin 0 -> 103244 bytes rtl/ip/open-la500/doc/picture/lacc_write.png | Bin 0 -> 90264 bytes rtl/ip/open-la500/doc/picture/框图.svg | 4 + rtl/ip/open-la500/doc/分支预测.md | 94 + rtl/ip/open-la500/doc/前言.md | 17 + rtl/ip/open-la500/doc/设计概述.md | 63 + rtl/ip/open-la500/exe_stage.v | 439 + rtl/ip/open-la500/icache.v | 410 + rtl/ip/open-la500/id_stage.v | 1005 ++ rtl/ip/open-la500/if_stage.v | 357 + rtl/ip/open-la500/lacc_core.v | 53 + rtl/ip/open-la500/lacc_demo.v | 166 + rtl/ip/open-la500/mem_stage.v | 368 + rtl/ip/open-la500/mul.v | 197 + rtl/ip/open-la500/mycpu.h | 32 + rtl/ip/open-la500/mycpu_top.v | 1296 ++ rtl/ip/open-la500/perf_counter.v | 57 + rtl/ip/open-la500/regfile.v | 39 + rtl/ip/open-la500/tlb_entry.v | 235 + rtl/ip/open-la500/tools.v | 167 + rtl/ip/open-la500/wb_stage.v | 324 + rtl/ip/ram_wrap/axi_wrap_ram_dp.v | 247 + rtl/ip/ram_wrap/axi_wrap_ram_sp.v | 244 + rtl/ip/ram_wrap/axi_wrap_ram_sp_external.v | 259 + rtl/ip/ram_wrap/cache_sram.v | 85 + rtl/ip/ram_wrap/fpga_sram_dp.v | 53 + rtl/ip/ram_wrap/fpga_sram_sp.v | 54 + rtl/ip/rst_sync/rst_sync.v | 18 + rtl/soc_top.v | 1684 +++ sdk/axi_ram.mif | 10004 ++++++++++++++++ sdk/hello_world.bin | Bin 0 -> 40012 bytes sdk/software/bsp/common.mk | 82 + sdk/software/bsp/drivers/common_func.c | 20 + sdk/software/bsp/drivers/confreg_time.c | 63 + sdk/software/bsp/drivers/core_time.c | 30 + sdk/software/bsp/drivers/dvi.c | 27 + sdk/software/bsp/drivers/led.c | 28 + sdk/software/bsp/drivers/seg7.c | 17 + sdk/software/bsp/env/convert.c | 103 + sdk/software/bsp/env/script.lds | 182 + sdk/software/bsp/env/start.S | 182 + sdk/software/bsp/env/trap_handler.S | 188 + sdk/software/bsp/include/common_func.h | 99 + sdk/software/bsp/include/confreg_time.h | 22 + sdk/software/bsp/include/core_time.h | 8 + sdk/software/bsp/include/dvi.h | 21 + sdk/software/bsp/include/handler.h | 31 + sdk/software/bsp/include/led.h | 14 + sdk/software/bsp/include/regdef.h | 104 + sdk/software/bsp/include/seg7.h | 17 + sdk/software/bsp/include/uart_print.h | 12 + sdk/software/examples/.gitignore | 56 + sdk/software/examples/asm/Makefile | 11 + sdk/software/examples/asm/user-sample.c | 0 .../examples/c_prg/inner_product/Makefile | 14 + .../c_prg/inner_product/inner_product.c | 446 + .../examples/c_prg/lookup_table/Makefile | 14 + .../c_prg/lookup_table/lookup_table.c | 315 + .../examples/c_prg/loop_induction/Makefile | 14 + .../c_prg/loop_induction/loop_induction.c | 131 + sdk/software/examples/c_prg/memcmp/Makefile | 14 + sdk/software/examples/c_prg/memcmp/memcmp.c | 177 + .../examples/c_prg/minmax_sequence/Makefile | 14 + .../c_prg/minmax_sequence/minmax_sequence.c | 1509 +++ .../examples/c_prg/product_sequence/Makefile | 14 + .../c_prg/product_sequence/product_sequence.c | 169 + sdk/software/examples/coremark/LICENSE.md | 100 + sdk/software/examples/coremark/Makefile | 25 + sdk/software/examples/coremark/README.md | 398 + .../examples/coremark/core_list_join.c | 599 + sdk/software/examples/coremark/core_main.c | 422 + sdk/software/examples/coremark/core_matrix.c | 359 + sdk/software/examples/coremark/core_portme.c | 53 + sdk/software/examples/coremark/core_portme.h | 64 + sdk/software/examples/coremark/core_state.c | 330 + sdk/software/examples/coremark/core_util.c | 249 + sdk/software/examples/coremark/coremark.h | 173 + sdk/software/examples/dhrystone/Makefile | 16 + sdk/software/examples/dhrystone/README.md | 10 + sdk/software/examples/dhrystone/dhry.h | 420 + sdk/software/examples/dhrystone/dhry_1.c | 392 + sdk/software/examples/dhrystone/dhry_2.c | 192 + sdk/software/examples/fireye/A0/A0.c | 35 + sdk/software/examples/fireye/A0/Makefile | 14 + sdk/software/examples/fireye/B2/B2.c | 61 + sdk/software/examples/fireye/B2/Makefile | 14 + sdk/software/examples/fireye/C0/C0.c | 74 + sdk/software/examples/fireye/C0/Makefile | 14 + sdk/software/examples/fireye/D1/D1.c | 76 + sdk/software/examples/fireye/D1/Makefile | 14 + sdk/software/examples/fireye/I2/I2.c | 122 + sdk/software/examples/fireye/I2/Makefile | 14 + sdk/software/examples/hello_world/Makefile | 11 + sdk/software/examples/hello_world/main.c | 36 + sdk/software/examples/int_test/Makefile | 11 + sdk/software/examples/int_test/main.c | 96 + sdk/software/examples/lenet/AccelConvFuncs.c | 179 + sdk/software/examples/lenet/AccelConvFuncs.h | 14 + sdk/software/examples/lenet/Accelop.h | 154 + sdk/software/examples/lenet/ConvFuncs.c | 97 + sdk/software/examples/lenet/ConvFuncs.h | 16 + sdk/software/examples/lenet/Makefile | 11 + sdk/software/examples/lenet/main.c | 160 + sdk/software/examples/lenet/test_image.h | 23 + sdk/software/examples/lenet/weights.h | 62 + sdk/software/examples/matmul_test/Makefile | 11 + sdk/software/examples/matmul_test/main.c | 253 + sdk/software/examples/pinball_game/Makefile | 11 + sdk/software/examples/pinball_game/main.c | 249 + sdk/toolchains | 1 + sim/matmul_flow_tb.v | 396 + sim/mycpu_tb.v | 230 + sim/sram.v | 52 + tools/generate_matmul_testdata.py | 164 + 181 files changed, 51135 insertions(+) create mode 100644 .gitignore create mode 100644 doc/2026集创赛龙芯中科杯初赛.pdf create mode 100644 doc/matmul_ip_spec.md create mode 100644 fpga/check_dsp.py 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100644 sdk/software/examples/lenet/Makefile create mode 100644 sdk/software/examples/lenet/main.c create mode 100644 sdk/software/examples/lenet/test_image.h create mode 100644 sdk/software/examples/lenet/weights.h create mode 100644 sdk/software/examples/matmul_test/Makefile create mode 100644 sdk/software/examples/matmul_test/main.c create mode 100644 sdk/software/examples/pinball_game/Makefile create mode 100644 sdk/software/examples/pinball_game/main.c create mode 120000 sdk/toolchains create mode 100644 sim/matmul_flow_tb.v create mode 100644 sim/mycpu_tb.v create mode 100644 sim/sram.v create mode 100644 tools/generate_matmul_testdata.py diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..bca1624 --- /dev/null +++ b/.gitignore @@ -0,0 +1,53 @@ +# ======================================== +# Vivado project & IP files (not tracked) +# ======================================== +fpga/.Xil/ +fpga/project/ +*.xpr +*.xci +*.xcix +*.xdc +*.bd +*.dcp +*.jou +*.log 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    pc

    pc
    nextpc
    nextpc
    +4
    +4
    btb
    btb
    pre_pc
    pre_pc
    icache
    icache
    tlb
    tlb
    tag&v ram
    tag&v ram
    inst ram
    inst ram
    fetch_pc
    fetch_pc
    vpn
    vpn
    index
    index
    tagcmp
    tagcmp
    ppn
    ppn
    inst
    inst
    decoder
    decoder
    regfile
    regfile
    dcache
    dcache
    tlb
    tlb
    tag&v ram
    tag&v ram
    data ram
    data ram
    data_addr
    data_addr
    vpn
    vpn
    index
    index
    tagcmp
    tagcmp
    ppn
    ppn
    div
    div
    mul
    mul
    data
    data
    btb_op
    btb_op
    axi_bridge
    axi_bridge
    inst_miss
    inst_miss
    data_miss
    data_miss
    AXI
    AXI

    inst

    inst

    op

    op

    rf

    data

    rf...
    es_forward
    es_forward
    alu
    alu

    alu

    res

    alu...

    op

    op
    final
    res
    fina...
    ms_forward
    ms_forward
    right_pc
    right_pc
    csr
    csr
    rd
    rd
    flush_pc
    flush_pc
    fs_stage
    fs_stage
    ds_stage
    ds_stage
    es_stage
    es_stage
    mem_stage
    mem_sta...
    wb_stage
    wb_stage    Text is not SVG - cannot display     \ No newline at end of file diff --git a/rtl/ip/open-la500/doc/分支预测.md b/rtl/ip/open-la500/doc/分支预测.md new file mode 100644 index 0000000..20d7d0b --- /dev/null +++ b/rtl/ip/open-la500/doc/分支预测.md @@ -0,0 +1,94 @@ +# 分支预测 +分支预测即根据分支历史，提前预测指令跳转方向及跳转目标。分支预测器种类繁多，例如BTB（Branch Target Buffer）、BHT（Branch History Table）、RAS（Return Address Stack）等，但适用于五级流水的其实并不多。如设计概述中所介绍的，五级流水中，pfs级发出取指请求，fs级取回指令，ds级开始译码，并明确跳转指令的所有信息。也就表示分支预测只有一拍的空间可以利用，且无预译码，可依据的信息只有pc，跳转方向及跳转目标都只能靠猜。适用的实际上仅有BTB。不过对于较为特殊的jirl指令，即寄存器跳转，若直接采用BTB的机制，会使得命中率极低。因此，在BTB的基础上进行改造，由CAM表记录jirl指令的pc，并由RAS机制预测其跳转目标。 + +---- + +接下来介绍分支预测器的具体实现，分为两点：分支预测器的内部实现；分支预测器同流水线的交互。 +## 分支预测器设计 +分支预测器的逻辑可以分为两个部分，由PC进行预测跳转目标及跳转方向的预测部分；根据指令译码结果与分支预测器预测结果的比较，对分支预测器历史信息进行修正的修正部分。 +### 预测部分 +首先来看模块的接口。 +- fetch_pc：取指pc +- fetch_en：取指使能 +- ret_en：预测结果使能 +- ret_pc：预测跳转目标 +- taken：预测跳转方向 +- ret_index：指示当前预测结果的对应项，用于修正 + +btb表有32项，包含四个内容： +- btb_pc：30位，用于和取指pc匹配 +- btb_target：30位，存放跳转目标 +- btb_counter：2位，由最高位指示跳转方向 +- btb_valid：1位，当前项是否有效 + +对于jirl指令的预测逻辑由两部分组成，16项的CAM表以及8项的RAS。 +CAM表包含两个内容： +- ras_pc：30位，用于和取指pc匹配 +- ras_valid：1位，当前项是否有效 + +RAS简单来说就是一个栈。存储30位的跳转目标，由ras_ptr指示栈顶。 + +明确表项内容后，来看预测逻辑。fetch_en以及fetch_pc进入分支预测器时，首先缓存一拍。单看分支预测器，缓存插在什么位置其实都可以，只要有一拍的延迟即可，但考虑到赋值nextpc即fetch_pc的路径非常长，因此将缓存插在靠前的位置。缓存后的信号为fetch_en_r及fetch_pc_r，将其与两个CAM的PC部分，btb_pc和ras_pc进行匹配。该项有效且pc匹配则表示命中。命中项记录在btb_match_rd和ras_match_rd中。 + +两个表中有一项命中，则置起ret_en。若命中在btb CAM表中，ret_pc取对应项的btb_target即可，若命中在ras CAM表中，则取ras栈顶的跳转目标。理论上btb_match_rd和ras_match_rd为one-hot且只会命中在一个表中，因此不必使用优先级逻辑。ret_index同理，而taken在btb_match时，需要看对应项btb_counter最高位，而ras_match时，直接置为1。预测阶段不会对分支预测器的历史信息进行任何修正。 + +### 修正部分 +在ds译码级，汇总分支预测信息以及译码得到的正确分支跳转信息。 +预测信息同上： +- ds_btb_target +- ds_btb_index +- ds_btb_taken +- ds_btb_en + +正确的分支跳转信息如下： +- br_to_btb：表示当前指令是否为分支预测器所覆盖的跳转指令，当前结构的分支预测器覆盖所有跳转指令。 +- br_taken：跳转方向 +- br_target：跳转目标 + +译码级根据以上信息，稍加分析并传递至分支预测器，传递信息包括： +- operate_en：分支预测器修正操作使能。注意该信号需要在ds_ready_go、es_allowin和ds_valid为1时置起且无例外。只有ds当拍允许流动至下一级时才能发出修正操作。对于ds_ready_go，因为流水线中指令寄存器的依赖有可能导致ds阻塞，阻塞时指令所得到的寄存器值是错误的，即译码得到的分支跳转信息也是错误的。而es_allowin的介入使其操作使能仅维持一拍，避免重复操作。 +- operate_pc：修正操作针对的分支指令的pc +- operate_index：修正操作针对的CAM表项 +- pop_ras：为jirl指令时置起 +- push_ras：为bl指令时置起 +- add_entry：当前指令为分支指令但预测器未进行预测时置起。这里与上了一个额外条件br_taken，因为当pc在分支预测器中未命中时，顺序指令，也算是预测为untaken。br_taken不为1时，并不需要在预测器中建项 +- delete_entry：当前指令不为分支指令但预测器进行预测时置起。这种情况出现的概率极低，只有在自修改代码中，可以不用考虑 +- pre_error：当前指令为分支指令且预测器进行预测，但跳转目标不一致时置起 +- pre_right：当前指令为分支指令且预测器进行预测，且跳转目标一致时置起 +- target_error：当前指令为分支指令且预测器进行预测，且跳转目标一致，但跳转目标不一致时置起 +- right_orien：正确的跳转方向 +- right_target：正确的跳转目标 + +分支预测器会根据以上信息进行修正，首先由pop_ras即是否为jirl指令区分当前操作的是BTB部分还是RAS部分，针对BTB部分，操作类型包括： +- 建项：add_entry置起时。使能指定项，并填入operate_pc和right_target，以及初始化btb_counter为2'b10。对于填入项即index的选择，若BTB CAM表中还留有未使能项，则选择其中一项。若所有项都有效则选择btb_counter为2'b00的一项，即大概率不跳转的预测项，因为未在btb中命中的pc即预测为不跳转，两者效果是相同的，只不过该pc若下一次为跳转，则会重新建项，相当于将其btb_counter由2'b00直接转为2'b10，很有可能导致下一次的预测出错。但是这种情况出现的概率肯定比替换掉其他btb_counter的值导致下一次预测错的概率低。若所有项都有效且btb_counter都不为2'b00，则随机选择一项。 +- 修正跳转目标：target_error置起时。重新填入right_target，并初始化btb_counter为2'b10。 +- 修正跳转方向：pre_error或者pre_right置起时。根据right_orien调整btb_counter，若正确的分支方向为taken则累加，若为untaken则递减。 + +针对RAS部分，操作类型包括： +- 建项：add_entry置起时。使能指定项，填入operate_pc即可。相当于预测pc的分支类型。index的选择同BTB部分。 +- 进栈：当push_ras置起且当前RAS非满时，存入当前pc的下一条指令，并将指针上移。即当前为bl函数跳转指令，其返回地址为bl的下一条指令。RAS指针指向的是空项。 +- 出栈：当pop_ras置起且当前RAS非空时，指针直接下移一项即可。 + +## 分支预测器与流水线交互逻辑 + +首先简单介绍取指逻辑，该部分内容会在后续逐步展开。来看几个关键信号，inst_valid指示当前取指pc是否有效，该信号直接送往icache等待接收。inst_valid主要看fs_allowin信号，即pfs指令允许向后流动时，其取指pc即为有效，能够避免相同pc取指请求的重复发出。nextpc即为取指pc，当前仅关注其最为常规的pc来源seq_pc，顺序取指pc。当inst_valid为1时，并不代表取指请求即刻便能发出，还需要等待icache空闲，由inst_addr_ok表示（取指请求的其他去向tlb、btb不需要等待）。当inst_valid && inst_addr_ok为1，取指请求发出，pfs_ready_go置起，pfs向fs流动。 +fetch_en和fetch_pc发送至分支预测器后，下一拍得到预测结果（btb_en/btb_ret_pc/btb_taken）。当btb_en && btb_taken为1时，fetch_btb_target置起，分支跳转，将nextpc纠正至btb_ret_pc。这段逻辑中有一点需要注意，分支预测器返回的结果仅维持一拍，但pfs并不一定能够向后流动，因此需要缓存分支预测器的返回结果，避免信息丢失。分支预测器的返回结果缓存在btb_lock_buffer中，由btb_lock_en指示缓存是否有效。缓存条件即为分支返回结果且pfs无法向后流动（btb_en && !pfs_ready_go），缓存释放条件为下一次取指重新发起。而nextpc的维护以及fs向ds传递分支预测结果时都将采用btb_ret_pc_t、btb_ret_pc_t、btb_ret_pc_t、btb_ret_pc_t信号，由分支预测器返回信息和缓存的信息相或得到，两者同一时刻仅有一个有效。 +译码级，根据译码和分支预测的结果，能够知道下一条指令取指的方向是否正确。取指级有两个方面的工作需要完成：修正分支预测的历史信息；若预测错误则需纠正取指方向。此处主要讲述第二方面的内容。若译码级检测到分支预测错误，则会置起btb_pre_error_flush信号，由该信号修正取指方向，该工作可继续细分为两个内容 +- 取消掉下一条进入译码级的指令，及错误预测导致错误取指的指令 +两种情况需要考虑： + - 当该分支指令向后流动的那一拍，即（btb_pre_error_flush && es_allowin）为1时，若下一拍下一条指令紧接着进入译码级，则可直接取消。不过可以用更粗犷的方法，即下一拍的ds_valid直接为0，无需识别是否有指令进入。 + - 同样的条件，若下一拍无指令进入，即当拍fs_to_ds_valid为0，则置起branch_slot_cancel触发器。该触发器为1时，会等待下一条指令进入，当检测fs_to_ds_valid为1时，将其取消，并恢复branch_slot_cancel至0。 +- 纠正nextpc。当译码级发现分支预测错误，会将正确的跳转目标（btb_pre_error_flush_target）和使能信号（btb_pre_error_flush）通过br_bus传递至取指阶段，修正nextpc。 +需要考虑两个问题： + - 当nextpc修正信息向前传递时，pfs并不一定处于能够取指的状态，例如inst_addr_ok不为1。此时若译码级不阻塞，且pfs不将修正信息存入buffer，会导致信息丢失。 + - 译码级会记录分支预测错误，并取消掉错误预测的分支指令的下一条指令。若pfs在取完预测错误的分支指令后始终处于阻塞状态，之后直接被修正至正确的跳转方向，则会导致正确的指令被取消掉。 + + 针对上述两个问题，可在pfs中构建一个状态机解决。br_target_inst_req_state表示状态。当发现预测错误后，根据流水线状态，进入不同的状态。 + - !fs_valid && !inst_addr_ok：预测错误分支指令取出后未进行任何取指，因为fs级为空，inst_addr_ok从未置起。且当前也不处于可取指的状态。进入br_target_inst_req_wait_slot状态。 + - !inst_addr_ok && fs_valid：已有一条错误取指的指令在fs中，但pfs并不处于能够取指的状态。进入br_target_inst_req_wait_br_target状态。 + - inst_addr_ok && !fs_valid：预测错误分支指令取出后未进行任何取指，当前处于可取指的状态，但当前的指令会在译码级取消。进入br_target_inst_req_wait_br_target状态。 + + br_target_inst_req_wait_slot状态会待取指请求发出后切换至br_target_inst_req_wait_br_target状态，该状态便会将nextpc修正至存储btb_pre_error_flush_target的pc buffer（br_target_inst_req_buffer）。当取指请求再次发出后，状态切换至空状态br_target_inst_req_empty。 + + 构建状态机后，还需要注意一个问题。也许pfs处于即刻能够发出取指请求的状态。可粗略的判断fs级是否有指令，便改变next_pc同时置起inst_valid，即使当前无法取指(inst_addr_ok为0)也没有关系。 + diff --git a/rtl/ip/open-la500/doc/前言.md b/rtl/ip/open-la500/doc/前言.md new file mode 100644 index 0000000..6e49d32 --- /dev/null +++ b/rtl/ip/open-la500/doc/前言.md @@ -0,0 +1,17 @@ +# 前言 +OpenLA500（齐物）是一款实现了`龙芯架构32位精简版指令集（LoongArch32 Reduced）`的处理器核。OpenLA500的架构为经典的单发射静态五级流水，配备两路组相连的指令/数据Cache，32项全相连的tlb实现虚实地址映射，以及BTB及RAS实现分支预测。基本按照国科大体系结构实验课程逐步设计得到。FPGA运行频率为50M。 + +OpenLA500经过全面验证，已处于稳定状态。并于2023年龙芯全流程平台项目中，在SMIC 180um工艺下流片。 + +以下将从8个方面介绍OpenLA500的设计细节。 + +- [设计概述](./设计概述.md)：基于顶层框图，介绍各级流水的划分和各级流水之间的交互，以及流水线与其他模块的交互。 +- [分支预测](./分支预测.md)：BTB及RAS两个分支预测器的具体设计，以及在流水线中的工作原理。 +- [流水线的发射部分]()：流水线发射阶段（译码级）操作数准备、前递网络、阻塞控制的设计。 +- [流水线的执行部分]()：alu、mul、div运算部件在流水线中的实现。 +- [MMU]()：虚实地址映射逻辑，tlb维护。 +- [例外实现]()：流水线中例外的判断及处理。 +- [访存子系统]()：指令/数据Cache及AXI总线接口的实现。 +- [调试部分]()：UART在线调试系统与OpenLA500的交互逻辑。 + + diff --git a/rtl/ip/open-la500/doc/设计概述.md b/rtl/ip/open-la500/doc/设计概述.md new file mode 100644 index 0000000..f93b5eb --- /dev/null +++ b/rtl/ip/open-la500/doc/设计概述.md @@ -0,0 +1,63 @@ +# 设计概述 +![系统框图](./picture/框图.svg) + +系统框图展示了OpenLA500处理器核的内部结构。指令的执行始终按照取指、译码、执行、访存、写回的顺序进行。各级流水会存储指令执行的中间状态，在完成当前阶段的操作后，将结果存入下一级流水，进行下一个阶段的操作。 + +## 执行流程 + +处理器核内维护`nextpc`信号，表示取指地址。待取指开始时，`fetch_pc`会发往`icache`、`tlb`、`btb`进行不同的工作，以及存入触发器。在下一拍即`fs_stage`取指级,`btb`完成分支预测，将结果直接送往`nextpc`，更改其取指方向。以及由`fetch_pc`以及`tlb`虚实地址翻译的结果，在`icache`指令缓存中得到`inst`指令码，并存入触发器。下一级`ds_stage`译码级在拿到指令码后，便交给`decoder`进行译码。译码后可以得到具体的操作码`op`，以及寄存器号，并可借此在`regfile`寄存器堆或者`csr`控制寄存器中索引到寄存器值`rf_data`。`es_stage`执行级在得到操作码及操作数后，便可送至`alu`运算部件进行简单运算，以及送往`div`除法部件、`mul`乘法部件进行多拍较复杂的运算。此外，由`alu`可以得到访存地址，并发至`tlb`及`dcache`数据缓存完成访存请求的处理，基本同`icache`。在`mem_stage`访存级，可得到访存、乘除法的运算结果，并由`op`选择最终的运算结果`final_res`，并存入触发器。`wb_stage`写回级便会将最终运算结果写回到`regfile`及`csr`。对于`i/dcache`，若取指/访存请求缺失，便会发送请求至`axi_bridge`并通过标准的`AXI3`总线协议与外界通信。 + +--- + +流水级的各阶段需要与其他不同的模块进行交互，确认其任务是否完成。以下针对流水级及各模块进行介绍： + +## 取指阶段 + +### `pfs` +该级流水的主要功能是维护`nextpc`，也就是流水线取指的虚地址。其实从更为严谨的角度来看`pfs`并不应该单独称为一级流水，因为`nextpc`为`wire`类型，或者说`pfs`在正常的执行流程中不会缓存信号，当拍便可获得取指方向。实际上`pfs`为各级能够影响取指地址的流水级的衍生。`nextpc`的维护逻辑可以说是五级流水中最为复杂的一部分，因为`icache`并不是时刻处于就绪的状态，由`inst_addr_ok`信号指示其是否就绪。因此，对于某些特殊情况下出现的转顺即逝的信息，比如流水线刷新等，需要构建状态机缓存信息。待取指方向确认，且`icache`就绪，`pfs`会置起`fetch_en`，紧接着`btb`、`icache`、`tlb`便会接收`pfs`发出的`fetch_pc`，开始相应的操作。 + +### `btb` +分支预测器，根据`PC`直接预测其跳转地址。32项`btb`组织为`CAM`表的形式，由`PC`查询。此外，还包括一个`ras`，组织为一个8项的栈，存储函数调用过程中的返回地址。`btb`分支预测的结果会在下一拍返回，若预测正确则可消除下一拍产生于`fs`级流水的空泡，预测错误不会造成任何性能损失。 + +### `icache` +指令缓存，两路组相连的结构。`fetch_pc`进入`icache`后，首先根据由`fetch_pc`拆解而来的`index`部分，索引出两路的`cache`行。其次再根据`tag`部分与`tlb`翻译得到的物理页号是否相等判断是否有命中项。若命中，下一拍返回`inst_rdata`，若未命中，则进入`icache`处理`miss`请求的状态机，`inst_addr_ok`拉低。等待`miss`请求处理完毕后再接收新的取指请求。替换策略为随机替换。 + +### `tlb` +组织为32项`CAM`表的形式，指令和数据共用，需要两个查询端口。通过`fetch_pc`的虚页号查询是否存在命中项，命中则返回物理页号。若未命中，则会标记该指令存在`tlb`缺失例外，并进入例外处理程序。待对应`tlb`项在页表中找到并由软件填入`tlb`后，重新执行该指令。 + +### `fs` +`fs`取值级便是真正意义上的第一级流水。`fs`级接收`icache`返回的指令码`inst_rdata`，由`inst_data_ok`指示指令码是否就绪。若`icache miss`，`fs`级便会阻塞。额外需要注意一点，`tlb`的读取有一拍的延迟，因为32项的CAM表会有较长的逻辑。因此`tlb`的读取结果是在`fs`级得到，也就表示`tlb`相关的例外判断是在`fs`级完成，而取指请求是在`pfs`级发出。所以`fs`级需要具备中止上一拍`pfs`级发往`icache`的取指请求的能力，体现在`tlb_excp_cancel_req`信号中，`dcache`同理。 + +## 译码阶段 + +### `ds` +译码级，其功能便是将指令码解析为对应的操作码，并根据寄存器号，从`regfile`中取出寄存器值。不过寄存器的最新值可能还未被写入到`regfile`中，因为后续流水线中的指令正在执行，结果未获得或者未写回，而当前指令可能依赖于这些指令的结果。因此译码级与后续流水线构建了前递路径（`es_to_ds_forward_bus/ms_to_ds_forward_bus`），用于前递未写回的结果，或者通知`ds`级结果未获取，需要阻塞。此外，经过译码，已知晓该指令是否为跳转指令，以及是否跳转。也就可以识别分支预测器的预测结果是否正确，`ds`级便可通过`br_bus`对取指方向进行修正，以及更新分支预测器的历史信息。`btb`的预测包括两个方面，该`PC`是否为跳转指令；识别为跳转指令时是否跳转。`ds`级需要鉴别并对分支预测器执行特定的更新操作。 + +## 执行阶段 + +### `es` +执行级，根据译码得到的操作码，送往`alu`、`mul`、`div`进行特定类型的运算。`alu`用于处理较简单的运算，比如加减、移位运算。`mul`为华莱士树实现的乘法部件，拆为两级。`div`为常规的迭代除法部件，需要34个周期得到结果。此外，若为访存指令，执行级便可通过加减运算得到访存地址。同`pfs`等待`dcache`准备就绪，即`data_addr_ok`置起，`es`便可发出`data_fetch`以及`data_addr`，由`tlb`进行虚实地址映射以及`dcache`取回数据。不过需要注意若当前指令或者后续流水线中的指令存在例外，需要及时中止`data_fetch`的置起。 + +## 访存阶段 + +### `dcache` +数据缓存，在`icache`的基础上新增了处理写请求的能力。每个`cache`行新增一个`dirty`位，用于标识该`cache`行是否为脏，在被替换时判断是否需要写回。此外，写请求在命中的情况下，相较于读请求，需要额外的一拍将数据写入到`ram`中。这额外一拍的延迟可以通过构建写请求状态机节省。待确认写请求命中后，进入状态机，使得`dcache`可以继续接收新的请求。不过需要注意规避读写请求同时出现在单端口的`ram`上。 +### `ms` +访存级，等待`dcache`数据返回，由`data_data_ok`指示`data_rdata`是否有效。`ms`级同`fs`级，需要由`tlb_excp_cancel_req`信号取消掉上一拍`es`发往`dcache`的访存请求。写请求不同于读请求需要等待接收数据，待请求发出后，不管命不命中，可继续向后流动。 + +## 写回阶段 + +### `ws` +写回级，此时指令已执行完毕，并得到`result`，需根据执行结果修改处理器状态，包括两个方面：写通用寄存器`regfile`以及状态寄存器`csr`；根据指令触发的例外类型，修改`csr`寄存器，以及清空流水线并调整取指方向至例外入口。 + +--- +## 流水级间交互 + +最理想的情况下，同一时刻五个阶段都处于工作的状态，也就表示同一时刻在处理五条指令。此时，处理器核在通过流水线切分得到较高频率时，带宽仍然保持为1指令/拍。但在实际情况下，如前文所述，并不会如此，各级流水总是会出现阻塞的情况。因此，流水级之间需要交互，避免一级流水的操作还未完成便被上一级覆盖。 + +流水级之间的交互逻辑中，需要维护以下关键信号： + +- `stage_valid`：由触发器维护，表示当前流水级是否在处理指令。 +- `stage_ready_go`：表示流水级是否需要被阻塞。 +- `stage_allowin`：表示当前流水级是否允许上一级流水进入，该信号传递至上一级，与上一级流水交互，两种情况下该信号置起，当前流水无正在处理的指令；或者当前流水级中的指令已处理完毕且下一级流水允许进入。该信号会由最后一级流水向前传递，只要某一流水级阻塞，其`stage_allowin`拉低，同一时刻，前面所有流水级的`stage_allowin`都会拉低（假设所有流水级中都有指令在处理）。 +- `stage_to_nextstage_valid`：表示当前流水级中是否有处理完毕的指令，该信号传递至下一级，与下一级流水交互。下一级流水在收到高电平信号时，且其下一级流水的`stage_allowin`为高电平，则会在下一拍置起下一级流水的`stage_valid`，实现流水级间指令的流动。`stage_to_nextstage_bus`总线信号中传递缓存信号，会随着`stage_to_nextstage_valid`流动。 diff --git a/rtl/ip/open-la500/exe_stage.v b/rtl/ip/open-la500/exe_stage.v new file mode 100644 index 0000000..e95171a --- /dev/null +++ b/rtl/ip/open-la500/exe_stage.v @@ -0,0 +1,439 @@ +`include "mycpu.h" +`include "csr.h" + +module exe_stage( + input clk , + input reset , + //allowin + input ms_allowin , + output es_allowin , + //from ds + input ds_to_es_valid , + input [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus , + //to ms + output es_to_ms_valid , + output [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus , + //to ds forward path + output [`ES_TO_DS_FORWARD_BUS -1:0] es_to_ds_forward_bus, + output es_to_ds_valid , + //div_mul + output es_div_enable , + output es_mul_div_sign , + output [31:0] es_rj_value , + output [31:0] es_rkd_value , + input div_complete , +`ifdef HAS_LACC + output es_lacc_req, + output [`LACC_OP_WIDTH-1:0] es_lacc_command, + input lacc_req_ready, + input lacc_data_valid, + input lacc_data_read, + input [31: 0] lacc_data_addr, + input [31: 0] lacc_data_wdata, + input [1: 0] lacc_data_size, + input lacc_rsp_valid, + input [31: 0] lacc_rsp_rdat, + output [6: 0] lacc_req_imm, + output lacc_flush, + input data_data_ok, + output lacc_drsp_valid, +`endif + //exception + input excp_flush , + input ertn_flush , + input refetch_flush , + input icacop_flush , + //idle + input idle_flush , + //tlb/cache ins + output tlb_inst_stall , + //cache ins + output icacop_op_en , + output dcacop_op_en , + output [ 1:0] cacop_op_mode , + //from icache + input icache_unbusy , + //preld ins + output [ 4:0] preld_hint , + output preld_en , + // data cache interface + output data_valid , + output data_op , + output [ 2:0] data_size , + output [ 3:0] data_wstrb , + output [31:0] data_wdata , + input data_addr_ok , + //from csr + input [18:0] csr_vppn , + //to addr trans + output [31:0] data_addr , + output data_fetch , + //from ms + input ms_wr_tlbehi , + input ms_flush +); + +reg es_valid ; +wire es_ready_go ; + +wire [31:0] error_va ; + +reg [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus_r; +wire [13:0] es_alu_op ; +wire es_src1_is_pc ; +wire es_src2_is_imm ; +wire es_src2_is_4 ; +wire es_gr_we ; +wire es_store_op ; +wire [ 4:0] es_dest ; +wire [31:0] es_imm ; +wire [31:0] es_pc ; +wire [ 3:0] es_mul_div_op ; +wire [ 1:0] es_mem_size ; +wire [31:0] es_csr_data ; +wire [13:0] es_csr_idx ; +wire [31:0] es_csr_result ; +wire [31:0] csr_mask_result; +wire es_res_from_csr; +wire es_csr_we ; +wire es_csr_mask ; +wire es_excp ; +wire excp ; +wire [ 8:0] es_excp_num ; +wire [ 9:0] excp_num ; +wire es_ertn ; +wire es_mul_enable ; +wire div_stall ; +wire es_ll_w ; +wire es_sc_w ; +wire es_tlbsrch ; +wire es_tlbwr ; +wire es_tlbfill ; +wire es_tlbrd ; +wire es_refetch ; +wire es_invtlb ; +wire [ 9:0] es_invtlb_asid ; +wire [18:0] es_invtlb_vpn ; +wire es_cacop ; +wire es_preld ; +wire es_br_inst ; +wire es_icache_miss ; +wire es_idle ; + +wire es_load_op ; + +wire dep_need_stall ; +wire forward_enable ; +wire dest_zero ; + +wire excp_ale ; + +wire es_flush_sign ; +wire [ 3:0] wr_byte_en ; + +wire access_mem ; +wire es_mem_sign_exted; +wire [ 1:0] sram_addr_low2bit; + +wire tlbsrch_stall ; + +wire [31:0] pv_addr ; + +wire [ 4:0] cacop_op ; + +wire dcache_req_or_inst_en; + +wire icacop_inst ; +wire icacop_inst_stall; +wire dcacop_inst ; +wire preld_inst ; + +wire es_br_pre_error ; +wire es_br_pre ; + +// difftest +wire [31:0] es_inst ; +wire [63:0] es_timer_64 ; +wire es_cnt_inst ; +wire [ 7:0] es_inst_ld_en ; +wire [ 7:0] es_inst_st_en ; +wire es_csr_rstat_en ; + +wire [2: 0] data_size_pre; +`ifdef HAS_LACC +wire lacc_stall; +wire [3: 0] lacc_data_mask, lacc_data_byte, lacc_data_half; +wire es_lacc_req_pre; +`endif + +assign { + `ifdef HAS_LACC + es_lacc_command, + es_lacc_req_pre, + `endif + es_csr_rstat_en , //349:349 for difftest + es_inst_st_en , //348:341 for difftest + es_inst_ld_en , //340:333 for difftst + es_cnt_inst , //332:332 for difftest + es_timer_64 , //331:268 for difftest + es_inst , //236:267 for difftest + es_idle , //235:235 + es_br_pre_error , //234:234 + es_br_pre , //233:233 + es_icache_miss , //232:232 + es_br_inst , //231:231 + es_preld , //230:230 + es_cacop , //229:229 + es_mem_sign_exted, //228:228 + es_invtlb , //227:227 + es_tlbrd , //226:226 + es_refetch , //225:225 + es_tlbfill , //224:224 + es_tlbwr , //223:223 + es_tlbsrch , //222:222 + es_sc_w , //221:221 + es_ll_w , //220:220 + es_excp_num , //219:211 + es_csr_mask , //210:210 + es_csr_we , //209:209 + es_csr_idx , //208:195 + es_res_from_csr , //194:194 + es_csr_data , //193:162 + es_ertn , //161:161 + es_excp , //160:160 + es_mem_size , //159:158 + es_mul_div_op , //157:154 + es_mul_div_sign , //153:153 + es_alu_op , //152:139 + es_load_op , //138:138 + es_src1_is_pc , //137:137 + es_src2_is_imm , //136:136 + es_src2_is_4 , //135:135 + es_gr_we , //134:134 + es_store_op , //133:133 + es_dest , //132:128 + es_imm , //127:96 + es_rj_value , //95 :64 + es_rkd_value , //63 :32 + es_pc //31 :0 + } = ds_to_es_bus_r; + +wire [31:0] es_alu_src1 ; +wire [31:0] es_alu_src2 ; +wire [31:0] es_alu_result ; +wire [31:0] exe_result ; + +assign es_to_ms_bus = {es_csr_data , //424:393 for difftest + es_csr_rstat_en , //392:392 for difftest + data_wdata , //391:360 for difftest + es_inst_st_en , //359:352 for difftest + data_addr , //351:320 for difftest + es_inst_ld_en , //319:312 for difftest + es_cnt_inst , //311:311 for difftest + es_timer_64 , //310:247 for difftest + es_inst , //246:215 for difftest + error_va , //214:183 + es_idle , //182:182 + es_cacop , //181:181 + preld_inst , //180:180 + es_br_pre_error , //179:179 + es_br_pre , //178:178 + es_icache_miss , //177:177 + es_br_inst , //176:176 + icacop_op_en , //175:175 + es_mem_sign_exted, //174:174 //only add this, not used. + es_invtlb_vpn , //173:155 + es_invtlb_asid , //154:145 + es_invtlb , //144:144 + es_tlbrd , //143:143 + es_refetch , //142:142 + es_tlbfill , //141:141 + es_tlbwr , //140:140 + es_tlbsrch , //139:139 + es_store_op , //138:138 + es_sc_w , //137:137 + es_ll_w , //136:136 + excp_num , //135:126 + es_csr_we , //125:125 + es_csr_idx , //124:111 + es_csr_result , //110:79 + es_ertn , //78:78 + excp , //77:77 + es_mem_size , //76:75 + es_mul_div_op , //74:71 + es_load_op , //70:70 + es_gr_we , //69:69 + es_dest , //68:64 + exe_result , //63:32 + es_pc //31:0 + }; + +assign es_to_ds_valid = es_valid; + +assign access_mem = es_load_op || es_store_op; + +assign es_flush_sign = excp_flush || ertn_flush || refetch_flush || icacop_flush || idle_flush; + +assign icacop_inst_stall = icacop_op_en && !icache_unbusy; + +assign es_ready_go = (!div_stall && + `ifdef HAS_LACC + !lacc_stall && + `endif +((dcache_req_or_inst_en && data_addr_ok) || !(access_mem || dcacop_inst || preld_inst)) && !tlbsrch_stall && !icacop_inst_stall) || excp; +assign es_allowin = !es_valid || es_ready_go && ms_allowin; +assign es_to_ms_valid = es_valid && es_ready_go; +always @(posedge clk) begin + if (reset || es_flush_sign) begin + es_valid <= 1'b0; + end + else if (es_allowin) begin + es_valid <= ds_to_es_valid; + end + + if (ds_to_es_valid && es_allowin) begin + ds_to_es_bus_r <= ds_to_es_bus; + end +end + +assign es_alu_src1 = es_src1_is_pc ? es_pc : es_rj_value; + +assign es_alu_src2 = (es_src2_is_imm) ? es_imm : + (es_src2_is_4) ? 32'd4 : es_rkd_value; + +assign es_div_enable = (es_mul_div_op[2] | es_mul_div_op[3]) & es_valid; +assign es_mul_enable = es_mul_div_op[0] | es_mul_div_op[1]; + +assign div_stall = es_div_enable & ~div_complete; + +`ifdef HAS_LACC +assign lacc_stall = es_lacc_req & ~lacc_rsp_valid; +assign es_lacc_req = es_lacc_req_pre & es_valid; +assign lacc_req_imm = es_imm[11: 5]; +assign lacc_drsp_valid = es_lacc_req & data_data_ok; +`endif + +alu u_alu( + .alu_op (es_alu_op ), + .alu_src1 (es_alu_src1 ), //bug3 es_alu_src2 + .alu_src2 (es_alu_src2 ), + .alu_result (es_alu_result) + ); + +assign exe_result = `ifdef HAS_LACC + es_lacc_req ? lacc_rsp_rdat : + `endif + es_res_from_csr ? es_csr_data : es_alu_result; + +//forward path +assign dest_zero = (es_dest == 5'b0); +assign forward_enable = es_gr_we & ~dest_zero & es_valid; +assign dep_need_stall = es_load_op | es_div_enable | es_mul_enable; +assign es_to_ds_forward_bus = {dep_need_stall , //38:38 + forward_enable , //37:37 + es_dest , //36:32 + exe_result //31:0 + }; + +assign tlb_inst_stall = (es_tlbsrch || es_tlbrd) && es_valid; + +//csr mask +assign csr_mask_result = (es_rj_value & es_rkd_value) | (~es_rj_value & es_csr_data); +assign es_csr_result = es_csr_mask ? csr_mask_result : es_rkd_value; + +assign error_va = pv_addr; + +//exception +assign excp_ale = access_mem & ((es_mem_size[0] & 1'b0) | + (es_mem_size[1] & es_alu_result[0]) | + (!es_mem_size & (es_alu_result[0] | es_alu_result[1]))) ; + +assign excp = es_excp || excp_ale; +assign excp_num = {excp_ale, es_excp_num}; + +assign sram_addr_low2bit = {es_alu_result[1], es_alu_result[0]}; + +//mem_size[0] byte size [1] halfword size +assign dcache_req_or_inst_en = es_valid && !excp && ms_allowin && !es_flush_sign && !ms_flush; +`ifdef HAS_LACC +assign data_valid = access_mem && dcache_req_or_inst_en || lacc_data_valid; +assign data_op = lacc_data_valid ? !lacc_data_read : + es_store_op && !es_cacop && !es_preld; +decoder_2_4 decoder_lacc_size (lacc_data_addr[1: 0], lacc_data_byte); +assign lacc_data_half[0] = ~(|lacc_data_addr); +assign lacc_data_half[1] = ~lacc_data_addr[1]; +assign lacc_data_half[2] = ^lacc_data_addr; +assign lacc_data_half[3] = lacc_data_addr[1]; +assign lacc_data_mask = lacc_data_size == 2'b00 ? lacc_data_byte : + lacc_data_size == 2'b01 ? lacc_data_half : 4'b1111; +assign data_wstrb = lacc_data_valid ? lacc_data_mask : wr_byte_en; +assign data_size = lacc_data_valid ? lacc_data_size : data_size_pre; +assign data_addr = lacc_data_valid ? lacc_data_addr : + es_tlbsrch ? {csr_vppn, 13'b0} : pv_addr; +`else +assign data_valid = access_mem && dcache_req_or_inst_en; +assign data_op = es_store_op && !es_cacop && !es_preld; +assign data_wstrb = wr_byte_en; +assign data_size = data_size_pre; +assign data_addr = es_tlbsrch ? {csr_vppn, 13'b0} : pv_addr; +`endif + +wire [3:0] es_stb_wen = { sram_addr_low2bit==2'b11 , + sram_addr_low2bit==2'b10 , + sram_addr_low2bit==2'b01 , + sram_addr_low2bit==2'b00} ; + +wire [3:0] es_sth_wen = { sram_addr_low2bit==2'b10 , + sram_addr_low2bit==2'b10 , + sram_addr_low2bit==2'b00 , + sram_addr_low2bit==2'b00} ; + +wire [31:0] es_stb_cont = { {8{es_stb_wen[3]}} & es_rkd_value[7:0] , + {8{es_stb_wen[2]}} & es_rkd_value[7:0] , + {8{es_stb_wen[1]}} & es_rkd_value[7:0] , + {8{es_stb_wen[0]}} & es_rkd_value[7:0]}; + +wire [31:0] es_sth_cont = { {16{es_sth_wen[3]}} & es_rkd_value[15:0] , + {16{es_sth_wen[0]}} & es_rkd_value[15:0]}; + +assign {wr_byte_en, data_size_pre} = ({7{es_mem_size[0]}} & {es_stb_wen, 3'b00}) | + ({7{es_mem_size[1]}} & {es_sth_wen, 3'b01}) | + ({7{!es_mem_size }} & {4'b1111 , 3'b10}) ; + +//assign data_wdata = es_rkd_value; +assign data_wdata = + `ifdef HAS_LACC + lacc_data_valid ? lacc_data_wdata : + `endif + ({32{es_mem_size[0]}} & es_stb_cont ) | + ({32{es_mem_size[1]}} & es_sth_cont ) | + ({32{!es_mem_size }} & es_rkd_value) ; + +assign tlbsrch_stall = es_tlbsrch && ms_wr_tlbehi; + +//invtlb +assign es_invtlb_asid = es_rj_value[9:0]; +assign es_invtlb_vpn = es_rkd_value[31:13]; + +assign pv_addr = es_alu_result; + +//cache ins +assign cacop_op = es_dest; +assign icacop_inst = es_cacop && (cacop_op[2:0] == 3'b0); +assign icacop_op_en = icacop_inst && dcache_req_or_inst_en; +assign dcacop_inst = es_cacop && (cacop_op[2:0] == 3'b1); +assign dcacop_op_en = dcacop_inst && dcache_req_or_inst_en; +assign cacop_op_mode = cacop_op[4:3]; + +//preld ins +assign preld_hint = es_dest; +assign preld_inst = es_preld && ((preld_hint == 5'd0) || (preld_hint == 5'd8))/* && !data_uncache_en*/; //preld must have bug +assign preld_en = preld_inst && dcache_req_or_inst_en; + +assign data_fetch = (data_valid || dcacop_inst || preld_en) && data_addr_ok || ((icacop_inst || es_tlbsrch) && es_ready_go && ms_allowin) + `ifdef HAS_LACC + || lacc_data_valid + `endif +; + +endmodule diff --git a/rtl/ip/open-la500/icache.v b/rtl/ip/open-la500/icache.v new file mode 100644 index 0000000..5f641ae --- /dev/null +++ b/rtl/ip/open-la500/icache.v @@ -0,0 +1,410 @@ +module icache +( + input clk , + input reset , + //to from cpu + input valid , + input op , + input [ 7:0] index , + input [19:0] tag , + input [ 3:0] offset , + input [ 3:0] wstrb , + input [31:0] wdata , + output addr_ok , + output data_ok , + output [31:0] rdata , + input uncache_en , + input icacop_op_en , + input [ 1:0] cacop_op_mode , + input [ 7:0] cacop_op_addr_index , //this signal from mem stage's va + input [19:0] cacop_op_addr_tag , + input [ 3:0] cacop_op_addr_offset, + output icache_unbusy, + input tlb_excp_cancel_req, + //to from axi + output rd_req , + output [ 2:0] rd_type , + output [31:0] rd_addr , + input rd_rdy , + input ret_valid , + input ret_last , + input [31:0] ret_data , + output reg wr_req , + output [ 2:0] wr_type , + output [31:0] wr_addr , + output [ 3:0] wr_wstrb , + output [127:0] wr_data , + input wr_rdy , + //to perf_counter + output cache_miss +); + +reg request_buffer_op ; +reg [ 7:0] request_buffer_index ; +reg [19:0] request_buffer_tag ; +reg [ 3:0] request_buffer_offset ; +reg [ 3:0] request_buffer_wstrb ; +reg [31:0] request_buffer_wdata ; +reg request_buffer_uncache_en ; +reg request_buffer_icacop ; +reg [ 1:0] request_buffer_cacop_op_mode; + +reg [ 1:0] miss_buffer_replace_way ; +reg [ 1:0] miss_buffer_ret_num ; +wire [ 1:0] ret_num_add_one ; + +wire [ 7:0] way_bank_addra [1:0][3:0]; +wire [31:0] way_bank_dina [1:0][3:0]; +wire [31:0] way_bank_douta [1:0][3:0]; +wire way_bank_ena [1:0][3:0]; +wire [ 3:0] way_bank_wea [1:0][3:0]; + +wire [ 7:0] way_tagv_addra [1:0]; +wire [20:0] way_tagv_dina [1:0]; +wire [20:0] way_tagv_douta [1:0]; +wire way_tagv_ena [1:0]; +wire way_tagv_wea [1:0]; + +wire [ 1:0] way_hit ; +wire cache_hit ; + +wire [ 31:0] way_load_word [1:0]; +wire [127:0] way_data [1:0]; +wire [31:0] load_res ; + +wire main_idle2lookup ; +wire main_lookup2lookup; + +wire main_state_is_idle ; +wire main_state_is_lookup ; +wire main_state_is_replace; +wire main_state_is_refill ; + +wire [1:0] way_wr_en; + +wire [31:0] refill_data; + +wire cacop_op_mode0; +wire cacop_op_mode1; +wire cacop_op_mode2; + +wire [1:0] random_val; +wire [3:0] chosen_way; +wire [1:0] replace_way; +wire [1:0] invalid_way; +wire has_invalid_way; +wire [1:0] rand_repl_way; +wire [3:0] cacop_chose_way; +wire cacop_op_mode2_hit_wr; +wire cacop_op_mode2_no_hit; + +reg [ 1:0] lookup_way_hit_buffer; + +wire [ 3:0] real_offset; +wire [19:0] real_tag ; +wire [ 7:0] real_index ; + +wire req_or_inst_valid ; + +localparam main_idle = 5'b00001; +localparam main_lookup = 5'b00010; +localparam main_replace = 5'b01000; +localparam main_refill = 5'b10000; +localparam write_buffer_idle = 1'b0; +localparam write_buffer_write = 1'b1; + +reg [4:0] main_state; + +reg rd_req_buffer; + +genvar i,j; + +//state machine +//main loop +always @(posedge clk) begin + if (reset) begin + main_state <= main_idle; + + request_buffer_op <= 1'b0; + request_buffer_index <= 8'b0; + request_buffer_tag <= 20'b0; + request_buffer_offset <= 4'b0; + request_buffer_wstrb <= 4'b0; + request_buffer_wdata <= 32'b0; + request_buffer_uncache_en <= 1'b0; + + request_buffer_cacop_op_mode <= 2'b0; + request_buffer_icacop <= 1'b0; + + miss_buffer_replace_way <= 2'b0; + + wr_req <= 1'b0; + end + else case (main_state) + main_idle: begin + if (req_or_inst_valid && main_idle2lookup) begin + main_state <= main_lookup; + + request_buffer_op <= op ; + request_buffer_index <= real_index ; + request_buffer_offset <= real_offset; + request_buffer_wstrb <= wstrb; + request_buffer_wdata <= wdata; + + request_buffer_cacop_op_mode <= cacop_op_mode; + request_buffer_icacop <= icacop_op_en ; + end + end + main_lookup: begin + if (req_or_inst_valid && main_lookup2lookup) begin + main_state <= main_lookup; + + request_buffer_op <= op ; + request_buffer_index <= real_index ; + request_buffer_offset <= real_offset; + request_buffer_wstrb <= wstrb; + request_buffer_wdata <= wdata; + + request_buffer_cacop_op_mode <= cacop_op_mode; + request_buffer_icacop <= icacop_op_en ; + end + else if (tlb_excp_cancel_req) begin + main_state <= main_idle; + end + else if (!cache_hit) begin + main_state <= main_replace; + + request_buffer_tag <= real_tag; + request_buffer_uncache_en <= (uncache_en && !request_buffer_icacop); + miss_buffer_replace_way <= replace_way; + end + else begin + main_state <= main_idle; + end + end + main_replace: begin + if (rd_rdy) begin + main_state <= main_refill; + miss_buffer_ret_num <= 2'b0; //when get ret data, it will be sent to cpu directly. + end + end + main_refill: begin + if ((ret_valid && ret_last) || !rd_req_buffer) begin //when rd_req is not set, go to next state directly + main_state <= main_idle; + end + else begin + if (ret_valid) begin + miss_buffer_ret_num <= ret_num_add_one; + end + end + end + default: begin + main_state <= main_idle; + end + endcase +end + +assign real_offset = icacop_op_en ? cacop_op_addr_offset : offset; +assign real_index = icacop_op_en ? cacop_op_addr_index : index ; + +assign real_tag = request_buffer_icacop ? cacop_op_addr_tag : tag ; + +/*====================================main state idle=======================================*/ + +assign req_or_inst_valid = valid || icacop_op_en; + +assign main_idle2lookup = 1'b1; + +assign icache_unbusy = main_state_is_idle; + +//addr_ok logic + +/*===================================main state lookup======================================*/ + +//tag compare +generate for(i=0;i<2;i=i+1) begin:gen_way_hit + assign way_hit[i] = way_tagv_douta[i][0] && (real_tag == way_tagv_douta[i][20:1]); //this signal will not maintain +end endgenerate +assign cache_hit = |way_hit && !(uncache_en || cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2); //uncache road reuse +//when cache inst op mode2 no hit, main state machine will still go a round. implement easy. + +assign main_lookup2lookup = cache_hit; + +assign addr_ok = ((main_state_is_idle && main_idle2lookup) || (main_state_is_lookup && main_lookup2lookup)) && !icacop_op_en; //request can be get + +//data select +generate for(i=0;i<2;i=i+1) begin: gen_data + assign way_data[i] = {way_bank_douta[i][3],way_bank_douta[i][2],way_bank_douta[i][1],way_bank_douta[i][0]}; + + assign way_load_word[i] = way_data[i][request_buffer_offset[3:2]*32 +: 32]; +end endgenerate + +assign load_res = {32{way_hit[0]}} & way_load_word[0] | + {32{way_hit[1]}} & way_load_word[1] ; + +//data_ok logic + +/*====================================main state miss=======================================*/ + +decoder_2_4 dec_rand_way (.in({1'b0,random_val[0]}),.out(chosen_way)); + +one_valid_n #(2) sel_one_invalid (.in(~{way_tagv_douta[1][0],way_tagv_douta[0][0]}),.out(invalid_way),.nozero(has_invalid_way)); + +assign rand_repl_way = has_invalid_way ? invalid_way : chosen_way[1:0]; //chose invalid way first. + +decoder_2_4 dec_cacop_way (.in({1'b0,request_buffer_offset[0]}),.out(cacop_chose_way)); + +assign replace_way = {2{cacop_op_mode0 || cacop_op_mode1}} & cacop_chose_way[1:0] | + {2{cacop_op_mode2}} & way_hit | + {2{!request_buffer_icacop}} & rand_repl_way; + +/*==================================main state replace======================================*/ + +assign rd_req = main_state_is_replace && !(cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2); + +/*===================================main state refill======================================*/ + +assign rd_type = request_buffer_uncache_en ? 3'b10 : 3'b100; +assign rd_addr = request_buffer_uncache_en ? {request_buffer_tag, request_buffer_index, request_buffer_offset} : {request_buffer_tag, request_buffer_index, 4'b0}; + +//write process will not block pipeline +assign data_ok = (main_state_is_lookup && (cache_hit || tlb_excp_cancel_req)) || + (main_state_is_refill && ((ret_valid && ((miss_buffer_ret_num == request_buffer_offset[3:2]) || request_buffer_uncache_en))/* || !rd_req_buffer*/)) && + !request_buffer_icacop; //when rd_req is not set, set data_ok directly. +//rdate connect with ret_data dirctly. maintain one clock only + +assign refill_data = ret_data; + +assign way_wr_en = miss_buffer_replace_way & {2{ret_valid}}; //when rd_req is not set, ret_valid and ret_last will not be set. block will not be wr also. + +assign cache_miss = main_state_is_refill && ret_last && !(request_buffer_uncache_en || request_buffer_icacop); + +//add one +assign ret_num_add_one[0] = miss_buffer_ret_num[0] ^ 1'b1; +assign ret_num_add_one[1] = miss_buffer_ret_num[1] ^ miss_buffer_ret_num[0]; + +always @(posedge clk) begin + if (reset) begin + rd_req_buffer <= 1'b0; + end + else if (rd_req) begin + rd_req_buffer <= 1'b1; + end + else if (main_state_is_refill && (ret_valid && ret_last)) begin + rd_req_buffer <= 1'b0; + end +end + +/*==========================================================================================*/ + +//cache ins control signal +assign cacop_op_mode0 = request_buffer_icacop && (request_buffer_cacop_op_mode == 2'b00); +assign cacop_op_mode1 = request_buffer_icacop && ((request_buffer_cacop_op_mode == 2'b01) || (request_buffer_cacop_op_mode == 2'b11)); +assign cacop_op_mode2 = request_buffer_icacop && (request_buffer_cacop_op_mode == 2'b10); + +assign cacop_op_mode2_hit_wr = cacop_op_mode2 && |lookup_way_hit_buffer; +assign cacop_op_mode2_no_hit = cacop_op_mode2 && ~|lookup_way_hit_buffer; + +always @(posedge clk) begin + if (reset) begin + lookup_way_hit_buffer <= 2'b0; + end + else if (cacop_op_mode2 && main_state_is_lookup) begin + lookup_way_hit_buffer <= way_hit; + end +end + +//output +assign rdata = {32{main_state_is_lookup}} & load_res | + {32{main_state_is_refill}} & ret_data ; + +generate +for(i=0;i<2;i=i+1) begin:gen_data_way + for(j=0;j<4;j=j+1) begin:gen_data_bank +/*===============================bank addra logic==============================*/ + + assign way_bank_addra[i][j] = {8{addr_ok}} & real_index | /*lookup*/ + {8{!addr_ok}} & request_buffer_index ; + +/*===============================bank we logic=================================*/ + + assign way_bank_wea[i][j] = {4{main_state_is_refill && + (way_wr_en[i] && (miss_buffer_ret_num == j[1:0]))}} & 4'hf; + +/*===============================bank dina logic=================================*/ + + assign way_bank_dina[i][j] = {32{main_state_is_refill}} & refill_data; + +/*===============================bank ena logic=================================*/ + + assign way_bank_ena[i][j] = (!(request_buffer_uncache_en || cacop_op_mode0)) || main_state_is_idle || main_state_is_lookup; + end +end +endgenerate + +generate +for(i=0;i<2;i=i+1) begin:gen_tagv_way +/*===============================tagv addra logic=================================*/ + + assign way_tagv_addra[i] = {8{addr_ok || (icacop_op_en && + (main_state_is_idle || main_state_is_lookup))}} & real_index | + {8{main_state_is_replace || main_state_is_refill}} & request_buffer_index ; + //{8{(main_state_is_miss && wr_rdy) || + +/*===============================tagv ena logic=================================*/ + + assign way_tagv_ena[i] = (!request_buffer_uncache_en) || main_state_is_idle || main_state_is_lookup; + +/*===============================tagv wea logic=================================*/ + + assign way_tagv_wea[i] = miss_buffer_replace_way[i] && main_state_is_refill && + ((ret_valid && ret_last) || cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2_hit_wr); //wirte at last 4B + +/*===============================tagv dina logic=================================*/ + + assign way_tagv_dina[i] = (cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2_hit_wr) ? 21'b0 : {request_buffer_tag, 1'b1}; +end +endgenerate +/*==============================================================================*/ + +generate +for(i=0;i<2;i=i+1) begin:data_ram_way + for(j=0;j<4;j=j+1) begin:data_ram_bank + data_bank_sram u( + .addra (way_bank_addra[i][j]) , + .clka (clk ) , + .dina (way_bank_dina[i][j] ) , + .douta (way_bank_douta[i][j]) , + .ena (way_bank_ena[i][j] ) , + .wea (way_bank_wea[i][j] ) + ); + end +end +endgenerate + +generate +for(i=0;i<2;i=i+1) begin:tagv_ram_way + //[20:1] tag [0:0] v + tagv_sram u( + .addra (way_tagv_addra[i]) , + .clka (clk ) , + .dina (way_tagv_dina[i] ) , + .douta (way_tagv_douta[i]) , + .ena (way_tagv_ena[i] ) , + .wea (way_tagv_wea[i] ) + ); +end +endgenerate + +lfsr lfsr( + .clk (clk ) , + .reset (reset ) , + .random_val (random_val ) +); + +assign main_state_is_idle = main_state == main_idle ; +assign main_state_is_lookup = main_state == main_lookup ; +assign main_state_is_replace = main_state == main_replace; +assign main_state_is_refill = main_state == main_refill ; + +endmodule diff --git a/rtl/ip/open-la500/id_stage.v b/rtl/ip/open-la500/id_stage.v new file mode 100644 index 0000000..93bb028 --- /dev/null +++ b/rtl/ip/open-la500/id_stage.v @@ -0,0 +1,1005 @@ +`include "mycpu.h" + +module id_stage( + input clk , + input reset , + //allowin + input es_allowin , + output ds_allowin , + //from fs + input fs_to_ds_valid, + input [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus , + //from es forward path + input [`ES_TO_DS_FORWARD_BUS -1:0] es_to_ds_forward_bus, + input [`MS_TO_DS_FORWARD_BUS -1:0] ms_to_ds_forward_bus, + //to es + output ds_to_es_valid, + output [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus , + //to fs + output [`BR_BUS_WD -1:0] br_bus , + //exception + input excp_flush , + input ertn_flush , + input refetch_flush , + input icacop_flush , + //idle + input idle_flush , + //tlb ins + input es_tlb_inst_stall, + input ms_tlb_inst_stall, + input ws_tlb_inst_stall, + //interrupt + input has_int , + //csr + output [13:0] rd_csr_addr , + input [31:0] rd_csr_data , + input [ 1:0] csr_plv , + //timer 64 + input [63:0] timer_64 , + input [31:0] csr_tid , + //llbit + input ds_llbit , + //every stage valid sign + input es_to_ds_valid, + input ms_to_ds_valid, + input ws_to_ds_valid, + //from axi + input write_buffer_empty, + //from dcache + input dcache_empty , + //to btb + output btb_operate_en , + output btb_pop_ras , + output btb_push_ras , + output btb_add_entry , + output btb_delete_entry , + output btb_pre_error , + output btb_pre_right , + output btb_target_error , + output btb_right_orien , + output [31:0] btb_right_target , + output [31:0] btb_operate_pc , + output [ 4:0] btb_operate_index , + + //debug + input infor_flag, + input [ 4:0] reg_num, + output [31:0] debug_rf_rdata1, + + //to rf: for write back + input [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus + `ifdef DIFFTEST_EN + , + // difftest + output [31:0] rf_to_diff [31:0] + `endif +); + +reg ds_valid ; +wire ds_ready_go; + +reg [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus_r; + +wire [31:0] ds_inst; +wire [31:0] ds_pc ; +wire [ 3:0] ds_excp_num; +wire ds_excp; +wire ds_icache_miss; +wire ds_btb_taken; +wire ds_btb_en; +wire [ 4:0] ds_btb_index; +wire [31:0] ds_btb_target; + +assign {ds_btb_target, //108:77 + ds_btb_index, //76:72 + ds_btb_taken, //71:71 + ds_btb_en, //70:70 + ds_icache_miss, //69:69 + ds_excp, //68:68 + ds_excp_num, //67:64 + ds_inst, //63:32 + ds_pc //31:0 + } = fs_to_ds_bus_r; + +wire rf_we ; +wire [ 4:0] rf_waddr; +wire [31:0] rf_wdata; +assign {rf_we , //37:37 + rf_waddr, //36:32 + rf_wdata //31:0 + } = ws_to_rf_bus; + +//wire idle_stall; +wire br_taken; +wire [31:0] br_target; +wire btb_pre_error_flush; +wire [31:0] btb_pre_error_flush_target; + +//wire jirl_br; +wire [13:0] alu_op; +wire [ 3:0] mul_div_op; +wire mul_div_sign; +wire src1_is_pc; +wire src2_is_imm; +wire src2_is_4; +wire load_op; +wire res_from_csr; +wire csr_mask; +wire mem_b_size; +wire mem_h_size; +wire mem_sign_exted; +wire dst_is_r1; +wire dst_is_rj; +wire gr_we; +wire store_op; +wire csr_we; +wire src_reg_is_rd; +wire [1: 0] mem_size; +wire [4: 0] dest; +wire [31:0] rj_value; +wire [31:0] rkd_value; +wire [31:0] ds_imm; + +wire [ 5:0] op_31_26; +wire [ 3:0] op_25_22; +wire [ 1:0] op_21_20; +wire [ 4:0] op_19_15; +wire [ 4:0] rd; +wire [ 4:0] rj; +wire [ 4:0] rk; +wire [11:0] i12; +wire [13:0] i14; +wire [19:0] i20; +wire [15:0] i16; +wire [25:0] i26; +wire [13:0] csr_idx; + +wire [63:0] op_31_26_d; +wire [15:0] op_25_22_d; +wire [ 3:0] op_21_20_d; +wire [31:0] op_19_15_d; +wire [31:0] rd_d; +wire [31:0] rj_d; +wire [31:0] rk_d; + +wire inst_add_w; +wire inst_sub_w; +wire inst_slt; +wire inst_sltu; +wire inst_nor; +wire inst_and; +wire inst_or; +wire inst_xor; +wire inst_lu12i_w; +wire inst_addi_w; +wire inst_slti; +wire inst_sltui; +wire inst_pcaddi; +wire inst_pcaddu12i; +wire inst_andn; +wire inst_orn; +wire inst_andi; +wire inst_ori; +wire inst_xori; +wire inst_mul_w; +wire inst_mulh_w; +wire inst_mulh_wu; +wire inst_div_w; +wire inst_mod_w; +wire inst_div_wu; +wire inst_mod_wu; + +wire inst_slli_w; +wire inst_srli_w; +wire inst_srai_w; +wire inst_sll_w; +wire inst_srl_w; +wire inst_sra_w; + +wire inst_jirl; +wire inst_b; +wire inst_bl; +wire inst_beq; +wire inst_bne; +wire inst_blt; +wire inst_bge; +wire inst_bltu; +wire inst_bgeu; + +wire inst_ll_w; +wire inst_sc_w; +wire inst_ld_b; +wire inst_ld_bu; +wire inst_ld_h; +wire inst_ld_hu; +wire inst_ld_w; +wire inst_st_b; +wire inst_st_h; +wire inst_st_w; + +wire inst_syscall; +wire inst_break; +wire inst_csrrd; +wire inst_csrwr; +wire inst_csrxchg; +wire inst_ertn; +wire inst_cpucfg; + +wire inst_rdcntid_w; +wire inst_rdcntvl_w; +wire inst_rdcntvh_w; +wire inst_idle; + +wire inst_tlbsrch; +wire inst_tlbrd; +wire inst_tlbwr; +wire inst_tlbfill; +wire inst_invtlb; + +wire inst_cacop; +wire inst_valid_cacop; +wire inst_preld; +wire inst_dbar; +wire inst_ibar; + +wire inst_nop; + +`ifdef HAS_LACC +// inst[31: 26] = 6'h30 +// inst[25: 22] = op +// rk rj rd +wire lacc_req, lacc_valid; +`endif + +wire need_ui5; +wire need_si12; +wire need_ui12; +wire need_si14_pc; +wire need_si16_pc; +wire need_si20; +wire need_si20_pc; +wire need_si26_pc; + +wire [ 4:0] rf_raddr1; +wire [31:0] rf_rdata1; +wire [ 4:0] rf_raddr2; +wire [31:0] rf_rdata2; + +wire pipeline_no_empty; +wire dbar_stall; +wire ibar_stall; + +wire rj_eq_rd; +wire rj_lt_rd_sign; +wire rj_lt_rd_unsign; + +wire ms_forward_enable; +wire [ 4:0] ms_forward_reg; +wire [31:0] ms_forward_data; +wire ms_dep_need_stall; +wire es_dep_need_stall; +wire es_forward_enable; +wire [ 4:0] es_forward_reg; +wire [31:0] es_forward_data; +wire rf1_forward_stall; +wire rf2_forward_stall; + +wire excp; +wire [ 8:0] excp_num; +wire inst_valid; +wire excp_ine; +wire excp_ipe; +wire [31:0] csr_data; +wire refetch; +wire flush_sign; + +wire fs_excp; + +wire kernel_inst; + +wire [31:0] rdcnt_result; +wire rdcnt_en; + +reg branch_slot_cancel; + +wire tlb_inst_stall; + +wire br_inst; + +reg br_jirl; + +wire br_need_reg_data; +wire br_to_btb; + +wire inst_need_rj; +wire inst_need_rkd; + +wire [31:0] rj_value_forward_es; +wire [31:0] rkd_value_forward_es; + +// difftest +wire [7:0] inst_ld_en; +wire [7:0] inst_st_en; +wire inst_csr_rstat_en; + +assign br_bus = {btb_pre_error_flush, //32:32 + btb_pre_error_flush_target //31:0 + }; + +assign ds_to_es_bus = { + `ifdef HAS_LACC + ds_inst[22 +: `LACC_OP_WIDTH], + lacc_req, + `endif + inst_csr_rstat_en, // 349:349 for difftest + inst_st_en , // 348:341 for difftest + inst_ld_en , // 340:333 for difftest + (inst_rdcntvl_w | inst_rdcntvh_w | inst_rdcntid_w), //332:332 for difftest + timer_64 , //331:268 for difftest + ds_inst , //267:236 for difftest + inst_idle , //235:235 + btb_pre_error_flush, //234:234 + br_to_btb , //233:233 + ds_icache_miss, //232:232 + br_inst , //231:231 + inst_preld , //230:230 + inst_valid_cacop, //229:229 + mem_sign_exted, //228:228 + inst_invtlb , //227:227 + inst_tlbrd , //226:226 + refetch , //225:225 + inst_tlbfill , //224:224 + inst_tlbwr , //223:223 + inst_tlbsrch , //222:222 + inst_sc_w , //221:221 + inst_ll_w , //220:220 + excp_num , //219:211 + csr_mask , //210:210 + csr_we , //209:209 + csr_idx , //208:195 + res_from_csr , //194:194 + csr_data , //193:162 + inst_ertn , //161:161 + excp , //160:160 + mem_size , //159:158 + mul_div_op , //157:154 + mul_div_sign , //153:153 + alu_op , //152:139 + load_op , //138:138 bug2 load_op + src1_is_pc , //137:137 + src2_is_imm , //136:136 + src2_is_4 , //135:135 + gr_we , //134:134 + store_op , //133:133 + dest , //132:128 + ds_imm , //127:96 + rj_value , //95 :64 + rkd_value , //63 :32 + ds_pc //31 :0 + }; + +assign flush_sign = excp_flush || ertn_flush || refetch_flush || icacop_flush || idle_flush; + +assign fs_excp = fs_to_ds_bus[68]; + +//wait inst will stall at ds. +assign ds_ready_go = !(rf2_forward_stall || rf1_forward_stall/*|| idle_stall*/ || tlb_inst_stall || ibar_stall || dbar_stall) || excp; +assign ds_allowin = !ds_valid || ds_ready_go && es_allowin; +assign ds_to_es_valid = ds_valid && ds_ready_go; +always @(posedge clk) begin //bug1 no reset; branch no delay slot + if (reset || flush_sign) begin + ds_valid <= 1'b0; + end + else begin + if (ds_allowin) begin //bug2 ?? + if ((btb_pre_error_flush && es_allowin) || branch_slot_cancel) begin + ds_valid <= 1'b0; + end + else begin + ds_valid <= fs_to_ds_valid; + end + end + end + + if (fs_to_ds_valid && ds_allowin) begin + fs_to_ds_bus_r <= fs_to_ds_bus; + end +end + +assign op_31_26 = ds_inst[31:26]; +assign op_25_22 = ds_inst[25:22]; +assign op_21_20 = ds_inst[21:20]; +assign op_19_15 = ds_inst[19:15]; + +assign rd = ds_inst[ 4: 0]; +assign rj = ds_inst[ 9: 5]; +assign rk = ds_inst[14:10]; + +assign i12 = ds_inst[21:10]; +assign i14 = ds_inst[23:10]; +assign i20 = ds_inst[24: 5]; +assign i16 = ds_inst[25:10]; +assign i26 = {ds_inst[ 9: 0], ds_inst[25:10]}; + +assign csr_idx = ds_inst[23:10]; + +decoder_6_64 u_dec0(.in(op_31_26 ), .out(op_31_26_d )); +decoder_4_16 u_dec1(.in(op_25_22 ), .out(op_25_22_d )); +decoder_2_4 u_dec2(.in(op_21_20 ), .out(op_21_20_d )); +decoder_5_32 u_dec3(.in(op_19_15 ), .out(op_19_15_d )); + +decoder_5_32 u_dec4(.in(rd ), .out(rd_d )); +decoder_5_32 u_dec5(.in(rj ), .out(rj_d )); +decoder_5_32 u_dec6(.in(rk ), .out(rk_d )); + +assign inst_add_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h00]; +assign inst_sub_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h02]; +assign inst_slt = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h04]; +assign inst_sltu = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h05]; +assign inst_nor = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h08]; +assign inst_and = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h09]; +assign inst_or = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0a]; +assign inst_xor = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0b]; +assign inst_orn = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0c]; +assign inst_andn = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0d]; +assign inst_sll_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0e]; +assign inst_srl_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0f]; +assign inst_sra_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h10]; +assign inst_mul_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h18]; +assign inst_mulh_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h19]; +assign inst_mulh_wu = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h1a]; +assign inst_div_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h00]; +assign inst_mod_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h01]; +assign inst_div_wu = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h02]; +assign inst_mod_wu = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h03]; +assign inst_break = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h14]; +assign inst_syscall = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h2] & op_19_15_d[5'h16]; +assign inst_slli_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h01]; +assign inst_srli_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h09]; +assign inst_srai_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h11]; +assign inst_idle = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h11]; +assign inst_invtlb = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h13]; +assign inst_dbar = op_31_26_d[6'h0e] & op_25_22_d[4'h1] & op_21_20_d[2'h3] & op_19_15_d[5'h04]; +assign inst_ibar = op_31_26_d[6'h0e] & op_25_22_d[4'h1] & op_21_20_d[2'h3] & op_19_15_d[5'h05]; +assign inst_slti = op_31_26_d[6'h00] & op_25_22_d[4'h8]; +assign inst_sltui = op_31_26_d[6'h00] & op_25_22_d[4'h9]; +assign inst_addi_w = op_31_26_d[6'h00] & op_25_22_d[4'ha]; +assign inst_andi = op_31_26_d[6'h00] & op_25_22_d[4'hd]; +assign inst_ori = op_31_26_d[6'h00] & op_25_22_d[4'he]; +assign inst_xori = op_31_26_d[6'h00] & op_25_22_d[4'hf]; +assign inst_ld_b = op_31_26_d[6'h0a] & op_25_22_d[4'h0]; +assign inst_ld_h = op_31_26_d[6'h0a] & op_25_22_d[4'h1]; +assign inst_ld_w = op_31_26_d[6'h0a] & op_25_22_d[4'h2]; +assign inst_st_b = op_31_26_d[6'h0a] & op_25_22_d[4'h4]; +assign inst_st_h = op_31_26_d[6'h0a] & op_25_22_d[4'h5]; +assign inst_st_w = op_31_26_d[6'h0a] & op_25_22_d[4'h6]; +assign inst_ld_bu = op_31_26_d[6'h0a] & op_25_22_d[4'h8]; +assign inst_ld_hu = op_31_26_d[6'h0a] & op_25_22_d[4'h9]; +assign inst_cacop = op_31_26_d[6'h01] & op_25_22_d[4'h8]; +assign inst_preld = op_31_26_d[6'h0a] & op_25_22_d[4'hb]; +assign inst_jirl = op_31_26_d[6'h13]; +assign inst_b = op_31_26_d[6'h14]; +assign inst_bl = op_31_26_d[6'h15]; +assign inst_beq = op_31_26_d[6'h16]; +assign inst_bne = op_31_26_d[6'h17]; +assign inst_blt = op_31_26_d[6'h18]; +assign inst_bge = op_31_26_d[6'h19]; +assign inst_bltu = op_31_26_d[6'h1a]; +assign inst_bgeu = op_31_26_d[6'h1b]; +assign inst_lu12i_w = op_31_26_d[6'h05] & ~ds_inst[25]; +assign inst_pcaddi = op_31_26_d[6'h06] & ~ds_inst[25]; +assign inst_pcaddu12i = op_31_26_d[6'h07] & ~ds_inst[25]; +assign inst_csrxchg = op_31_26_d[6'h01] & ~ds_inst[25] & ~ds_inst[24] & (~rj_d[5'h00] & ~rj_d[5'h01]); //rj != 0,1 +assign inst_ll_w = op_31_26_d[6'h08] & ~ds_inst[25] & ~ds_inst[24]; +assign inst_sc_w = op_31_26_d[6'h08] & ~ds_inst[25] & ds_inst[24]; +assign inst_csrrd = op_31_26_d[6'h01] & ~ds_inst[25] & ~ds_inst[24] & rj_d[5'h00]; +assign inst_csrwr = op_31_26_d[6'h01] & ~ds_inst[25] & ~ds_inst[24] & rj_d[5'h01]; +assign inst_rdcntid_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h0] & op_19_15_d[5'h00] & rk_d[5'h18] & rd_d[5'h00]; +assign inst_rdcntvl_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h0] & op_19_15_d[5'h00] & rk_d[5'h18] & rj_d[5'h00] & !rd_d[5'h00]; +assign inst_rdcntvh_w = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h0] & op_19_15_d[5'h00] & rk_d[5'h19] & rj_d[5'h00]; +assign inst_ertn = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h10] & rk_d[5'h0e] & rj_d[5'h00] & rd_d[5'h00]; +assign inst_tlbsrch = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h10] & rk_d[5'h0a] & rj_d[5'h00] & rd_d[5'h00]; +assign inst_tlbrd = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h10] & rk_d[5'h0b] & rj_d[5'h00] & rd_d[5'h00]; +assign inst_tlbwr = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h10] & rk_d[5'h0c] & rj_d[5'h00] & rd_d[5'h00]; +assign inst_tlbfill = op_31_26_d[6'h01] & op_25_22_d[4'h9] & op_21_20_d[2'h0] & op_19_15_d[5'h10] & rk_d[5'h0d] & rj_d[5'h00] & rd_d[5'h00]; +assign inst_cpucfg = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h0] & op_19_15_d[5'h00] & rk_d[5'h1b]; + +assign inst_valid_cacop = inst_cacop&&(dest[2:0]==3'b0||dest[2:0]==3'b1)&&(dest[4:3]==2'd0||dest[4:3]==2'd1||dest[4:3]==2'd2); +assign inst_nop = inst_cacop&&((dest[2:0]!=3'b0&&dest[2:0]!=3'b1)||(dest[4:3]==2'd3)); + +`ifdef HAS_LACC + assign lacc_req = ds_inst[31] & ds_inst[30] & ~ds_inst[29] & ~ds_inst[28]; + assign lacc_valid = ds_inst[22 +: `LACC_OP_WIDTH] < `LACC_OP_SIZE; +`endif + +assign alu_op[ 0] = inst_add_w | + inst_addi_w | + inst_ld_b | + inst_ld_h | + inst_ld_w | + inst_st_b | + inst_st_h | + inst_st_w | + inst_ld_bu | + inst_ld_hu | + inst_ll_w | + inst_sc_w | + inst_jirl | + inst_bl | + inst_pcaddi | + inst_pcaddu12i | + inst_valid_cacop| + inst_preld ; + +assign alu_op[ 1] = inst_sub_w; +assign alu_op[ 2] = inst_slt | inst_slti; +assign alu_op[ 3] = inst_sltu | inst_sltui; +assign alu_op[ 4] = inst_and | inst_andi; +assign alu_op[ 5] = inst_nor; +assign alu_op[ 6] = inst_or | inst_ori; +assign alu_op[ 7] = inst_xor | inst_xori; +assign alu_op[ 8] = inst_sll_w | inst_slli_w; +assign alu_op[ 9] = inst_srl_w | inst_srli_w; +assign alu_op[10] = inst_sra_w | inst_srai_w; +assign alu_op[11] = inst_lu12i_w; +assign alu_op[12] = inst_andn; +assign alu_op[13] = inst_orn; + +assign mul_div_op[ 0] = inst_mul_w; +assign mul_div_op[ 1] = inst_mulh_w | inst_mulh_wu; +assign mul_div_op[ 2] = inst_div_w | inst_div_wu; +assign mul_div_op[ 3] = inst_mod_w | inst_mod_wu; + +assign mul_div_sign = inst_mul_w | inst_mulh_w | inst_div_w | inst_mod_w; + +assign need_ui5 = inst_slli_w | inst_srli_w | inst_srai_w; +assign need_si12 = inst_addi_w | + inst_ld_b | + inst_ld_h | + inst_ld_w | + inst_st_b | + inst_st_h | + inst_st_w | + inst_ld_bu | + inst_ld_hu | + inst_slti | + inst_sltui | + inst_valid_cacop| + inst_preld ; + +assign need_ui12 = inst_andi | inst_ori | inst_xori + `ifdef HAS_LACC + | lacc_req + `endif + ; +assign need_si14_pc = inst_ll_w | inst_sc_w; +assign need_si16_pc = inst_jirl | + inst_beq | + inst_bne | + inst_blt | + inst_bge | + inst_bltu | + inst_bgeu; + +assign need_si20 = inst_lu12i_w | inst_pcaddu12i; +assign need_si20_pc = inst_pcaddi; +assign need_si26_pc = inst_b | inst_bl; + +assign ds_imm = ({32{need_ui5 }} & {27'b0, rk} ) | + ({32{need_si12 }} & {{20{i12[11]}}, i12} ) | + ({32{need_ui12 }} & {20'b0, i12} ) | + ({32{need_si14_pc}} & {{16{i14[13]}}, i14, 2'b0}) | + ({32{need_si16_pc}} & {{14{i16[15]}}, i16, 2'b0}) | + ({32{need_si20 }} & {i20, 12'b0} ) | + ({32{need_si20_pc}} & {{10{i20[19]}}, i20, 2'b0}) | + ({32{need_si26_pc}} & {{ 4{i26[25]}}, i26, 2'b0}) ; + +assign src_reg_is_rd = inst_beq | + inst_bne | + inst_blt | + inst_bltu | + inst_bge | + inst_bgeu | + inst_st_b | + inst_st_h | + inst_st_w | + inst_sc_w | + inst_csrwr | + inst_csrxchg; + +assign src1_is_pc = inst_jirl | inst_bl | inst_pcaddi | inst_pcaddu12i; + +assign src2_is_imm = inst_slli_w | + inst_srli_w | + inst_srai_w | + inst_addi_w | + inst_slti | + inst_sltui | + inst_andi | + inst_ori | + inst_xori | + inst_pcaddi | + inst_pcaddu12i | + inst_ld_b | + inst_ld_h | + inst_ld_w | + inst_ld_bu | + inst_ld_hu | + inst_st_b | + inst_st_h | + inst_st_w | + inst_ll_w | + inst_sc_w | + inst_lu12i_w | + inst_valid_cacop| + inst_preld ; + +assign src2_is_4 = inst_jirl | inst_bl; + +assign load_op = inst_ld_b | inst_ld_h | inst_ld_w | inst_ld_bu | inst_ld_hu | inst_ll_w; +assign mem_b_size = inst_ld_b | inst_ld_bu | inst_st_b; +assign mem_h_size = inst_ld_h | inst_ld_hu | inst_st_h; +assign mem_sign_exted= inst_ld_b | inst_ld_h; +assign dst_is_r1 = inst_bl; +assign gr_we = ~inst_st_b & + ~inst_st_h & + ~inst_st_w & + ~inst_beq & + ~inst_bne & + ~inst_blt & + ~inst_bge & + ~inst_bltu & + ~inst_bgeu & + ~inst_b & + ~inst_syscall & + ~inst_tlbsrch & + ~inst_tlbrd & + ~inst_tlbwr & + ~inst_tlbfill & + ~inst_invtlb & + ~inst_valid_cacop& + ~inst_preld & + ~inst_dbar & + ~inst_ibar & + ~inst_nop ; + +assign store_op = inst_st_b | inst_st_h | inst_st_w | (inst_sc_w & ds_llbit); + +assign dest = (dst_is_r1) ? 5'd1 : + (dst_is_rj) ? rj : rd; + +assign dst_is_rj = inst_rdcntid_w; + +assign {rdcnt_en, rdcnt_result} = ({33{inst_rdcntvl_w}} & {1'b1, timer_64[31: 0]}) | + ({33{inst_rdcntvh_w}} & {1'b1, timer_64[63:32]}) | + ({33{inst_rdcntid_w}} & {1'b1, csr_tid}); + +assign csr_data = rdcnt_en ? rdcnt_result : + inst_sc_w ? {31'b0, ds_llbit} : rd_csr_data; + +assign res_from_csr = inst_csrrd | inst_csrwr | inst_csrxchg | inst_rdcntid_w | inst_rdcntvh_w | inst_rdcntvl_w | inst_sc_w | inst_cpucfg; +assign csr_we = inst_csrwr | inst_csrxchg; +assign csr_mask = inst_csrxchg; + +assign mem_size = {mem_h_size, mem_b_size}; + +assign inst_need_rj = inst_add_w | + inst_sub_w | + inst_addi_w | + inst_slt | + inst_sltu | + inst_slti | + inst_sltui | + inst_and | + inst_or | + inst_nor | + inst_xor | + inst_andi | + inst_ori | + inst_xori | + inst_mul_w | + inst_mulh_w | + inst_mulh_wu | + inst_div_w | + inst_div_wu | + inst_mod_w | + inst_mod_wu | + inst_sll_w | + inst_srl_w | + inst_sra_w | + inst_slli_w | + inst_srli_w | + inst_srai_w | + inst_beq | + inst_bne | + inst_blt | + inst_bltu | + inst_bge | + inst_bgeu | + inst_jirl | + inst_ld_b | + inst_ld_bu | + inst_ld_h | + inst_ld_hu | + inst_ld_w | + inst_st_b | + inst_st_h | + inst_st_w | + inst_preld | + inst_ll_w | + inst_sc_w | + inst_csrxchg | + inst_valid_cacop| + `ifdef HAS_LACC + lacc_req | + `endif + inst_invtlb ; + +assign inst_need_rkd = inst_add_w | + inst_sub_w | + inst_slt | + inst_sltu | + inst_and | + inst_or | + inst_nor | + inst_xor | + inst_mul_w | + inst_mulh_w | + inst_mulh_wu | + inst_div_w | + inst_div_wu | + inst_mod_w | + inst_mod_wu | + inst_sll_w | + inst_srl_w | + inst_sra_w | + inst_beq | + inst_bne | + inst_blt | + inst_bltu | + inst_bge | + inst_bgeu | + inst_st_b | + inst_st_h | + inst_st_w | + inst_sc_w | + inst_csrwr | + inst_csrxchg | + `ifdef HAS_LACC + lacc_req | + `endif + inst_invtlb ; + + +assign rf_raddr1 = infor_flag?reg_num:rj; +assign rf_raddr2 = src_reg_is_rd ? rd : rk; +regfile u_regfile( + .clk (clk ), + .raddr1 (rf_raddr1), + .rdata1 (rf_rdata1), + .raddr2 (rf_raddr2), + .rdata2 (rf_rdata2), + .we (rf_we ), + .waddr (rf_waddr ), + .wdata (rf_wdata ) + `ifdef DIFFTEST_EN + , + .rf_o (rf_to_diff) + `endif + ); + +assign {es_dep_need_stall, + es_forward_enable, + es_forward_reg , + es_forward_data + } = es_to_ds_forward_bus; + +assign {ms_dep_need_stall, + ms_forward_enable, + ms_forward_reg , + ms_forward_data + } = ms_to_ds_forward_bus; + +//exe stage first forward +assign {rf1_forward_stall, rj_value, rj_value_forward_es} = ((rf_raddr1 == es_forward_reg) && es_forward_enable && inst_need_rj) ? {es_dep_need_stall, es_forward_data, es_forward_data} : + ((rf_raddr1 == ms_forward_reg) && ms_forward_enable && inst_need_rj) ? {ms_dep_need_stall || br_need_reg_data, ms_forward_data, rf_rdata1} : + {1'b0, rf_rdata1, rf_rdata1}; + +assign {rf2_forward_stall, rkd_value, rkd_value_forward_es} = ((rf_raddr2 == es_forward_reg) && es_forward_enable && inst_need_rkd) ? {es_dep_need_stall, es_forward_data, es_forward_data} : + ((rf_raddr2 == ms_forward_reg) && ms_forward_enable && inst_need_rkd) ? {ms_dep_need_stall || br_need_reg_data, ms_forward_data, rf_rdata2} : + {1'b0, rf_rdata2, rf_rdata2}; + +assign rj_eq_rd = (rj_value_forward_es == rkd_value_forward_es); +assign rj_lt_rd_unsign = (rj_value_forward_es < rkd_value_forward_es); //operate "<" has nice timing +assign rj_lt_rd_sign = (rj_value_forward_es[31] && ~rkd_value_forward_es[31]) ? 1'b1 : + (~rj_value_forward_es[31] && rkd_value_forward_es[31]) ? 1'b0 : rj_lt_rd_unsign; + +assign br_taken = ( inst_beq && rj_eq_rd + || inst_bne && !rj_eq_rd + || inst_blt && rj_lt_rd_sign + || inst_bge && !rj_lt_rd_sign + || inst_bltu && rj_lt_rd_unsign + || inst_bgeu && !rj_lt_rd_unsign + || inst_jirl + || inst_bl + || inst_b + ) && ds_valid && !ds_excp; + +assign br_inst = br_need_reg_data || inst_bl || inst_b; + +assign br_to_btb = inst_beq || + inst_bne || + inst_blt || + inst_bge || + inst_bltu || + inst_bgeu || + inst_bl || + inst_b || + inst_jirl; + +assign br_need_reg_data = inst_beq || + inst_bne || + inst_blt || + inst_bge || + inst_bltu || + inst_bgeu || + inst_jirl; + +assign br_target = ({32{inst_beq || inst_bne || inst_bl || inst_b || + inst_blt || inst_bge || inst_bltu || inst_bgeu}} & (ds_pc + ds_imm )) | + ({32{inst_jirl}} & (rj_value_forward_es + ds_imm)) ; + +//assign idle_stall = inst_idle & ds_valid & !has_int; + +assign excp = excp_ipe | inst_syscall | inst_break | ds_excp | excp_ine | has_int; +assign excp_num = {excp_ipe, excp_ine, inst_break, inst_syscall, ds_excp_num, has_int}; + +assign rd_csr_addr = inst_cpucfg ? (rj_value[13:0]+14'h00b0) : csr_idx; + +//when cache operate icache, will refetch inst after this inst. +assign refetch = (inst_tlbwr || inst_tlbfill || inst_tlbrd || inst_invtlb || inst_ibar) && ds_valid; //this inst will change addr trans + +assign tlb_inst_stall = es_tlb_inst_stall || ms_tlb_inst_stall || ws_tlb_inst_stall; + +assign inst_valid = inst_add_w | + inst_sub_w | + inst_slt | + inst_sltu | + inst_nor | + inst_and | + inst_or | + inst_xor | + inst_sll_w | + inst_srl_w | + inst_sra_w | + inst_mul_w | + inst_mulh_w | + inst_mulh_wu | + inst_div_w | + inst_mod_w | + inst_div_wu | + inst_mod_wu | + inst_break | + inst_syscall | + inst_slli_w | + inst_srli_w | + inst_srai_w | + inst_idle | + inst_slti | + inst_sltui | + inst_addi_w | + inst_andi | + inst_ori | + inst_xori | + inst_ld_b | + inst_ld_h | + inst_ld_w | + inst_st_b | + inst_st_h | + inst_st_w | + inst_ld_bu | + inst_ld_hu | + inst_ll_w | + inst_sc_w | + inst_jirl | + inst_b | + inst_bl | + inst_beq | + inst_bne | + inst_blt | + inst_bge | + inst_bltu | + inst_bgeu | + inst_lu12i_w | + inst_pcaddu12i | + inst_csrrd | + inst_csrwr | + inst_csrxchg | + inst_rdcntid_w | + inst_rdcntvh_w | + inst_rdcntvl_w | + inst_ertn | + inst_valid_cacop| + inst_preld | + inst_dbar | + inst_ibar | + inst_tlbsrch | + inst_tlbrd | + inst_tlbwr | + inst_tlbfill | + inst_nop | + inst_cpucfg | + `ifdef HAS_LACC + lacc_req & lacc_valid | + `endif + (inst_invtlb && (rd == 5'd0 || + rd == 5'd1 || + rd == 5'd2 || + rd == 5'd3 || + rd == 5'd4 || + rd == 5'd5 || + rd == 5'd6 )); //invtlb valid op + +assign excp_ine = ~inst_valid; + +assign kernel_inst = inst_csrrd | + inst_csrwr | + inst_csrxchg | + inst_valid_cacop & (rd[4:3] != 2'b10)| + inst_tlbsrch | + inst_tlbrd | + inst_tlbwr | + inst_tlbfill | + inst_invtlb | + inst_ertn | + inst_idle ; + +assign excp_ipe = kernel_inst && (csr_plv == 2'b11); + +//branch slot cancel, need wait next valid inst after branch +//only valid br_taken sign can generate slot_cancel. +always @(posedge clk) begin + if (reset || flush_sign) begin + //flush signal need flush this buffer + branch_slot_cancel <= 1'b0; + end + else if (btb_pre_error_flush && es_allowin && !fs_to_ds_valid) begin + branch_slot_cancel <= 1'b1; + end + else if (branch_slot_cancel && fs_to_ds_valid) begin + branch_slot_cancel <= 1'b0; + end +end + +assign btb_operate_en = ds_valid && ds_ready_go && es_allowin && !ds_excp; +assign btb_operate_pc = ds_pc; +assign btb_pop_ras = inst_jirl; +assign btb_push_ras = inst_bl; +assign btb_add_entry = br_to_btb && !ds_btb_en && br_taken; +assign btb_delete_entry = !br_to_btb && ds_btb_en; +assign btb_pre_error = br_to_btb && ds_btb_en && (ds_btb_taken ^ br_taken); +assign btb_target_error = br_to_btb && ds_btb_en && (ds_btb_taken && br_taken) && (ds_btb_target != br_target); +assign btb_pre_right = br_to_btb && ds_btb_en && !(ds_btb_taken ^ br_taken); +assign btb_right_orien = br_taken; +assign btb_right_target = br_target; +assign btb_operate_index = ds_btb_index; + +assign btb_pre_error_flush = (btb_add_entry || btb_delete_entry || btb_pre_error || btb_target_error) && ds_valid && ds_ready_go && !ds_excp; +assign btb_pre_error_flush_target = br_taken ? br_target : ds_pc + 32'h4; + +//ibar dbar +assign pipeline_no_empty = es_to_ds_valid || ms_to_ds_valid || ws_to_ds_valid || !write_buffer_empty || !dcache_empty; +assign dbar_stall = inst_dbar && pipeline_no_empty; +assign ibar_stall = inst_ibar && pipeline_no_empty; + + +// ll ldw ldhu ldh ldbu ldb +assign inst_ld_en = {2'b0, inst_ll_w, inst_ld_w, inst_ld_hu, inst_ld_h, inst_ld_bu, inst_ld_b}; +// sc(llbit = 1) stw sth stb +assign inst_st_en = {4'b0, ds_llbit && inst_sc_w, inst_st_w, inst_st_h, inst_st_b}; +assign inst_csr_rstat_en = (inst_csrrd || inst_csrwr || inst_csrxchg) && (csr_idx == 14'd5); + +// debug +assign debug_rf_rdata1 = rf_raddr1; + +endmodule diff --git a/rtl/ip/open-la500/if_stage.v b/rtl/ip/open-la500/if_stage.v new file mode 100644 index 0000000..f0684f1 --- /dev/null +++ b/rtl/ip/open-la500/if_stage.v @@ -0,0 +1,357 @@ +`include "mycpu.h" +`include "csr.h" + +module if_stage( + input clk , + input reset , + //allwoin + input ds_allowin , + //brbus + input [`BR_BUS_WD -1:0] br_bus , + //to ds + output fs_to_ds_valid , + output [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus , + //exception + input excp_flush , + input ertn_flush , + input refetch_flush , + input icacop_flush , + input [31:0] ws_pc , + input [31:0] csr_eentry , + input [31:0] csr_era , + input excp_tlbrefill , + input [31:0] csr_tlbrentry , + input has_int , + //idle + input idle_flush , + // inst cache interface + output inst_valid , + output inst_op , + output [ 3:0] inst_wstrb , + output [31:0] inst_wdata , + input inst_addr_ok , + input inst_data_ok , + input icache_miss , + input [31:0] inst_rdata , + output inst_uncache_en , + output tlb_excp_cancel_req, + //from csr + input csr_pg , + input csr_da , + input [31:0] csr_dmw0 , + input [31:0] csr_dmw1 , + input [ 1:0] csr_plv , + input [ 1:0] csr_datf , + input disable_cache , + //to btb + output [31:0] fetch_pc , + output fetch_en , + input [31:0] btb_ret_pc , + input btb_taken , + input btb_en , + input [ 4:0] btb_index , + //to addr trans + output [31:0] inst_addr , + output inst_addr_trans_en, + output dmw0_en , + output dmw1_en , + //tlb + input inst_tlb_found , + input inst_tlb_v , + input inst_tlb_d , + input [ 1:0] inst_tlb_mat , + input [ 1:0] inst_tlb_plv +); + +reg fs_valid; +wire fs_ready_go; +wire fs_allowin; +wire to_fs_valid; +wire pfs_ready_go; + +wire [31:0] seq_pc; +wire [31:0] nextpc; + +wire pfs_excp_adef; +wire fs_excp_tlbr; +wire fs_excp_pif; +wire fs_excp_ppi; +reg fs_excp; +reg fs_excp_num; +wire excp; +wire [3:0] excp_num; +wire pfs_excp; +wire pfs_excp_num; + +wire flush_sign; + +reg [31:0] inst_rd_buff; +reg inst_buff_enable; + +wire da_mode; +wire pg_mode; + +wire btb_pre_error_flush; +wire [31:0] btb_pre_error_flush_target; + +wire flush_inst_delay; +wire flush_inst_go_dirt; + +wire fetch_btb_target; + +reg idle_lock; + +wire tlb_excp_lock_pc; + +wire [31:0] btb_ret_pc_t; +wire [ 4:0] btb_index_t; +wire btb_taken_t; +wire btb_en_t; + +wire [31:0] excp_entry; +wire [31:0] inst_flush_pc; + +assign {btb_pre_error_flush, + btb_pre_error_flush_target } = br_bus; + +wire [31:0] fs_inst; +reg [31:0] fs_pc; + +reg [37:0] btb_lock_buffer; +reg btb_lock_en; + +assign fs_to_ds_bus = {btb_ret_pc_t, //108:77 + btb_index_t, //76:72 + btb_taken_t, //71:71 + btb_en_t, //70:70 + icache_miss, //69:69 + excp, //68:68 + excp_num, //67:64 + fs_inst, //63:32 + fs_pc //31:0 + }; + +assign flush_sign = ertn_flush || excp_flush || refetch_flush || icacop_flush || idle_flush; + +assign flush_inst_delay = flush_sign && !inst_addr_ok || idle_flush; +assign flush_inst_go_dirt = flush_sign && inst_addr_ok && !idle_flush; + +//flush state machine +reg [31:0] flush_inst_req_buffer; +reg flush_inst_req_state; +localparam flush_inst_req_empty = 1'b0; +localparam flush_inst_req_full = 1'b1; + +always @(posedge clk) begin + if (reset) begin + flush_inst_req_state <= flush_inst_req_empty; + end + else case (flush_inst_req_state) + flush_inst_req_empty: begin + if(flush_inst_delay) begin + flush_inst_req_buffer <= nextpc; + flush_inst_req_state <= flush_inst_req_full; + end + end + flush_inst_req_full: begin + if(pfs_ready_go) begin + flush_inst_req_state <= flush_inst_req_empty; + end + else if (flush_sign) begin + flush_inst_req_buffer <= nextpc; + end + end + endcase +end + +assign fetch_btb_target = (btb_taken && btb_en) || (btb_lock_en && btb_lock_buffer[37]); + +/* +* idle lock +* when idle inst commit, stop inst fetch until interrupted +*/ +always @(posedge clk) begin + if (reset) begin + idle_lock <= 1'b0; + end + else if (idle_flush && !has_int) begin + idle_lock <= 1'b1; + end + else if (has_int) begin + idle_lock <= 1'b0; + end +end + +/* +* br state machine +* when btb pre error, id stage will cancel one inst. so need confirm useless +* inst (will be canceled) is generated. +*/ +reg [31:0] br_target_inst_req_buffer; +reg [ 2:0] br_target_inst_req_state; +localparam br_target_inst_req_empty = 3'b001; +localparam br_target_inst_req_wait_slot = 3'b010; +localparam br_target_inst_req_wait_br_target = 3'b100; + +always @(posedge clk) begin + if (reset) begin + br_target_inst_req_state <= br_target_inst_req_empty; + end + else case (br_target_inst_req_state) + br_target_inst_req_empty: begin + if (flush_sign) begin + br_target_inst_req_state <= br_target_inst_req_empty; + end + else if(btb_pre_error_flush && !fs_valid && !inst_addr_ok) begin + br_target_inst_req_state <= br_target_inst_req_wait_slot; + br_target_inst_req_buffer <= btb_pre_error_flush_target; + end + else if(btb_pre_error_flush && !inst_addr_ok && fs_valid || btb_pre_error_flush && inst_addr_ok && !fs_valid) begin + br_target_inst_req_state <= br_target_inst_req_wait_br_target; + br_target_inst_req_buffer <= btb_pre_error_flush_target; + end + end + br_target_inst_req_wait_slot: begin + if(flush_sign) begin + br_target_inst_req_state <= br_target_inst_req_empty; + end + else if(pfs_ready_go) begin + br_target_inst_req_state <= br_target_inst_req_wait_br_target; + end + end + br_target_inst_req_wait_br_target: begin + if(pfs_ready_go || flush_sign) begin + br_target_inst_req_state <= br_target_inst_req_empty; + end + end + default: begin + br_target_inst_req_state <= br_target_inst_req_empty; + end + endcase +end + +/* +* btb lock +* btb ret only maintain one clock +* when pfs not ready go, should buffer btb ret +*/ +always @(posedge clk) begin + if (reset || flush_sign || fetch_en) + btb_lock_en <= 1'b0; + else if (btb_en && !pfs_ready_go) begin + btb_lock_en <= 1'b1; + btb_lock_buffer <= {btb_taken, btb_index, btb_ret_pc}; + end +end + +assign btb_ret_pc_t = {32{btb_lock_en}} & btb_lock_buffer[31:0] | btb_ret_pc; +assign btb_index_t = {5{btb_lock_en}} & btb_lock_buffer[36:32] | btb_index; +assign btb_taken_t = btb_lock_en && btb_lock_buffer[37] || btb_taken; +assign btb_en_t = btb_lock_en || btb_en; + +// pre-IF stage +assign pfs_ready_go = (inst_valid || pfs_excp) && inst_addr_ok; +assign to_fs_valid = ~reset && pfs_ready_go; +assign seq_pc = fs_pc + 32'h4; +assign excp_entry = {32{excp_tlbrefill}} & csr_tlbrentry | + {32{!excp_tlbrefill}} & csr_eentry ; + +assign inst_flush_pc = {32{ertn_flush}} & csr_era | + {32{refetch_flush || icacop_flush || idle_flush}} & (ws_pc + 32'h4) ; + +assign nextpc = (flush_inst_req_state == flush_inst_req_full) ? flush_inst_req_buffer : + excp_flush ? excp_entry : + (ertn_flush || refetch_flush || icacop_flush || idle_flush) ? inst_flush_pc : + (br_target_inst_req_state == br_target_inst_req_wait_br_target) ? br_target_inst_req_buffer : + btb_pre_error_flush && fs_valid ? btb_pre_error_flush_target: + fetch_btb_target ? btb_ret_pc_t : + seq_pc ; +/* +*when encounter tlb excp, stop inst fetch until excp_flush. avoid fetch useless inst. +*but should not lock when btb state machine or flush state machine is work. +*/ +assign tlb_excp_lock_pc = tlb_excp_cancel_req && br_target_inst_req_state != br_target_inst_req_wait_br_target && flush_inst_req_state != flush_inst_req_full; + +//when flush_sign meet icache_busy 1, flush_sign's inst valid should not set immediately +assign inst_valid = (fs_allowin && !pfs_excp && !tlb_excp_lock_pc || flush_sign || btb_pre_error_flush) && !(idle_flush || idle_lock); +assign inst_op = 1'b0; +assign inst_wstrb = 4'h0; +assign inst_addr = nextpc; //nextpc +assign inst_wdata = 32'b0; + +assign fs_inst = (inst_buff_enable) ? inst_rd_buff : inst_rdata; + +//inst read buffer use for stall situation +always @(posedge clk) begin + if (reset || (fs_ready_go && ds_allowin) || flush_sign) begin + inst_buff_enable <= 1'b0; + end + else if ((inst_data_ok) && !ds_allowin) begin + inst_rd_buff <= inst_rdata; + inst_buff_enable <= 1'b1; + end +end + +//exception +assign pfs_excp_adef = (nextpc[0] || nextpc[1]); //word align +//tlb +assign fs_excp_tlbr = !inst_tlb_found && inst_addr_trans_en; +assign fs_excp_pif = !inst_tlb_v && inst_addr_trans_en; +assign fs_excp_ppi = (csr_plv > inst_tlb_plv) && inst_addr_trans_en; + +assign tlb_excp_cancel_req = fs_excp_tlbr || fs_excp_pif || fs_excp_ppi; + +assign pfs_excp = pfs_excp_adef; +assign pfs_excp_num = {pfs_excp_adef}; + +assign excp = fs_excp || fs_excp_tlbr || fs_excp_pif || fs_excp_ppi ; +assign excp_num = {fs_excp_ppi, fs_excp_pif, fs_excp_tlbr, fs_excp_num}; + +//addr trans +assign inst_addr_trans_en = pg_mode && !dmw0_en && !dmw1_en; + +//addr dmw trans //TOT +assign dmw0_en = ((csr_dmw0[`PLV0] && csr_plv == 2'd0) || (csr_dmw0[`PLV3] && csr_plv == 2'd3)) && (fs_pc[31:29] == csr_dmw0[`VSEG]) && pg_mode; +assign dmw1_en = ((csr_dmw1[`PLV0] && csr_plv == 2'd0) || (csr_dmw1[`PLV3] && csr_plv == 2'd3)) && (fs_pc[31:29] == csr_dmw1[`VSEG]) && pg_mode; + +//uncache judgement +assign da_mode = csr_da && !csr_pg; +assign pg_mode = csr_pg && !csr_da; + +assign inst_uncache_en = (da_mode && (csr_datf == 2'b0)) || + (dmw0_en && (csr_dmw0[`DMW_MAT] == 2'b0)) || + (dmw1_en && (csr_dmw1[`DMW_MAT] == 2'b0)) || + (inst_addr_trans_en && (inst_tlb_mat == 2'b0)) || + disable_cache; + +//assign inst_uncache_en = 1'b1; //used for debug + +// IF stage +assign fs_ready_go = inst_data_ok || inst_buff_enable || excp; +assign fs_allowin = !fs_valid || fs_ready_go && ds_allowin; +assign fs_to_ds_valid = fs_valid && fs_ready_go; +always @(posedge clk) begin + if (reset || flush_inst_delay) begin + fs_valid <= 1'b0; + end + else if (fs_allowin) begin + fs_valid <= to_fs_valid; + end + + if (reset) begin + fs_pc <= 32'h1bfffffc; //trick: to make nextpc be 0x1c000000 during reset + fs_excp <= 1'b0; + fs_excp_num <= 4'b0; + end + else if (to_fs_valid && (fs_allowin || flush_inst_go_dirt)) begin + fs_pc <= nextpc; + fs_excp <= pfs_excp; + fs_excp_num <= pfs_excp_num; + end +end + +//go btb and tlb +assign fetch_pc = nextpc; +assign fetch_en = inst_valid && inst_addr_ok; + +endmodule diff --git a/rtl/ip/open-la500/lacc_core.v b/rtl/ip/open-la500/lacc_core.v new file mode 100644 index 0000000..4e6b4b3 --- /dev/null +++ b/rtl/ip/open-la500/lacc_core.v @@ -0,0 +1,53 @@ +`include "mycpu.h" +`include "csr.h" + +`ifdef HAS_LACC +module lacc_core( + input clk, + input reset, + + input lacc_flush, + + input lacc_req_valid, + input [`LACC_OP_WIDTH-1: 0] lacc_req_command, + input [6: 0] lacc_req_imm, + input [31: 0] lacc_req_rj, + input [31: 0] lacc_req_rk, + + output lacc_rsp_valid, + output [31: 0] lacc_rsp_rdat, + + // wreq will also send valid sign + output lacc_data_valid, + input lacc_data_ready, + output [31: 0] lacc_data_addr, + output lacc_data_read, + output [31: 0] lacc_data_wdata, + output [1: 0] lacc_data_size, + + input lacc_drsp_valid, + input [31: 0] lacc_drsp_rdata +); + + lacc_demo demo( + .clk(clk), + .reset(reset), + .lacc_flush (lacc_flush), + .lacc_req_valid (lacc_req_valid), + .lacc_req_command(lacc_req_command), + .lacc_req_imm (lacc_req_imm), + .lacc_req_rj (lacc_req_rj), + .lacc_req_rk (lacc_req_rk), + .lacc_rsp_valid (lacc_rsp_valid), + .lacc_rsp_rdat (lacc_rsp_rdat), + .lacc_data_valid(lacc_data_valid), + .lacc_data_ready(lacc_data_ready), + .lacc_data_addr (lacc_data_addr), + .lacc_data_read (lacc_data_read), + .lacc_data_wdata(lacc_data_wdata), + .lacc_data_size (lacc_data_size), + .lacc_drsp_valid(lacc_drsp_valid), + .lacc_drsp_rdata(lacc_drsp_rdata) + ); +endmodule +`endif \ No newline at end of file diff --git a/rtl/ip/open-la500/lacc_demo.v b/rtl/ip/open-la500/lacc_demo.v new file mode 100644 index 0000000..d09a09b --- /dev/null +++ b/rtl/ip/open-la500/lacc_demo.v @@ -0,0 +1,166 @@ + + +module lacc_demo( + input clk, + input reset, + + input lacc_flush, + + input lacc_req_valid, + input [`LACC_OP_WIDTH-1: 0] lacc_req_command, + input [6: 0] lacc_req_imm, + input [31: 0] lacc_req_rj, + input [31: 0] lacc_req_rk, + + output lacc_rsp_valid, + output [31: 0] lacc_rsp_rdat, + + output lacc_data_valid, + input lacc_data_ready, + output [31: 0] lacc_data_addr, + output lacc_data_read, + output [31: 0] lacc_data_wdata, + output [1: 0] lacc_data_size, + + input lacc_drsp_valid, + input [31: 0] lacc_drsp_rdata +); + + wire op_lmadd; + wire op_cfg; + + reg [31: 0] req_addr1, req_addr2, waddr; + reg [6: 0] req_size; + wire [31: 0] nxt_req_addr1, nxt_req_addr2, req_addr1_n4, req_addr2_n4; + wire [31: 0] nxt_waddr, waddr_n4; + wire [6: 0] nxt_req_size, req_size_p1; + wire req_addr1_en, req_addr2_en, req_size_en, waddr_en; + wire req_size_nz = |req_size; + + reg [31: 0] conv_data; + wire [31: 0] add_data; + /********************************* + * func: + * rj and rk are addr + * read from rj and rk and add them + * write back to waddr + * then write add res to rd + **********************************/ + assign op_lmadd = lacc_req_command == 0; + // rj is size of read, rk is waddr + assign op_cfg = lacc_req_command == 1; + + + parameter FSM_WIDTH = 2; + parameter IDLE = 'b0; + parameter REQ_ADDR1 = 'b1; + parameter REQ_ADDR2 = 'd2; + parameter FINAL = 'd3; + reg [FSM_WIDTH-1: 0] state_r; + wire [FSM_WIDTH-1: 0] state_n; + wire [FSM_WIDTH-1: 0] state_final_n; + wire state_idle = state_r == IDLE; + wire state_req_addr1 = state_r == REQ_ADDR1; + wire state_req_addr2 = state_r == REQ_ADDR2; + wire state_final = state_r == FINAL; + wire data_hsk = lacc_data_valid & lacc_data_ready; + wire idle_exit = state_idle & lacc_req_valid & op_lmadd & req_size_nz; + wire req_addr1_exit = state_req_addr1 & data_hsk; + wire req_addr2_exit = state_req_addr2 & data_hsk; + wire final_exit = state_final & data_hsk; + wire exit2idle = final_exit & ~req_size_nz; + + assign state_final_n = ~req_size_nz ? IDLE : REQ_ADDR1; + + wire state_en = idle_exit | req_addr1_exit | req_addr2_exit | final_exit; + assign state_n = {FSM_WIDTH{idle_exit}} & REQ_ADDR1 | + {FSM_WIDTH{req_addr1_exit}} & REQ_ADDR2 | + {FSM_WIDTH{req_addr2_exit}} & FINAL | + {FSM_WIDTH{final_exit}} & state_final_n; + + + + assign req_addr1_en = state_idle & lacc_req_valid & op_lmadd | req_addr1_exit; + assign req_addr2_en = state_idle & lacc_req_valid & op_lmadd | req_addr2_exit; + assign req_size_en = lacc_req_valid & op_cfg | req_addr2_exit; + assign waddr_en = lacc_req_valid & op_cfg | final_exit; + assign req_addr1_n4 = req_addr1 + 4; + assign req_addr2_n4 = req_addr2 + 4; + assign req_size_p1 = req_size - 1; + assign waddr_n4 = waddr + 4; + assign nxt_req_addr1 = {32{lacc_req_valid & state_idle & op_lmadd}} & lacc_req_rj | + {32{req_addr1_exit}} & req_addr1_n4; + assign nxt_req_addr2 = {32{lacc_req_valid & state_idle & op_lmadd}} & lacc_req_rk | + {32{req_addr2_exit}} & req_addr2_n4; + assign nxt_req_size = {7{lacc_req_valid & op_cfg}} & lacc_req_rj | + {7{req_addr2_exit}} & req_size_p1; + assign nxt_waddr = {32{lacc_req_valid & op_cfg}} & lacc_req_rk | + {32{final_exit}} & waddr_n4; + + reg data_req; + wire data_req_en; + wire nxt_data_req; + + assign data_req_en = idle_exit | req_addr1_exit | req_addr2_exit | final_exit; + assign nxt_data_req = ~exit2idle & ~req_addr2_exit; + + reg buffer_valid, wdata_valid, wdata_valid_n; + reg [31: 0] buffer_data; + reg [31: 0] buffer_wdata; + + always @(posedge clk)begin + if(req_addr1_en) req_addr1 <= nxt_req_addr1; + if(req_addr2_en) req_addr2 <= nxt_req_addr2; + if(waddr_en) waddr <= nxt_waddr; + if(~buffer_valid) buffer_data <= lacc_drsp_rdata; + if(buffer_valid & lacc_drsp_valid) begin + buffer_wdata <= lacc_drsp_rdata + buffer_data; + end + wdata_valid_n <= wdata_valid; + if(reset | lacc_flush)begin + req_size <= 7'b0; + state_r <= IDLE; + data_req <= 1'b0; + buffer_valid <= 1'b0; + wdata_valid <= 1'b0; + end + else begin + if(req_size_en) req_size <= nxt_req_size; + if(state_en) state_r <= state_n; + if(data_req_en) data_req <= nxt_data_req; + + if(final_exit) buffer_valid <= 1'b0; + else if(lacc_drsp_valid & ~wdata_valid_n) buffer_valid <= 1'b1; + + if(final_exit) wdata_valid <= 1'b0; + else if(buffer_valid & lacc_drsp_valid) wdata_valid <= 1'b1; + end + end + + assign lacc_data_valid = data_req | wdata_valid; + assign lacc_data_read = ~wdata_valid; + assign lacc_data_addr = {32{state_req_addr1}} & req_addr1 | + {32{state_req_addr2}} & req_addr2 | + {32{state_final}} & waddr; + assign lacc_data_size = 2'b10; + assign lacc_data_wdata = buffer_wdata; + + + assign add_data = conv_data + lacc_drsp_rdata; + + always @(posedge clk)begin + if(idle_exit)begin + conv_data <= 0; + end + else begin + if(lacc_drsp_valid)begin + conv_data <= add_data; + end + end + end + + assign lacc_rsp_valid = exit2idle | lacc_req_valid & state_idle & ((op_lmadd & ~req_size_nz) | op_cfg); + assign lacc_rsp_rdat = conv_data; + + +endmodule \ No newline at end of file diff --git a/rtl/ip/open-la500/mem_stage.v b/rtl/ip/open-la500/mem_stage.v new file mode 100644 index 0000000..ebeacf8 --- /dev/null +++ b/rtl/ip/open-la500/mem_stage.v @@ -0,0 +1,368 @@ +`include "mycpu.h" +`include "csr.h" + +module mem_stage( + input clk , + input reset , + //allowin + input ws_allowin , + output ms_allowin , + //from es + input es_to_ms_valid, + input [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus , + //to ws + output ms_to_ws_valid, + output [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus , + //to ds forward path + output [`MS_TO_DS_FORWARD_BUS-1:0] ms_to_ds_forward_bus, + output ms_to_ds_valid, + //div mul + input [31:0] div_result , + input [31:0] mod_result , + input [63:0] mul_result , + //exception + input excp_flush , + input ertn_flush , + input refetch_flush , + input icacop_flush , + //idle + input idle_flush , + //tlb ins + output tlb_inst_stall, + //to es + output ms_wr_tlbehi , + output ms_flush , + //from cache + input data_data_ok , + input dcache_miss , + input [31:0] data_rdata , + //to cache + output data_uncache_en, + output tlb_excp_cancel_req, + output sc_cancel_req , + //from csr + input csr_pg , + input csr_da , + input [31:0] csr_dmw0 , + input [31:0] csr_dmw1 , + input [ 1:0] csr_plv , + input [ 1:0] csr_datm , + input disable_cache , + input [27:0] lladdr , + // from addr trans for difftest + input [ 7:0] data_index_diff , + input [19:0] data_tag_diff , + input [ 3:0] data_offset_diff , + //to addr trans + output data_addr_trans_en, + output dmw0_en , + output dmw1_en , + output cacop_op_mode_di , + //tlb + input data_tlb_found , + input [ 4:0] data_tlb_index , + input data_tlb_v , + input data_tlb_d , + input [ 1:0] data_tlb_mat , + input [ 1:0] data_tlb_plv , + input [19:0] data_tlb_ppn +); + +reg ms_valid; +wire ms_ready_go; + +wire dep_need_stall; +reg [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus_r; +wire [ 3:0] ms_mul_div_op; +wire [ 1:0] sram_addr_low2bit; +wire [ 1:0] ms_mem_size; +wire ms_load_op; +wire ms_gr_we; +wire [ 4:0] ms_dest; +wire [31:0] ms_exe_result; +wire [31:0] ms_pc; +wire ms_excp; +wire [ 9:0] ms_excp_num; +wire ms_ertn; +wire [31:0] ms_csr_result; +wire [13:0] ms_csr_idx; +wire ms_csr_we; +wire ms_ll_w; +wire ms_sc_w; +wire ms_store_op; +wire ms_tlbsrch; +wire ms_tlbfill; +wire ms_tlbwr; +wire ms_tlbrd; +wire ms_refetch; +wire ms_invtlb; +wire [ 9:0] ms_invtlb_asid; +wire [18:0] ms_invtlb_vpn; +wire ms_mem_sign_exted; +wire ms_icacop_op_en; +wire ms_br_inst; +wire ms_icache_miss; +wire ms_br_pre; +wire ms_br_pre_error; +wire ms_preld_inst; +wire ms_cacop; +wire ms_idle; +wire [31:0] ms_error_va; + +// difftest +wire ms_cnt_inst ; +wire [63:0] ms_timer_64 ; +wire [31:0] ms_inst ; +wire [ 7:0] ms_inst_ld_en ; +wire [31:0] ms_ld_paddr ; +wire [31:0] ms_ld_vaddr ; +wire [ 7:0] ms_inst_st_en ; +wire [31:0] ms_st_data ; +wire ms_csr_rstat_en ; +wire [31:0] ms_csr_data ; + +assign {ms_csr_data , //424:393 for difftest + ms_csr_rstat_en , //392:392 for difftest + ms_st_data , //391:360 for difftest + ms_inst_st_en , //359:352 for difftest + ms_ld_vaddr , //351:320 for difftest + ms_inst_ld_en , //319:312 for difftest + ms_cnt_inst , //311:311 for difftest + ms_timer_64 , //310:247 for difftest + ms_inst , //246:215 for difftest + ms_error_va , //214:183 + ms_idle , //182:182 + ms_cacop , //181:181 + ms_preld_inst , //180:180 + ms_br_pre_error , //179:179 + ms_br_pre , //178:178 + ms_icache_miss , //177:177 + ms_br_inst , //176:176 + ms_icacop_op_en , //175:175 + ms_mem_sign_exted, //174:174 + ms_invtlb_vpn , //173:155 + ms_invtlb_asid , //154:145 + ms_invtlb , //144:144 + ms_tlbrd , //143:143 + ms_refetch , //142:142 + ms_tlbfill , //141:141 + ms_tlbwr , //140:140 + ms_tlbsrch , //139:139 + ms_store_op , //138:138 + ms_sc_w , //137:137 + ms_ll_w , //136:136 + ms_excp_num , //135:126 + ms_csr_we , //125:125 + ms_csr_idx , //124:111 + ms_csr_result , //110:79 + ms_ertn , //78:78 + ms_excp , //77:77 + ms_mem_size , //76:75 + ms_mul_div_op , //74:71 + ms_load_op , //70:70 + ms_gr_we , //69:69 + ms_dest , //68:64 + ms_exe_result , //63:32 + ms_pc //31:0 + } = es_to_ms_bus_r; + +wire [31:0] mem_result; +wire [31:0] ms_final_result; +wire flush_sign; + +wire [31:0] ms_rdata; +reg [31:0] data_rd_buff; +reg data_buff_enable; + +wire access_mem; + +wire [ 4:0] cacop_op; +wire [ 1:0] cacop_op_mode; + +wire forward_enable; +wire dest_zero; + +wire [31:0] paddr; + +wire [15:0] excp_num; +wire excp; + +wire excp_tlbr; +wire excp_pil ; +wire excp_pis ; +wire excp_pme ; +wire excp_ppi ; + +wire da_mode ; +wire pg_mode ; + +wire sc_addr_eq; + +assign ms_to_ws_bus = {ms_csr_data , //492:461 for difftest + ms_csr_rstat_en, //460:460 for difftest + ms_st_data , //459:428 for difftest + ms_inst_st_en , //427:420 for difftest + ms_ld_vaddr , //419:388 for difftest + ms_ld_paddr , //387:356 for difftest + ms_inst_ld_en , //355:348 for difftest + ms_cnt_inst , //347:347 for difftest + ms_timer_64 , //346:283 for difftest + ms_inst , //282:251 for difftest + data_uncache_en, //250:250 + paddr , //249:218 + ms_idle , //217:217 + ms_br_pre_error, //216:216 + ms_br_pre , //215:215 + dcache_miss , //214:214 + access_mem , //213:213 + ms_icache_miss , //212:212 + ms_br_inst , //211:211 + ms_icacop_op_en, //210:210 + ms_invtlb_vpn , //209:191 + ms_invtlb_asid , //190:181 + ms_invtlb , //180:180 + ms_tlbrd , //179:179 + ms_refetch , //178:178 + ms_tlbfill , //177:177 + ms_tlbwr , //176:176 + data_tlb_index , //175:171 + data_tlb_found , //170:170 + ms_tlbsrch , //169:169 + ms_error_va , //168:137 + ms_sc_w , //136:136 + ms_ll_w , //135:135 + excp_num , //134:119 + ms_csr_we , //118:118 + ms_csr_idx , //117:104 + ms_csr_result , //103:72 + ms_ertn , //71:71 + excp , //70:70 + ms_gr_we , //69:69 + ms_dest , //68:64 + ms_final_result, //63:32 + ms_pc //31:0 + }; + +assign ms_to_ds_valid = ms_valid; + +//cache inst need wait data_data_ok signal +assign ms_ready_go = (data_data_ok || data_buff_enable) || !access_mem || excp || sc_cancel_req; +assign ms_allowin = !ms_valid || ms_ready_go && ws_allowin; +assign ms_to_ws_valid = ms_valid && ms_ready_go; +always @(posedge clk) begin + if (reset || flush_sign) begin + ms_valid <= 1'b0; + end + else if (ms_allowin) begin + ms_valid <= es_to_ms_valid; + end + + if (es_to_ms_valid && ms_allowin) begin + es_to_ms_bus_r <= es_to_ms_bus; + end +end + +assign access_mem = ms_store_op || ms_load_op; + +assign flush_sign = excp_flush || ertn_flush || refetch_flush || icacop_flush || idle_flush; + +assign ms_rdata = data_buff_enable ? data_rd_buff : data_rdata; + +assign sram_addr_low2bit = {ms_exe_result[1], ms_exe_result[0]}; + +wire [7:0] mem_byteLoaded = ({8{sram_addr_low2bit==2'b00}} & ms_rdata[ 7: 0]) | + ({8{sram_addr_low2bit==2'b01}} & ms_rdata[15: 8]) | + ({8{sram_addr_low2bit==2'b10}} & ms_rdata[23:16]) | + ({8{sram_addr_low2bit==2'b11}} & ms_rdata[31:24]) ; + + +wire [15:0] mem_halfLoaded = ({16{sram_addr_low2bit==2'b00}} & ms_rdata[15: 0]) | + ({16{sram_addr_low2bit==2'b10}} & ms_rdata[31:16]) ; + +assign mem_result = ({32{ms_mem_size[0] && ms_mem_sign_exted}} & {{24{mem_byteLoaded[ 7]}}, mem_byteLoaded}) | + ({32{ms_mem_size[0] && ~ms_mem_sign_exted}} & { 24'b0 , mem_byteLoaded}) | + ({32{ms_mem_size[1] && ms_mem_sign_exted}} & {{16{mem_halfLoaded[15]}}, mem_halfLoaded}) | + ({32{ms_mem_size[1] && ~ms_mem_sign_exted}} & { 16'b0 , mem_halfLoaded}) | + ({32{!ms_mem_size}} & ms_rdata ) ; + +assign ms_final_result = ({32{ms_load_op }} & mem_result ) | + ({32{ms_mul_div_op[0]}} & mul_result[31:0] ) | + ({32{ms_mul_div_op[1]}} & mul_result[63:32]) | + ({32{ms_mul_div_op[2]}} & div_result ) | + ({32{ms_mul_div_op[3]}} & mod_result ) | + ({32{!ms_mul_div_op && !ms_load_op}} & (ms_exe_result&{32{!sc_cancel_req}})); + +assign dest_zero = (ms_dest == 5'b0); +assign forward_enable = ms_gr_we & ~dest_zero & ms_valid; +assign dep_need_stall = ms_load_op && !ms_to_ws_valid; +assign ms_to_ds_forward_bus = {dep_need_stall, //38:38 + forward_enable, //37:37 + ms_dest , //36:32 + ms_final_result //31:0 + }; + +//addr trans +assign pg_mode = !csr_da && csr_pg; +//uncache judgement +assign da_mode = csr_da && !csr_pg; + +assign data_addr_trans_en = pg_mode && !dmw0_en && !dmw1_en && !cacop_op_mode_di; + +assign paddr = {data_tlb_ppn, ms_error_va[11:0]}; + +assign sc_addr_eq = (lladdr == paddr[31:4]); +assign sc_cancel_req = (!sc_addr_eq||data_uncache_en) && ms_sc_w && access_mem; + +//addr dmw trans +assign dmw0_en = ((csr_dmw0[`PLV0] && csr_plv == 2'd0) || (csr_dmw0[`PLV3] && csr_plv == 2'd3)) && (ms_error_va[31:29] == csr_dmw0[`VSEG]) && pg_mode; +assign dmw1_en = ((csr_dmw1[`PLV0] && csr_plv == 2'd0) || (csr_dmw1[`PLV3] && csr_plv == 2'd3)) && (ms_error_va[31:29] == csr_dmw1[`VSEG]) && pg_mode; + +assign excp = excp_tlbr || excp_pil || excp_pis || excp_ppi || excp_pme || ms_excp; +assign excp_num = {excp_pil, excp_pis, excp_ppi, excp_pme, excp_tlbr, 1'b0, ms_excp_num}; + +//tlb exception //preld should not generate these excp +assign excp_tlbr = (access_mem || ms_cacop) && !data_tlb_found && data_addr_trans_en; +assign excp_pil = (ms_load_op || ms_cacop) && !data_tlb_v && data_addr_trans_en; //cache will generate pil exception?? +assign excp_pis = ms_store_op && !data_tlb_v && data_addr_trans_en; +assign excp_ppi = access_mem && data_tlb_v && (csr_plv > data_tlb_plv) && data_addr_trans_en; +assign excp_pme = ms_store_op && data_tlb_v && (csr_plv <= data_tlb_plv) && !data_tlb_d && data_addr_trans_en; + +assign tlb_excp_cancel_req = excp_tlbr || excp_pil || excp_pis || excp_ppi || excp_pme; + +assign data_uncache_en = (da_mode && (csr_datm == 2'b0)) || + (dmw0_en && (csr_dmw0[`DMW_MAT] == 2'b0)) || + (dmw1_en && (csr_dmw1[`DMW_MAT] == 2'b0)) || + (data_addr_trans_en && (data_tlb_mat == 2'b0)) || + disable_cache; + +assign ms_flush = (excp | ms_ertn | (ms_csr_we | (ms_ll_w | ms_sc_w) & !excp) | ms_refetch | ms_idle) & ms_valid; + +assign tlb_inst_stall = (ms_tlbsrch || ms_tlbrd) && ms_valid; + +always @(posedge clk) begin + if (reset || (ms_ready_go && ws_allowin) || flush_sign) begin + data_rd_buff <= 32'b0; + data_buff_enable <= 1'b0; + end + else if (data_data_ok && !ws_allowin) begin + data_rd_buff <= data_rdata; + data_buff_enable <= 1'b1; + end +end + +assign ms_wr_tlbehi = ms_csr_we && (ms_csr_idx == 14'h11) && ms_valid; //stall es tlbsrch + +assign cacop_op = ms_dest; +assign cacop_op_mode = cacop_op[4:3]; +assign cacop_op_mode_di = ms_cacop && ((cacop_op_mode == 2'b0) || (cacop_op_mode == 2'b1)); + +reg [ 7:0] tmp_data_index ; +reg [ 3:0] tmp_data_offset ; +always @(posedge clk) begin + tmp_data_index <= data_index_diff; + tmp_data_offset <= data_offset_diff; +end + +assign ms_ld_paddr = {data_tag_diff, tmp_data_index, tmp_data_offset}; + +endmodule diff --git a/rtl/ip/open-la500/mul.v b/rtl/ip/open-la500/mul.v new file mode 100644 index 0000000..9aa9e7e --- /dev/null +++ b/rtl/ip/open-la500/mul.v @@ -0,0 +1,197 @@ +module YDecoder( + input yc, yb, ya, //c -> i+1; b -> i; a -> i-1 + output negx, x, neg2x, _2x + ); + +assign negx = (yc & yb & ~ya) | (yc & ~yb & ya); +assign x = (~yc & ~yb & ya) | (~yc & yb & ~ya); +assign neg2x = (yc & ~yb & ~ya); +assign _2x = (~yc & yb & ya); + +endmodule + + +module BoothBase( + input negx, x, neg2x, _2x, + input InX, + input PosLastX, NegLastX, + output PosNextX, NegNextX, + output OutX + ); + +assign OutX = (negx & ~InX) | (x & InX) | (neg2x & NegLastX) | (_2x & PosLastX); +assign PosNextX = InX; +assign NegNextX = ~InX; + +endmodule + + +module BoothInterBase( + input [2:0] y, + input [63:0] InX, + output [63:0] OutX, + output Carry +); + +wire negx, x, neg2x, _2x; +wire [1:0] CarrySig [64:0]; + +YDecoder uu(.yc(y[2]), .yb(y[1]), .ya(y[0]), .negx(negx), .x(x), .neg2x(neg2x), ._2x(_2x)); + +BoothBase fir(.negx(negx), .x(x), .neg2x(neg2x), ._2x(_2x), .InX(InX[0]), .PosLastX(1'b0), .NegLastX(1'b1), .PosNextX(CarrySig[1][0]), .NegNextX(CarrySig[1][1]), .OutX(OutX[0])); + +generate + genvar i; + for (i=1; i<64; i=i+1) begin: gfor + BoothBase ui( + .negx(negx), + .x(x), + .neg2x(neg2x), + ._2x(_2x), + .InX(InX[i]), + .PosLastX(CarrySig[i][0]), + .NegLastX(CarrySig[i][1]), + .PosNextX(CarrySig[i+1][0]), + .NegNextX(CarrySig[i+1][1]), + .OutX(OutX[i]) + ); + end +endgenerate + +assign Carry = negx || neg2x; + +endmodule + + +module addr( + input A, B, C, + output Carry, S + ); + +assign S = ~A & ~B & C | ~A & B & ~C | A & ~B & ~C | A & B & C; +assign Carry = A & B | A & C | B & C; + +endmodule + + +module WallaceTreeBase( + input [16:0] InData, + input [13:0] CIn, + output [13:0] COut, + output C, S + ); + +//first stage +wire [4:0] FirSig; +addr first1(.A(InData[4]), .B(InData[3]), .C(InData[2]), .Carry(COut[0]), .S(FirSig[0])); +addr first2(.A(InData[7]), .B(InData[6]), .C(InData[5]), .Carry(COut[1]), .S(FirSig[1])); +addr first3(.A(InData[10]), .B(InData[9]), .C(InData[8]), .Carry(COut[2]), .S(FirSig[2])); +addr first4(.A(InData[13]), .B(InData[12]), .C(InData[11]), .Carry(COut[3]), .S(FirSig[3])); +addr first5(.A(InData[16]), .B(InData[15]), .C(InData[14]), .Carry(COut[4]), .S(FirSig[4])); + +//second stage +wire [3:0] SecSig; +addr second1(.A(CIn[2]), .B(CIn[1]), .C(CIn[0]), .Carry(COut[5]), .S(SecSig[0])); +addr second2(.A(InData[0]), .B(CIn[4]), .C(CIn[3]), .Carry(COut[6]), .S(SecSig[1])); +addr second3(.A(FirSig[1]), .B(FirSig[0]), .C(InData[1]), .Carry(COut[7]), .S(SecSig[2])); +addr second4(.A(FirSig[4]), .B(FirSig[3]), .C(FirSig[2]), .Carry(COut[8]), .S(SecSig[3])); + +//third stage +wire [1:0] ThiSig; +addr third1(.A(SecSig[0]), .B(CIn[6]), .C(CIn[5]), .Carry(COut[9]), .S(ThiSig[0])); +addr third2(.A(SecSig[3]), .B(SecSig[2]), .C(SecSig[1]), .Carry(COut[10]), .S(ThiSig[1])); + +//fourth stage +wire [1:0] ForSig; +addr fourth1(.A(CIn[9]), .B(CIn[8]), .C(CIn[7]), .Carry(COut[11]), .S(ForSig[0])); +addr fourth2(.A(ThiSig[1]), .B(ThiSig[0]), .C(CIn[10]), .Carry(COut[12]), .S(ForSig[1])); + +//fifth stage +wire FifSig; +addr fifth1(.A(ForSig[1]), .B(ForSig[0]), .C(CIn[11]), .Carry(COut[13]), .S(FifSig)); + +//sixth stage +addr sixth1(.A(FifSig), .B(CIn[13]), .C(CIn[12]), .Carry(C), .S(S)); + +endmodule + +//------------------------------------------------------------------------------------------------------------------- + +module mul( + input mul_clk, reset, + input mul_signed, + input [31:0] x, y, //x扩展至64位 y扩展至33位 区别有无符号 + output [63:0] result + ); + +wire [63:0] CalX; +wire [32:0] CalY; + +assign CalX = mul_signed ? {{32{x[31]}}, x} : {32'b0, x}; +assign CalY = mul_signed ? {y[31], y} : {1'b0, y}; + +//booth +wire [16:0] Carry; //booth计算得到的进位 +wire [63:0] BoothRes [16:0]; //booth的计算结果 +BoothInterBase fir(.y({CalY[1], CalY[0], 1'b0}), .InX(CalX), .OutX(BoothRes[0]), .Carry(Carry[0])); + +generate + genvar i; + for (i=2; i<32; i=i+2) begin: boothfor + BoothInterBase ai( + .y(CalY[i+1:i-1]), + .InX(CalX<>1]), + .Carry(Carry[i>>1]) + ); + end +endgenerate + +BoothInterBase las(.y({CalY[32], CalY[32], CalY[31]}), .InX(CalX<<32), .OutX(BoothRes[16]), .Carry(Carry[16])); + +reg [16:0] SecStageCarry; +reg [63:0] SecStageBoothRes [16:0]; +integer p; + +always @(posedge mul_clk) begin + if (~reset) begin + SecStageCarry <= Carry; + for(p=0; p<17; p=p+1) begin + SecStageBoothRes[p] <= BoothRes[p]; + end + end +end + +//wallace +wire [13:0] WallaceInter [64:0]; +wire [63:0] COut, SOut; + +WallaceTreeBase firs( + .InData({SecStageBoothRes[0][0], SecStageBoothRes[1][0], SecStageBoothRes[2][0], SecStageBoothRes[3][0], SecStageBoothRes[4][0], SecStageBoothRes[5][0], SecStageBoothRes[6][0], + SecStageBoothRes[7][0], SecStageBoothRes[8][0], SecStageBoothRes[9][0], SecStageBoothRes[10][0], SecStageBoothRes[11][0], SecStageBoothRes[12][0], SecStageBoothRes[13][0], SecStageBoothRes[14][0], + SecStageBoothRes[15][0], SecStageBoothRes[16][0]}), + .CIn(SecStageCarry[13:0]), + .COut(WallaceInter[1]), + .C(COut[0]), + .S(SOut[0]) + ); + +generate + genvar n; + for (n=1; n<64; n=n+1) begin: wallacefor + WallaceTreeBase bi( + .InData({SecStageBoothRes[0][n], SecStageBoothRes[1][n], SecStageBoothRes[2][n], SecStageBoothRes[3][n], SecStageBoothRes[4][n], SecStageBoothRes[5][n], SecStageBoothRes[6][n], + SecStageBoothRes[7][n], SecStageBoothRes[8][n], SecStageBoothRes[9][n], SecStageBoothRes[10][n], SecStageBoothRes[11][n], SecStageBoothRes[12][n], SecStageBoothRes[13][n], SecStageBoothRes[14][n], + SecStageBoothRes[15][n], SecStageBoothRes[16][n]}), + .CIn(WallaceInter[n]), + .COut(WallaceInter[n+1]), + .C(COut[n]), + .S(SOut[n]) + ); + end +endgenerate + +//64bit add +assign result = SOut + {COut[62:0], SecStageCarry[14]} + SecStageCarry[15]; + +endmodule diff --git a/rtl/ip/open-la500/mycpu.h b/rtl/ip/open-la500/mycpu.h new file mode 100644 index 0000000..7a84d1c --- /dev/null +++ b/rtl/ip/open-la500/mycpu.h @@ -0,0 +1,32 @@ +`ifndef MYCPU_H + `define MYCPU_H + +// `define BR_BUS_WD 33 //bug5 32->33 +// `define FS_TO_DS_BUS_WD 109 +// `define DS_TO_ES_BUS_WD 236 +// `define ES_TO_MS_BUS_WD 215 +// `define MS_TO_WS_BUS_WD 218 +// `define WS_TO_RF_BUS_WD 38 +// `define ES_TO_DS_FORWARD_BUS 39 +// `define MS_TO_DS_FORWARD_BUS 39 + + // `define HAS_LACC + `define LACC_OP_SIZE 3 + `define LACC_OP_WIDTH $clog2(`LACC_OP_SIZE) + `define BR_BUS_WD 33 //bug5 32->33 + `define FS_TO_DS_BUS_WD 109 + `define DS_TO_ES_BUS_WD (350 \ + `ifdef HAS_LACC \ + +`LACC_OP_WIDTH+1 \ + `endif \ + ) + + `define ES_TO_MS_BUS_WD 425 + + `define MS_TO_WS_BUS_WD 493 + `define WS_TO_RF_BUS_WD 38 + `define ES_TO_DS_FORWARD_BUS 39 + `define MS_TO_DS_FORWARD_BUS 39 +`endif + +//`define SIMU diff --git a/rtl/ip/open-la500/mycpu_top.v b/rtl/ip/open-la500/mycpu_top.v new file mode 100644 index 0000000..64725d6 --- /dev/null +++ b/rtl/ip/open-la500/mycpu_top.v @@ -0,0 +1,1296 @@ +module core_top +#( + parameter TLBNUM = 32 +) +( + input aclk, + input aresetn, + input [ 7:0] intrpt, + //AXI interface + //read reqest + output [ 3:0] arid, + output [31:0] araddr, + output [ 7:0] arlen, + output [ 2:0] arsize, + output [ 1:0] arburst, + output [ 1:0] arlock, + output [ 3:0] arcache, + output [ 2:0] arprot, + output arvalid, + input arready, + //read back + input [ 3:0] rid, + input [31:0] rdata, + input [ 1:0] rresp, + input rlast, + input rvalid, + output rready, + //write request + output [ 3:0] awid, + output [31:0] awaddr, + output [ 7:0] awlen, + output [ 2:0] awsize, + output [ 1:0] awburst, + output [ 1:0] awlock, + output [ 3:0] awcache, + output [ 2:0] awprot, + output awvalid, + input awready, + //write data + output [ 3:0] wid, + output [31:0] wdata, + output [ 3:0] wstrb, + output wlast, + output wvalid, + input wready, + //write back + input [ 3:0] bid, + input [ 1:0] bresp, + input bvalid, + output bready, + + //debug + input break_point, + input infor_flag, + input [ 4:0] reg_num, + output ws_valid, + output [31:0] rf_rdata, + + output [31:0] debug0_wb_pc, + output [ 3:0] debug0_wb_rf_wen, + output [ 4:0] debug0_wb_rf_wnum, + output [31:0] debug0_wb_rf_wdata, + output [31:0] debug0_wb_inst +); +reg reset; +always @(posedge aclk) reset <= ~aresetn; + +wire ds_allowin; +wire es_allowin; +wire ms_allowin; +wire ws_allowin; +wire fs_to_ds_valid; +wire ds_to_es_valid; +wire es_to_ms_valid; +wire ms_to_ws_valid; +wire [31:0] fs_csr_eentry; +wire [31:0] fs_csr_era; +wire [31:0] ws_csr_era; +wire [ 8:0] ws_csr_esubcode; +wire [ 5:0] ws_csr_ecode; +wire [63:0] ds_timer_64; +wire [31:0] ds_csr_tid; +wire [13:0] rd_csr_addr; +wire [31:0] rd_csr_data; +wire [13:0] wr_csr_addr; +wire [31:0] wr_csr_data; +wire [31:0] ws_bad_va; +wire ws_va_error; +wire ds_llbit; +wire [27:0] lladdr_out; +wire ws_llbit; +wire ws_llbit_set; +wire ws_lladdr_set; +wire [27:0] ws_lladdr; +wire has_int; +wire csr_wr_en; +wire excp_flush; +wire ertn_flush; +wire icacop_flush; +wire idle_flush; +wire es_div_enable; +wire es_mul_div_sign; +wire [31:0] es_rj_value; +wire [31:0] es_rkd_value; +wire div_complete; +wire [31:0] div_result; +wire [31:0] mod_result; +wire [63:0] mul_result; +wire [ 9:0] csr_asid; +wire [ 4:0] rand_index; +wire [31:0] tlbw_tlbehi; +wire [31:0] tlbw_tlbelo0; +wire [31:0] tlbw_tlbelo1; +wire [31:0] tlbw_r_tlbidx; +wire [ 5:0] tlbw_ecode; +wire tlbrd_en; +wire [31:0] tlbr_tlbehi; +wire [31:0] tlbr_tlbelo0; +wire [31:0] tlbr_tlbelo1; +wire [31:0] tlbr_tlbidx; +wire [ 9:0] tlbr_asid; +wire invtlb_en; +wire [ 9:0] invtlb_asid; +wire [18:0] invtlb_vpn; +wire [ 4:0] invtlb_op; +wire [18:0] csr_vppn; +wire inst_tlb_found; +wire inst_tlb_v; +wire inst_tlb_d; +wire [ 1:0] inst_tlb_mat; +wire [ 1:0] inst_tlb_plv; +wire data_tlb_found; +wire [ 4:0] data_tlb_index; +wire data_tlb_v; +wire data_tlb_d; +wire [ 1:0] data_tlb_mat; +wire [ 1:0] data_tlb_plv; +wire tlbsrch_en; +wire tlbfill_en; +wire tlbwr_en; +wire refetch_flush; +wire tlbsrch_found; +wire [ 4:0] tlbsrch_index; +wire ms_wr_tlbehi; +wire ms_flush; +wire excp_tlbrefill; +wire [31:0] csr_tlbrentry; +wire csr_pg; +wire csr_da; +wire [31:0] csr_dmw0; +wire [31:0] csr_dmw1; +wire [ 1:0] csr_plv; +wire [ 1:0] csr_datf; +wire [ 1:0] csr_datm; +wire inst_addr_trans_en; +wire data_addr_trans_en; +wire cacop_op_mode_di; +wire excp_tlb; +wire [18:0] excp_tlb_vppn; +wire icacop_op_en; +wire dcacop_op_en; +wire [ 1:0] cacop_op_mode; +wire icache_unbusy; +wire dcache_unbusy; +wire [31:0] fetch_pc; +wire fetch_en; +wire [31:0] btb_ret_pc; +wire btb_taken; +wire btb_en; +wire [ 4:0] btb_index; +wire btb_add_entry; +wire btb_pop_ras; +wire btb_push_ras; +wire btb_operate_en; +wire btb_delete_entry; +wire btb_pre_error; +wire btb_pre_right; +wire btb_target_error; +wire btb_right_orien; +wire [31:0] btb_right_target; +wire [31:0] btb_operate_pc; +wire [ 4:0] btb_operate_index; +wire es_tlb_inst_stall; +wire ms_tlb_inst_stall; +wire ws_tlb_inst_stall; +wire data_fetch; +wire [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus; +wire [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus; +wire [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus; +wire [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus; +wire [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus; +wire [`BR_BUS_WD -1:0] br_bus; +wire [`ES_TO_DS_FORWARD_BUS -1:0] es_to_ds_forward_bus; +wire [`MS_TO_DS_FORWARD_BUS -1:0] ms_to_ds_forward_bus; + +wire [31:0] inst_vaddr; +wire inst_valid; +wire inst_op; +wire [ 7:0] inst_index; +wire [19:0] inst_tag; +wire [ 3:0] inst_offset; +wire [ 3:0] inst_wstrb; +wire [31:0] inst_wdata; +wire inst_addr_ok; +wire inst_data_ok; +wire [31:0] inst_rdata; +wire inst_rd_req; +wire [ 2:0] inst_rd_type; +wire [31:0] inst_rd_addr; +wire inst_rd_rdy; +wire inst_ret_valid; +wire inst_ret_last; +wire [31:0] inst_ret_data; +wire inst_wr_req; +wire [ 2:0] inst_wr_type; +wire [31:0] inst_wr_addr; +wire [ 3:0] inst_wr_wstrb; +wire [127:0] inst_wr_data; +wire inst_wr_rdy; +wire inst_uncache_en; +wire inst_tlb_excp_cancel_req; +wire inst_dmw0_en; +wire inst_dmw1_en; +wire [31:0] data_vaddr; +wire data_valid; +wire data_op; +wire [ 2:0] data_size; +wire [ 7:0] data_index; +wire [19:0] data_tag; +wire [ 3:0] data_offset; +wire [ 3:0] data_wstrb; +wire [31:0] data_wdata; +wire data_addr_ok; +wire data_data_ok; +wire [31:0] data_rdata; +wire data_rd_req; +wire [ 2:0] data_rd_type; +wire [31:0] data_rd_addr; +wire data_rd_rdy; +wire data_ret_valid; +wire data_ret_last; +wire [31:0] data_ret_data; +wire data_wr_req; +wire [ 2:0] data_wr_type; +wire [31:0] data_wr_addr; +wire [ 3:0] data_wr_wstrb; +wire [127:0] data_wr_data; +wire data_wr_rdy; +wire data_uncache_en; +wire data_dmw0_en; +wire data_dmw1_en; +wire data_tlb_excp_cancel_req; +wire sc_cancel_req; +wire dcache_empty; + +wire es_to_ds_valid; +wire ms_to_ds_valid; +wire ws_to_ds_valid; +wire write_buffer_empty; +wire [ 4:0] preld_hint; +wire preld_en; + +wire commit_inst; +wire br_inst; +wire icache_miss; +wire dcache_miss; +wire mem_inst; +wire br_pre; +wire br_pre_error; +wire fs_icache_miss; +wire ms_dcache_miss; +wire disable_cache; + +`ifdef DIFFTEST_EN +// difftest +// from wb_stage +wire ws_valid_diff ; +wire cnt_inst_diff ; +wire [63:0] timer_64_diff ; +wire [ 7:0] inst_ld_en_diff ; +wire [31:0] ld_paddr_diff ; +wire [31:0] ld_vaddr_diff ; +wire [ 7:0] inst_st_en_diff ; +wire [31:0] st_paddr_diff ; +wire [31:0] st_vaddr_diff ; +wire [31:0] st_data_diff ; +wire csr_rstat_en_diff ; +wire [31:0] csr_data_diff ; + +wire inst_valid_diff = ws_valid_diff; +reg cmt_valid ; +reg cmt_cnt_inst ; +reg [63:0] cmt_timer_64 ; +reg [ 7:0] cmt_inst_ld_en ; +reg [31:0] cmt_ld_paddr ; +reg [31:0] cmt_ld_vaddr ; +reg [ 7:0] cmt_inst_st_en ; +reg [31:0] cmt_st_paddr ; +reg [31:0] cmt_st_vaddr ; +reg [31:0] cmt_st_data ; +reg cmt_csr_rstat_en ; +reg [31:0] cmt_csr_data ; + +reg cmt_wen ; +reg [ 7:0] cmt_wdest ; +reg [31:0] cmt_wdata ; +reg [31:0] cmt_pc ; +reg [31:0] cmt_inst ; + +reg cmt_excp_flush ; +reg cmt_ertn ; +reg [5:0] cmt_csr_ecode ; +reg cmt_tlbfill_en ; +reg [4:0] cmt_rand_index ; + +// to difftest debug +reg trap ; +reg [ 7:0] trap_code ; +reg [63:0] cycleCnt ; +reg [63:0] instrCnt ; + +// from regfile +wire [31:0] regs[31:0] ; + +// from csr +wire [31:0] csr_crmd_diff_0 ; +wire [31:0] csr_prmd_diff_0 ; +wire [31:0] csr_ectl_diff_0 ; +wire [31:0] csr_estat_diff_0 ; +wire [31:0] csr_era_diff_0 ; +wire [31:0] csr_badv_diff_0 ; +wire [31:0] csr_eentry_diff_0 ; +wire [31:0] csr_tlbidx_diff_0 ; +wire [31:0] csr_tlbehi_diff_0 ; +wire [31:0] csr_tlbelo0_diff_0 ; +wire [31:0] csr_tlbelo1_diff_0 ; +wire [31:0] csr_asid_diff_0 ; +wire [31:0] csr_save0_diff_0 ; +wire [31:0] csr_save1_diff_0 ; +wire [31:0] csr_save2_diff_0 ; +wire [31:0] csr_save3_diff_0 ; +wire [31:0] csr_tid_diff_0 ; +wire [31:0] csr_tcfg_diff_0 ; +wire [31:0] csr_tval_diff_0 ; +wire [31:0] csr_ticlr_diff_0 ; +wire [31:0] csr_llbctl_diff_0 ; +wire [31:0] csr_tlbrentry_diff_0; +wire [31:0] csr_dmw0_diff_0 ; +wire [31:0] csr_dmw1_diff_0 ; +wire [31:0] csr_pgdl_diff_0 ; +wire [31:0] csr_pgdh_diff_0 ; +`endif + +`ifdef HAS_LACC +wire es_lacc_req; +wire [`LACC_OP_WIDTH-1: 0] es_lacc_command; +wire [31:0] lacc_req_rj; +wire [31:0] lacc_req_rk; +wire lacc_rsp_valid; +wire [31:0] lacc_rsp_rdat; +wire lacc_data_valid; +wire [31:0] lacc_data_addr; +wire lacc_data_read; +wire [31:0] lacc_data_wdata; +wire [ 2:0] lacc_data_size; +wire lacc_drsp_valid; +wire [31:0] lacc_drsp_rdata; +wire [6: 0] lacc_req_imm; +wire lacc_flush; +`endif + +// IF stage +if_stage if_stage( + .clk (aclk ), + .reset (reset ), + //allowin + .ds_allowin (ds_allowin ), + //brbus + .br_bus (br_bus ), + //outputs + .fs_to_ds_valid (fs_to_ds_valid ), + .fs_to_ds_bus (fs_to_ds_bus ), + //exception + .excp_flush (excp_flush ), + .ertn_flush (ertn_flush ), + .refetch_flush (refetch_flush ), + .icacop_flush (icacop_flush ), + .ws_pc (ws_csr_era ), + .csr_eentry (fs_csr_eentry ), + .csr_era (fs_csr_era ), + .excp_tlbrefill (excp_tlbrefill ), + .csr_tlbrentry (csr_tlbrentry ), + .has_int (has_int ), + //idle + .idle_flush (idle_flush ), + // inst cache interface + .inst_valid (inst_valid ), + .inst_op (inst_op ), + .inst_addr (inst_vaddr ), + .inst_wstrb (inst_wstrb ), + .inst_wdata (inst_wdata ), + .inst_addr_ok (inst_addr_ok ), + .inst_data_ok (inst_data_ok ), + .icache_miss (fs_icache_miss ), + .inst_rdata (inst_rdata ), + .inst_uncache_en (inst_uncache_en ), + .tlb_excp_cancel_req (inst_tlb_excp_cancel_req), + //from csr + .csr_pg (csr_pg ), + .csr_da (csr_da ), + .csr_dmw0 (csr_dmw0 ), + .csr_dmw1 (csr_dmw1 ), + .csr_plv (csr_plv ), + .csr_datf (csr_datf ), + .disable_cache (disable_cache ), + //to btb + .fetch_pc (fetch_pc ), + .fetch_en (fetch_en ), + .btb_ret_pc (btb_ret_pc ), + .btb_taken (btb_taken ), + .btb_en (btb_en ), + .btb_index (btb_index ), + //to addr trans + .inst_addr_trans_en(inst_addr_trans_en), + .dmw0_en (inst_dmw0_en ), + .dmw1_en (inst_dmw1_en ), + //tlb + .inst_tlb_found (inst_tlb_found ), + .inst_tlb_v (inst_tlb_v ), + .inst_tlb_d (inst_tlb_d ), + .inst_tlb_mat (inst_tlb_mat ), + .inst_tlb_plv (inst_tlb_plv ) +); +// ID stage +id_stage id_stage( + .clk (aclk ), + .reset (reset ), + //allowin + .es_allowin (es_allowin ), + .ds_allowin (ds_allowin ), + //from fs + .fs_to_ds_valid (fs_to_ds_valid ), + .fs_to_ds_bus (fs_to_ds_bus ), + //from ds forward path + .es_to_ds_forward_bus (es_to_ds_forward_bus), + .ms_to_ds_forward_bus (ms_to_ds_forward_bus), + //to es + .ds_to_es_valid (ds_to_es_valid ), + .ds_to_es_bus (ds_to_es_bus ), + //to fs + .br_bus (br_bus ), + //exception + .excp_flush (excp_flush ), + .ertn_flush (ertn_flush ), + .refetch_flush (refetch_flush ), + .icacop_flush (icacop_flush ), + //idle + .idle_flush (idle_flush ), + //tlb ins + .es_tlb_inst_stall (es_tlb_inst_stall ), + .ms_tlb_inst_stall (ms_tlb_inst_stall ), + .ws_tlb_inst_stall (ws_tlb_inst_stall ), + //interrupt + .has_int (has_int ), + //csr + .rd_csr_addr (rd_csr_addr ), + .rd_csr_data (rd_csr_data ), + .csr_plv (csr_plv ), + //timer 64 + .timer_64 (ds_timer_64 ), + .csr_tid (ds_csr_tid ), + //llbit + .ds_llbit (ds_llbit ), + //every stage valid sign + .es_to_ds_valid (es_to_ds_valid ), + .ms_to_ds_valid (ms_to_ds_valid ), + .ws_to_ds_valid (ws_to_ds_valid ), + //from axi + .write_buffer_empty (write_buffer_empty ), + //from dcache + .dcache_empty (dcache_empty ), + //to btb + .btb_operate_en (btb_operate_en ), + .btb_pop_ras (btb_pop_ras ), + .btb_push_ras (btb_push_ras ), + .btb_add_entry (btb_add_entry ), + .btb_delete_entry (btb_delete_entry ), + .btb_pre_error (btb_pre_error ), + .btb_pre_right (btb_pre_right ), + .btb_target_error (btb_target_error ), + .btb_right_orien (btb_right_orien ), + .btb_right_target (btb_right_target ), + .btb_operate_pc (btb_operate_pc ), + .btb_operate_index (btb_operate_index ), + //debug + .infor_flag (infor_flag ), + .reg_num (reg_num ), + .debug_rf_rdata1 (rf_rdata ), + //to rf: for write back + .ws_to_rf_bus (ws_to_rf_bus ) + `ifdef DIFFTEST_EN + , + .rf_to_diff (regs ) + `endif +); +// EXE stage +exe_stage exe_stage( + .clk (aclk ), + .reset (reset ), + //allowin + .ms_allowin (ms_allowin ), + .es_allowin (es_allowin ), + //from ds + .ds_to_es_valid (ds_to_es_valid ), + .ds_to_es_bus (ds_to_es_bus ), + //to ms + .es_to_ms_valid (es_to_ms_valid ), + .es_to_ms_bus (es_to_ms_bus ), + //to ds forward path + .es_to_ds_forward_bus (es_to_ds_forward_bus), + .es_to_ds_valid (es_to_ds_valid ), + //div_mul + .es_div_enable (es_div_enable ), + .es_mul_div_sign (es_mul_div_sign ), + .es_rj_value (es_rj_value ), + .es_rkd_value (es_rkd_value ), + .div_complete (div_complete ), +`ifdef HAS_LACC + .es_lacc_req (es_lacc_req ), + .es_lacc_command (es_lacc_command ), + .lacc_data_valid (lacc_data_valid ), + .lacc_data_read (lacc_data_read ), + .lacc_data_addr (lacc_data_addr ), + .lacc_data_wdata (lacc_data_wdata ), + .lacc_data_size (lacc_data_size ), + .lacc_rsp_valid (lacc_rsp_valid ), + .lacc_rsp_rdat (lacc_rsp_rdat ), + .lacc_flush (lacc_flush ), + .data_data_ok (data_data_ok ), + .lacc_drsp_valid (lacc_drsp_valid ), + .lacc_req_imm (lacc_req_imm ), +`endif + //exception + .excp_flush (excp_flush ), + .ertn_flush (ertn_flush ), + .refetch_flush (refetch_flush ), + .icacop_flush (icacop_flush ), + //idle + .idle_flush (idle_flush ), + //tlb/cache ins + .tlb_inst_stall (es_tlb_inst_stall ), + //cache ins + .icacop_op_en (icacop_op_en ), + .dcacop_op_en (dcacop_op_en ), + .cacop_op_mode (cacop_op_mode ), + //from icache + .icache_unbusy (icache_unbusy ), + //preld ins + .preld_hint (preld_hint ), + .preld_en (preld_en ), + // data cache interface + .data_valid (data_valid ), + .data_op (data_op ), + .data_size (data_size ), + .data_wstrb (data_wstrb ), + .data_wdata (data_wdata ), + .data_addr_ok (data_addr_ok ), + //from csr + .csr_vppn (csr_vppn ), + //to addr trans + .data_addr (data_vaddr ), + .data_fetch (data_fetch ), + //from ms + .ms_wr_tlbehi (ms_wr_tlbehi ), + .ms_flush (ms_flush ) +); + +div u_div( + .div_clk (aclk ), + .reset (reset ), + .div (es_div_enable ), + .div_signed (es_mul_div_sign), + .x (es_rj_value ), + .y (es_rkd_value ), + .s (div_result ), + .r (mod_result ), + .complete (div_complete ) + ); + +mul u_mul( + .mul_clk (aclk ), + .reset (reset ), + .mul_signed (es_mul_div_sign), + .x (es_rj_value ), + .y (es_rkd_value ), + .result (mul_result ) + ); + +`ifdef HAS_LACC +lacc_core u_lacc_core( + .clk (aclk ), + .reset (reset ), + .lacc_flush (lacc_flush ), + + .lacc_req_valid (es_lacc_req ), + .lacc_req_command(es_lacc_command), + .lacc_req_rj (es_rj_value ), + .lacc_req_rk (es_rkd_value ), + .lacc_req_imm (lacc_req_imm ), + + .lacc_rsp_valid (lacc_rsp_valid ), + .lacc_rsp_rdat (lacc_rsp_rdat ), + + .lacc_data_valid (lacc_data_valid ), + .lacc_data_ready (data_addr_ok ), + .lacc_data_addr (lacc_data_addr ), + .lacc_data_read (lacc_data_read ), + .lacc_data_wdata (lacc_data_wdata ), + .lacc_data_size (lacc_data_size ), + + .lacc_drsp_valid (lacc_drsp_valid ), + .lacc_drsp_rdata (data_rdata ) + ); +`endif + +// MEM stage +mem_stage mem_stage( + .clk (aclk ), + .reset (reset ), + //allowin + .ws_allowin (ws_allowin ), + .ms_allowin (ms_allowin ), + //from es + .es_to_ms_valid (es_to_ms_valid ), + .es_to_ms_bus (es_to_ms_bus ), + //to ws + .ms_to_ws_valid (ms_to_ws_valid ), + .ms_to_ws_bus (ms_to_ws_bus ), + //to ds forward path + .ms_to_ds_forward_bus (ms_to_ds_forward_bus), + .ms_to_ds_valid (ms_to_ds_valid ), + //div mul + .div_result (div_result ), + .mod_result (mod_result ), + .mul_result (mul_result ), + //exception + .excp_flush (excp_flush ), + .ertn_flush (ertn_flush ), + .refetch_flush (refetch_flush ), + .icacop_flush (icacop_flush ), + //idle + .idle_flush (idle_flush ), + //tlb ins + .tlb_inst_stall (ms_tlb_inst_stall ), + //to es + .ms_wr_tlbehi (ms_wr_tlbehi ), + .ms_flush (ms_flush ), + //from cache + .data_data_ok (data_data_ok ), + .dcache_miss (ms_dcache_miss ), + .data_rdata (data_rdata ), + //to cache + .data_uncache_en (data_uncache_en ), + .tlb_excp_cancel_req (data_tlb_excp_cancel_req), + .sc_cancel_req (sc_cancel_req ), + //from csr + .csr_pg (csr_pg ), + .csr_da (csr_da ), + .csr_dmw0 (csr_dmw0 ), + .csr_dmw1 (csr_dmw1 ), + .csr_plv (csr_plv ), + .csr_datm (csr_datm ), + .disable_cache (disable_cache ), + .lladdr (lladdr_out ), + //from addr trans for difftest + .data_index_diff (data_index ), + .data_tag_diff (data_tag ), + .data_offset_diff (data_offset ), + //to addr trans + .data_addr_trans_en (data_addr_trans_en ), + .dmw0_en (data_dmw0_en ), + .dmw1_en (data_dmw1_en ), + .cacop_op_mode_di (cacop_op_mode_di ), + //tlb + .data_tlb_found (data_tlb_found ), + .data_tlb_index (data_tlb_index ), + .data_tlb_v (data_tlb_v ), + .data_tlb_d (data_tlb_d ), + .data_tlb_mat (data_tlb_mat ), + .data_tlb_plv (data_tlb_plv ), + .data_tlb_ppn (data_tag ) +); +// WB stage +wb_stage wb_stage( + .clk (aclk ), + .reset (reset ), + //allowin + .ws_allowin (ws_allowin ), + //from ms + .ms_to_ws_valid (ms_to_ws_valid ), + .ms_to_ws_bus (ms_to_ws_bus ), + //to rf: for write back + .ws_to_rf_bus (ws_to_rf_bus ), + //to ds + .ws_to_ds_valid (ws_to_ds_valid ), + //exception + .csr_era (ws_csr_era ), + .csr_esubcode (ws_csr_esubcode ), + .csr_ecode (ws_csr_ecode ), + .excp_flush (excp_flush ), + .ertn_flush (ertn_flush ), + .refetch_flush (refetch_flush ), + .icacop_flush (icacop_flush ), + .csr_wr_en (csr_wr_en ), + .wr_csr_addr (wr_csr_addr ), + .wr_csr_data (wr_csr_data ), + .va_error (ws_va_error ), + .bad_va (ws_bad_va ), + .excp_tlbrefill (excp_tlbrefill ), + .excp_tlb (excp_tlb ), + .excp_tlb_vppn (excp_tlb_vppn ), + //idle + .idle_flush (idle_flush ), + //llbit + .ws_llbit_set (ws_llbit_set ), + .ws_llbit (ws_llbit ), + .ws_lladdr_set (ws_lladdr_set ), + .ws_lladdr (ws_lladdr ), + //tlb ins + .tlb_inst_stall (ws_tlb_inst_stall), + .tlbsrch_en (tlbsrch_en ), + .tlbsrch_found (tlbsrch_found ), + .tlbsrch_index (tlbsrch_index ), + .tlbfill_en (tlbfill_en ), + .tlbwr_en (tlbwr_en ), + .tlbrd_en (tlbrd_en ), + .invtlb_en (invtlb_en ), + .invtlb_asid (invtlb_asid ), + .invtlb_vpn (invtlb_vpn ), + .invtlb_op (invtlb_op ), + //to perf_counter + .real_valid (commit_inst ), + .real_br_inst (br_inst ), + .real_icache_miss (icache_miss ), + .real_dcache_miss (dcache_miss ), + .real_mem_inst (mem_inst ), + .real_br_pre (br_pre ), + .real_br_pre_error (br_pre_error ), + //debug + .debug_ws_valid (ws_valid ), + .debug_break_point (break_point ), + + //trace debug interface + .debug_wb_pc (debug0_wb_pc ), + .debug_wb_rf_wen (debug0_wb_rf_wen ), + .debug_wb_rf_wnum (debug0_wb_rf_wnum ), + .debug_wb_rf_wdata (debug0_wb_rf_wdata), + .debug_wb_inst (debug0_wb_inst ) +`ifdef DIFFTEST_EN + , + .ws_valid_diff (ws_valid_diff ), + .ws_cnt_inst_diff (cnt_inst_diff ), + .ws_timer_64_diff (timer_64_diff ), + .ws_inst_ld_en_diff (inst_ld_en_diff ), + .ws_ld_paddr_diff (ld_paddr_diff ), + .ws_ld_vaddr_diff (ld_vaddr_diff ), + .ws_inst_st_en_diff (inst_st_en_diff ), + .ws_st_paddr_diff (st_paddr_diff ), + .ws_st_vaddr_diff (st_vaddr_diff ), + .ws_st_data_diff (st_data_diff ), + .ws_csr_rstat_en_diff (csr_rstat_en_diff ), + .ws_csr_data_diff (csr_data_diff ) +`endif +); + +csr #(TLBNUM) u_csr( + .clk (aclk ), + .reset (reset ), + //from to ds + .rd_addr (rd_csr_addr ), + .rd_data (rd_csr_data ), + //timer 64 + .timer_64_out (ds_timer_64 ), + .tid_out (ds_csr_tid ), + //from ws + .csr_wr_en (csr_wr_en ), + .wr_addr (wr_csr_addr ), + .wr_data (wr_csr_data ), + //interrupt + .interrupt (intrpt ), + .has_int (has_int ), + //from ws + .excp_flush (excp_flush ), + .ertn_flush (ertn_flush ), + .era_in (ws_csr_era ), + .esubcode_in (ws_csr_esubcode), + .ecode_in (ws_csr_ecode ), + .va_error_in (ws_va_error ), + .bad_va_in (ws_bad_va ), + .tlbsrch_en (tlbsrch_en ), + .tlbsrch_found (tlbsrch_found ), + .tlbsrch_index (tlbsrch_index ), + .excp_tlbrefill (excp_tlbrefill ), + .excp_tlb (excp_tlb ), + .excp_tlb_vppn (excp_tlb_vppn ), + //from ws llbit + .llbit_in (ws_llbit ), + .llbit_set_in (ws_llbit_set ), + .lladdr_in (ws_lladdr ), + .lladdr_set_in (ws_lladdr_set ), + //to es + .llbit_out (ds_llbit ), + .vppn_out (csr_vppn ), + //to ms + .lladdr_out (lladdr_out ), + //to fs + .eentry_out (fs_csr_eentry ), + .era_out (fs_csr_era ), + .tlbrentry_out (csr_tlbrentry ), + .disable_cache_out (disable_cache), + //to addr trans + .asid_out (csr_asid ), + .rand_index (rand_index ), + .tlbehi_out (tlbw_tlbehi ), + .tlbelo0_out (tlbw_tlbelo0 ), + .tlbelo1_out (tlbw_tlbelo1 ), + .tlbidx_out (tlbw_r_tlbidx ), + .pg_out (csr_pg ), + .da_out (csr_da ), + .dmw0_out (csr_dmw0 ), + .dmw1_out (csr_dmw1 ), + .datf_out (csr_datf ), + .datm_out (csr_datm ), + .ecode_out (tlbw_ecode ), + //from addr trans + .tlbrd_en (tlbrd_en ), + .tlbehi_in (tlbr_tlbehi ), + .tlbelo0_in (tlbr_tlbelo0 ), + .tlbelo1_in (tlbr_tlbelo1 ), + .tlbidx_in (tlbr_tlbidx ), + .asid_in (tlbr_asid ), + //general use + .plv_out (csr_plv ) + //difftest +`ifdef DIFFTEST_EN + , + .csr_crmd_diff (csr_crmd_diff_0 ), + .csr_prmd_diff (csr_prmd_diff_0 ), + .csr_ectl_diff (csr_ectl_diff_0 ), + .csr_estat_diff (csr_estat_diff_0 ), + .csr_era_diff (csr_era_diff_0 ), + .csr_badv_diff (csr_badv_diff_0 ), + .csr_eentry_diff (csr_eentry_diff_0 ), + .csr_tlbidx_diff (csr_tlbidx_diff_0 ), + .csr_tlbehi_diff (csr_tlbehi_diff_0 ), + .csr_tlbelo0_diff (csr_tlbelo0_diff_0 ), + .csr_tlbelo1_diff (csr_tlbelo1_diff_0 ), + .csr_asid_diff (csr_asid_diff_0 ), + .csr_save0_diff (csr_save0_diff_0 ), + .csr_save1_diff (csr_save1_diff_0 ), + .csr_save2_diff (csr_save2_diff_0 ), + .csr_save3_diff (csr_save3_diff_0 ), + .csr_tid_diff (csr_tid_diff_0 ), + .csr_tcfg_diff (csr_tcfg_diff_0 ), + .csr_tval_diff (csr_tval_diff_0 ), + .csr_ticlr_diff (csr_ticlr_diff_0 ), + .csr_llbctl_diff (csr_llbctl_diff_0 ), + .csr_tlbrentry_diff (csr_tlbrentry_diff_0), + .csr_dmw0_diff (csr_dmw0_diff_0 ), + .csr_dmw1_diff (csr_dmw1_diff_0 ), + .csr_pgdl_diff (csr_pgdl_diff_0 ), + .csr_pgdh_diff (csr_pgdh_diff_0 ) +`endif +); + +axi_bridge axi_bridge( + .clk (aclk ), + .reset (reset ), + + .arid (arid ), + .araddr (araddr ), + .arlen (arlen ), + .arsize (arsize ), + .arburst (arburst ), + .arlock (arlock ), + .arcache (arcache ), + .arprot (arprot ), + .arvalid (arvalid ), + .arready (arready ), + + .rid (rid ), + .rdata (rdata ), + .rresp (rresp ), + .rlast (rlast ), + .rvalid (rvalid ), + .rready (rready ), + + .awid (awid ), + .awaddr (awaddr ), + .awlen (awlen ), + .awsize (awsize ), + .awburst (awburst ), + .awlock (awlock ), + .awcache (awcache ), + .awprot (awprot ), + .awvalid (awvalid ), + .awready (awready ), + + .wid (wid ), + .wdata (wdata ), + .wstrb (wstrb ), + .wlast (wlast ), + .wvalid (wvalid ), + .wready (wready ), + + .bid (bid ), + .bresp (bresp ), + .bvalid (bvalid ), + .bready (bready ), + + .inst_rd_req (inst_rd_req ), + .inst_rd_type (inst_rd_type ), + .inst_rd_addr (inst_rd_addr ), + .inst_rd_rdy (inst_rd_rdy ), + .inst_ret_valid (inst_ret_valid ), + .inst_ret_last (inst_ret_last ), + .inst_ret_data (inst_ret_data ), + .inst_wr_req (inst_wr_req ), + .inst_wr_type (inst_wr_type ), + .inst_wr_addr (inst_wr_addr ), + .inst_wr_wstrb (inst_wr_wstrb ), + .inst_wr_data (inst_wr_data ), + .inst_wr_rdy (inst_wr_rdy ), + + + .data_rd_req (data_rd_req ), + .data_rd_type (data_rd_type ), + .data_rd_addr (data_rd_addr ), + .data_rd_rdy (data_rd_rdy ), + .data_ret_valid (data_ret_valid ), + .data_ret_last (data_ret_last ), + .data_ret_data (data_ret_data ), + .data_wr_req (data_wr_req ), + .data_wr_type (data_wr_type ), + .data_wr_addr (data_wr_addr ), + .data_wr_wstrb (data_wr_wstrb ), + .data_wr_data (data_wr_data ), + .data_wr_rdy (data_wr_rdy ), + .write_buffer_empty (write_buffer_empty) +); + +addr_trans #(TLBNUM) addr_trans( + .clk (aclk ), + .asid (csr_asid ), + //trans mode + .inst_addr_trans_en (inst_addr_trans_en), + .data_addr_trans_en (data_addr_trans_en), + //inst addr trans + .inst_fetch (fetch_en ), + .inst_vaddr (inst_vaddr ), + .inst_dmw0_en (inst_dmw0_en ), + .inst_dmw1_en (inst_dmw1_en ), + .inst_index (inst_index ), + .inst_tag (inst_tag ), + .inst_offset (inst_offset ), + .inst_tlb_found (inst_tlb_found ), + .inst_tlb_v (inst_tlb_v ), + .inst_tlb_d (inst_tlb_d ), + .inst_tlb_mat (inst_tlb_mat ), + .inst_tlb_plv (inst_tlb_plv ), + //data addr trans + .data_fetch (data_fetch ), + .data_vaddr (data_vaddr ), + .data_dmw0_en (data_dmw0_en ), + .data_dmw1_en (data_dmw1_en ), + .cacop_op_mode_di (cacop_op_mode_di), + .data_index (data_index ), + .data_tag (data_tag ), + .data_offset (data_offset ), + .data_tlb_found (data_tlb_found ), + .data_tlb_index (data_tlb_index ), + .data_tlb_v (data_tlb_v ), + .data_tlb_d (data_tlb_d ), + .data_tlb_mat (data_tlb_mat ), + .data_tlb_plv (data_tlb_plv ), + //tlbwr tlbfill tlb write + .tlbfill_en (tlbfill_en ), + .tlbwr_en (tlbwr_en ), + .rand_index (rand_index ), + .tlbehi_in (tlbw_tlbehi ), + .tlbelo0_in (tlbw_tlbelo0 ), + .tlbelo1_in (tlbw_tlbelo1 ), + .tlbidx_in (tlbw_r_tlbidx ), + .ecode_in (tlbw_ecode ), + //tlbp tlb read + .tlbehi_out (tlbr_tlbehi ), + .tlbelo0_out (tlbr_tlbelo0 ), + .tlbelo1_out (tlbr_tlbelo1 ), + .tlbidx_out (tlbr_tlbidx ), + .asid_out (tlbr_asid ), + //invtlb + .invtlb_en (invtlb_en ), + .invtlb_asid (invtlb_asid ), + .invtlb_vpn (invtlb_vpn ), + .invtlb_op (invtlb_op ), + //from csr + .csr_dmw0 (csr_dmw0 ), + .csr_dmw1 (csr_dmw1 ), + .csr_da (csr_da ), + .csr_pg (csr_pg ) +); + +icache icache( + .clk (aclk ), + .reset (reset ), +//to from cpu + .valid (inst_valid ), + .op (inst_op ), + .index (inst_index ), + .tag (inst_tag ), + .offset (inst_offset ), + .wstrb (inst_wstrb ), + .wdata (inst_wdata ), + .addr_ok (inst_addr_ok ), + .data_ok (inst_data_ok ), + .rdata (inst_rdata ), + .uncache_en (inst_uncache_en), + .icacop_op_en (icacop_op_en ), + .cacop_op_mode (cacop_op_mode ), + .cacop_op_addr_index (data_index ), + .cacop_op_addr_tag (data_tag ), + .cacop_op_addr_offset (data_offset ), + .icache_unbusy (icache_unbusy ), + .tlb_excp_cancel_req (inst_tlb_excp_cancel_req), +//to from axi + .rd_req (inst_rd_req ), + .rd_type (inst_rd_type ), + .rd_addr (inst_rd_addr ), + .rd_rdy (inst_rd_rdy ), + .ret_valid (inst_ret_valid ), + .ret_last (inst_ret_last ), + .ret_data (inst_ret_data ), + .wr_req (inst_wr_req ), + .wr_type (inst_wr_type ), + .wr_addr (inst_wr_addr ), + .wr_wstrb (inst_wr_wstrb ), + .wr_data (inst_wr_data ), + .wr_rdy (inst_wr_rdy ), + .cache_miss (fs_icache_miss ) +); + +dcache dcache( + .clk (aclk ), + .reset (reset ), +//to from cpu + .valid (data_valid ), + .op (data_op ), + .size (data_size ), + .index (data_index ), + .tag (data_tag ), + .offset (data_offset ), + .wstrb (data_wstrb ), + .wdata (data_wdata ), + .addr_ok (data_addr_ok ), + .data_ok (data_data_ok ), + .rdata (data_rdata ), + .uncache_en (data_uncache_en), + .dcacop_op_en (dcacop_op_en ), + .cacop_op_mode (cacop_op_mode ), + .preld_hint (preld_hint ), + .preld_en (preld_en ), + .tlb_excp_cancel_req (data_tlb_excp_cancel_req), + .sc_cancel_req (sc_cancel_req ), + .dcache_empty (dcache_empty ), +//to from axi + .rd_req (data_rd_req ), + .rd_type (data_rd_type ), + .rd_addr (data_rd_addr ), + .rd_rdy (data_rd_rdy ), + .ret_valid (data_ret_valid ), + .ret_last (data_ret_last ), + .ret_data (data_ret_data ), + .wr_req (data_wr_req ), + .wr_type (data_wr_type ), + .wr_addr (data_wr_addr ), + .wr_wstrb (data_wr_wstrb ), + .wr_data (data_wr_data ), + .wr_rdy (data_wr_rdy ), + .cache_miss (ms_dcache_miss ) +); + +btb btb( + .clk (aclk ), + .reset (reset ), + //from/to if + .fetch_pc (fetch_pc ), + .fetch_en (fetch_en ), + .ret_pc (btb_ret_pc ), + .taken (btb_taken ), + .ret_en (btb_en ), + .ret_index (btb_index ), + //from id + .operate_en (btb_operate_en ), + .operate_pc (btb_operate_pc ), + .operate_index (btb_operate_index), + .pop_ras (btb_pop_ras ), + .push_ras (btb_push_ras ), + .add_entry (btb_add_entry ), + .delete_entry (btb_delete_entry ), + .pre_error (btb_pre_error ), + .pre_right (btb_pre_right ), + .target_error (btb_target_error ), + .right_orien (btb_right_orien ), + .right_target (btb_right_target ) +); + +perf_counter perf_counter( + .clk (aclk ), + .reset (reset ), + .dcache_miss (dcache_miss ), + .icache_miss (icache_miss ), + .commit_inst (commit_inst ), + .br_inst (br_inst ), + .mem_inst (mem_inst ), + .br_pre (br_pre ), + .br_pre_error (br_pre_error ) +); + +`ifdef DIFFTEST_EN +always @(posedge aclk) begin + if (reset) begin + {cmt_valid, cmt_cnt_inst, cmt_timer_64, cmt_inst_ld_en, cmt_ld_paddr, cmt_ld_vaddr, cmt_inst_st_en, cmt_st_paddr, cmt_st_vaddr, cmt_st_data, cmt_csr_rstat_en, cmt_csr_data} <= 0; + {cmt_wen, cmt_wdest, cmt_wdata, cmt_pc, cmt_inst} <= 0; + {trap, trap_code, cycleCnt, instrCnt} <= 0; + end else if (~trap) begin + cmt_valid <= inst_valid_diff ; + cmt_cnt_inst <= cnt_inst_diff ; + cmt_timer_64 <= timer_64_diff ; + cmt_inst_ld_en <= inst_ld_en_diff ; + cmt_ld_paddr <= ld_paddr_diff ; + cmt_ld_vaddr <= ld_vaddr_diff ; + cmt_inst_st_en <= inst_st_en_diff ; + cmt_st_paddr <= st_paddr_diff ; + cmt_st_vaddr <= st_vaddr_diff ; + cmt_st_data <= st_data_diff ; + cmt_csr_rstat_en<= csr_rstat_en_diff ; + cmt_csr_data <= csr_data_diff ; + + cmt_wen <= debug0_wb_rf_wen ; + cmt_wdest <= {3'd0, debug0_wb_rf_wnum} ; + cmt_wdata <= debug0_wb_rf_wdata ; + cmt_pc <= debug0_wb_pc ; + cmt_inst <= debug0_wb_inst ; + + cmt_excp_flush <= excp_flush ; + cmt_ertn <= ertn_flush ; + cmt_csr_ecode <= ws_csr_ecode ; + cmt_tlbfill_en <= tlbfill_en ; + cmt_rand_index <= rand_index ; + + trap <= 0 ; + trap_code <= regs[10][7:0] ; + cycleCnt <= cycleCnt + 1 ; + instrCnt <= instrCnt + inst_valid_diff; + end +end + +DifftestInstrCommit DifftestInstrCommit( + .clock (aclk ), + .coreid (0 ), + .index (0 ), + .valid (cmt_valid ), + .pc (cmt_pc ), + .instr (cmt_inst ), + .skip (0 ), + .is_TLBFILL (cmt_tlbfill_en ), + .TLBFILL_index (cmt_rand_index ), + .is_CNTinst (cmt_cnt_inst ), + .timer_64_value (cmt_timer_64 ), + .wen (cmt_wen ), + .wdest (cmt_wdest ), + .wdata (cmt_wdata ), + .csr_rstat (cmt_csr_rstat_en), + .csr_data (cmt_csr_data ) +); + +DifftestExcpEvent DifftestExcpEvent( + .clock (aclk ), + .coreid (0 ), + .excp_valid (cmt_excp_flush ), + .eret (cmt_ertn ), + .intrNo (csr_estat_diff_0[12:2]), + .cause (cmt_csr_ecode ), + .exceptionPC (cmt_pc ), + .exceptionInst (cmt_inst ) +); + +DifftestTrapEvent DifftestTrapEvent( + .clock (aclk ), + .coreid (0 ), + .valid (trap ), + .code (trap_code ), + .pc (cmt_pc ), + .cycleCnt (cycleCnt ), + .instrCnt (instrCnt ) +); + +DifftestStoreEvent DifftestStoreEvent( + .clock (aclk ), + .coreid (0 ), + .index (0 ), + .valid (cmt_inst_st_en ), + .storePAddr (cmt_st_paddr ), + .storeVAddr (cmt_st_vaddr ), + .storeData (cmt_st_data ) +); + +DifftestLoadEvent DifftestLoadEvent( + .clock (aclk ), + .coreid (0 ), + .index (0 ), + .valid (cmt_inst_ld_en ), + .paddr (cmt_ld_paddr ), + .vaddr (cmt_ld_vaddr ) +); + +DifftestCSRRegState DifftestCSRRegState( + .clock (aclk ), + .coreid (0 ), + .crmd (csr_crmd_diff_0 ), + .prmd (csr_prmd_diff_0 ), + .euen (0 ), + .ecfg (csr_ectl_diff_0 ), + .estat (csr_estat_diff_0 ), + .era (csr_era_diff_0 ), + .badv (csr_badv_diff_0 ), + .eentry (csr_eentry_diff_0 ), + .tlbidx (csr_tlbidx_diff_0 ), + .tlbehi (csr_tlbehi_diff_0 ), + .tlbelo0 (csr_tlbelo0_diff_0 ), + .tlbelo1 (csr_tlbelo1_diff_0 ), + .asid (csr_asid_diff_0 ), + .pgdl (csr_pgdl_diff_0 ), + .pgdh (csr_pgdh_diff_0 ), + .save0 (csr_save0_diff_0 ), + .save1 (csr_save1_diff_0 ), + .save2 (csr_save2_diff_0 ), + .save3 (csr_save3_diff_0 ), + .tid (csr_tid_diff_0 ), + .tcfg (csr_tcfg_diff_0 ), + .tval (csr_tval_diff_0 ), + .ticlr (csr_ticlr_diff_0 ), + .llbctl (csr_llbctl_diff_0 ), + .tlbrentry (csr_tlbrentry_diff_0), + .dmw0 (csr_dmw0_diff_0 ), + .dmw1 (csr_dmw1_diff_0 ) +); + +DifftestGRegState DifftestGRegState( + .clock (aclk ), + .coreid (0 ), + .gpr_0 (0 ), + .gpr_1 (regs[1] ), + .gpr_2 (regs[2] ), + .gpr_3 (regs[3] ), + .gpr_4 (regs[4] ), + .gpr_5 (regs[5] ), + .gpr_6 (regs[6] ), + .gpr_7 (regs[7] ), + .gpr_8 (regs[8] ), + .gpr_9 (regs[9] ), + .gpr_10 (regs[10] ), + .gpr_11 (regs[11] ), + .gpr_12 (regs[12] ), + .gpr_13 (regs[13] ), + .gpr_14 (regs[14] ), + .gpr_15 (regs[15] ), + .gpr_16 (regs[16] ), + .gpr_17 (regs[17] ), + .gpr_18 (regs[18] ), + .gpr_19 (regs[19] ), + .gpr_20 (regs[20] ), + .gpr_21 (regs[21] ), + .gpr_22 (regs[22] ), + .gpr_23 (regs[23] ), + .gpr_24 (regs[24] ), + .gpr_25 (regs[25] ), + .gpr_26 (regs[26] ), + .gpr_27 (regs[27] ), + .gpr_28 (regs[28] ), + .gpr_29 (regs[29] ), + .gpr_30 (regs[30] ), + .gpr_31 (regs[31] ) +); +`endif +endmodule diff --git a/rtl/ip/open-la500/perf_counter.v b/rtl/ip/open-la500/perf_counter.v new file mode 100644 index 0000000..7fa24d4 --- /dev/null +++ b/rtl/ip/open-la500/perf_counter.v @@ -0,0 +1,57 @@ +module perf_counter ( + input clk , + input reset , + + input dcache_miss , + input icache_miss , + input commit_inst , + input br_inst , + input mem_inst , + input br_pre , + input br_pre_error +); + +reg[31:0] dcache_miss_counter; +reg[31:0] icache_miss_counter; +reg[31:0] commit_inst_counter; +reg[31:0] br_inst_counter; +reg[31:0] mem_inst_counter; +reg[31:0] br_pre_counter; +reg[31:0] br_pre_error_counter; + +always @(posedge clk) begin + if (reset) begin + dcache_miss_counter <= 32'b0; + icache_miss_counter <= 32'b0; + commit_inst_counter <= 32'b0; + br_inst_counter <= 32'b0; + mem_inst_counter <= 32'b0; + br_pre_counter <= 32'b0; + br_pre_error_counter <= 32'b0; + end + else begin + if (dcache_miss) begin + dcache_miss_counter <= dcache_miss_counter + 32'b1; + end + if (icache_miss) begin + icache_miss_counter <= icache_miss_counter + 32'b1; + end + if (commit_inst) begin + commit_inst_counter <= commit_inst_counter + 32'b1; + end + if (br_inst) begin + br_inst_counter <= br_inst_counter + 32'b1; + end + if (mem_inst) begin + mem_inst_counter <= mem_inst_counter + 32'b1; + end + if (br_pre) begin + br_pre_counter <= br_pre_counter + 32'b1; + end + if (br_pre_error) begin + br_pre_error_counter <= br_pre_error_counter + 32'b1; + end + end +end + +endmodule diff --git a/rtl/ip/open-la500/regfile.v b/rtl/ip/open-la500/regfile.v new file mode 100644 index 0000000..3caa2b6 --- /dev/null +++ b/rtl/ip/open-la500/regfile.v @@ -0,0 +1,39 @@ +module regfile( + input clk, + // READ PORT 1 + input [ 4:0] raddr1, + output [31:0] rdata1, + // READ PORT 2 + input [ 4:0] raddr2, + output [31:0] rdata2, + // WRITE PORT + input we, //write enable, HIGH valid + input [ 4:0] waddr, + input [31:0] wdata + `ifdef DIFFTEST_EN + , + output [31:0] rf_o [31:0] // difftest + `endif +); +reg [31:0] rf[31:0]; + +//WRITE +always @(posedge clk) begin + if (we) rf[waddr]<= wdata; +end + +//READ OUT 1 +assign rdata1 = (raddr1==5'b0) ? 32'b0 : + ((raddr1==waddr) && we) ? wdata : + rf[raddr1]; + +//READ OUT 2 +assign rdata2 = (raddr2==5'b0) ? 32'b0 : + ((raddr2==waddr) && we) ? wdata : + rf[raddr2]; +// difftest +`ifdef DIFFTEST_EN +assign rf_o = rf; +`endif + +endmodule diff --git a/rtl/ip/open-la500/tlb_entry.v b/rtl/ip/open-la500/tlb_entry.v new file mode 100644 index 0000000..0dad79a --- /dev/null +++ b/rtl/ip/open-la500/tlb_entry.v @@ -0,0 +1,235 @@ +module tlb_entry +#( + parameter TLBNUM = 32 +) +( + input clk, + // search port 0 + input s0_fetch , + input [18:0] s0_vppn , + input s0_odd_page , + input [ 9:0] s0_asid , + output s0_found , + output [ 4:0] s0_index , + output [ 5:0] s0_ps , + output [19:0] s0_ppn , + output s0_v , + output s0_d , + output [ 1:0] s0_mat , + output [ 1:0] s0_plv , + //search port 1 + input s1_fetch , + input [18:0] s1_vppn , + input s1_odd_page , + input [ 9:0] s1_asid , + output s1_found , + output [ 4:0] s1_index , + output [ 5:0] s1_ps , + output [19:0] s1_ppn , + output s1_v , + output s1_d , + output [ 1:0] s1_mat , + output [ 1:0] s1_plv , + // write port + input we , + input [$clog2(TLBNUM)-1:0] w_index , + input [18:0] w_vppn , + input [ 9:0] w_asid , + input w_g , + input [ 5:0] w_ps , + input w_e , + input w_v0 , + input w_d0 , + input [ 1:0] w_mat0 , + input [ 1:0] w_plv0 , + input [19:0] w_ppn0 , + input w_v1 , + input w_d1 , + input [ 1:0] w_mat1 , + input [ 1:0] w_plv1 , + input [19:0] w_ppn1 , + // read port + input [$clog2(TLBNUM)-1:0] r_index , + output [18:0] r_vppn , + output [ 9:0] r_asid , + output r_g , + output [ 5:0] r_ps , + output r_e , + output r_v0 , + output r_d0 , + output [ 1:0] r_mat0 , + output [ 1:0] r_plv0 , + output [19:0] r_ppn0 , + output r_v1 , + output r_d1 , + output [ 1:0] r_mat1 , + output [ 1:0] r_plv1 , + output [19:0] r_ppn1 , + // invalid port + input inv_en , + input [ 4:0] inv_op , + input [ 9:0] inv_asid , + input [18:0] inv_vpn +); + +reg [18:0] tlb_vppn [TLBNUM-1:0]; +reg tlb_e [TLBNUM-1:0]; +reg [ 9:0] tlb_asid [TLBNUM-1:0]; +reg tlb_g [TLBNUM-1:0]; +reg [ 5:0] tlb_ps [TLBNUM-1:0]; +reg [19:0] tlb_ppn0 [TLBNUM-1:0]; +reg [ 1:0] tlb_plv0 [TLBNUM-1:0]; +reg [ 1:0] tlb_mat0 [TLBNUM-1:0]; +reg tlb_d0 [TLBNUM-1:0]; +reg tlb_v0 [TLBNUM-1:0]; +reg [19:0] tlb_ppn1 [TLBNUM-1:0]; +reg [ 1:0] tlb_plv1 [TLBNUM-1:0]; +reg [ 1:0] tlb_mat1 [TLBNUM-1:0]; +reg tlb_d1 [TLBNUM-1:0]; +reg tlb_v1 [TLBNUM-1:0]; + +reg s0_fetch_r ; +reg [18:0] s0_vppn_r ; +reg s0_odd_page_r; +reg [ 9:0] s0_asid_r ; +reg s1_fetch_r ; +reg [18:0] s1_vppn_r ; +reg s1_odd_page_r; +reg [ 9:0] s1_asid_r ; + +wire [TLBNUM-1:0] match0; +wire [TLBNUM-1:0] match1; + +wire [$clog2(TLBNUM)-1:0] match0_en; +wire [$clog2(TLBNUM)-1:0] match1_en; + +wire [TLBNUM-1:0] s0_odd_page_buffer; +wire [TLBNUM-1:0] s1_odd_page_buffer; + +always @(posedge clk) begin + s0_fetch_r <= s0_fetch; + if (s0_fetch) begin + s0_vppn_r <= s0_vppn; + s0_odd_page_r <= s0_odd_page; + s0_asid_r <= s0_asid; + end + s1_fetch_r <= s1_fetch; + if (s1_fetch) begin + s1_vppn_r <= s1_vppn; + s1_odd_page_r <= s1_odd_page; + s1_asid_r <= s1_asid; + end +end + +genvar i; +generate + for (i = 0; i < TLBNUM; i = i + 1) + begin: match + assign s0_odd_page_buffer[i] = (tlb_ps[i] == 6'd12) ? s0_odd_page_r : s0_vppn_r[8]; + assign match0[i] = tlb_e[i] && ((tlb_ps[i] == 6'd12) ? s0_vppn_r == tlb_vppn[i] : s0_vppn_r[18: 9] == tlb_vppn[i][18: 9]) && ((s0_asid_r == tlb_asid[i]) || tlb_g[i]); + assign s1_odd_page_buffer[i] = (tlb_ps[i] == 6'd12) ? s1_odd_page_r : s1_vppn_r[8]; + assign match1[i] = tlb_e[i] && ((tlb_ps[i] == 6'd12) ? s1_vppn_r == tlb_vppn[i] : s1_vppn_r[18: 9] == tlb_vppn[i][18: 9]) && ((s1_asid_r == tlb_asid[i]) || tlb_g[i]); + end +endgenerate + +encoder_32_5 en_match0 (.in({{(32-TLBNUM){1'b0}},match0}), .out(match0_en)); +encoder_32_5 en_match1 (.in({{(32-TLBNUM){1'b0}},match1}), .out(match1_en)); + +assign s0_found = |match0; +assign s0_index = {{(5-$clog2(TLBNUM)){1'b0}},match0_en}; +assign s0_ps = tlb_ps[match0_en]; +assign s0_ppn = s0_odd_page_buffer[match0_en] ? tlb_ppn1[match0_en] : tlb_ppn0[match0_en]; +assign s0_v = s0_odd_page_buffer[match0_en] ? tlb_v1[match0_en] : tlb_v0[match0_en] ; +assign s0_d = s0_odd_page_buffer[match0_en] ? tlb_d1[match0_en] : tlb_d0[match0_en] ; +assign s0_mat = s0_odd_page_buffer[match0_en] ? tlb_mat1[match0_en] : tlb_mat0[match0_en]; +assign s0_plv = s0_odd_page_buffer[match0_en] ? tlb_plv1[match0_en] : tlb_plv0[match0_en]; + +assign s1_found = |match1; +assign s1_index = {{(5-$clog2(TLBNUM)){1'b0}},match1_en}; +assign s1_ps = tlb_ps[match1_en]; +assign s1_ppn = s1_odd_page_buffer[match1_en] ? tlb_ppn1[match1_en] : tlb_ppn0[match1_en]; +assign s1_v = s1_odd_page_buffer[match1_en] ? tlb_v1[match1_en] : tlb_v0[match1_en] ; +assign s1_d = s1_odd_page_buffer[match1_en] ? tlb_d1[match1_en] : tlb_d0[match1_en] ; +assign s1_mat = s1_odd_page_buffer[match1_en] ? tlb_mat1[match1_en] : tlb_mat0[match1_en]; +assign s1_plv = s1_odd_page_buffer[match1_en] ? tlb_plv1[match1_en] : tlb_plv0[match1_en]; + +always @(posedge clk) begin + if (we) begin + tlb_vppn [w_index] <= w_vppn; + tlb_asid [w_index] <= w_asid; + tlb_g [w_index] <= w_g; + tlb_ps [w_index] <= w_ps; + tlb_ppn0 [w_index] <= w_ppn0; + tlb_plv0 [w_index] <= w_plv0; + tlb_mat0 [w_index] <= w_mat0; + tlb_d0 [w_index] <= w_d0; + tlb_v0 [w_index] <= w_v0; + tlb_ppn1 [w_index] <= w_ppn1; + tlb_plv1 [w_index] <= w_plv1; + tlb_mat1 [w_index] <= w_mat1; + tlb_d1 [w_index] <= w_d1; + tlb_v1 [w_index] <= w_v1; + end +end + +assign r_vppn = tlb_vppn [r_index]; +assign r_asid = tlb_asid [r_index]; +assign r_g = tlb_g [r_index]; +assign r_ps = tlb_ps [r_index]; +assign r_e = tlb_e [r_index]; +assign r_v0 = tlb_v0 [r_index]; +assign r_d0 = tlb_d0 [r_index]; +assign r_mat0 = tlb_mat0 [r_index]; +assign r_plv0 = tlb_plv0 [r_index]; +assign r_ppn0 = tlb_ppn0 [r_index]; +assign r_v1 = tlb_v1 [r_index]; +assign r_d1 = tlb_d1 [r_index]; +assign r_mat1 = tlb_mat1 [r_index]; +assign r_plv1 = tlb_plv1 [r_index]; +assign r_ppn1 = tlb_ppn1 [r_index]; + +//tlb entry invalid +generate + for (i = 0; i < TLBNUM; i = i + 1) + begin: invalid_tlb_entry + always @(posedge clk) begin + if (we && (w_index == i)) begin + tlb_e[i] <= w_e; + end + else if (inv_en) begin + if (inv_op == 5'd0 || inv_op == 5'd1) begin + tlb_e[i] <= 1'b0; + end + else if (inv_op == 5'd2) begin + if (tlb_g[i]) begin + tlb_e[i] <= 1'b0; + end + end + else if (inv_op == 5'd3) begin + if (!tlb_g[i]) begin + tlb_e[i] <= 1'b0; + end + end + else if (inv_op == 5'd4) begin + if (!tlb_g[i] && (tlb_asid[i] == inv_asid)) begin + tlb_e[i] <= 1'b0; + end + end + else if (inv_op == 5'd5) begin + if (!tlb_g[i] && (tlb_asid[i] == inv_asid) && + ((tlb_ps[i] == 6'd12) ? (tlb_vppn[i] == inv_vpn) : (tlb_vppn[i][18:9] == inv_vpn[18:9]))) begin + tlb_e[i] <= 1'b0; + end + end + else if (inv_op == 5'd6) begin + if ((tlb_g[i] || (tlb_asid[i] == inv_asid)) && + ((tlb_ps[i] == 6'd12) ? (tlb_vppn[i] == inv_vpn) : (tlb_vppn[i][18:9] == inv_vpn[18:9]))) begin + tlb_e[i] <= 1'b0; + end + end + end + end + end +endgenerate + +endmodule diff --git a/rtl/ip/open-la500/tools.v b/rtl/ip/open-la500/tools.v new file mode 100644 index 0000000..28022d1 --- /dev/null +++ b/rtl/ip/open-la500/tools.v @@ -0,0 +1,167 @@ +module decoder_2_4( + input [ 1:0] in, + output [ 3:0] out +); + +genvar i; +generate for (i=0; i<4; i=i+1) begin : gen_for_dec_2_4 + assign out[i] = (in == i); +end endgenerate + +endmodule + + +module encoder_4_2( + input [3:0] in, + output [1:0] out +); + +assign out = {2{in[0]}} & 2'd0 | + {2{in[1]}} & 2'd1 | + {2{in[2]}} & 2'd2 | + {2{in[3]}} & 2'd3 ; + +endmodule + +module decoder_4_16( + input [ 3:0] in, + output [15:0] out +); + +genvar i; +generate for (i=0; i<16; i=i+1) begin : gen_for_dec_4_16 + assign out[i] = (in == i); +end endgenerate + +endmodule + +module encoder_16_4( + input [15:0] in, + output [ 3:0] out +); + +wire [1:0] out_0, out_1, out_2, out_3; + +encoder_4_2 one (.in(in[ 3: 0]), .out(out_0)); +encoder_4_2 two (.in(in[ 7: 4]), .out(out_1)); +encoder_4_2 thr (.in(in[11: 8]), .out(out_2)); +encoder_4_2 fou (.in(in[15:12]), .out(out_3)); + +assign out = {4{|in[ 3: 0]}} & {2'd0, out_0} | + {4{|in[ 7: 4]}} & {2'd1, out_1} | + {4{|in[11: 8]}} & {2'd2, out_2} | + {4{|in[15:12]}} & {2'd3, out_3} ; + +endmodule + +module decoder_5_32( + input [ 4:0] in, + output [31:0] out +); + +genvar i; +generate for (i=0; i<32; i=i+1) begin : gen_for_dec_5_32 + assign out[i] = (in == i); +end endgenerate + +endmodule + +module encoder_32_5( + input [31:0] in, + output [ 4:0] out +); + +wire [3:0] out_0, out_1; + +encoder_16_4 one (.in(in[15: 0]), .out(out_0)); +encoder_16_4 two (.in(in[31:16]), .out(out_1)); + +assign out = {5{|in[15: 0]}} & {1'd0, out_0} | + {5{|in[31:16]}} & {1'd1, out_1} ; + +endmodule + + +module decoder_6_64( + input [ 5:0] in, + output [63:0] out +); + +genvar i; +generate + for (i=0; i<64; i=i+1) + begin : gen_for_dec_6_64 //bug7 + assign out[i] = (in == i); + end +endgenerate + +endmodule + +module one_valid_n #( + parameter n = 16 +)( + input [n-1:0] in, + output [n-1:0] out, + output nozero +); + +wire [n-1:0] one_in; + +assign one_in[0] = in[0]; + +genvar i; +generate + for (i=1; i + [11] tlbr | + [12] pme |data tlb exceptions + [13] ppi | + [14] pis | + [15] pil | + +*/ + +//exception have piority, onle one exception is valid +assign {csr_ecode, + va_error, + bad_va, + csr_esubcode, + excp_tlbrefill, + excp_tlb, + excp_tlb_vppn} = ws_excp_num[ 0] ? {`ECODE_INT , 1'b0 , 32'b0 , 9'b0 , 1'b0 , 1'b0 , 19'b0 } : + ws_excp_num[ 1] ? {`ECODE_ADEF, ws_valid, ws_pc , `ESUBCODE_ADEF, 1'b0 , 1'b0 , 19'b0 } : + ws_excp_num[ 2] ? {`ECODE_TLBR, ws_valid, ws_pc , 9'b0 , ws_valid, ws_valid, ws_pc[31:13] } : + ws_excp_num[ 3] ? {`ECODE_PIF , ws_valid, ws_pc , 9'b0 , 1'b0 , ws_valid, ws_pc[31:13] } : + ws_excp_num[ 4] ? {`ECODE_PPI , ws_valid, ws_pc , 9'b0 , 1'b0 , ws_valid, ws_pc[31:13] } : + ws_excp_num[ 5] ? {`ECODE_SYS , 1'b0 , 32'b0 , 9'b0 , 1'b0 , 1'b0 , 19'b0 } : + ws_excp_num[ 6] ? {`ECODE_BRK , 1'b0 , 32'b0 , 9'b0 , 1'b0 , 1'b0 , 19'b0 } : + ws_excp_num[ 7] ? {`ECODE_INE , 1'b0 , 32'b0 , 9'b0 , 1'b0 , 1'b0 , 19'b0 } : + ws_excp_num[ 8] ? {`ECODE_IPE , 1'b0 , 32'b0 , 9'b0 , 1'b0 , 1'b0 , 19'b0 } : //close ipe excp now + ws_excp_num[ 9] ? {`ECODE_ALE , ws_valid, ws_error_va, 9'b0 , 1'b0 , 1'b0 , 19'b0 } : + ws_excp_num[11] ? {`ECODE_TLBR, ws_valid, ws_error_va, 9'b0 , ws_valid, ws_valid, ws_error_va[31:13]} : + ws_excp_num[12] ? {`ECODE_PME , ws_valid, ws_error_va, 9'b0 , 1'b0 , ws_valid, ws_error_va[31:13]} : + ws_excp_num[13] ? {`ECODE_PPI , ws_valid, ws_error_va, 9'b0 , 1'b0 , ws_valid, ws_error_va[31:13]} : + ws_excp_num[14] ? {`ECODE_PIS , ws_valid, ws_error_va, 9'b0 , 1'b0 , ws_valid, ws_error_va[31:13]} : + ws_excp_num[15] ? {`ECODE_PIL , ws_valid, ws_error_va, 9'b0 , 1'b0 , ws_valid, ws_error_va[31:13]} : + 69'b0; + +//invtlb ins +assign invtlb_op = ws_dest; + +// debug info generate +assign debug_wb_pc = ws_pc; +assign debug_wb_rf_wen = {4{rf_we}}; +assign debug_wb_rf_wnum = ws_dest; +assign debug_wb_rf_wdata = ws_final_result; +assign debug_wb_inst = ws_inst; +assign debug_ws_valid = ws_valid; + +`ifdef DIFFTEST_EN +assign ws_valid_diff = real_valid ; +assign ws_timer_64_diff = ws_timer_64 ; +assign ws_cnt_inst_diff = ws_cnt_inst ; + +assign ws_inst_ld_en_diff = ws_inst_ld_en ; +assign ws_ld_paddr_diff = ws_ld_paddr ; +assign ws_ld_vaddr_diff = ws_ld_vaddr ; + +assign ws_inst_st_en_diff = ws_inst_st_en ; +assign ws_st_paddr_diff = ws_ld_paddr_diff ; +assign ws_st_vaddr_diff = ws_ld_vaddr_diff ; +assign ws_st_data_diff = ws_st_data ; + +assign ws_csr_rstat_en_diff = ws_csr_rstat_en ; +assign ws_csr_data_diff = ws_csr_data ; +`endif + +endmodule diff --git a/rtl/ip/ram_wrap/axi_wrap_ram_dp.v b/rtl/ip/ram_wrap/axi_wrap_ram_dp.v new file mode 100644 index 0000000..d8d67d8 --- /dev/null +++ b/rtl/ip/ram_wrap/axi_wrap_ram_dp.v @@ -0,0 +1,247 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +module axi_wrap_ram_dp #( + parameter Init_File = "none" +) +( + input aclk, + input aresetn, + //ar + input [4 :0] axi_arid , + input [31:0] axi_araddr , + input [7 :0] axi_arlen , + input [2 :0] axi_arsize , + input [1 :0] axi_arburst, + input [1 :0] axi_arlock , + input [3 :0] axi_arcache, + input [2 :0] axi_arprot , + input axi_arvalid, + output axi_arready, + //r + output [4 :0] axi_rid , + output [31:0] axi_rdata , + output [1 :0] axi_rresp , + output axi_rlast , + output axi_rvalid , + input axi_rready , + //aw + input [4 :0] axi_awid , + input [31:0] axi_awaddr , + input [7 :0] axi_awlen , + input [2 :0] axi_awsize , + input [1 :0] axi_awburst, + input [1 :0] axi_awlock , + input [3 :0] axi_awcache, + input [2 :0] axi_awprot , + input axi_awvalid, + output axi_awready, + //w + input [31:0] axi_wdata , + input [3 :0] axi_wstrb , + input axi_wlast , + input axi_wvalid , + output axi_wready , + //b + output [4 :0] axi_bid , + output [1 :0] axi_bresp , + output axi_bvalid , + input axi_bready +); + + +//ram axi +//ar +wire [4 :0] ram_arid ; +wire [31:0] ram_araddr ; +wire [7 :0] ram_arlen ; +wire [2 :0] ram_arsize ; +wire [1 :0] ram_arburst; +wire [1 :0] ram_arlock ; +wire [3 :0] ram_arcache; +wire [2 :0] ram_arprot ; +wire ram_arvalid; +wire ram_arready; +//r +wire [4 :0] ram_rid ; +wire [31:0] ram_rdata ; +wire [1 :0] ram_rresp ; +wire ram_rlast ; +wire ram_rvalid ; +wire ram_rready ; +//aw +wire [4 :0] ram_awid ; +wire [31:0] ram_awaddr ; +wire [7 :0] ram_awlen ; +wire [2 :0] ram_awsize ; +wire [1 :0] ram_awburst; +wire [1 :0] ram_awlock ; +wire [3 :0] ram_awcache; +wire [2 :0] ram_awprot ; +wire ram_awvalid; +wire ram_awready; +//w +wire [31:0] ram_wdata ; +wire [3 :0] ram_wstrb ; +wire ram_wlast ; +wire ram_wvalid ; +wire ram_wready ; +//b +wire [4 :0] ram_bid ; +wire [1 :0] ram_bresp ; +wire ram_bvalid ; +wire ram_bready ; + +//sram signal +wire [31:0] fpga_sram_raddr; +wire [31:0] fpga_sram_rdata; +wire fpga_sram_ren; +wire [31:0] fpga_sram_waddr; +wire [31:0] fpga_sram_wdata; +wire [3:0] fpga_sram_wen; + + +//ar +assign ram_arid = axi_arid ; +assign ram_araddr = axi_araddr ; +assign ram_arlen = axi_arlen ; +assign ram_arsize = axi_arsize ; +assign ram_arburst = axi_arburst; +assign ram_arlock = axi_arlock ; +assign ram_arcache = axi_arcache; +assign ram_arprot = axi_arprot ; +assign ram_arvalid = axi_arvalid; +assign axi_arready = ram_arready; +//r +assign axi_rid = axi_rvalid ? ram_rid : 5'd0 ; +assign axi_rdata = axi_rvalid ? ram_rdata : 32'd0 ; +assign axi_rresp = axi_rvalid ? ram_rresp : 2'd0 ; +assign axi_rlast = axi_rvalid ? ram_rlast : 1'd0 ; +assign axi_rvalid = ram_rvalid; +assign ram_rready = axi_rready; +//aw +assign ram_awid = axi_awid ; +assign ram_awaddr = axi_awaddr ; +assign ram_awlen = axi_awlen ; +assign ram_awsize = axi_awsize ; +assign ram_awburst = axi_awburst; +assign ram_awlock = axi_awlock ; +assign ram_awcache = axi_awcache; +assign ram_awprot = axi_awprot ; +assign ram_awvalid = axi_awvalid; +assign axi_awready = ram_awready; +//w +assign ram_wdata = axi_wdata ; +assign ram_wstrb = axi_wstrb ; +assign ram_wlast = axi_wlast ; +assign ram_wvalid = axi_wvalid ; +assign axi_wready = ram_wready ; +//b +assign axi_bid = axi_bvalid ? ram_bid : 5'd0 ; +assign axi_bresp = axi_bvalid ? ram_bresp : 2'd0 ; +assign axi_bvalid = ram_bvalid ; +assign ram_bready = axi_bready ; + +axi2sram_dp #( + .BUS_WIDTH ( 32 ), + .DATA_WIDTH ( 32 ), + .CPU_WIDTH ( 32 )) + u_axi2sram_dp ( + .aclk ( aclk ), + .aresetn ( aresetn ), + + .m_araddr ( ram_araddr ), + .m_arburst ( ram_arburst ), + .m_arcache ( 4'h0 ), + .m_arid ( ram_arid ), + .m_arlen ( ram_arlen ), + .m_arlock ( 2'h0 ), + .m_arprot ( 3'h0 ), + .m_arsize ( ram_arsize ), + .m_arvalid ( ram_arvalid ), + .m_arready ( ram_arready ), + + .m_rready ( ram_rready ), + .m_rdata ( ram_rdata ), + .m_rid ( ram_rid ), + .m_rlast ( ram_rlast ), + .m_rresp ( ram_rresp ), + .m_rvalid ( ram_rvalid ), + + .m_awaddr ( ram_awaddr ), + .m_awburst ( ram_awburst ), + .m_awcache ( 4'h0 ), + .m_awid ( ram_awid ), + .m_awlen ( ram_awlen ), + .m_awlock ( 2'h0 ), + .m_awprot ( 3'h0 ), + .m_awsize ( ram_awsize ), + .m_awvalid ( ram_awvalid ), + .m_awready ( ram_awready ), + + .m_wdata ( ram_wdata ), + .m_wlast ( ram_wlast ), + .m_wstrb ( ram_wstrb ), + .m_wvalid ( ram_wvalid ), + .m_wready ( ram_wready ), + + .m_bready ( ram_bready ), + .m_bid ( ram_bid ), + .m_bresp ( ram_bresp ), + .m_bvalid ( ram_bvalid ), + + .ram_raddr ( fpga_sram_raddr ), + .ram_ren ( fpga_sram_ren ), + .ram_waddr ( fpga_sram_waddr ), + .ram_wdata ( fpga_sram_wdata ), + .ram_wen ( fpga_sram_wen ), + .ram_rdata ( fpga_sram_rdata ) +); + +//1MByte SRAM +fpga_sram_dp #( +.AW ( 18 ), +.Init_File (Init_File) +)u_fpga_sram ( + .CLK ( aclk ), + .ram_raddr ( fpga_sram_raddr[19:2] ), + .ram_ren ( fpga_sram_ren ), + .ram_rdata ( fpga_sram_rdata ), + .ram_waddr ( fpga_sram_waddr[19:2] ), + .ram_wdata ( fpga_sram_wdata ), + .ram_wen ( fpga_sram_wen ) + +); + + +endmodule diff --git a/rtl/ip/ram_wrap/axi_wrap_ram_sp.v b/rtl/ip/ram_wrap/axi_wrap_ram_sp.v new file mode 100644 index 0000000..e2e0833 --- /dev/null +++ b/rtl/ip/ram_wrap/axi_wrap_ram_sp.v @@ -0,0 +1,244 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +module axi_wrap_ram_sp #( + parameter Init_File = "none" +) +( + input aclk, + input aresetn, + //ar + input [4 :0] axi_arid , + input [31:0] axi_araddr , + input [7 :0] axi_arlen , + input [2 :0] axi_arsize , + input [1 :0] axi_arburst, + input [1 :0] axi_arlock , + input [3 :0] axi_arcache, + input [2 :0] axi_arprot , + input axi_arvalid, + output axi_arready, + //r + output [4 :0] axi_rid , + output [31:0] axi_rdata , + output [1 :0] axi_rresp , + output axi_rlast , + output axi_rvalid , + input axi_rready , + //aw + input [4 :0] axi_awid , + input [31:0] axi_awaddr , + input [7 :0] axi_awlen , + input [2 :0] axi_awsize , + input [1 :0] axi_awburst, + input [1 :0] axi_awlock , + input [3 :0] axi_awcache, + input [2 :0] axi_awprot , + input axi_awvalid, + output axi_awready, + //w + input [31:0] axi_wdata , + input [3 :0] axi_wstrb , + input axi_wlast , + input axi_wvalid , + output axi_wready , + //b + output [4 :0] axi_bid , + output [1 :0] axi_bresp , + output axi_bvalid , + input axi_bready +); + + +//ram axi +//ar +wire [4 :0] ram_arid ; +wire [31:0] ram_araddr ; +wire [7 :0] ram_arlen ; +wire [2 :0] ram_arsize ; +wire [1 :0] ram_arburst; +wire [1 :0] ram_arlock ; +wire [3 :0] ram_arcache; +wire [2 :0] ram_arprot ; +wire ram_arvalid; +wire ram_arready; +//r +wire [4 :0] ram_rid ; +wire [31:0] ram_rdata ; +wire [1 :0] ram_rresp ; +wire ram_rlast ; +wire ram_rvalid ; +wire ram_rready ; +//aw +wire [4 :0] ram_awid ; +wire [31:0] ram_awaddr ; +wire [7 :0] ram_awlen ; +wire [2 :0] ram_awsize ; +wire [1 :0] ram_awburst; +wire [1 :0] ram_awlock ; +wire [3 :0] ram_awcache; +wire [2 :0] ram_awprot ; +wire ram_awvalid; +wire ram_awready; +//w +wire [31:0] ram_wdata ; +wire [3 :0] ram_wstrb ; +wire ram_wlast ; +wire ram_wvalid ; +wire ram_wready ; +//b +wire [4 :0] ram_bid ; +wire [1 :0] ram_bresp ; +wire ram_bvalid ; +wire ram_bready ; + +//sram signal +wire [31:0] fpga_sram_addr; +wire fpga_sram_cs; +wire fpga_sram_we; +wire [3:0] fpga_sram_be; +wire [31:0] fpga_sram_wdata; +wire [31:0] fpga_sram_rdata; + + +//ar +assign ram_arid = axi_arid ; +assign ram_araddr = axi_araddr ; +assign ram_arlen = axi_arlen ; +assign ram_arsize = axi_arsize ; +assign ram_arburst = axi_arburst; +assign ram_arlock = axi_arlock ; +assign ram_arcache = axi_arcache; +assign ram_arprot = axi_arprot ; +assign ram_arvalid = axi_arvalid; +assign axi_arready = ram_arready; +//r +assign axi_rid = axi_rvalid ? ram_rid : 5'd0 ; +assign axi_rdata = axi_rvalid ? ram_rdata : 32'd0 ; +assign axi_rresp = axi_rvalid ? ram_rresp : 2'd0 ; +assign axi_rlast = axi_rvalid ? ram_rlast : 1'd0 ; +assign axi_rvalid = ram_rvalid; +assign ram_rready = axi_rready; +//aw +assign ram_awid = axi_awid ; +assign ram_awaddr = axi_awaddr ; +assign ram_awlen = axi_awlen ; +assign ram_awsize = axi_awsize ; +assign ram_awburst = axi_awburst; +assign ram_awlock = axi_awlock ; +assign ram_awcache = axi_awcache; +assign ram_awprot = axi_awprot ; +assign ram_awvalid = axi_awvalid; +assign axi_awready = ram_awready; +//w +assign ram_wdata = axi_wdata ; +assign ram_wstrb = axi_wstrb ; +assign ram_wlast = axi_wlast ; +assign ram_wvalid = axi_wvalid ; +assign axi_wready = ram_wready ; +//b +assign axi_bid = axi_bvalid ? ram_bid : 5'd0 ; +assign axi_bresp = axi_bvalid ? ram_bresp : 2'd0 ; +assign axi_bvalid = ram_bvalid ; +assign ram_bready = axi_bready ; + + +axi2sram_sp #( + .AXI_ID_WIDTH ( 5 ), + .AXI_ADDR_WIDTH ( 32 ), + .AXI_DATA_WIDTH ( 32 )) + u_axi_sram_sp ( + .clk ( aclk ), + .resetn ( aresetn ), + + .s_araddr ( ram_araddr ), + .s_arburst ( ram_arburst ), + .s_arcache ( ram_arcache ), + .s_arid ( ram_arid ), + .s_arlen ( ram_arlen ), + .s_arlock ( ram_arlock ), + .s_arprot ( ram_arprot ), + .s_arsize ( ram_arsize ), + .s_arvalid ( ram_arvalid ), + .s_awaddr ( ram_awaddr ), + .s_awburst ( ram_awburst ), + .s_awcache ( ram_awcache ), + .s_awid ( ram_awid ), + .s_awlen ( ram_awlen ), + .s_awlock ( ram_awlock ), + .s_awprot ( ram_awprot ), + .s_awsize ( ram_awsize ), + .s_awvalid ( ram_awvalid ), + .s_bready ( ram_bready ), + .s_rready ( ram_rready ), + .s_wdata ( ram_wdata ), + .s_wlast ( ram_wlast ), + .s_wstrb ( ram_wstrb ), + .s_wvalid ( ram_wvalid ), + .s_arready ( ram_arready ), + .s_awready ( ram_awready ), + .s_bid ( ram_bid ), + .s_bresp ( ram_bresp ), + .s_bvalid ( ram_bvalid ), + .s_rdata ( ram_rdata ), + .s_rid ( ram_rid ), + .s_rlast ( ram_rlast ), + .s_rresp ( ram_rresp ), + .s_rvalid ( ram_rvalid ), + .s_wready ( ram_wready ), + + .req_o ( fpga_sram_cs ), + .we_o ( fpga_sram_we ), + .addr_o ( fpga_sram_addr ), + .be_o ( fpga_sram_be ), + .data_o ( fpga_sram_wdata ), + .data_i ( fpga_sram_rdata ) +); + +wire [3:0] fpga_sram_wren = {4{fpga_sram_we}} & fpga_sram_be; + +//1MByte SRAM +fpga_sram_sp #( +.AW ( 18 ), +.Init_File (Init_File) +)u_fpga_sram ( + .CLK ( aclk ), + .ADDR ( fpga_sram_addr[19:2] ), + .WDATA ( fpga_sram_wdata ), + .WREN ( fpga_sram_wren ), + .CS ( fpga_sram_cs ), + .RDATA ( fpga_sram_rdata ) +); + + +endmodule diff --git a/rtl/ip/ram_wrap/axi_wrap_ram_sp_external.v b/rtl/ip/ram_wrap/axi_wrap_ram_sp_external.v new file mode 100644 index 0000000..3446a87 --- /dev/null +++ b/rtl/ip/ram_wrap/axi_wrap_ram_sp_external.v @@ -0,0 +1,259 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +module axi_wrap_ram_sp_external ( + input aclk, + input aresetn, + //ar + input [4 :0] axi_arid , + input [31:0] axi_araddr , + input [7 :0] axi_arlen , + input [2 :0] axi_arsize , + input [1 :0] axi_arburst, + input axi_arlock , + input [3 :0] axi_arcache, + input [2 :0] axi_arprot , + input axi_arvalid, + output axi_arready, + //r + output [4 :0] axi_rid , + output [31:0] axi_rdata , + output [1 :0] axi_rresp , + output axi_rlast , + output axi_rvalid , + input axi_rready , + //aw + input [4 :0] axi_awid , + input [31:0] axi_awaddr , + input [7 :0] axi_awlen , + input [2 :0] axi_awsize , + input [1 :0] axi_awburst, + input axi_awlock , + input [3 :0] axi_awcache, + input [2 :0] axi_awprot , + input axi_awvalid, + output axi_awready, + //w + input [31:0] axi_wdata , + input [3 :0] axi_wstrb , + input axi_wlast , + input axi_wvalid , + output axi_wready , + //b + output [4 :0] axi_bid , + output [1 :0] axi_bresp , + output axi_bvalid , + input axi_bready , + + //BaseRAM信号 + inout [31:0] base_ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享 + output [19:0] base_ram_addr, //BaseRAM地址 + output [ 3:0] base_ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0 + output base_ram_ce_n, //BaseRAM片选，低有效 + output base_ram_oe_n, //BaseRAM读使能，低有效 + output base_ram_we_n, //BaseRAM写使能，低有效 + + //ExtRAM信号 + inout [31:0] ext_ram_data, //ExtRAM数据 + output [19:0] ext_ram_addr, //ExtRAM地址 + output [ 3:0] ext_ram_be_n, //ExtRAM字节使能，低有效。如果不使用字节使能，请保持为0 + output ext_ram_ce_n, //ExtRAM片选，低有效 + output ext_ram_oe_n, //ExtRAM读使能，低有效 + output ext_ram_we_n //ExtRAM写使能，低有效 +); + + +//ram axi +//ar +wire [4 :0] ram_arid ; +wire [31:0] ram_araddr ; +wire [7 :0] ram_arlen ; +wire [2 :0] ram_arsize ; +wire [1 :0] ram_arburst; +wire ram_arlock ; +wire [3 :0] ram_arcache; +wire [2 :0] ram_arprot ; +wire ram_arvalid; +wire ram_arready; +//r +wire [4 :0] ram_rid ; +wire [31:0] ram_rdata ; +wire [1 :0] ram_rresp ; +wire ram_rlast ; +wire ram_rvalid ; +wire ram_rready ; +//aw +wire [4 :0] ram_awid ; +wire [31:0] ram_awaddr ; +wire [7 :0] ram_awlen ; +wire [2 :0] ram_awsize ; +wire [1 :0] ram_awburst; +wire ram_awlock ; +wire [3 :0] ram_awcache; +wire [2 :0] ram_awprot ; +wire ram_awvalid; +wire ram_awready; +//w +wire [31:0] ram_wdata ; +wire [3 :0] ram_wstrb ; +wire ram_wlast ; +wire ram_wvalid ; +wire ram_wready ; +//b +wire [4 :0] ram_bid ; +wire [1 :0] ram_bresp ; +wire ram_bvalid ; +wire ram_bready ; + +//sram signal +wire [31:0] soc_sram_addr; +wire soc_sram_cs; +wire soc_sram_we; +wire [3:0] soc_sram_be; +wire [31:0] soc_sram_wdata; +wire [31:0] soc_sram_rdata; + +//ar +assign ram_arid = axi_arid ; +assign ram_araddr = axi_araddr ; +assign ram_arlen = axi_arlen ; +assign ram_arsize = axi_arsize ; +assign ram_arburst = axi_arburst; +assign ram_arlock = axi_arlock ; +assign ram_arcache = axi_arcache; +assign ram_arprot = axi_arprot ; +assign ram_arvalid = axi_arvalid; +assign axi_arready = ram_arready; +//r +assign axi_rid = axi_rvalid ? ram_rid : 5'd0 ; +assign axi_rdata = axi_rvalid ? ram_rdata : 32'd0 ; +assign axi_rresp = axi_rvalid ? ram_rresp : 2'd0 ; +assign axi_rlast = axi_rvalid ? ram_rlast : 1'd0 ; +assign axi_rvalid = ram_rvalid; +assign ram_rready = axi_rready; +//aw +assign ram_awid = axi_awid ; +assign ram_awaddr = axi_awaddr ; +assign ram_awlen = axi_awlen ; +assign ram_awsize = axi_awsize ; +assign ram_awburst = axi_awburst; +assign ram_awlock = axi_awlock ; +assign ram_awcache = axi_awcache; +assign ram_awprot = axi_awprot ; +assign ram_awvalid = axi_awvalid; +assign axi_awready = ram_awready; +//w +assign ram_wdata = axi_wdata ; +assign ram_wstrb = axi_wstrb ; +assign ram_wlast = axi_wlast ; +assign ram_wvalid = axi_wvalid ; +assign axi_wready = ram_wready ; +//b +assign axi_bid = axi_bvalid ? ram_bid : 5'd0 ; +assign axi_bresp = axi_bvalid ? ram_bresp : 2'd0 ; +assign axi_bvalid = ram_bvalid ; +assign ram_bready = axi_bready ; + + +axi2sram_sp_external #( + .AXI_ID_WIDTH ( 5 ), + .AXI_ADDR_WIDTH ( 32 ), + .AXI_DATA_WIDTH ( 32 )) + u_axi_sram_sp ( + .clk ( aclk ), + .resetn ( aresetn ), + + .s_araddr ( ram_araddr ), + .s_arburst ( ram_arburst ), + .s_arcache ( ram_arcache ), + .s_arid ( ram_arid ), + .s_arlen ( ram_arlen ), + .s_arlock ( ram_arlock ), + .s_arprot ( ram_arprot ), + .s_arsize ( ram_arsize ), + .s_arvalid ( ram_arvalid ), + .s_awaddr ( ram_awaddr ), + .s_awburst ( ram_awburst ), + .s_awcache ( ram_awcache ), + .s_awid ( ram_awid ), + .s_awlen ( ram_awlen ), + .s_awlock ( ram_awlock ), + .s_awprot ( ram_awprot ), + .s_awsize ( ram_awsize ), + .s_awvalid ( ram_awvalid ), + .s_bready ( ram_bready ), + .s_rready ( ram_rready ), + .s_wdata ( ram_wdata ), + .s_wlast ( ram_wlast ), + .s_wstrb ( ram_wstrb ), + .s_wvalid ( ram_wvalid ), + .s_arready ( ram_arready ), + .s_awready ( ram_awready ), + .s_bid ( ram_bid ), + .s_bresp ( ram_bresp ), + .s_bvalid ( ram_bvalid ), + .s_rdata ( ram_rdata ), + .s_rid ( ram_rid ), + .s_rlast ( ram_rlast ), + .s_rresp ( ram_rresp ), + .s_rvalid ( ram_rvalid ), + .s_wready ( ram_wready ), + + .req_o ( soc_sram_cs ), + .we_o ( soc_sram_we ), + .addr_o ( soc_sram_addr ), + .be_o ( soc_sram_be ), + .data_o ( soc_sram_wdata ), + .data_i ( soc_sram_rdata ) +); + +wire choose_sram = soc_sram_addr[22];//1:ExtRAM 0:BaseRAM +wire [3:0] be_out = soc_sram_we ? soc_sram_be : 4'b1111; + +assign base_ram_addr = soc_sram_addr[21:2]; +assign base_ram_be_n = choose_sram ? 4'b1111 : ~be_out; +assign base_ram_ce_n = ~(soc_sram_cs & (~choose_sram)); +assign base_ram_oe_n = soc_sram_we | choose_sram; +assign base_ram_we_n = ~(soc_sram_we & (~choose_sram)); +assign base_ram_data = ((~choose_sram) & soc_sram_cs & soc_sram_we) ? soc_sram_wdata : 32'hzzzzzzzz; + +assign ext_ram_addr = soc_sram_addr[21:2]; +assign ext_ram_be_n = choose_sram ? ~be_out : 4'b1111; +assign ext_ram_ce_n = choose_sram ? ~soc_sram_cs : 1'b1; +assign ext_ram_oe_n = choose_sram ? soc_sram_we : 1'b1; +assign ext_ram_we_n = choose_sram ? ~soc_sram_we : 1'b1; +assign ext_ram_data = ((choose_sram) & soc_sram_cs & soc_sram_we) ? soc_sram_wdata : 32'hzzzzzzzz; + +assign soc_sram_rdata = choose_sram ? ext_ram_data : base_ram_data; + +endmodule diff --git a/rtl/ip/ram_wrap/cache_sram.v b/rtl/ip/ram_wrap/cache_sram.v new file mode 100644 index 0000000..bbd1d2d --- /dev/null +++ b/rtl/ip/ram_wrap/cache_sram.v @@ -0,0 +1,85 @@ +`include "config.h" + +module data_bank_sram ( + input [ 7:0] addra , + input clka , + input [31:0] dina , + output [31:0] douta , + input ena , + input [ 3:0] wea +); +`ifdef USE_CACHE + localparam V_STYLE = "block"; + localparam P_STYLE = (V_STYLE == "ultra") ? "uram" : + (V_STYLE == "distributed") ? "select_ram" : + "block_ram"; + + (*ram_style = V_STYLE*) reg [31:0] mem_reg [255:0]/*synthesis syn_ramstyle=P_STYLE*/; + reg [31:0] output_buffer; + + always @(posedge clka) begin + if (ena) begin + if (wea) begin + if (wea[0]) begin + mem_reg[addra][ 7: 0] <= dina[ 7: 0]; + end + + if (wea[1]) begin + mem_reg[addra][15: 8] <= dina[15: 8]; + end + + if (wea[2]) begin + mem_reg[addra][23:16] <= dina[23:16]; + end + + if (wea[3]) begin + mem_reg[addra][31:24] <= dina[31:24]; + end + end + else begin + output_buffer <= mem_reg[addra]; + end + end + end + + assign douta = output_buffer; +`else + assign douta = 32'h0; +`endif + +endmodule + +module tagv_sram ( + input [ 7:0] addra , + input clka , + input [20:0] dina , + output [20:0] douta , + input ena , + input wea +); +`ifdef USE_CACHE + localparam V_STYLE = "block"; + localparam P_STYLE = (V_STYLE == "ultra") ? "uram" : + (V_STYLE == "distributed") ? "select_ram" : + "block_ram"; + + (*ram_style = V_STYLE*) reg [20:0] mem_reg [255:0]/*synthesis syn_ramstyle=P_STYLE*/; + reg [20:0] output_buffer; + + always @(posedge clka) begin + if (ena) begin + if (wea) begin + mem_reg[addra] <= dina; + end + else begin + output_buffer <= mem_reg[addra]; + end + end + end + + assign douta = output_buffer; +`else + assign douta = 21'h0; +`endif + +endmodule \ No newline at end of file diff --git a/rtl/ip/ram_wrap/fpga_sram_dp.v b/rtl/ip/ram_wrap/fpga_sram_dp.v new file mode 100644 index 0000000..4bc06fc --- /dev/null +++ b/rtl/ip/ram_wrap/fpga_sram_dp.v @@ -0,0 +1,53 @@ +module fpga_sram_dp #( + parameter AW = 16, + parameter Init_File = "none" +) +( + input wire CLK, + + input wire [AW-1:0] ram_raddr, + output wire [31 :0] ram_rdata, + input wire ram_ren , + + input wire [AW-1:0] ram_waddr, + input wire [31 :0] ram_wdata, + input wire [3 :0] ram_wen +); + + localparam AWT = ((1<<(AW-0))-1); + localparam V_STYLE = "block"; + localparam P_STYLE = (V_STYLE == "ultra") ? "uram" : + (V_STYLE == "distributed") ? "select_ram" : + "block_ram"; + + (*ram_style = V_STYLE*)reg [31:0] BRAM [AWT:0]/*synthesis syn_ramstyle=P_STYLE*/; + + initial begin + if(Init_File != "none") begin + $readmemb(Init_File,BRAM); + end + end + + reg [AW-1:0] addr_q1; + + always@(posedge CLK) begin + if(ram_wen[0]) BRAM[ram_waddr][7:0] <= ram_wdata[7:0]; + end + always@(posedge CLK) begin + if(ram_wen[1]) BRAM[ram_waddr][15:8] <= ram_wdata[15:8]; + end + always@(posedge CLK) begin + if(ram_wen[2]) BRAM[ram_waddr][23:16] <= ram_wdata[23:16]; + end + always@(posedge CLK) begin + if(ram_wen[3]) BRAM[ram_waddr][31:24] <= ram_wdata[31:24]; + end + + always @ (posedge CLK) begin + if(ram_ren) + addr_q1 <= ram_raddr; + end + + assign ram_rdata = BRAM[addr_q1]; + +endmodule diff --git a/rtl/ip/ram_wrap/fpga_sram_sp.v b/rtl/ip/ram_wrap/fpga_sram_sp.v new file mode 100644 index 0000000..69d2c9e --- /dev/null +++ b/rtl/ip/ram_wrap/fpga_sram_sp.v @@ -0,0 +1,54 @@ +module fpga_sram_sp #( + parameter AW = 16, + parameter Init_File = "none" +) +( + input wire CLK, + input wire [AW-1:0] ADDR, + input wire [31:0] WDATA, + input wire [3:0] WREN, + input wire CS, + output wire [31:0] RDATA +); + + localparam AWT = ((1<<(AW-0))-1); + localparam V_STYLE = "block"; + localparam P_STYLE = (V_STYLE == "ultra") ? "uram" : + (V_STYLE == "distributed") ? "select_ram" : + "block_ram"; + + (*ram_style = V_STYLE*)reg [31:0] BRAM [AWT:0]/*synthesis syn_ramstyle=P_STYLE*/; + + initial begin + if(Init_File != "none") begin + $readmemb(Init_File,BRAM); + end + end + + reg [AW-1:0] addr_q1; + wire [3:0] write_enable; + + assign write_enable[3:0] = WREN[3:0] & {4{CS}}; + + + always@(posedge CLK) begin + if(write_enable[0]) BRAM[ADDR][7:0] <= WDATA[7:0]; + end + always@(posedge CLK) begin + if(write_enable[1]) BRAM[ADDR][15:8] <= WDATA[15:8]; + end + always@(posedge CLK) begin + if(write_enable[2]) BRAM[ADDR][23:16] <= WDATA[23:16]; + end + always@(posedge CLK) begin + if(write_enable[3]) BRAM[ADDR][31:24] <= WDATA[31:24]; + end + + always @ (posedge CLK) begin + if(CS && !(|WREN)) + addr_q1 <= ADDR[AW-1:0]; + end + + assign RDATA = BRAM[addr_q1]; + +endmodule diff --git a/rtl/ip/rst_sync/rst_sync.v b/rtl/ip/rst_sync/rst_sync.v new file mode 100644 index 0000000..71a37de --- /dev/null +++ b/rtl/ip/rst_sync/rst_sync.v @@ -0,0 +1,18 @@ +module rst_sync( + input clk, + input rst_n_in, + output rst_n_out +); + + reg [1:0] delay; + always @(posedge clk or negedge rst_n_in) begin + if(~rst_n_in) begin + delay <= 2'b00; + end + else begin + delay <= {delay[0],1'b1}; + end + end + assign rst_n_out = delay[1]; + +endmodule \ No newline at end of file diff --git a/rtl/soc_top.v b/rtl/soc_top.v new file mode 100644 index 0000000..66f1fb6 --- /dev/null +++ b/rtl/soc_top.v @@ -0,0 +1,1684 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ +`timescale 1ns / 1ps + +//1f00_0000 apb +//1f10_0000 dvi +//1f20_0000 confreg +//1f30_0000 dma + +`include "config.h" + +module soc_top #(parameter SIMULATION=1'b0) +( + input clk, + input reset, + + //图像输出信号 + output [2:0] video_red, //红色像素，3位 + output [2:0] video_green, //绿色像素，3位 + output [1:0] video_blue, //蓝色像素，2位 + output video_hsync, //行同步（水平同步）信号 + output video_vsync, //场同步（垂直同步）信号 + output video_clk, //像素时钟输出 + output video_de, //行数据有效信号，用于区分消隐区 + + input [3:0] touch_btn, //BTN1~BTN4，按钮开关，按下时为1 + input [31:0] dip_sw, //32位拨码开关，拨到“ON”时为1 + output [15:0] leds, //16位LED，输出时1点亮 + output [7:0] dpy0, //数码管低位信号，包括小数点，输出1点亮 + output [7:0] dpy1, //数码管高位信号，包括小数点，输出1点亮 + + //BaseRAM信号 + inout [31:0] base_ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享 + output [19:0] base_ram_addr, //BaseRAM地址 + output [ 3:0] base_ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0 + output base_ram_ce_n, //BaseRAM片选，低有效 + output base_ram_oe_n, //BaseRAM读使能，低有效 + output base_ram_we_n, //BaseRAM写使能，低有效 + //ExtRAM信号 + inout [31:0] ext_ram_data, //ExtRAM数据 + output [19:0] ext_ram_addr, //ExtRAM地址 + output [ 3:0] ext_ram_be_n, //ExtRAM字节使能，低有效。如果不使用字节使能，请保持为0 + output ext_ram_ce_n, //ExtRAM片选，低有效 + output ext_ram_oe_n, //ExtRAM读使能，低有效 + output ext_ram_we_n, //ExtRAM写使能，低有效 + + //------uart------- + inout UART_RX, //串口RX接收 + inout UART_TX //串口TX发送 +); + +wire cpu_clk; +wire cpu_resetn; +wire sys_clk; +wire sys_resetn; +wire pll_locked; + +generate if(SIMULATION) begin: sim_clk + //simulation clk. + reg clk_sim; + initial begin + clk_sim = 1'b0; + end + always #15 clk_sim = ~clk_sim; + + assign cpu_clk = clk_sim; + assign sys_clk = clk; + rst_sync u_rst_sys( + .clk(sys_clk), + .rst_n_in(~reset), + .rst_n_out(sys_resetn) + ); + rst_sync u_rst_cpu( + .clk(cpu_clk), + .rst_n_in(sys_resetn), + .rst_n_out(cpu_resetn) + ); +end +else begin: pll_clk + clk_pll u_clk_pll( + .cpu_clk (cpu_clk), + .sys_clk (sys_clk), + .resetn (~reset), + .locked (pll_locked), + .clk_in1 (clk) + ); + rst_sync u_rst_sys( + .clk(sys_clk), + .rst_n_in(pll_locked), + .rst_n_out(sys_resetn) + ); + rst_sync u_rst_cpu( + .clk(cpu_clk), + .rst_n_in(sys_resetn), + .rst_n_out(cpu_resetn) + ); +end +endgenerate + +//debug signals +wire [31:0] debug_wb_pc; +wire [31:0] debug_wb_inst; +wire [3 :0] debug_wb_rf_wen; +wire [4 :0] debug_wb_rf_wnum; +wire [31:0] debug_wb_rf_wdata; + +//cpu axi +wire [3 :0] cpu_arid ; +wire [31:0] cpu_araddr ; +wire [7 :0] cpu_arlen ; +wire [2 :0] cpu_arsize ; +wire [1 :0] cpu_arburst; +wire [1 :0] cpu_arlock ; +wire [3 :0] cpu_arcache; +wire [2 :0] cpu_arprot ; +wire cpu_arvalid; +wire cpu_arready; +wire [3 :0] cpu_rid ; +wire [31:0] cpu_rdata ; +wire [1 :0] cpu_rresp ; +wire cpu_rlast ; +wire cpu_rvalid ; +wire cpu_rready ; +wire [3 :0] cpu_awid ; +wire [31:0] cpu_awaddr ; +wire [7 :0] cpu_awlen ; +wire [2 :0] cpu_awsize ; +wire [1 :0] cpu_awburst; +wire [1 :0] cpu_awlock ; +wire [3 :0] cpu_awcache; +wire [2 :0] cpu_awprot ; +wire cpu_awvalid; +wire cpu_awready; +wire [3 :0] cpu_wid ; +wire [31:0] cpu_wdata ; +wire [3 :0] cpu_wstrb ; +wire cpu_wlast ; +wire cpu_wvalid ; +wire cpu_wready ; +wire [3 :0] cpu_bid ; +wire [1 :0] cpu_bresp ; +wire cpu_bvalid ; +wire cpu_bready ; +wire cpu_sync_awid_4 ; +wire cpu_bid_4 ; +wire cpu_sync_arid_4 ; +wire cpu_rid_4 ; + +//cpu axi sync +wire [3 :0] cpu_sync_arid ; +wire [31:0] cpu_sync_araddr ; +wire [7 :0] cpu_sync_arlen ; +wire [2 :0] cpu_sync_arsize ; +wire [1 :0] cpu_sync_arburst; +wire cpu_sync_arlock ; +wire [3 :0] cpu_sync_arcache; +wire [2 :0] cpu_sync_arprot ; +wire cpu_sync_arvalid; +wire cpu_sync_arready; +wire [3 :0] cpu_sync_rid ; +wire [31:0] cpu_sync_rdata ; +wire [1 :0] cpu_sync_rresp ; +wire cpu_sync_rlast ; +wire cpu_sync_rvalid ; +wire cpu_sync_rready ; +wire [3 :0] cpu_sync_awid ; +wire [31:0] cpu_sync_awaddr ; +wire [7 :0] cpu_sync_awlen ; +wire [2 :0] cpu_sync_awsize ; +wire [1 :0] cpu_sync_awburst; +wire cpu_sync_awlock ; +wire [3 :0] cpu_sync_awcache; +wire [2 :0] cpu_sync_awprot ; +wire cpu_sync_awvalid; +wire cpu_sync_awready; +wire [3 :0] cpu_sync_wid ; +wire [31:0] cpu_sync_wdata ; +wire [3 :0] cpu_sync_wstrb ; +wire cpu_sync_wlast ; +wire cpu_sync_wvalid ; +wire cpu_sync_wready ; +wire [3 :0] cpu_sync_bid ; +wire [1 :0] cpu_sync_bresp ; +wire cpu_sync_bvalid ; +wire cpu_sync_bready ; + +//axi ram +wire [4 :0] ram_arid ; +wire [31:0] ram_araddr ; +wire [7 :0] ram_arlen ; +wire [2 :0] ram_arsize ; +wire [1 :0] ram_arburst; +wire ram_arlock ; +wire [3 :0] ram_arcache; +wire [2 :0] ram_arprot ; +wire ram_arvalid; +wire ram_arready; +wire [4 :0] ram_rid ; +wire [31:0] ram_rdata ; +wire [1 :0] ram_rresp ; +wire ram_rlast ; +wire ram_rvalid ; +wire ram_rready ; +wire [4 :0] ram_awid ; +wire [31:0] ram_awaddr ; +wire [7 :0] ram_awlen ; +wire [2 :0] ram_awsize ; +wire [1 :0] ram_awburst; +wire ram_awlock ; +wire [3 :0] ram_awcache; +wire [2 :0] ram_awprot ; +wire ram_awvalid; +wire ram_awready; +wire [4 :0] ram_wid ; +wire [31:0] ram_wdata ; +wire [3 :0] ram_wstrb ; +wire ram_wlast ; +wire ram_wvalid ; +wire ram_wready ; +wire [4 :0] ram_bid ; +wire [1 :0] ram_bresp ; +wire ram_bvalid ; +wire ram_bready ; + +//uart axi +wire uart_arready; +wire [ 4:0] uart_rid; +wire [31:0] uart_rdata; +wire [ 1:0] uart_rresp; +wire uart_rlast; +wire uart_rvalid; +wire uart_awready; +wire uart_wready; +wire [ 4:0] uart_bid; +wire [ 1:0] uart_bresp; +wire uart_bvalid; +wire [ 4:0] uart_arid; +wire [31:0] uart_araddr; +wire [ 7:0] uart_arlen; +wire [ 2:0] uart_arsize; +wire [ 1:0] uart_arburst; +wire uart_arlock; +wire [ 3:0] uart_arcache; +wire [ 2:0] uart_arprot; +wire uart_arvalid; +wire uart_rready; +wire [ 4:0] uart_awid; +wire [31:0] uart_awaddr; +wire [ 7:0] uart_awlen; +wire [ 2:0] uart_awsize; +wire [ 1:0] uart_awburst; +wire uart_awlock; +wire [ 3:0] uart_awcache; +wire [ 2:0] uart_awprot; +wire uart_awvalid; +wire [ 4:0] uart_wid; +wire [31:0] uart_wdata; +wire [ 3:0] uart_wstrb; +wire uart_wlast; +wire uart_wvalid; +wire uart_bready; +wire irq_rx; + +//uart +wire UART_CTS, UART_RTS; +wire UART_DTR, UART_DSR; +wire UART_RI, UART_DCD; +assign UART_CTS = 1'b0; +assign UART_DSR = 1'b0; +assign UART_DCD = 1'b0; +assign UART_RI = 1'b0; +wire uart0_int ; +wire uart0_txd_o ; +wire uart0_txd_i ; +wire uart0_txd_oe; +wire uart0_rxd_o ; +wire uart0_rxd_i ; +wire uart0_rxd_oe; +wire uart0_rts_o ; +wire uart0_cts_i ; +wire uart0_dsr_i ; +wire uart0_dcd_i ; +wire uart0_dtr_o ; +wire uart0_ri_i ; +assign UART_RX = uart0_rxd_oe ? 1'bz : uart0_rxd_o ; +assign UART_TX = uart0_txd_oe ? 1'bz : uart0_txd_o ; +assign UART_RTS = uart0_rts_o ; +assign UART_DTR = uart0_dtr_o ; +assign uart0_txd_i = UART_TX; +assign uart0_rxd_i = UART_RX; +assign uart0_cts_i = UART_CTS; +assign uart0_dcd_i = UART_DCD; +assign uart0_dsr_i = UART_DSR; +assign uart0_ri_i = UART_RI ; + +//dma master axi +wire [3 :0] dma_m_arid ; +wire [31:0] dma_m_araddr ; +wire [7 :0] dma_m_arlen ; +wire [2 :0] dma_m_arsize ; +wire [1 :0] dma_m_arburst; +wire dma_m_arlock ; +wire [3 :0] dma_m_arcache; +wire [2 :0] dma_m_arprot ; +wire dma_m_arvalid; +wire dma_m_arready; +wire [3 :0] dma_m_rid ; +wire [31:0] dma_m_rdata ; +wire [1 :0] dma_m_rresp ; +wire dma_m_rlast ; +wire dma_m_rvalid ; +wire dma_m_rready ; +wire [3 :0] dma_m_awid ; +wire [31:0] dma_m_awaddr ; +wire [7 :0] dma_m_awlen ; +wire [2 :0] dma_m_awsize ; +wire [1 :0] dma_m_awburst; +wire dma_m_awlock ; +wire [3 :0] dma_m_awcache; +wire [2 :0] dma_m_awprot ; +wire dma_m_awvalid; +wire dma_m_awready; +wire [3 :0] dma_m_wid ; +wire [31:0] dma_m_wdata ; +wire [3 :0] dma_m_wstrb ; +wire dma_m_wlast ; +wire dma_m_wvalid ; +wire dma_m_wready ; +wire [3 :0] dma_m_bid ; +wire [1 :0] dma_m_bresp ; +wire dma_m_bvalid ; +wire dma_m_bready ; + +wire [4 :0] dma_s_arid ; +wire [31:0] dma_s_araddr ; +wire [7 :0] dma_s_arlen ; +wire [2 :0] dma_s_arsize ; +wire [1 :0] dma_s_arburst; +wire dma_s_arlock ; +wire [3 :0] dma_s_arcache; +wire [2 :0] dma_s_arprot ; +wire dma_s_arvalid; +wire dma_s_arready; +wire [4 :0] dma_s_rid ; +wire [31:0] dma_s_rdata ; +wire [1 :0] dma_s_rresp ; +wire dma_s_rlast ; +wire dma_s_rvalid ; +wire dma_s_rready ; +wire [4 :0] dma_s_awid ; +wire [31:0] dma_s_awaddr ; +wire [7 :0] dma_s_awlen ; +wire [2 :0] dma_s_awsize ; +wire [1 :0] dma_s_awburst; +wire dma_s_awlock ; +wire [3 :0] dma_s_awcache; +wire [2 :0] dma_s_awprot ; +wire dma_s_awvalid; +wire dma_s_awready; +wire [31:0] dma_s_wdata ; +wire [3 :0] dma_s_wstrb ; +wire dma_s_wlast ; +wire dma_s_wvalid ; +wire dma_s_wready ; +wire [4 :0] dma_s_bid ; +wire [1 :0] dma_s_bresp ; +wire dma_s_bvalid ; +wire dma_s_bready ; +wire dma_finish ; + +// reserved +wire [4 :0] axiOut_1_arid ; +wire [31:0] axiOut_1_araddr ; +wire [7 :0] axiOut_1_arlen ; +wire [2 :0] axiOut_1_arsize ; +wire [1 :0] axiOut_1_arburst; +wire axiOut_1_arlock ; +wire [3 :0] axiOut_1_arcache; +wire [2 :0] axiOut_1_arprot ; +wire axiOut_1_arvalid; +wire axiOut_1_arready; +wire [4 :0] axiOut_1_rid ; +wire [31:0] axiOut_1_rdata ; +wire [1 :0] axiOut_1_rresp ; +wire axiOut_1_rlast ; +wire axiOut_1_rvalid ; +wire axiOut_1_rready ; +wire [4 :0] axiOut_1_awid ; +wire [31:0] axiOut_1_awaddr ; +wire [7 :0] axiOut_1_awlen ; +wire [2 :0] axiOut_1_awsize ; +wire [1 :0] axiOut_1_awburst; +wire axiOut_1_awlock ; +wire [3 :0] axiOut_1_awcache; +wire [2 :0] axiOut_1_awprot ; +wire axiOut_1_awvalid; +wire axiOut_1_awready; +wire [4 :0] axiOut_1_wid ; +wire [31:0] axiOut_1_wdata ; +wire [3 :0] axiOut_1_wstrb ; +wire axiOut_1_wlast ; +wire axiOut_1_wvalid ; +wire axiOut_1_wready ; +wire [4 :0] axiOut_1_bid ; +wire [1 :0] axiOut_1_bresp ; +wire axiOut_1_bvalid ; +wire axiOut_1_bready ; + +assign axiOut_1_arready = 1'b1; +assign axiOut_1_rid = 5'b0; +assign axiOut_1_rdata = 32'b0; +assign axiOut_1_rresp = 2'b0; +assign axiOut_1_rlast = 1'b0; +assign axiOut_1_rvalid = 1'b0; +assign axiOut_1_awready = 1'b1; +assign axiOut_1_wready = 1'b1; +assign axiOut_1_bid = 5'b0; +assign axiOut_1_bresp = 2'b0; +assign axiOut_1_bvalid = 1'b0; + + +//axi dvi +wire [4 :0] dvi_arid ; +wire [31:0] dvi_araddr ; +wire [7 :0] dvi_arlen ; +wire [2 :0] dvi_arsize ; +wire [1 :0] dvi_arburst; +wire [1 :0] dvi_arlock ; +wire [3 :0] dvi_arcache; +wire [2 :0] dvi_arprot ; +wire dvi_arvalid; +wire dvi_arready; +wire [4 :0] dvi_rid ; +wire [31:0] dvi_rdata ; +wire [1 :0] dvi_rresp ; +wire dvi_rlast ; +wire dvi_rvalid ; +wire dvi_rready ; +wire [4 :0] dvi_awid ; +wire [31:0] dvi_awaddr ; +wire [7 :0] dvi_awlen ; +wire [2 :0] dvi_awsize ; +wire [1 :0] dvi_awburst; +wire [1 :0] dvi_awlock ; +wire [3 :0] dvi_awcache; +wire [2 :0] dvi_awprot ; +wire dvi_awvalid; +wire dvi_awready; +wire [4 :0] dvi_wid ; +wire [31:0] dvi_wdata ; +wire [3 :0] dvi_wstrb ; +wire dvi_wlast ; +wire dvi_wvalid ; +wire dvi_wready ; +wire [4 :0] dvi_bid ; +wire [1 :0] dvi_bresp ; +wire dvi_bvalid ; +wire dvi_bready ; + +//axi confreg +wire [4 :0] confreg_arid ; +wire [31:0] confreg_araddr ; +wire [7 :0] confreg_arlen ; +wire [2 :0] confreg_arsize ; +wire [1 :0] confreg_arburst; +wire confreg_arlock ; +wire [3 :0] confreg_arcache; +wire [2 :0] confreg_arprot ; +wire confreg_arvalid; +wire confreg_arready; +wire [4 :0] confreg_rid ; +wire [31:0] confreg_rdata ; +wire [1 :0] confreg_rresp ; +wire confreg_rlast ; +wire confreg_rvalid ; +wire confreg_rready ; +wire [4 :0] confreg_awid ; +wire [31:0] confreg_awaddr ; +wire [7 :0] confreg_awlen ; +wire [2 :0] confreg_awsize ; +wire [1 :0] confreg_awburst; +wire confreg_awlock ; +wire [3 :0] confreg_awcache; +wire [2 :0] confreg_awprot ; +wire confreg_awvalid; +wire confreg_awready; +wire [4 :0] confreg_wid ; +wire [31:0] confreg_wdata ; +wire [3 :0] confreg_wstrb ; +wire confreg_wlast ; +wire confreg_wvalid ; +wire confreg_wready ; +wire [4 :0] confreg_bid ; +wire [1 :0] confreg_bresp ; +wire confreg_bvalid ; +wire confreg_bready ; + +//slave 6 FFT/IFFT +wire [4 :0] fft_arid ; +wire [31:0] fft_araddr ; +wire [7 :0] fft_arlen ; +wire [2 :0] fft_arsize ; +wire [1 :0] fft_arburst; +wire fft_arlock ; +wire [3 :0] fft_arcache; +wire [2 :0] fft_arprot ; +wire fft_arvalid; +wire fft_arready; +wire [4 :0] fft_rid ; +wire [31:0] fft_rdata ; +wire [1 :0] fft_rresp ; +wire fft_rlast ; +wire fft_rvalid ; +wire fft_rready ; +wire [4 :0] fft_awid ; +wire [31:0] fft_awaddr ; +wire [7 :0] fft_awlen ; +wire [2 :0] fft_awsize ; +wire [1 :0] fft_awburst; +wire fft_awlock ; +wire [3 :0] fft_awcache; +wire [2 :0] fft_awprot ; +wire fft_awvalid; +wire fft_awready; +wire [4 :0] fft_wid ; +wire [31:0] fft_wdata ; +wire [3 :0] fft_wstrb ; +wire fft_wlast ; +wire fft_wvalid ; +wire fft_wready ; +wire [4 :0] fft_bid ; +wire [1 :0] fft_bresp ; +wire fft_bvalid ; +wire fft_bready ; +wire fft_finish ; + +//slave 7 +wire [4 :0] axiOut_7_arid ; +wire [31:0] axiOut_7_araddr ; +wire [7 :0] axiOut_7_arlen ; +wire [2 :0] axiOut_7_arsize ; +wire [1 :0] axiOut_7_arburst; +wire axiOut_7_arlock ; +wire [3 :0] axiOut_7_arcache; +wire [2 :0] axiOut_7_arprot ; +wire axiOut_7_arvalid; +wire axiOut_7_arready; +wire [4 :0] axiOut_7_rid ; +wire [31:0] axiOut_7_rdata ; +wire [1 :0] axiOut_7_rresp ; +wire axiOut_7_rlast ; +wire axiOut_7_rvalid ; +wire axiOut_7_rready ; +wire [4 :0] axiOut_7_awid ; +wire [31:0] axiOut_7_awaddr ; +wire [7 :0] axiOut_7_awlen ; +wire [2 :0] axiOut_7_awsize ; +wire [1 :0] axiOut_7_awburst; +wire axiOut_7_awlock ; +wire [3 :0] axiOut_7_awcache; +wire [2 :0] axiOut_7_awprot ; +wire axiOut_7_awvalid; +wire axiOut_7_awready; +wire [4 :0] axiOut_7_wid ; +wire [31:0] axiOut_7_wdata ; +wire [3 :0] axiOut_7_wstrb ; +wire axiOut_7_wlast ; +wire axiOut_7_wvalid ; +wire axiOut_7_wready ; +wire [4 :0] axiOut_7_bid ; +wire [1 :0] axiOut_7_bresp ; +wire axiOut_7_bvalid ; +wire axiOut_7_bready ; + +//slave 7 - matmul accelerator +matmul_axi_slave u_matmul_axi_slave ( + .clk (sys_clk), + .resetn (sys_resetn), + + .s_axi_awid (axiOut_7_awid ), + .s_axi_awaddr (axiOut_7_awaddr ), + .s_axi_awlen (axiOut_7_awlen ), + .s_axi_awsize (axiOut_7_awsize ), + .s_axi_awburst (axiOut_7_awburst), + .s_axi_awlock (axiOut_7_awlock ), + .s_axi_awcache (axiOut_7_awcache), + .s_axi_awprot (axiOut_7_awprot ), + .s_axi_awvalid (axiOut_7_awvalid), + .s_axi_awready (axiOut_7_awready), + + .s_axi_wid (axiOut_7_wid ), + .s_axi_wdata (axiOut_7_wdata ), + .s_axi_wstrb (axiOut_7_wstrb ), + .s_axi_wlast (axiOut_7_wlast ), + .s_axi_wvalid (axiOut_7_wvalid), + .s_axi_wready (axiOut_7_wready), + + .s_axi_bid (axiOut_7_bid ), + .s_axi_bresp (axiOut_7_bresp ), + .s_axi_bvalid (axiOut_7_bvalid), + .s_axi_bready (axiOut_7_bready), + + .s_axi_arid (axiOut_7_arid ), + .s_axi_araddr (axiOut_7_araddr ), + .s_axi_arlen (axiOut_7_arlen ), + .s_axi_arsize (axiOut_7_arsize ), + .s_axi_arburst (axiOut_7_arburst), + .s_axi_arlock (axiOut_7_arlock ), + .s_axi_arcache (axiOut_7_arcache), + .s_axi_arprot (axiOut_7_arprot ), + .s_axi_arvalid (axiOut_7_arvalid), + .s_axi_arready (axiOut_7_arready), + + .s_axi_rid (axiOut_7_rid ), + .s_axi_rdata (axiOut_7_rdata ), + .s_axi_rresp (axiOut_7_rresp ), + .s_axi_rlast (axiOut_7_rlast ), + .s_axi_rvalid (axiOut_7_rvalid), + .s_axi_rready (axiOut_7_rready) +); + +wire confreg_int; + +AxiCrossbar_2x8 u_AxiCrossbar_2x8 ( + .clk ( sys_clk ), + .resetn ( sys_resetn ), + + //master 0 + //aw + .axiIn_0_awvalid ( cpu_sync_awvalid ), + .axiIn_0_awready ( cpu_sync_awready ), + .axiIn_0_awaddr ( cpu_sync_awaddr ), + .axiIn_0_awid ( cpu_sync_awid ), + .axiIn_0_awlen ( cpu_sync_awlen ), + .axiIn_0_awsize ( cpu_sync_awsize ), + .axiIn_0_awburst ( cpu_sync_awburst ), + .axiIn_0_awlock ( cpu_sync_awlock ), + .axiIn_0_awcache ( cpu_sync_awcache ), + .axiIn_0_awprot ( cpu_sync_awprot ), + //w + .axiIn_0_wvalid ( cpu_sync_wvalid ), + .axiIn_0_wready ( cpu_sync_wready ), + .axiIn_0_wdata ( cpu_sync_wdata ), + .axiIn_0_wstrb ( cpu_sync_wstrb ), + .axiIn_0_wlast ( cpu_sync_wlast ), + //b + .axiIn_0_bready ( cpu_sync_bready ), + .axiIn_0_bvalid ( cpu_sync_bvalid ), + .axiIn_0_bid ( cpu_sync_bid ), + .axiIn_0_bresp ( cpu_sync_bresp ), + //ar + .axiIn_0_arvalid ( cpu_sync_arvalid ), + .axiIn_0_arready ( cpu_sync_arready ), + .axiIn_0_araddr ( cpu_sync_araddr ), + .axiIn_0_arid ( cpu_sync_arid ), + .axiIn_0_arlen ( cpu_sync_arlen ), + .axiIn_0_arsize ( cpu_sync_arsize ), + .axiIn_0_arburst ( cpu_sync_arburst ), + .axiIn_0_arlock ( cpu_sync_arlock ), + .axiIn_0_arcache ( cpu_sync_arcache ), + .axiIn_0_arprot ( cpu_sync_arprot ), + //r + .axiIn_0_rvalid ( cpu_sync_rvalid ), + .axiIn_0_rready ( cpu_sync_rready ), + .axiIn_0_rdata ( cpu_sync_rdata ), + .axiIn_0_rid ( cpu_sync_rid ), + .axiIn_0_rresp ( cpu_sync_rresp ), + .axiIn_0_rlast ( cpu_sync_rlast ), + + //master 1 + //aw + .axiIn_1_awvalid ( dma_m_awvalid ), + .axiIn_1_awready ( dma_m_awready ), + .axiIn_1_awaddr ( dma_m_awaddr ), + .axiIn_1_awid ( dma_m_awid ), + .axiIn_1_awlen ( dma_m_awlen ), + .axiIn_1_awsize ( dma_m_awsize ), + .axiIn_1_awburst ( dma_m_awburst ), + .axiIn_1_awlock ( dma_m_awlock ), + .axiIn_1_awcache ( dma_m_awcache ), + .axiIn_1_awprot ( dma_m_awprot ), + //w + .axiIn_1_wvalid ( dma_m_wvalid ), + .axiIn_1_wready ( dma_m_wready ), + .axiIn_1_wdata ( dma_m_wdata ), + .axiIn_1_wstrb ( dma_m_wstrb ), + .axiIn_1_wlast ( dma_m_wlast ), + //b + .axiIn_1_bready ( dma_m_bready ), + .axiIn_1_bvalid ( dma_m_bvalid ), + .axiIn_1_bid ( dma_m_bid ), + .axiIn_1_bresp ( dma_m_bresp ), + //ar + .axiIn_1_arvalid ( dma_m_arvalid ), + .axiIn_1_arready ( dma_m_arready ), + .axiIn_1_araddr ( dma_m_araddr ), + .axiIn_1_arid ( dma_m_arid ), + .axiIn_1_arlen ( dma_m_arlen ), + .axiIn_1_arsize ( dma_m_arsize ), + .axiIn_1_arburst ( dma_m_arburst ), + .axiIn_1_arlock ( dma_m_arlock ), + .axiIn_1_arcache ( dma_m_arcache ), + .axiIn_1_arprot ( dma_m_arprot ), + //r + .axiIn_1_rvalid ( dma_m_rvalid ), + .axiIn_1_rready ( dma_m_rready ), + .axiIn_1_rdata ( dma_m_rdata ), + .axiIn_1_rid ( dma_m_rid ), + .axiIn_1_rresp ( dma_m_rresp ), + .axiIn_1_rlast ( dma_m_rlast ), + + //slave 0 + //aw + .axiOut_0_awvalid ( ram_awvalid ), + .axiOut_0_awready ( ram_awready ), + .axiOut_0_awaddr ( ram_awaddr ), + .axiOut_0_awid ( ram_awid ), + .axiOut_0_awlen ( ram_awlen ), + .axiOut_0_awsize ( ram_awsize ), + .axiOut_0_awburst ( ram_awburst ), + .axiOut_0_awlock ( ram_awlock ), + .axiOut_0_awcache ( ram_awcache ), + .axiOut_0_awprot ( ram_awprot ), + //w + .axiOut_0_wvalid ( ram_wvalid ), + .axiOut_0_wready ( ram_wready ), + .axiOut_0_wdata ( ram_wdata ), + .axiOut_0_wstrb ( ram_wstrb ), + .axiOut_0_wlast ( ram_wlast ), + //b + .axiOut_0_bready ( ram_bready ), + .axiOut_0_bvalid ( ram_bvalid ), + .axiOut_0_bid ( ram_bid ), + .axiOut_0_bresp ( ram_bresp ), + //ar + .axiOut_0_arvalid ( ram_arvalid ), + .axiOut_0_arready ( ram_arready ), + .axiOut_0_araddr ( ram_araddr ), + .axiOut_0_arid ( ram_arid ), + .axiOut_0_arlen ( ram_arlen ), + .axiOut_0_arsize ( ram_arsize ), + .axiOut_0_arburst ( ram_arburst ), + .axiOut_0_arlock ( ram_arlock ), + .axiOut_0_arcache ( ram_arcache ), + .axiOut_0_arprot ( ram_arprot ), + //r + .axiOut_0_rvalid ( ram_rvalid ), + .axiOut_0_rready ( ram_rready ), + .axiOut_0_rdata ( ram_rdata ), + .axiOut_0_rid ( ram_rid ), + .axiOut_0_rresp ( ram_rresp ), + .axiOut_0_rlast ( ram_rlast ), + + //slave 1 + //aw + .axiOut_1_awvalid ( axiOut_1_awvalid ), + .axiOut_1_awready ( axiOut_1_awready ), + .axiOut_1_awaddr ( axiOut_1_awaddr ), + .axiOut_1_awid ( axiOut_1_awid ), + .axiOut_1_awlen ( axiOut_1_awlen ), + .axiOut_1_awsize ( axiOut_1_awsize ), + .axiOut_1_awburst ( axiOut_1_awburst ), + .axiOut_1_awlock ( axiOut_1_awlock ), + .axiOut_1_awcache ( axiOut_1_awcache ), + .axiOut_1_awprot ( axiOut_1_awprot ), + //w + .axiOut_1_wvalid ( axiOut_1_wvalid ), + .axiOut_1_wready ( axiOut_1_wready ), + .axiOut_1_wdata ( axiOut_1_wdata ), + .axiOut_1_wstrb ( axiOut_1_wstrb ), + .axiOut_1_wlast ( axiOut_1_wlast ), + //b + .axiOut_1_bready ( axiOut_1_bready ), + .axiOut_1_bvalid ( axiOut_1_bvalid ), + .axiOut_1_bid ( axiOut_1_bid ), + .axiOut_1_bresp ( axiOut_1_bresp ), + //ar + .axiOut_1_arvalid ( axiOut_1_arvalid ), + .axiOut_1_arready ( axiOut_1_arready ), + .axiOut_1_araddr ( axiOut_1_araddr ), + .axiOut_1_arid ( axiOut_1_arid ), + .axiOut_1_arlen ( axiOut_1_arlen ), + .axiOut_1_arsize ( axiOut_1_arsize ), + .axiOut_1_arburst ( axiOut_1_arburst ), + .axiOut_1_arlock ( axiOut_1_arlock ), + .axiOut_1_arcache ( axiOut_1_arcache ), + .axiOut_1_arprot ( axiOut_1_arprot ), + //r + .axiOut_1_rvalid ( axiOut_1_rvalid ), + .axiOut_1_rready ( axiOut_1_rready ), + .axiOut_1_rdata ( axiOut_1_rdata ), + .axiOut_1_rid ( axiOut_1_rid ), + .axiOut_1_rresp ( axiOut_1_rresp ), + .axiOut_1_rlast ( axiOut_1_rlast ), + + //slave 2 + //aw + .axiOut_2_awvalid ( uart_awvalid ), + .axiOut_2_awready ( uart_awready ), + .axiOut_2_awaddr ( uart_awaddr ), + .axiOut_2_awid ( uart_awid ), + .axiOut_2_awlen ( uart_awlen ), + .axiOut_2_awsize ( uart_awsize ), + .axiOut_2_awburst ( uart_awburst ), + .axiOut_2_awlock ( uart_awlock ), + .axiOut_2_awcache ( uart_awcache ), + .axiOut_2_awprot ( uart_awprot ), + //w + .axiOut_2_wvalid ( uart_wvalid ), + .axiOut_2_wready ( uart_wready ), + .axiOut_2_wdata ( uart_wdata ), + .axiOut_2_wstrb ( uart_wstrb ), + .axiOut_2_wlast ( uart_wlast ), + //b + .axiOut_2_bready ( uart_bready ), + .axiOut_2_bvalid ( uart_bvalid ), + .axiOut_2_bid ( uart_bid ), + .axiOut_2_bresp ( uart_bresp ), + //ar + .axiOut_2_arvalid ( uart_arvalid ), + .axiOut_2_arready ( uart_arready ), + .axiOut_2_araddr ( uart_araddr ), + .axiOut_2_arid ( uart_arid ), + .axiOut_2_arlen ( uart_arlen ), + .axiOut_2_arsize ( uart_arsize ), + .axiOut_2_arburst ( uart_arburst ), + .axiOut_2_arlock ( uart_arlock ), + .axiOut_2_arcache ( uart_arcache ), + .axiOut_2_arprot ( uart_arprot ), + //r + .axiOut_2_rvalid ( uart_rvalid ), + .axiOut_2_rready ( uart_rready ), + .axiOut_2_rdata ( uart_rdata ), + .axiOut_2_rid ( uart_rid ), + .axiOut_2_rresp ( uart_rresp ), + .axiOut_2_rlast ( uart_rlast ), + + //slave 3 + //aw + .axiOut_3_awvalid ( dvi_awvalid ), + .axiOut_3_awready ( dvi_awready ), + .axiOut_3_awaddr ( dvi_awaddr ), + .axiOut_3_awid ( dvi_awid ), + .axiOut_3_awlen ( dvi_awlen ), + .axiOut_3_awsize ( dvi_awsize ), + .axiOut_3_awburst ( dvi_awburst ), + .axiOut_3_awlock ( dvi_awlock ), + .axiOut_3_awcache ( dvi_awcache ), + .axiOut_3_awprot ( dvi_awprot ), + //w + .axiOut_3_wvalid ( dvi_wvalid ), + .axiOut_3_wready ( dvi_wready ), + .axiOut_3_wdata ( dvi_wdata ), + .axiOut_3_wstrb ( dvi_wstrb ), + .axiOut_3_wlast ( dvi_wlast ), + //b + .axiOut_3_bready ( dvi_bready ), + .axiOut_3_bvalid ( dvi_bvalid ), + .axiOut_3_bid ( dvi_bid ), + .axiOut_3_bresp ( dvi_bresp ), + //ar + .axiOut_3_arvalid ( dvi_arvalid ), + .axiOut_3_arready ( dvi_arready ), + .axiOut_3_araddr ( dvi_araddr ), + .axiOut_3_arid ( dvi_arid ), + .axiOut_3_arlen ( dvi_arlen ), + .axiOut_3_arsize ( dvi_arsize ), + .axiOut_3_arburst ( dvi_arburst ), + .axiOut_3_arlock ( dvi_arlock ), + .axiOut_3_arcache ( dvi_arcache ), + .axiOut_3_arprot ( dvi_arprot ), + //r + .axiOut_3_rvalid ( dvi_rvalid ), + .axiOut_3_rready ( dvi_rready ), + .axiOut_3_rdata ( dvi_rdata ), + .axiOut_3_rid ( dvi_rid ), + .axiOut_3_rresp ( dvi_rresp ), + .axiOut_3_rlast ( dvi_rlast ), + + + //slave 4 + //aw + .axiOut_4_awvalid ( confreg_awvalid ), + .axiOut_4_awready ( confreg_awready ), + .axiOut_4_awaddr ( confreg_awaddr ), + .axiOut_4_awid ( confreg_awid ), + .axiOut_4_awlen ( confreg_awlen ), + .axiOut_4_awsize ( confreg_awsize ), + .axiOut_4_awburst ( confreg_awburst ), + .axiOut_4_awlock ( confreg_awlock ), + .axiOut_4_awcache ( confreg_awcache ), + .axiOut_4_awprot ( confreg_awprot ), + //w + .axiOut_4_wvalid ( confreg_wvalid ), + .axiOut_4_wready ( confreg_wready ), + .axiOut_4_wdata ( confreg_wdata ), + .axiOut_4_wstrb ( confreg_wstrb ), + .axiOut_4_wlast ( confreg_wlast ), + //b + .axiOut_4_bready ( confreg_bready ), + .axiOut_4_bvalid ( confreg_bvalid ), + .axiOut_4_bid ( confreg_bid ), + .axiOut_4_bresp ( confreg_bresp ), + //ar + .axiOut_4_arvalid ( confreg_arvalid ), + .axiOut_4_arready ( confreg_arready ), + .axiOut_4_araddr ( confreg_araddr ), + .axiOut_4_arid ( confreg_arid ), + .axiOut_4_arlen ( confreg_arlen ), + .axiOut_4_arsize ( confreg_arsize ), + .axiOut_4_arburst ( confreg_arburst ), + .axiOut_4_arlock ( confreg_arlock ), + .axiOut_4_arcache ( confreg_arcache ), + .axiOut_4_arprot ( confreg_arprot ), + //r + .axiOut_4_rvalid ( confreg_rvalid ), + .axiOut_4_rready ( confreg_rready ), + .axiOut_4_rdata ( confreg_rdata ), + .axiOut_4_rid ( confreg_rid ), + .axiOut_4_rresp ( confreg_rresp ), + .axiOut_4_rlast ( confreg_rlast ), + + //slave 5 + //aw + .axiOut_5_awvalid ( dma_s_awvalid ), + .axiOut_5_awready ( dma_s_awready ), + .axiOut_5_awaddr ( dma_s_awaddr ), + .axiOut_5_awid ( dma_s_awid ), + .axiOut_5_awlen ( dma_s_awlen ), + .axiOut_5_awsize ( dma_s_awsize ), + .axiOut_5_awburst ( dma_s_awburst ), + .axiOut_5_awlock ( dma_s_awlock ), + .axiOut_5_awcache ( dma_s_awcache ), + .axiOut_5_awprot ( dma_s_awprot ), + //w + .axiOut_5_wvalid ( dma_s_wvalid ), + .axiOut_5_wready ( dma_s_wready ), + .axiOut_5_wdata ( dma_s_wdata ), + .axiOut_5_wstrb ( dma_s_wstrb ), + .axiOut_5_wlast ( dma_s_wlast ), + //b + .axiOut_5_bready ( dma_s_bready ), + .axiOut_5_bvalid ( dma_s_bvalid ), + .axiOut_5_bid ( dma_s_bid ), + .axiOut_5_bresp ( dma_s_bresp ), + //ar + .axiOut_5_arvalid ( dma_s_arvalid ), + .axiOut_5_arready ( dma_s_arready ), + .axiOut_5_araddr ( dma_s_araddr ), + .axiOut_5_arid ( dma_s_arid ), + .axiOut_5_arlen ( dma_s_arlen ), + .axiOut_5_arsize ( dma_s_arsize ), + .axiOut_5_arburst ( dma_s_arburst ), + .axiOut_5_arlock ( dma_s_arlock ), + .axiOut_5_arcache ( dma_s_arcache ), + .axiOut_5_arprot ( dma_s_arprot ), + //r + .axiOut_5_rvalid ( dma_s_rvalid ), + .axiOut_5_rready ( dma_s_rready ), + .axiOut_5_rdata ( dma_s_rdata ), + .axiOut_5_rid ( dma_s_rid ), + .axiOut_5_rresp ( dma_s_rresp ), + .axiOut_5_rlast ( dma_s_rlast ), + + //slave 6 + //aw + .axiOut_6_awvalid ( fft_awvalid ), + .axiOut_6_awready ( fft_awready ), + .axiOut_6_awaddr ( fft_awaddr ), + .axiOut_6_awid ( fft_awid ), + .axiOut_6_awlen ( fft_awlen ), + .axiOut_6_awsize ( fft_awsize ), + .axiOut_6_awburst ( fft_awburst ), + .axiOut_6_awlock ( fft_awlock ), + .axiOut_6_awcache ( fft_awcache ), + .axiOut_6_awprot ( fft_awprot ), + //w + .axiOut_6_wvalid ( fft_wvalid ), + .axiOut_6_wready ( fft_wready ), + .axiOut_6_wdata ( fft_wdata ), + .axiOut_6_wstrb ( fft_wstrb ), + .axiOut_6_wlast ( fft_wlast ), + //b + .axiOut_6_bready ( fft_bready ), + .axiOut_6_bvalid ( fft_bvalid ), + .axiOut_6_bid ( fft_bid ), + .axiOut_6_bresp ( fft_bresp ), + //ar + .axiOut_6_arvalid ( fft_arvalid ), + .axiOut_6_arready ( fft_arready ), + .axiOut_6_araddr ( fft_araddr ), + .axiOut_6_arid ( fft_arid ), + .axiOut_6_arlen ( fft_arlen ), + .axiOut_6_arsize ( fft_arsize ), + .axiOut_6_arburst ( fft_arburst ), + .axiOut_6_arlock ( fft_arlock ), + .axiOut_6_arcache ( fft_arcache ), + .axiOut_6_arprot ( fft_arprot ), + //r + .axiOut_6_rvalid ( fft_rvalid ), + .axiOut_6_rready ( fft_rready ), + .axiOut_6_rdata ( fft_rdata ), + .axiOut_6_rid ( fft_rid ), + .axiOut_6_rresp ( fft_rresp ), + .axiOut_6_rlast ( fft_rlast ), + + //slave 7 + //aw + .axiOut_7_awvalid ( axiOut_7_awvalid ), + .axiOut_7_awready ( axiOut_7_awready ), + .axiOut_7_awaddr ( axiOut_7_awaddr ), + .axiOut_7_awid ( axiOut_7_awid ), + .axiOut_7_awlen ( axiOut_7_awlen ), + .axiOut_7_awsize ( axiOut_7_awsize ), + .axiOut_7_awburst ( axiOut_7_awburst ), + .axiOut_7_awlock ( axiOut_7_awlock ), + .axiOut_7_awcache ( axiOut_7_awcache ), + .axiOut_7_awprot ( axiOut_7_awprot ), + //w + .axiOut_7_wvalid ( axiOut_7_wvalid ), + .axiOut_7_wready ( axiOut_7_wready ), + .axiOut_7_wdata ( axiOut_7_wdata ), + .axiOut_7_wstrb ( axiOut_7_wstrb ), + .axiOut_7_wlast ( axiOut_7_wlast ), + //b + .axiOut_7_bready ( axiOut_7_bready ), + .axiOut_7_bvalid ( axiOut_7_bvalid ), + .axiOut_7_bid ( axiOut_7_bid ), + .axiOut_7_bresp ( axiOut_7_bresp ), + //ar + .axiOut_7_arvalid ( axiOut_7_arvalid ), + .axiOut_7_arready ( axiOut_7_arready ), + .axiOut_7_araddr ( axiOut_7_araddr ), + .axiOut_7_arid ( axiOut_7_arid ), + .axiOut_7_arlen ( axiOut_7_arlen ), + .axiOut_7_arsize ( axiOut_7_arsize ), + .axiOut_7_arburst ( axiOut_7_arburst ), + .axiOut_7_arlock ( axiOut_7_arlock ), + .axiOut_7_arcache ( axiOut_7_arcache ), + .axiOut_7_arprot ( axiOut_7_arprot ), + //r + .axiOut_7_rvalid ( axiOut_7_rvalid ), + .axiOut_7_rready ( axiOut_7_rready ), + .axiOut_7_rdata ( axiOut_7_rdata ), + .axiOut_7_rid ( axiOut_7_rid ), + .axiOut_7_rresp ( axiOut_7_rresp ), + .axiOut_7_rlast ( axiOut_7_rlast ) + +); + +// add your code + +core_top u_cpu( + .intrpt ({7'b0, confreg_int}), //high active + + .aclk (cpu_clk ), + .aresetn (cpu_resetn ), //low active + + .arid (cpu_arid ), + .araddr (cpu_araddr ), + .arlen (cpu_arlen ), + .arsize (cpu_arsize ), + .arburst (cpu_arburst ), + .arlock (cpu_arlock ), + .arcache (cpu_arcache ), + .arprot (cpu_arprot ), + .arvalid (cpu_arvalid ), + .arready (cpu_arready ), + + .rid (cpu_rid ), + .rdata (cpu_rdata ), + .rresp (cpu_rresp ), + .rlast (cpu_rlast ), + .rvalid (cpu_rvalid ), + .rready (cpu_rready ), + + .awid (cpu_awid ), + .awaddr (cpu_awaddr ), + .awlen (cpu_awlen ), + .awsize (cpu_awsize ), + .awburst (cpu_awburst ), + .awlock (cpu_awlock ), + .awcache (cpu_awcache ), + .awprot (cpu_awprot ), + .awvalid (cpu_awvalid ), + .awready (cpu_awready ), + + .wid (cpu_wid ), + .wdata (cpu_wdata ), + .wstrb (cpu_wstrb ), + .wlast (cpu_wlast ), + .wvalid (cpu_wvalid ), + .wready (cpu_wready ), + + .bid (cpu_bid ), + .bresp (cpu_bresp ), + .bvalid (cpu_bvalid ), + .bready (cpu_bready ), + + //debug interface + .break_point (1'b0 ), + .infor_flag (1'b0 ), + .reg_num (5'b0 ), + .ws_valid ( ), + .rf_rdata ( ), + + .debug0_wb_pc (debug_wb_pc ), + .debug0_wb_inst (debug_wb_inst ), + .debug0_wb_rf_wen (debug_wb_rf_wen ), + .debug0_wb_rf_wnum (debug_wb_rf_wnum ), + .debug0_wb_rf_wdata (debug_wb_rf_wdata ) +); + +//clock sync: from CPU to AXI_Crossbar +Axi_CDC u_Axi_CDC ( + .axiInClk ( cpu_clk ), + .axiInRstn ( cpu_resetn ), + .axiOutClk ( sys_clk ), + .axiOutRstn ( sys_resetn ), + + .axiIn_awvalid ( cpu_awvalid ), + .axiIn_awaddr ( cpu_awaddr ), + .axiIn_awid ( {1'b0,cpu_awid} ), + .axiIn_awlen ( cpu_awlen ), + .axiIn_awsize ( cpu_awsize ), + .axiIn_awburst ( cpu_awburst ), + .axiIn_awlock ( cpu_awlock[0] ), + .axiIn_awcache ( cpu_awcache ), + .axiIn_awprot ( cpu_awprot ), + .axiIn_wvalid ( cpu_wvalid ), + .axiIn_wdata ( cpu_wdata ), + .axiIn_wstrb ( cpu_wstrb ), + .axiIn_wlast ( cpu_wlast ), + .axiIn_bready ( cpu_bready ), + .axiIn_arvalid ( cpu_arvalid ), + .axiIn_araddr ( cpu_araddr ), + .axiIn_arid ( {1'b0,cpu_arid} ), + .axiIn_arlen ( cpu_arlen ), + .axiIn_arsize ( cpu_arsize ), + .axiIn_arburst ( cpu_arburst ), + .axiIn_arlock ( cpu_arlock[0] ), + .axiIn_arcache ( cpu_arcache ), + .axiIn_arprot ( cpu_arprot ), + .axiIn_rready ( cpu_rready ), + .axiOut_awready ( cpu_sync_awready ), + .axiOut_wready ( cpu_sync_wready ), + .axiOut_bvalid ( cpu_sync_bvalid ), + .axiOut_bid ( {1'b0,cpu_sync_bid}), + .axiOut_bresp ( cpu_sync_bresp ), + .axiOut_arready ( cpu_sync_arready ), + .axiOut_rvalid ( cpu_sync_rvalid ), + .axiOut_rdata ( cpu_sync_rdata ), + .axiOut_rid ( {1'b0,cpu_sync_rid}), + .axiOut_rresp ( cpu_sync_rresp ), + .axiOut_rlast ( cpu_sync_rlast ), + + .axiIn_awready ( cpu_awready ), + .axiIn_wready ( cpu_wready ), + .axiIn_bvalid ( cpu_bvalid ), + .axiIn_bid ( {cpu_bid_4,cpu_bid} ), + .axiIn_bresp ( cpu_bresp ), + .axiIn_arready ( cpu_arready ), + .axiIn_rvalid ( cpu_rvalid ), + .axiIn_rdata ( cpu_rdata ), + .axiIn_rid ( {cpu_rid_4,cpu_rid} ), + .axiIn_rresp ( cpu_rresp ), + .axiIn_rlast ( cpu_rlast ), + .axiOut_awvalid ( cpu_sync_awvalid ), + .axiOut_awaddr ( cpu_sync_awaddr ), + .axiOut_awid ( {cpu_sync_awid_4,cpu_sync_awid}), + .axiOut_awlen ( cpu_sync_awlen ), + .axiOut_awsize ( cpu_sync_awsize ), + .axiOut_awburst ( cpu_sync_awburst ), + .axiOut_awlock ( cpu_sync_awlock ), + .axiOut_awcache ( cpu_sync_awcache ), + .axiOut_awprot ( cpu_sync_awprot ), + .axiOut_wvalid ( cpu_sync_wvalid ), + .axiOut_wdata ( cpu_sync_wdata ), + .axiOut_wstrb ( cpu_sync_wstrb ), + .axiOut_wlast ( cpu_sync_wlast ), + .axiOut_bready ( cpu_sync_bready ), + .axiOut_arvalid ( cpu_sync_arvalid ), + .axiOut_araddr ( cpu_sync_araddr ), + .axiOut_arid ( {cpu_sync_arid_4,cpu_sync_arid}), + .axiOut_arlen ( cpu_sync_arlen ), + .axiOut_arsize ( cpu_sync_arsize ), + .axiOut_arburst ( cpu_sync_arburst ), + .axiOut_arlock ( cpu_sync_arlock ), + .axiOut_arcache ( cpu_sync_arcache ), + .axiOut_arprot ( cpu_sync_arprot ), + .axiOut_rready ( cpu_sync_rready ) +); + +//axi ram +axi_wrap_ram_sp_external u_axi_ram ( + .aclk ( sys_clk ), + .aresetn ( sys_resetn ), + //ar + .axi_arid ( ram_arid ), + .axi_araddr ( ram_araddr ), + .axi_arlen ( ram_arlen ), + .axi_arsize ( ram_arsize ), + .axi_arburst ( ram_arburst ), + .axi_arlock ( ram_arlock ), + .axi_arcache ( ram_arcache ), + .axi_arprot ( ram_arprot ), + .axi_arvalid ( ram_arvalid ), + .axi_arready ( ram_arready ), + //r + .axi_rid ( ram_rid ), + .axi_rdata ( ram_rdata ), + .axi_rresp ( ram_rresp ), + .axi_rlast ( ram_rlast ), + .axi_rvalid ( ram_rvalid ), + .axi_rready ( ram_rready ), + //aw + .axi_awid ( ram_awid ), + .axi_awaddr ( ram_awaddr ), + .axi_awlen ( ram_awlen ), + .axi_awsize ( ram_awsize ), + .axi_awburst ( ram_awburst ), + .axi_awlock ( ram_awlock ), + .axi_awcache ( ram_awcache ), + .axi_awprot ( ram_awprot ), + .axi_awvalid ( ram_awvalid ), + .axi_awready ( ram_awready ), + //w + .axi_wdata ( ram_wdata ), + .axi_wstrb ( ram_wstrb ), + .axi_wlast ( ram_wlast ), + .axi_wvalid ( ram_wvalid ), + .axi_wready ( ram_wready ), + //b ram + .axi_bid ( ram_bid ), + .axi_bresp ( ram_bresp ), + .axi_bvalid ( ram_bvalid ), + .axi_bready ( ram_bready ), + + .base_ram_addr ( base_ram_addr ), + .base_ram_be_n ( base_ram_be_n ), + .base_ram_ce_n ( base_ram_ce_n ), + .base_ram_oe_n ( base_ram_oe_n ), + .base_ram_we_n ( base_ram_we_n ), + .ext_ram_addr ( ext_ram_addr ), + .ext_ram_be_n ( ext_ram_be_n ), + .ext_ram_ce_n ( ext_ram_ce_n ), + .ext_ram_oe_n ( ext_ram_oe_n ), + .ext_ram_we_n ( ext_ram_we_n ), + + .base_ram_data ( base_ram_data ), + .ext_ram_data ( ext_ram_data ) +); + +//AXI2APB +axi_uart_controller u_axi_uart_controller +( + .clk (sys_clk ), + .rst_n (sys_resetn ), + + .axi_s_awid (uart_awid ), + .axi_s_awaddr (uart_awaddr ), + .axi_s_awlen (uart_awlen ), + .axi_s_awsize (uart_awsize ), + .axi_s_awburst (uart_awburst ), + .axi_s_awlock (uart_awlock ), + .axi_s_awcache (uart_awcache ), + .axi_s_awprot (uart_awprot ), + .axi_s_awvalid (uart_awvalid ), + .axi_s_awready (uart_awready ), + .axi_s_wid (uart_awid ), + .axi_s_wdata (uart_wdata ), + .axi_s_wstrb (uart_wstrb ), + .axi_s_wlast (uart_wlast ), + .axi_s_wvalid (uart_wvalid ), + .axi_s_wready (uart_wready ), + .axi_s_bid (uart_bid ), + .axi_s_bresp (uart_bresp ), + .axi_s_bvalid (uart_bvalid ), + .axi_s_bready (uart_bready ), + .axi_s_arid (uart_arid ), + .axi_s_araddr (uart_araddr ), + .axi_s_arlen (uart_arlen ), + .axi_s_arsize (uart_arsize ), + .axi_s_arburst (uart_arburst ), + .axi_s_arlock (uart_arlock ), + .axi_s_arcache (uart_arcache ), + .axi_s_arprot (uart_arprot ), + .axi_s_arvalid (uart_arvalid ), + .axi_s_arready (uart_arready ), + .axi_s_rid (uart_rid ), + .axi_s_rdata (uart_rdata ), + .axi_s_rresp (uart_rresp ), + .axi_s_rlast (uart_rlast ), + .axi_s_rvalid (uart_rvalid ), + .axi_s_rready (uart_rready ), + + .apb_rw_dma (1'b0 ), + .apb_psel_dma (1'b0 ), + .apb_enab_dma (1'b0 ), + .apb_addr_dma (20'b0 ), + .apb_valid_dma (1'b0 ), + .apb_wdata_dma (32'b0 ), + .apb_rdata_dma ( ), + .apb_ready_dma ( ), + .dma_grant ( ), + + .dma_req_o ( ), + .dma_ack_i (1'b0 ), + + //UART0 + .uart0_txd_i (uart0_txd_i ), + .uart0_txd_o (uart0_txd_o ), + .uart0_txd_oe (uart0_txd_oe ), + .uart0_rxd_i (uart0_rxd_i ), + .uart0_rxd_o (uart0_rxd_o ), + .uart0_rxd_oe (uart0_rxd_oe ), + .uart0_rts_o (uart0_rts_o ), + .uart0_dtr_o (uart0_dtr_o ), + .uart0_cts_i (uart0_cts_i ), + .uart0_dsr_i (uart0_dsr_i ), + .uart0_dcd_i (uart0_dcd_i ), + .uart0_ri_i (uart0_ri_i ), + .uart0_int (uart0_int ) +); + +confreg #( + .SIMULATION(SIMULATION) +) u_confreg ( + // 时钟与复位 + .aclk (sys_clk), // AXI总线时钟 + .aresetn (sys_resetn), // AXI总线复位 + .cpu_clk (cpu_clk), // CPU时钟 + .cpu_resetn (cpu_resetn), // CPU复位 + + // AXI写地址通道 + .s_awid (confreg_awid), + .s_awaddr (confreg_awaddr), + .s_awlen (confreg_awlen), + .s_awsize (confreg_awsize), + .s_awburst (confreg_awburst), + .s_awlock (confreg_awlock), + .s_awcache (confreg_awcache), + .s_awprot (confreg_awprot), + .s_awvalid (confreg_awvalid), + .s_awready (confreg_awready), + + // AXI写数据通道 + .s_wid (confreg_wid), + .s_wdata (confreg_wdata), + .s_wstrb (confreg_wstrb), + .s_wlast (confreg_wlast), + .s_wvalid (confreg_wvalid), + .s_wready (confreg_wready), + + // AXI写响应通道 + .s_bid (confreg_bid), + .s_bresp (confreg_bresp), + .s_bvalid (confreg_bvalid), + .s_bready (confreg_bready), + + // AXI读地址通道 + .s_arid (confreg_arid), + .s_araddr (confreg_araddr), + .s_arlen (confreg_arlen), + .s_arsize (confreg_arsize), + .s_arburst (confreg_arburst), + .s_arlock (confreg_arlock), + .s_arcache (confreg_arcache), + .s_arprot (confreg_arprot), + .s_arvalid (confreg_arvalid), + .s_arready (confreg_arready), + + // AXI读数据通道 + .s_rid (confreg_rid), + .s_rdata (confreg_rdata), + .s_rresp (confreg_rresp), + .s_rlast (confreg_rlast), + .s_rvalid (confreg_rvalid), + .s_rready (confreg_rready), + + // IO外设接口 (与soc_top顶层引脚相连) + .led (leds), // 顶层引脚名称为 + .dpy0 (dpy0), // 低位数码管 + .dpy1 (dpy1), // 高位数码管 + .switch (dip_sw), // 拨码开关，顶层名称为 dip_sw + .touch_btn (touch_btn), // 触摸按钮 + + // 中断与状态信号 + .uart0_int (uart0_int), // UART0中断 + .dma_finish (dma_finish), // DMA完成信号 + .fft_finish (fft_finish), // FFT完成信号 + .confreg_int(confreg_int) // 输出中断给CPU +); + +axi_dvi u_axi_dvi ( + .s_awvalid ( dvi_awvalid ), + .s_awaddr ( dvi_awaddr ), + .s_awid ( dvi_awid ), + .s_awlen ( dvi_awlen ), + .s_awsize ( dvi_awsize ), + .s_awburst ( dvi_awburst ), + .s_awlock ( dvi_awlock ), + .s_awcache ( dvi_awcache ), + .s_awprot ( dvi_awprot ), + .s_wvalid ( dvi_wvalid ), + .s_wdata ( dvi_wdata ), + .s_wstrb ( dvi_wstrb ), + .s_wlast ( dvi_wlast ), + .s_bready ( dvi_bready ), + .s_arvalid ( dvi_arvalid ), + .s_araddr ( dvi_araddr ), + .s_arid ( dvi_arid ), + .s_arlen ( dvi_arlen ), + .s_arsize ( dvi_arsize ), + .s_arburst ( dvi_arburst ), + .s_arlock ( dvi_arlock ), + .s_arcache ( dvi_arcache ), + .s_arprot ( dvi_arprot ), + .s_rready ( dvi_rready ), + .aclk ( sys_clk ), + .aresetn ( sys_resetn ), + + .s_awready ( dvi_awready ), + .s_wready ( dvi_wready ), + .s_bvalid ( dvi_bvalid ), + .s_bid ( dvi_bid ), + .s_bresp ( dvi_bresp ), + .s_arready ( dvi_arready ), + .s_rvalid ( dvi_rvalid ), + .s_rdata ( dvi_rdata ), + .s_rid ( dvi_rid ), + .s_rresp ( dvi_rresp ), + .s_rlast ( dvi_rlast ), + .video_clk ( video_clk ), + .hsync ( video_hsync ), + .vsync ( video_vsync ), + .data_enable ( video_de ), + .video_red ( video_red ), + .video_green ( video_green ), + .video_blue ( video_blue ) +); + +fft_controller u_fft_controller( + .aclk (sys_clk ), + .aresetn (sys_resetn ), + .s_awid (fft_awid ), + .s_awaddr (fft_awaddr ), + .s_awlen (fft_awlen ), + .s_awsize (fft_awsize ), + .s_awburst (fft_awburst ), + .s_awlock (fft_awlock ), + .s_awcache (fft_awcache ), + .s_awprot (fft_awprot ), + .s_awvalid (fft_awvalid ), + .s_awready (fft_awready ), + .s_wid (fft_wid ), + .s_wdata (fft_wdata ), + .s_wstrb (fft_wstrb ), + .s_wlast (fft_wlast ), + .s_wvalid (fft_wvalid ), + .s_wready (fft_wready ), + .s_bid (fft_bid ), + .s_bresp (fft_bresp ), + .s_bvalid (fft_bvalid ), + .s_bready (fft_bready ), + .s_arid (fft_arid ), + .s_araddr (fft_araddr ), + .s_arlen (fft_arlen ), + .s_arsize (fft_arsize ), + .s_arburst (fft_arburst ), + .s_arlock (fft_arlock ), + .s_arcache (fft_arcache ), + .s_arprot (fft_arprot ), + .s_arvalid (fft_arvalid ), + .s_arready (fft_arready ), + .s_rid (fft_rid ), + .s_rdata (fft_rdata ), + .s_rresp (fft_rresp ), + .s_rlast (fft_rlast ), + .s_rvalid (fft_rvalid ), + .s_rready (fft_rready ), + .fft_finish (fft_finish ) +); + +wire [31:0] cdma_s_awaddr; +wire [2:0] cdma_s_awprot; +wire cdma_s_awvalid; +wire cdma_s_awready; +wire [31:0] cdma_s_wdata; +wire [3:0] cdma_s_wstrb; +wire cdma_s_wvalid; +wire cdma_s_wready; +wire [1:0] cdma_s_bresp; +wire cdma_s_bvalid; +wire cdma_s_bready; +wire [31:0] cdma_s_araddr; +wire [2:0] cdma_s_arprot; +wire cdma_s_arvalid; +wire cdma_s_arready; +wire [31:0] cdma_s_rdata; +wire [1:0] cdma_s_rresp; +wire cdma_s_rvalid; +wire cdma_s_rready; + +axi_axil_adapter #( + .ADDR_WIDTH(32), + .AXI_DATA_WIDTH(32), + .AXI_ID_WIDTH(5), + .AXIL_DATA_WIDTH(32), + .CONVERT_BURST(1), + .CONVERT_NARROW_BURST(0) +) +u_axi_axil_adapter( + .clk(sys_clk), + .rst(~sys_resetn), + .s_axi_awid(dma_s_awid), + .s_axi_awaddr(dma_s_awaddr), + .s_axi_awlen(dma_s_awlen), + .s_axi_awsize(dma_s_awsize), + .s_axi_awburst(dma_s_awburst), + .s_axi_awlock(dma_s_awlock), + .s_axi_awcache(dma_s_awcache), + .s_axi_awprot(dma_s_awprot), + .s_axi_awvalid(dma_s_awvalid), + .s_axi_awready(dma_s_awready), + .s_axi_wdata(dma_s_wdata), + .s_axi_wstrb(dma_s_wstrb), + .s_axi_wlast(dma_s_wlast), + .s_axi_wvalid(dma_s_wvalid), + .s_axi_wready(dma_s_wready), + .s_axi_bid(dma_s_bid), + .s_axi_bresp(dma_s_bresp), + .s_axi_bvalid(dma_s_bvalid), + .s_axi_bready(dma_s_bready), + .s_axi_arid(dma_s_arid), + .s_axi_araddr(dma_s_araddr), + .s_axi_arlen(dma_s_arlen), + .s_axi_arsize(dma_s_arsize), + .s_axi_arburst(dma_s_arburst), + .s_axi_arlock(dma_s_arlock), + .s_axi_arcache(dma_s_arcache), + .s_axi_arprot(dma_s_arprot), + .s_axi_arvalid(dma_s_arvalid), + .s_axi_arready(dma_s_arready), + .s_axi_rid(dma_s_rid), + .s_axi_rdata(dma_s_rdata), + .s_axi_rresp(dma_s_rresp), + .s_axi_rlast(dma_s_rlast), + .s_axi_rvalid(dma_s_rvalid), + .s_axi_rready(dma_s_rready), + + .m_axil_awaddr(cdma_s_awaddr), + .m_axil_awprot(cdma_s_awprot), + .m_axil_awvalid(cdma_s_awvalid), + .m_axil_awready(cdma_s_awready), + .m_axil_wdata(cdma_s_wdata), + .m_axil_wstrb(cdma_s_wstrb), + .m_axil_wvalid(cdma_s_wvalid), + .m_axil_wready(cdma_s_wready), + .m_axil_bresp(cdma_s_bresp), + .m_axil_bvalid(cdma_s_bvalid), + .m_axil_bready(cdma_s_bready), + .m_axil_araddr(cdma_s_araddr), + .m_axil_arprot(cdma_s_arprot), + .m_axil_arvalid(cdma_s_arvalid), + .m_axil_arready(cdma_s_arready), + .m_axil_rdata(cdma_s_rdata), + .m_axil_rresp(cdma_s_rresp), + .m_axil_rvalid(cdma_s_rvalid), + .m_axil_rready(cdma_s_rready) +); + +// 8 通道 DMA +snix_axil_cdma_mux #( + .ADDR_WIDTH (32), + .DATA_WIDTH (32), // 适配你的 32-bit 总线 + .AXIL_ADDR_WIDTH (32), + .AXIL_DATA_WIDTH (32), + .ID_WIDTH (4), // 匹配 Crossbar 的 Master ID 宽度 + .USER_WIDTH (1), + .PORTS (4), // 8 个通道 + .FIFO_DEPTH (64) +) u_snix_axil_cdma_mux_8ch ( + .clk (sys_clk), + .rst_n (sys_resetn), // 低电平复位 + + // AXI-Lite 从机接口 (接 CPU 发来的配置请求) + .s_axil_awaddr (cdma_s_awaddr), + .s_axil_awvalid (cdma_s_awvalid), + .s_axil_awready (cdma_s_awready), + .s_axil_wdata (cdma_s_wdata), + .s_axil_wstrb (cdma_s_wstrb), + .s_axil_wvalid (cdma_s_wvalid), + .s_axil_wready (cdma_s_wready), + .s_axil_bresp (cdma_s_bresp), + .s_axil_bvalid (cdma_s_bvalid), + .s_axil_bready (cdma_s_bready), + .s_axil_araddr (cdma_s_araddr), + .s_axil_arvalid (cdma_s_arvalid), + .s_axil_arready (cdma_s_arready), + .s_axil_rdata (cdma_s_rdata), + .s_axil_rresp (cdma_s_rresp), + .s_axil_rvalid (cdma_s_rvalid), + .s_axil_rready (cdma_s_rready), + + // AXI4 主机接口 (接 Crossbar 去搬运数据) + .mm2mm_awid (dma_m_awid), + .mm2mm_awaddr (dma_m_awaddr), + .mm2mm_awlen (dma_m_awlen), + .mm2mm_awsize (dma_m_awsize), + .mm2mm_awburst (dma_m_awburst), + .mm2mm_awlock (dma_m_awlock), + .mm2mm_awcache (dma_m_awcache), + .mm2mm_awprot (dma_m_awprot), + .mm2mm_awqos (), // 悬空即可 + .mm2mm_awuser (), // 悬空即可 + .mm2mm_awvalid (dma_m_awvalid), + .mm2mm_awready (dma_m_awready), + .mm2mm_wdata (dma_m_wdata), + .mm2mm_wstrb (dma_m_wstrb), + .mm2mm_wlast (dma_m_wlast), + .mm2mm_wuser (), // 悬空即可 + .mm2mm_wvalid (dma_m_wvalid), + .mm2mm_wready (dma_m_wready), + .mm2mm_bid (dma_m_bid), + .mm2mm_bresp (dma_m_bresp), + .mm2mm_buser (1'b0), + .mm2mm_bvalid (dma_m_bvalid), + .mm2mm_bready (dma_m_bready), + .mm2mm_arid (dma_m_arid), + .mm2mm_araddr (dma_m_araddr), + .mm2mm_arlen (dma_m_arlen), + .mm2mm_arsize (dma_m_arsize), + .mm2mm_arburst (dma_m_arburst), + .mm2mm_arlock (dma_m_arlock), + .mm2mm_arcache (dma_m_arcache), + .mm2mm_arprot (dma_m_arprot), + .mm2mm_arqos (), // 悬空即可 + .mm2mm_aruser (), // 悬空即可 + .mm2mm_arvalid (dma_m_arvalid), + .mm2mm_arready (dma_m_arready), + .mm2mm_rid (dma_m_rid), + .mm2mm_rdata (dma_m_rdata), + .mm2mm_rresp (dma_m_rresp), + .mm2mm_rlast (dma_m_rlast), + .mm2mm_ruser (1'b0), + .mm2mm_rvalid (dma_m_rvalid), + .mm2mm_rready (dma_m_rready), + + // 全局中断输出 + .dma_finish (dma_finish) +); + +endmodule \ No newline at end of file diff --git a/sdk/axi_ram.mif b/sdk/axi_ram.mif new file mode 100644 index 0000000..573fd83 --- /dev/null +++ b/sdk/axi_ram.mif @@ -0,0 +1,10004 @@ +00000010100000000000000000000001 +00000010100000000000000000000010 +00000010100000000000000000000011 +00000010100000000000000000000100 +00000010100000000000000000000101 +00000010100000000000000000000110 +00000010100000000000000000000111 +00000010100000000000000000001000 +00000010100000000000000000001001 +00000010100000000000000000001010 +00000010100000000000000000001011 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file mode 100644 index 0000000..88764f5 --- /dev/null +++ b/sdk/software/bsp/common.mk @@ -0,0 +1,82 @@ + +LA32R_GCC := loongarch32r-linux-gnusf-gcc +LA32R_AS := loongarch32r-linux-gnusf-as +LA32R_GXX := loongarch32r-linux-gnusf-g++ +LA32R_OBJDUMP := loongarch32r-linux-gnusf-objdump +LA32R_GDB := loongarch32r-linux-gnusf-gdb +LA32R_AR := loongarch32r-linux-gnusf-ar +LA32R_OBJCOPY := loongarch32r-linux-gnusf-objcopy +LA32R_READELF := loongarch32r-linux-gnusf-readelf + +.PHONY: all +all: $(TARGET) + +#TODO: 根据Cache实际情况调整has_cache宏，以在start.S中生成正确的Cache初始化代码 +CFLAGS += -Dhas_cache=1 +CFLAGS += -Dcache_index_depth=0x100 -Dcache_offset_width=0x4 -Dcache_way=2 +CFLAGS += -ffunction-sections -fdata-sections +CFLAGS += -nostartfiles -nostdlib -nostdinc -static -fno-builtin +CFLAGS += -DCLOCKS_PER_SEC=CORE_CLOCKS_PER_SEC -D_CLOCKS_PER_SEC_=CORE_CLOCKS_PER_SEC +CFLAGS += -DUSE_CPU_CLOCK_COUNT + +#若使用 newlib , 将下面的 -lsemihost 替换为 -lgloss +LDFLAGS += -T $(LINKER_SCRIPT) \ + -Wl,--gc-sections -Wl,--check-sections \ + -lc -lm -lg -lsemihost -lgcc -L$(PICOLIBC_DIR)/lib + +LINKER_SCRIPT := $(COMMON_DIR)/env/script.lds + +ASM_SRCS += $(COMMON_DIR)/env/start.S + +ifeq ($(TARGET), RTThread_Nano) + +else +ASM_SRCS += $(COMMON_DIR)/env/trap_handler.S +endif + +C_SRCS += $(COMMON_DIR)/drivers/confreg_time.c +C_SRCS += $(COMMON_DIR)/drivers/core_time.c +C_SRCS += $(COMMON_DIR)/drivers/common_func.c +C_SRCS += $(COMMON_DIR)/drivers/dvi.c \ + $(COMMON_DIR)/drivers/led.c \ + $(COMMON_DIR)/drivers/seg7.c + +INCLUDES += -I./ \ + -I$(COMMON_DIR)/include \ + -I$(PICOLIBC_DIR)/include \ + -I$(GCC_DIR)/lib/gcc/loongarch32r-linux-gnusf/8.3.0/include \ + -I$(GCC_DIR)/lib/gcc/loongarch32r-linux-gnusf/8.3.0/include-fixed + +ASM_OBJS := $(ASM_SRCS:.S=.o) +C_OBJS := $(C_SRCS:.c=.o) + +LINK_OBJS += $(ASM_OBJS) $(C_OBJS) +LINK_DEPS += $(LINKER_SCRIPT) + +CLEAN_OBJS += $(OBJDIR)/$(TARGET).elf $(LINK_OBJS) $(OBJDIR)/$(TARGET).s $(OBJDIR)/$(TARGET).bin $(OBJDIR)/convert $(OBJDIR)/axi_ram.coe $(OBJDIR)/axi_ram.mif $(OBJDIR)/rom.vlog + +$(TARGET): $(LINK_OBJS) $(LINK_DEPS) convert Makefile + $(LA32R_GCC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $(OBJDIR)/$@.elf $(LDFLAGS) + $(LA32R_OBJCOPY) -O binary $(OBJDIR)/$@.elf $(OBJDIR)/$@.bin + $(LA32R_OBJDUMP) --disassemble-all -S $(OBJDIR)/$@.elf > $(OBJDIR)/$@.s + $(OBJDIR)/convert $@.bin $(OBJDIR)/ + cp ./$(OBJDIR)/axi_ram.mif $(COMMON_DIR)/../../ + cp ./$(OBJDIR)/axi_ram.mif $(LA32RSOC_WINDOWS_HOME)/sdk + cp ./$(OBJDIR)/$@.bin $(COMMON_DIR)/../../ + cp ./$(OBJDIR)/$@.bin $(LA32RSOC_WINDOWS_HOME)/sdk + rm -f $(LINK_OBJS) + rm -f $(OBJDIR)/convert + +$(ASM_OBJS): %.o: %.S + $(LA32R_GCC) $(CFLAGS) $(INCLUDES) -c -o $@ $< + +$(C_OBJS): %.o: %.c + $(LA32R_GCC) $(CFLAGS) $(INCLUDES) -c -o $@ $< + +convert: $(COMMON_DIR)/env/convert.c + mkdir -p $(OBJDIR)/ + gcc -o $(OBJDIR)/convert $(COMMON_DIR)/env/convert.c + +.PHONY: clean +clean: + rm -f $(CLEAN_OBJS) diff --git a/sdk/software/bsp/drivers/common_func.c b/sdk/software/bsp/drivers/common_func.c new file mode 100644 index 0000000..9b47921 --- /dev/null +++ b/sdk/software/bsp/drivers/common_func.c @@ -0,0 +1,20 @@ +#include "common_func.h" + +void RegWrite(unsigned int addr,unsigned int var) +{ + *((volatile unsigned int *)(addr)) = var; +} + +unsigned int RegRead(unsigned int addr) +{ + return (*((volatile unsigned int *)(addr))); +} + +//memcpy 32bit +void SaveMemory(unsigned int *DestAddr, unsigned int *SrcAddr, unsigned int Size) +{ + unsigned int i; + for (i = 0; i < Size; i += 1) + *(U32*)(DestAddr + i) = SrcAddr[i]; +} + diff --git a/sdk/software/bsp/drivers/confreg_time.c b/sdk/software/bsp/drivers/confreg_time.c new file mode 100644 index 0000000..4f9854f --- /dev/null +++ b/sdk/software/bsp/drivers/confreg_time.c @@ -0,0 +1,63 @@ +#include "confreg_time.h" +#include "time.h" + +unsigned long __attribute__((weak)) CONFREG_TIMER_BASE = 0xbf20f100; +unsigned long __attribute__((weak)) CONFREG_CLOCKS_PER_SEC = 50000000L; +unsigned long __attribute__((weak)) CORE_CLOCKS_PER_SEC = 33000000L; + +unsigned long get_confreg_clock_count() +{ + unsigned long contval; + asm volatile( + "la.local $r25, CONFREG_TIMER_BASE\n\t" + "ld.w $r25, $r25, 0\n\t" + "ld.w %0,$r25,0\n\t" + :"=r"(contval) + : + :"$r25" + ); + return contval; +} + +unsigned long get_cpu_clock_count() +{ + unsigned long contval; + asm volatile( + "rdcntvl.w %0\n\t" + :"=r"(contval) + ); + return contval; +} + +unsigned long get_clock_count() +{ +#ifdef USE_CPU_CLOCK_COUNT + return get_cpu_clock_count(); +#else + return get_confreg_clock_count(); +#endif +} + +unsigned long get_ns(void) +{ + unsigned long n=0; + n = get_clock_count(); +#ifdef USE_CPU_CLOCK_COUNT + n=n*(NSEC_PER_USEC/(CORE_CLOCKS_PER_SEC/USEC_PER_SEC)); +#else + n=n*(NSEC_PER_USEC/(CONFREG_CLOCKS_PER_SEC/USEC_PER_SEC)); +#endif + return n; +} + +unsigned long get_us(void) +{ + unsigned long n=0; + n = get_clock_count(); +#ifdef USE_CPU_CLOCK_COUNT + n=n/(CORE_CLOCKS_PER_SEC/USEC_PER_SEC); +#else + n=n/(CONFREG_CLOCKS_PER_SEC/USEC_PER_SEC); +#endif + return n; +} diff --git a/sdk/software/bsp/drivers/core_time.c b/sdk/software/bsp/drivers/core_time.c new file mode 100644 index 0000000..dc895ab --- /dev/null +++ b/sdk/software/bsp/drivers/core_time.c @@ -0,0 +1,30 @@ +#include "core_time.h" +#include "confreg_time.h" + +// default : 33 mhz + +void delay_ms(uint32_t ms) +{ + unsigned char overflow; + unsigned long time,target_time,time_r,target_time_r; + + time = get_cpu_clock_count(); + time_r = time; + target_time = time + (CORE_CLOCKS_PER_SEC/1000)*ms; + target_time_r = target_time; + if( target_time < time){ + overflow = 1; + target_time = 0xffffffff; + } + while(time < target_time){ + time = get_cpu_clock_count(); + if (time_r > time) break; + time_r = time; + } + if (overflow) { + while( time < target_time_r){ + time = get_cpu_clock_count(); + } + overflow = 0; + } +} diff --git a/sdk/software/bsp/drivers/dvi.c b/sdk/software/bsp/drivers/dvi.c new file mode 100644 index 0000000..cfb1fb9 --- /dev/null +++ b/sdk/software/bsp/drivers/dvi.c @@ -0,0 +1,27 @@ +#include "dvi.h" + +// 设置坐标和颜色的绘图函数 +void DVI_Draw_Rect(uint32_t x, uint32_t y, uint32_t l, uint32_t w) +{ + // 创建坐标值，x 和 y 分别占用 12 位; width 和 height 用于定义范围 + uint32_t coordinates = ((x & 0xFFFF)<<16) | (y & 0xFFFF); + + uint32_t size = ((l & 0xFFFF)<<16) | (w & 0xFFFF); + + // 写入坐标和颜色寄存器 + RegWrite(DVI_RECT_DIR, coordinates); + RegWrite(DVI_RECT_L_W, size); +} + +// 在指定位置绘制一个点的函数 +void DVI_Draw_SQU(uint32_t x, uint32_t y, uint32_t r) +{ + // 创建坐标值，x 和 y 分别占用 12 位; width 和 height 用于定义范围 + uint32_t coordinates = ((x & 0xFFFF)<<16) | (y & 0xFFFF); + + uint32_t size = ((r & 0xFFFF)<<16) | (r & 0xFFFF); + + // 写入坐标和颜色寄存器 + RegWrite(DVI_SQU_DIR, coordinates); + RegWrite(DVI_SQU_R, size); +} diff --git a/sdk/software/bsp/drivers/led.c b/sdk/software/bsp/drivers/led.c new file mode 100644 index 0000000..38045d2 --- /dev/null +++ b/sdk/software/bsp/drivers/led.c @@ -0,0 +1,28 @@ +#include "led.h" + +// set leds pin +void setLedPin(uint32_t data) +{ + RegWrite(LEDS_GPIO_DATA,data); +} + +// toggle one led pin +void toggleLedPin(uint32_t data) +{ + uint32_t led_data; + uint32_t process_bit; + + led_data = RegRead(LEDS_GPIO_DATA); + process_bit = 0x1 << data; + + if(led_data & process_bit) + { + led_data = led_data & (~process_bit); + } + else + { + led_data = led_data | process_bit; + } + + RegWrite(LEDS_GPIO_DATA,led_data); +} \ No newline at end of file diff --git a/sdk/software/bsp/drivers/seg7.c b/sdk/software/bsp/drivers/seg7.c new file mode 100644 index 0000000..c32fede --- /dev/null +++ b/sdk/software/bsp/drivers/seg7.c @@ -0,0 +1,17 @@ +// seg7.c + +#include "seg7.h" + +void setSegNum(uint32_t seg1,uint32_t num1,uint32_t seg2,uint32_t num2) +{ + // select seg + uint32_t select_seg = ((seg1<<2) + seg2); + + RegWrite(SEG7_SELECT,select_seg); + + // set num + uint32_t num_seg = ((num1<<4) + num2); + + RegWrite(SEG7_NUM,num_seg); + +} \ No newline at end of file diff --git a/sdk/software/bsp/env/convert.c b/sdk/software/bsp/env/convert.c new file mode 100644 index 0000000..d7c5c09 --- /dev/null +++ b/sdk/software/bsp/env/convert.c @@ -0,0 +1,103 @@ +#include +#include +#include + +void binary_out(FILE* out,unsigned char* mem) +{ + char tmp; + unsigned char num[8]; + int i; + int j; + + num[0] = 1; + num[1] = 2; + num[2] = 4; + num[3] = 8; + num[4] = 16; + num[5] = 32; + num[6] = 64; + num[7] = 128; + for(i=3;i>=0;i--) + { + for(j=7;j>=0;j--) + { + if( (mem[i] & num[j] ) != 0) + tmp = '1'; + else + tmp = '0'; + fprintf(out,"%c",tmp); + } + } + fprintf(out,"\n"); + return; +} + +int main(int argc, char** argv) +{ + FILE *in; + FILE *out; + + if(argc < 3){ + fprintf(stderr, "Usage: convert main.bin directory\n"); + return 1; + } + + char str_bin[256]; + char str_coe[256], str_mif[256], str_vlog[256]; + strncpy(str_bin, argv[2], 256); + strncpy(str_coe, argv[2], 256); + strncpy(str_mif, argv[2], 256); + strncpy(str_vlog,argv[2], 256); + strncat(str_bin, argv[1], 255); + strncat(str_coe, "axi_ram.coe", 255); + strncat(str_mif, "axi_ram.mif", 255); + strncat(str_vlog,"rom.vlog" , 255); + //printf("%s\n%s\n%s\n%s\n%s\n%s\n", str_bin, str_data, str_inst_coe, str_inst_mif, str_data_coe, str_data_mif); + + int i,j,k; + unsigned char mem[32]; + + in = fopen(str_bin, "rb"); + out = fopen(str_coe,"w"); + + fprintf(out, "memory_initialization_radix = 16;\n"); + fprintf(out, "memory_initialization_vector =\n"); + while(!feof(in)) { + if(fread(mem,1,4,in)!=4) { + fprintf(out, "%02x%02x%02x%02x\n", mem[3], mem[2], mem[1], mem[0]); + break; + } + fprintf(out, "%02x%02x%02x%02x\n", mem[3], mem[2], mem[1],mem[0]); + } + fclose(in); + fclose(out); + + in = fopen(str_bin, "rb"); + out = fopen(str_mif,"w"); + + while(!feof(in)) { + if(fread(mem,1,4,in)!=4) { + binary_out(out,mem); + break; + } + binary_out(out,mem); + } + fclose(in); + fclose(out); + + in = fopen(str_bin, "rb"); + out = fopen(str_vlog,"w"); + + fprintf(out,"@1c000000\n"); + while(!feof(in)) { + if (fread(mem,1,1,in) != 1) { + fprintf(out,"%02x\n", mem[0]); + break; + } + fprintf(out,"%02x\n", mem[0]); + } + fclose(in); + fclose(out); + + return 0; +} diff --git a/sdk/software/bsp/env/script.lds b/sdk/software/bsp/env/script.lds new file mode 100644 index 0000000..088c3d6 --- /dev/null +++ b/sdk/software/bsp/env/script.lds @@ -0,0 +1,182 @@ +OUTPUT_ARCH(loongarch) +ENTRY(_start) + +MEMORY +{ + isram (rwxai) : ORIGIN = 0x1c000000, LENGTH = 512K + dsram (rwxai) : ORIGIN = 0x1c080000, LENGTH = 512K +} +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 64K; + .init : + { + KEEP (*(SORT_NONE(.init))) + } >isram AT>isram + .ilalign : + { + . = ALIGN(16); + PROVIDE( _isram_lma = . ); + } >isram AT>isram + .ialign : + { + PROVIDE( _isram = . ); + } >isram AT>isram + .text : + { + _ftext = . ; + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for at server */ + . = ALIGN(4); + __rtatcmdtab_start = .; + KEEP(*(RtAtCmdTab)) + __rtatcmdtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + } >isram AT>isram + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >isram AT>isram + . = ALIGN(16); + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >isram AT>isram + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >isram AT>isram + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >isram AT>isram + .ctors : + { + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >isram AT>isram + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >isram AT>isram + + . = ALIGN(16); + .ex_table_base : + { + _ex_table_base_start = .; + . = 0x500; + _ex_table_base_end = .; + } >isram AT>isram + + . = ALIGN(16); + PROVIDE( _eisram = . ); + + .lalign : + { + . = ALIGN(16); + PROVIDE( _data_lma = . ); + } >isram AT>isram + .dalign : + { + . = ALIGN(16); + PROVIDE( _data = . ); + } >dsram AT>isram + .data : + { + *(.rdata) + *(.rodata .rodata.*) + rodata_end = .; + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(16); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(16); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >dsram AT>isram + . = ALIGN(16); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( _fbss = . ); + .bss : + { + PROVIDE( __bss_start = . ); + *(.sbss*) + *(.sbss.*) + *(.dynsbss) + *(.scommon) + *(.bss) + *(.bss.*) + *(.dynbss) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(16); + } >dsram AT>dsram + . = ALIGN(16); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE (__heap_start = _end); + .stack ORIGIN(dsram) + LENGTH(dsram) - __stack_size : + { + PROVIDE( _heap_end = . ); + PROVIDE (__heap_end = _heap_end); + PROVIDE (__heap_size = __heap_end - __heap_start); + . = __stack_size; + PROVIDE( _stack = . ); + } >dsram AT>dsram +} diff --git a/sdk/software/bsp/env/start.S b/sdk/software/bsp/env/start.S new file mode 100644 index 0000000..d79d218 --- /dev/null +++ b/sdk/software/bsp/env/start.S @@ -0,0 +1,182 @@ +#include "regdef.h" +#include "uart_print.h" +#include "handler.h" + +.extern UART_BASE + + .section .init + .globl _start + .type _start,@function + +_start: + + ##init regs + addi.w $r1,zero,0x0; addi.w $r2,zero,0x0; addi.w $r3,zero,0x0; addi.w $r4,zero,0x0; + addi.w $r5,zero,0x0; addi.w $r6,zero,0x0; addi.w $r7,zero,0x0; addi.w $r8,zero,0x0; + addi.w $r9,zero,0x0; addi.w $r10,zero,0x0; addi.w $r11,zero,0x0; addi.w $r12,zero,0x0; + addi.w $r13,zero,0x0; addi.w $r14,zero,0x0; addi.w $r15,zero,0x0; addi.w $r16,zero,0x0; + addi.w $r17,zero,0x0; addi.w $r18,zero,0x0; addi.w $r19,zero,0x0; addi.w $r20,zero,0x0; + addi.w $r21,zero,0x0; addi.w $r22,zero,0x0; addi.w $r23,zero,0x0; addi.w $r24,zero,0x0; + addi.w $r25,zero,0x0; addi.w $r26,zero,0x0; addi.w $r27,zero,0x0; addi.w $r28,zero,0x0; + addi.w $r29,zero,0x0; addi.w $r30,zero,0x0; addi.w $r31,zero,0x0; + +#if has_cache==1 + # invalid the old inst in icache and old data in dcache by index + li.w t0,0x0 + #li.w t2,0x100 + li.w t2, cache_index_depth +1: + #slli.w t1, t0, 0x4 + slli.w t1, t0, cache_offset_width +#if cache_way==1 + cacop 0x00, t1, 0x0 + cacop 0x01, t1, 0x0 +#elif cache_way==2 + cacop 0x00, t1, 0x0 + cacop 0x00, t1, 0x1 + cacop 0x01, t1, 0x0 + cacop 0x01, t1, 0x1 +#elif cache_way==4 + cacop 0x00, t1, 0x0 + cacop 0x00, t1, 0x1 + cacop 0x00, t1, 0x2 + cacop 0x00, t1, 0x3 + cacop 0x01, t1, 0x0 + cacop 0x01, t1, 0x1 + cacop 0x01, t1, 0x2 + cacop 0x01, t1, 0x3 +#endif + addi.w t0, t0, 0x1 + bne t0, t2, 1b +#else + /* disable cache */ + li.w $r12,0x1 + csrwr $r12,0x101 +#endif + + /* open da mode */ + li.w $r12,0x8 + li.w $r13,0x18 + csrxchg $r12,$r13,0x0 + + /* init dmw */ + csrwr $r0,0x180 + csrwr $r0,0x181 + li.w $r12,0x09 + csrwr $r12,0x180 + li.w $r12,0xa0000009 + csrwr $r12,0x181 + + /* open pg mode */ + li.w $r12,0x10 + li.w $r13,0x18 + csrxchg $r12,$r13,0x0 + + /* load data section */ + la.local t0, _data_lma + la.local t1, _data + la.local t2, _edata + bgeu t1, t2, 2f +1: + ld.w t3, t0, 0 + st.w t3, t1, 0 + addi.w t0, t0, 4 + addi.w t1, t1, 4 + bltu t1, t2, 1b +2: + + /* clear bss section */ + la.local t0, __bss_start + la.local t1, _end + bgeu t0, t1, 2f +1: + st.w $r0, t0, 0 + addi.w t0, t0, 4 + bltu t0, t1, 1b +2: + + /* enable cache */ +#if has_cache==1 + li.w $r12,0x19 + csrwr $r12,0x180 +#else + +#endif + + /* init UART */ + la.local t0, UART_BASE + ld.w t1, t0, 0 + #WRITE(li.wne,OFS_FIFO,FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_0); + li.w t2, 0x07 + st.b t2, t1, 2 + #WRITE(li.wne,OFS_LINE_CONTROL, 0x80); + li.w t2, 0x80 + st.b t2, t1, 3 + #WRITE(li.wne,OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); + li.w t2, 0x00 + st.b t2, t1, 1 + #WRITE(li.wne,OFS_DIVISOR_LSB, divisor & 0xff); + li.w t3, 0xbf20f500 + ld.w t3, t3, 0 + li.w t2, 0x1b + beq zero, t3, 1f + li.w t2, 0x1 +1: + st.b t2, t1, 0 + #WRITE(li.wne,OFS_DATA_FORMAT, data | parity | stop); + li.w t2, 0x3 + st.b t2, t1, 3 + #WRITE(li.wne,OFS_MODEM_CONTROL,0); + li.w t2, 0x0 + st.b t2, t1, 4 + + /* init exception */ +#ifdef RTThread + la.local t0, rtthread_irq_entry +#else + la.local t0, trap_handler +#endif + csrwr t0, csr_eentry + + #clear int + li.w t1, 0x1 + csrwr t1, csr_ticlr + + #enable int + li.w t1, 0x4 +#ifdef RTThread + csrxchg zero, t1, csr_crmd +#else + csrxchg t1, t1, csr_crmd +#endif + csrwr zero, csr_prmd + li.w t1, 0x1fff + csrwr zero, csr_ecfg + csrwr t1, csr_ecfg + + + la.local sp, _stack + + /* argc = argv = 0 */ + li.w a0, 0 + li.w a1, 0 + +#ifdef RTThread + bl entry +#else + bl main +#endif + + /*tail exit*/ + bl _myexit +1: + b 1b + +.globl _myexit +.org 0x200 +_myexit: +1: + b 1b + + + diff --git a/sdk/software/bsp/env/trap_handler.S b/sdk/software/bsp/env/trap_handler.S new file mode 100644 index 0000000..c55bb8b --- /dev/null +++ b/sdk/software/bsp/env/trap_handler.S @@ -0,0 +1,188 @@ +#include "regdef.h" + +.macro TRAP_ENTRY_SETJMP + addi.w sp, sp, -124 + + st.w ra, sp, 120 + st.w tp, sp, 116 + st.w sp, sp, 112 + st.w a0, sp, 108 + st.w a1, sp, 104 + st.w a2, sp, 100 + st.w a3, sp, 96 + st.w a4, sp, 92 + st.w a5, sp, 88 + st.w a6, sp, 84 + st.w a7, sp, 80 + st.w t0, sp, 76 + st.w t1, sp, 72 + st.w t2, sp, 68 + st.w t3, sp, 64 + st.w t4, sp, 60 + st.w t5, sp, 56 + st.w t6, sp, 52 + st.w t7, sp, 48 + st.w t8, sp, 44 + st.w $r21, sp,40 + st.w fp, sp, 36 + st.w s0, sp, 32 + st.w s1, sp, 28 + st.w s2, sp, 24 + st.w s3, sp, 20 + st.w s4, sp, 16 + st.w s5, sp, 12 + st.w s6, sp, 8 + st.w s7, sp, 4 + st.w s8, sp, 0 + +.endm + +.macro TRAP_EXIT_LONGJMP + + ld.w ra, sp, 120 + ld.w tp, sp, 116 + ld.w sp, sp, 112 + ld.w a0, sp, 108 + ld.w a1, sp, 104 + ld.w a2, sp, 100 + ld.w a3, sp, 96 + ld.w a4, sp, 92 + ld.w a5, sp, 88 + ld.w a6, sp, 84 + ld.w a7, sp, 80 + ld.w t0, sp, 76 + ld.w t1, sp, 72 + ld.w t2, sp, 68 + ld.w t3, sp, 64 + ld.w t4, sp, 60 + ld.w t5, sp, 56 + ld.w t6, sp, 52 + ld.w t7, sp, 48 + ld.w t8, sp, 44 + ld.w $r21, sp,40 + ld.w fp, sp, 36 + ld.w s0, sp, 32 + ld.w s1, sp, 28 + ld.w s2, sp, 24 + ld.w s3, sp, 20 + ld.w s4, sp, 16 + ld.w s5, sp, 12 + ld.w s6, sp, 8 + ld.w s7, sp, 4 + ld.w s8, sp, 0 + + addi.w sp, sp, 124 + + ertn + +.endm + + .section .text + .align 6 + .global trap_handler + .weak trap_handler +trap_handler: + + TRAP_ENTRY_SETJMP + + csrrd a0, csr_estat + csrrd a1, csr_era + + srli.w t0, a0, 16 + bne zero, t0, is_exceptions + andi t0, a0, 0x3FC + srli.w t1, t0, 2 + + # 根据中断号跳转到相应的处理程序 priority + move t2, t1 + andi t2, t2, 0x1 + li.w t8, 0x1 + beq t2, t8, handle_hwi0 + + move t2, t1 + andi t2, t2, 0x2 + li.w t8, 0x2 + beq t2, t8, handle_hwi1 + + move t2, t1 + andi t2, t2, 0x4 + li.w t8, 0x4 + beq t2, t8, handle_hwi2 + + move t2, t1 + andi t2, t2, 0x8 + li.w t8, 0x8 + beq t2, t8, handle_hwi3 + + move t2, t1 + andi t2, t2, 0x10 + li.w t8, 0x10 + beq t2, t8, handle_hwi4 + + move t2, t1 + andi t2, t2, 0x20 + li.w t8, 0x20 + beq t2, t8, handle_hwi5 + + move t2, t1 + andi t2, t2, 0x40 + li.w t8, 0x40 + beq t2, t8, handle_hwi6 + + move t2, t1 + andi t2, t2, 0x80 + li.w t8, 0x80 + beq t2, t8, handle_hwi7 + + b trap_jump_exit + +is_exceptions: + addi.w t8, a1, 4 + csrwr t8, csr_era +1: + b 1b + +trap_jump_exit: + TRAP_EXIT_LONGJMP + + +# HWI0 处理程序 +handle_hwi0: + + bl HWI0_IntrHandler + + b trap_jump_exit + +# HWI1 处理程序 +handle_hwi1: + b trap_jump_exit + +# HWI2 处理程序 +handle_hwi2: + b trap_jump_exit + +# HWI3 处理程序 +handle_hwi3: + b trap_jump_exit + +# HWI4 处理程序 +handle_hwi4: + b trap_jump_exit + +# HWI5 处理程序 +handle_hwi5: + b trap_jump_exit + +# HWI6 处理程序 +handle_hwi6: + b trap_jump_exit + +# HWI7 处理程序 +handle_hwi7: + b trap_jump_exit + + +.weak HWI0_IntrHandler +HWI0_IntrHandler: +1: + b 1b diff --git a/sdk/software/bsp/include/common_func.h b/sdk/software/bsp/include/common_func.h new file mode 100644 index 0000000..33fbfa5 --- /dev/null +++ b/sdk/software/bsp/include/common_func.h @@ -0,0 +1,99 @@ +#ifndef common_func_H +#define common_func_H + +#include + +typedef signed int S32; +typedef unsigned int U32; +typedef unsigned int uint32_t; +typedef signed short S16; +typedef unsigned short U16; +typedef signed char S8; +typedef unsigned char U8; +typedef long long S64; +typedef unsigned long long U64; + +void RegWrite(unsigned int addr,unsigned int var); +unsigned int RegRead(unsigned int addr); +void SaveMemory(unsigned int *DestAddr, unsigned int *SrcAddr, unsigned int Size); + +static inline U32 csr_readl(U32 reg) +{ + return __csrrd_w(reg); +} + +static inline U64 csr_readq(U32 reg) +{ + return __csrrd_w(reg); +} + +static inline void csr_writel(U32 val, U32 reg) +{ + __csrwr_w(val, reg); +} + +static inline void csr_writeq(U64 val, U32 reg) +{ + __csrwr_w(val, reg); +} + +static inline U32 csr_xchgl(U32 val, U32 mask, U32 reg) +{ + return __csrxchg_w(val, mask, reg); +} + +static inline U64 csr_xchgq(U64 val, U64 mask, U32 reg) +{ + return __csrxchg_w(val, mask, reg); +} + +#define CacheOp_Cache 0x03 +#define CacheOp_Op 0x1c + +#define Cache_I 0x00 +#define Cache_D 0x01 +#define Cache_V 0x02 +#define Cache_S 0x03 + +#define Index_Invalidate 0x08 +#define Index_Writeback_Inv 0x08 +#define Hit_Invalidate 0x10 +#define Hit_Writeback_Inv 0x10 + +#define Index_Invalidate_I (Cache_I | Index_Invalidate) +#define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv) +#define Hit_Invalidate_I (Cache_I | Hit_Invalidate) +#define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv) + +#define cache_op(op, addr) \ + __asm__ __volatile__( \ + " cacop %0, %1 \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +static inline void flush_icache_line_indexed(unsigned long addr) +{ + cache_op(Index_Invalidate_I, addr); +} + +static inline void flush_dcache_line_indexed(unsigned long addr) +{ + cache_op(Index_Writeback_Inv_D, addr); +} + +static inline void flush_icache_line(unsigned long addr) +{ + cache_op(Hit_Invalidate_I, addr); +} + +static inline void flush_dcache_line(unsigned long addr) +{ + cache_op(Hit_Writeback_Inv_D, addr); +} + +static inline void init_dcache_line(unsigned long addr) +{ + cache_op(0x01, addr); +} + +#endif diff --git a/sdk/software/bsp/include/confreg_time.h b/sdk/software/bsp/include/confreg_time.h new file mode 100644 index 0000000..9276762 --- /dev/null +++ b/sdk/software/bsp/include/confreg_time.h @@ -0,0 +1,22 @@ +#ifndef _CONFREG_TIME_H_H +#define _CONFREG_TIME_H_H + +extern unsigned long CONFREG_TIMER_BASE; +extern unsigned long CONFREG_CLOCKS_PER_SEC; +extern unsigned long CORE_CLOCKS_PER_SEC; + +#define MSEC_PER_SEC 1000L +#define USEC_PER_MSEC 1000L +#define NSEC_PER_USEC 1000L +#define NSEC_PER_MSCEC 1000000L +#define USEC_PER_SEC 1000000L +#define NSEC_PER_SEC 1000000000L +#define FSEC_PER_SEC 1000000000000000LL + +unsigned long get_cpu_clock_count();//获取处理器核统计的时钟周期数 +unsigned long get_confreg_clock_count();//获取CONFREG的时钟周期数 +unsigned long get_clock_count();//根据是否存在宏 USE_CPU_CLOCK_COUNT 输出 处理器核/CONFREG 的计数器值 +unsigned long get_ns(void);//获取统计的纳秒数 +unsigned long get_us(void);//获取统计的微秒数 + +#endif diff --git a/sdk/software/bsp/include/core_time.h b/sdk/software/bsp/include/core_time.h new file mode 100644 index 0000000..e847179 --- /dev/null +++ b/sdk/software/bsp/include/core_time.h @@ -0,0 +1,8 @@ +#ifndef CORE_TIME_H +#define CORE_TIME_H + +#include "common_func.h" + +void delay_ms(uint32_t ms); + +#endif diff --git a/sdk/software/bsp/include/dvi.h b/sdk/software/bsp/include/dvi.h new file mode 100644 index 0000000..75b5854 --- /dev/null +++ b/sdk/software/bsp/include/dvi.h @@ -0,0 +1,21 @@ +#ifndef DVI_H +#define DVI_H +#include "common_func.h" + +#define DVI_BASEADDR 0xbf100000 + +#define DVI_RECT_DIR (DVI_BASEADDR + 0x0) + +#define DVI_RECT_L_W (DVI_BASEADDR + 0x4) + +#define DVI_SQU_DIR (DVI_BASEADDR + 0x8) + +#define DVI_SQU_R (DVI_BASEADDR + 0xC) + +// draw rect on DVI to x y +void DVI_Draw_Rect(uint32_t x, uint32_t y, uint32_t l, uint32_t w); + +// draw squ on DVI to x y r +void DVI_Draw_SQU(uint32_t x, uint32_t y, uint32_t r); + +#endif // DVI diff --git a/sdk/software/bsp/include/handler.h b/sdk/software/bsp/include/handler.h new file mode 100644 index 0000000..a412b8c --- /dev/null +++ b/sdk/software/bsp/include/handler.h @@ -0,0 +1,31 @@ +#ifndef _HANDLER_H +#define _HANDLER_H + +#define ex_tlb_load_present_type 0x1 +#define ex_tlb_store_present_type 0x2 +#define ex_tlb_fetch_present_type 0x3 +#define ex_tlb_modify_type 0x4 +#define ex_tlb_read_inhibit_type 0x5 +#define ex_tlb_execute_inhibit_type 0x6 +#define ex_tlb_privilege_error_type 0x7 +#define ex_ade_type 0x8 +#define ex_align_check_type 0x9 +#define ex_bound_check_error_type 0xa +#define ex_syscall_type 0xb +#define ex_break_type 0xc +#define ex_ri_type 0xd +#define ex_previlege_inst_type 0xe +#define ex_fpe_disable_type 0xf +#define ex_lsx_disable_type 0x10 +#define ex_lasx_disable_type 0x11 +#define ex_fpe_type 0x12 +#define ex_watch_type 0x13 +#define ex_bt_disable_type 0x14 +#define ex_bt_help_type 0x15 +#define ex_psi_type 0x16 +#define ex_hypcall_type 0x17 +#define ex_field_change_type 0x18 +#define ex_sate_related_type 0x19 +#define ex_tlb_refill 0x3f + +#endif diff --git a/sdk/software/bsp/include/led.h b/sdk/software/bsp/include/led.h new file mode 100644 index 0000000..8ba60e1 --- /dev/null +++ b/sdk/software/bsp/include/led.h @@ -0,0 +1,14 @@ +#ifndef LED_H +#define LED_H + +#include "common_func.h" + +#define LEDS_BASEADDR 0xbf20f300 + +#define LEDS_GPIO_DATA (LEDS_BASEADDR + 0x00) + +// set leds pin +void setLedPin(uint32_t data); +void toggleLedPin(uint32_t data); + +#endif diff --git a/sdk/software/bsp/include/regdef.h b/sdk/software/bsp/include/regdef.h new file mode 100644 index 0000000..f93c476 --- /dev/null +++ b/sdk/software/bsp/include/regdef.h @@ -0,0 +1,104 @@ +#ifndef _SYS_REGDEF_H +#define _SYS_REGDEF_H + +# define zero $r0 +# define ra $r1 +# define tp $r2 +# define sp $r3 +# define a0 $r4 +# define a1 $r5 +# define a2 $r6 +# define a3 $r7 +# define a4 $r8 +# define a5 $r9 +# define a6 $r10 +# define a7 $r11 +# define v0 $r4 +# define v1 $r5 +# define t0 $r12 +# define t1 $r13 +# define t2 $r14 +# define t3 $r15 +# define t4 $r16 +# define t5 $r17 +# define t6 $r18 +# define t7 $r19 +# define t8 $r20 +# define x $r21 +# define fp $r22 +# define s0 $r23 +# define s1 $r24 +# define s2 $r25 +# define s3 $r26 +# define s4 $r27 +# define s5 $r28 +# define s6 $r29 +# define s7 $r30 +# define s8 $r31 + +# define fa0 $f0 +# define fa1 $f1 +# define fa2 $f2 +# define fa3 $f3 +# define fa4 $f4 +# define fa5 $f5 +# define fa6 $f6 +# define fa7 $f7 +# define fv0 $f0 +# define fv1 $f1 +# define ft0 $f8 +# define ft1 $f9 +# define ft2 $f10 +# define ft3 $f11 +# define ft4 $f12 +# define ft5 $f13 +# define ft6 $f14 +# define ft7 $f15 +# define ft8 $f16 +# define ft9 $f17 +# define ft10 $f18 +# define ft11 $f19 +# define ft12 $f20 +# define ft13 $f21 +# define ft14 $f22 +# define ft15 $f23 +# define fs0 $f24 +# define fs1 $f25 +# define fs2 $f26 +# define fs3 $f27 +# define fs4 $f28 +# define fs5 $f29 +# define fs6 $f30 +# define fs7 $f31 + +#define csr_crmd 0x0 +#define csr_prmd 0x1 +#define csr_euen 0x2 +#define csr_ecfg 0x4 +#define csr_estat 0x5 +#define csr_era 0x6 +#define csr_badv 0x7 +#define csr_eentry 0xc +#define csr_tlbidx 0x10 +#define csr_tlbehi 0x11 +#define csr_tlbelo0 0x12 +#define csr_tlbelo1 0x13 +#define csr_asid 0x18 +#define csr_pgdl 0x19 +#define csr_pgdh 0x1a +#define csr_pgd 0x1b +#define csr_cpuid 0x20 +#define csr_save0 0x30 +#define csr_save1 0x31 +#define csr_save2 0x32 +#define csr_save3 0x33 +#define csr_tid 0x40 +#define csr_tcfg 0x41 +#define csr_tval 0x42 +#define csr_ticlr 0x44 +#define csr_llbctl 0x60 +#define csr_tlbrentry 0x88 +#define csr_dmw0 0x180 +#define csr_dmw1 0x181 + +#endif diff --git a/sdk/software/bsp/include/seg7.h b/sdk/software/bsp/include/seg7.h new file mode 100644 index 0000000..6d2e7ad --- /dev/null +++ b/sdk/software/bsp/include/seg7.h @@ -0,0 +1,17 @@ +// seg7.h + +#ifndef SEG7_H +#define SEG7_H + +#include "common_func.h" + +#define SEG7_BASEADDR 0xbf20f200 + +#define SEG7_SELECT (SEG7_BASEADDR + 0x00) + +#define SEG7_NUM (SEG7_BASEADDR + 0x04) + +// set seg num +void setSegNum(uint32_t seg1,uint32_t num1,uint32_t seg2,uint32_t num2); + +#endif diff --git a/sdk/software/bsp/include/uart_print.h b/sdk/software/bsp/include/uart_print.h new file mode 100644 index 0000000..5e35324 --- /dev/null +++ b/sdk/software/bsp/include/uart_print.h @@ -0,0 +1,12 @@ +#ifndef _UART_PRINT_H +#define _UART_PRINT_H + +#define UART_PRINT(str)\ + la a0, 1f;\ + .section .rodata ;\ + 1: ;\ + .asciz str ;\ + .section .init ;\ + bl %plt(puts) + +#endif diff --git a/sdk/software/examples/.gitignore b/sdk/software/examples/.gitignore new file mode 100644 index 0000000..9da6d68 --- /dev/null +++ b/sdk/software/examples/.gitignore @@ -0,0 +1,56 @@ +# ======================================== +# Build outputs (per-project obj/ directories) +# ======================================== +obj/ +*.o + +# ======================================== +# Editor / IDE +# ======================================== +.vscode/ +.idea/ +*.swp +*.swo +*~ +\#*\# +.\#* + +# ======================================== +# OS generated files +# ======================================== +.DS_Store +Thumbs.db +desktop.ini + +# ======================================== +# FPGA / Vivado project files (if any leak in) +# ======================================== +*.bit +*.dcp +*.jou +*.xpr +*.xrf +*.bd +*.xci +*.xdc +*.vcd +*.wcfg +*.wdb +*.edif +.svn/ +.Xil/ +.hw/ +.runs/ +.sim/ +.ip_user_files/ +vivado_*.log +vivado_*.backup.jou +Nexys4DDR/ +*.cache/ +*.gen/ + +# ======================================== +# Misc +# ======================================== +*.tmp +*.log diff --git a/sdk/software/examples/asm/Makefile b/sdk/software/examples/asm/Makefile new file mode 100644 index 0000000..c953dd5 --- /dev/null +++ b/sdk/software/examples/asm/Makefile @@ -0,0 +1,11 @@ +TARGET = user-sample + +CFLAGS += -O3 -g + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../bsp +GCC_DIR=../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../toolchains/picolibc +include ../../bsp/common.mk diff --git a/sdk/software/examples/asm/user-sample.c b/sdk/software/examples/asm/user-sample.c new file mode 100644 index 0000000..e69de29 diff --git a/sdk/software/examples/c_prg/inner_product/Makefile b/sdk/software/examples/c_prg/inner_product/Makefile new file mode 100644 index 0000000..c80b65f --- /dev/null +++ b/sdk/software/examples/c_prg/inner_product/Makefile @@ -0,0 +1,14 @@ +TARGET = inner_product + +CFLAGS += -O3 -g + +#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真 +CFLAGS += -DSIMU=0 + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../../bsp +GCC_DIR=../../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../../toolchains/picolibc +include ../../../bsp/common.mk diff --git a/sdk/software/examples/c_prg/inner_product/inner_product.c b/sdk/software/examples/c_prg/inner_product/inner_product.c new file mode 100644 index 0000000..2e62d88 --- /dev/null +++ b/sdk/software/examples/c_prg/inner_product/inner_product.c @@ -0,0 +1,446 @@ +/* + Copyright 2008 Adobe Systems Incorporated + Copyright 2018-2019 Chris Cox + Distributed under the MIT License (see accompanying file LICENSE_1_0_0.txt + or a copy at http://stlab.adobe.com/licenses.html ) + + +Goal: Test performance of various idioms for calculating the inner product of two sequences. + +NOTE: Inner products are common in mathematical and geometry processing applications, + plus some audio and image processing. + + +Assumptions: + 1) The compiler will optimize inner product operations. + + 2) The compiler may recognize ineffecient inner product idioms + and substitute efficient methods when it can. + NOTE: the best method is highly dependent on the data types and CPU architecture + + 3) std::inner_product will be well optimized for all types and containers. + + +*/ + +/******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************/ +/******************************************************************************/ +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbfe001e0; //UART16550的虚地址 +unsigned long CONFREG_UART_BASE = 0xbfafff10; //CONFREG模拟UART的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbfafe000; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 100000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +clock_t start_time, end_time; + +// this constant may need to be adjusted to give reasonable minimum times +// For best results, times should be about 1.0 seconds for the minimum test run +int iterations = 5; + + +// 8000 items, or between 8 and 64k of data +// this is intended to remain within the L2 cache of most common CPUs +const int SIZE = 8000; + + +// initial value for filling our arrays, may be changed from the command line +int32_t init_value_8 = 3; +int32_t init_value_16 = 211; +int32_t init_value_32 = 1065; +float init_value_f16 = 5.0; +double init_value_f32 = 365.0; + +/******************************************************************************/ +/******************************************************************************/ + +void fill_8(int8_t * first, int8_t * last, int8_t value) { + while (first != last) *first++ = (int8_t)(value); +} + +void fill_u8(uint8_t * first, uint8_t * last, uint8_t value) { + while (first != last) *first++ = (uint8_t)(value); +} + +void fill_16(int16_t * first, int16_t * last, int16_t value) { + while (first != last) *first++ = (int16_t)(value); +} + +void fill_u16(uint16_t * first, uint16_t * last, uint16_t value) { + while (first != last) *first++ = (uint16_t)(value); +} + +void fill_32(int32_t * first, int32_t * last, int32_t value) { + while (first != last) *first++ = (int32_t)(value); +} + +void fill_u32(uint32_t * first, uint32_t * last, uint32_t value) { + while (first != last) *first++ = (uint32_t)(value); +} + +void fill_f16(float * first, float * last, float value) { + while (first != last) *first++ = (float)(value); +} + +void fill_f32(double * first, double * last, double value) { + while (first != last) *first++ = (double)(value); +} + +/******************************************************************************/ +/******************************************************************************/ +// a trivial for loop + +void test_inner_product_8( const int8_t* first, const int8_t* second, const size_t count, const char *label) { + + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + + int8_t sum = 0 ; + for (size_t j = 0; j < count; ++j) { + sum += first[j] * second[j]; + } + + //check_sum( sum, label ); + int8_t target = (int8_t)(init_value_8)*(int8_t)(init_value_8)*SIZE; + if ( abs( sum - target ) > (int8_t)(1.0e-6) ) + printf("test %s failed\n", label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("CLOCKS_PER_SEC=%d\n",CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_inner_product_u8( const uint8_t* first, const uint8_t* second, const size_t count, const char *label) { + + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + + uint8_t sum = 0 ; + for (size_t j = 0; j < count; ++j) { + sum += first[j] * second[j]; + } + + //check_sum( sum, label ); + uint8_t target = (uint8_t)(init_value_8)*(uint8_t)(init_value_8)*SIZE; + if ( ( sum - target ) > (uint8_t)(1.0e-6) ) + printf("test %s failed\n", label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_inner_product_16( const int16_t* first, const int16_t* second, const size_t count, const char *label) { + + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + + int16_t sum = 0 ; + for (size_t j = 0; j < count; ++j) { + sum += first[j] * second[j]; + } + + //check_sum( sum, label ); + int16_t target = (int16_t)(init_value_16)*(int16_t)(init_value_16)*SIZE; + if ( abs( sum - target ) > (int16_t)(1.0e-6) ) + printf("test %s failed\n", label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_inner_product_u16( const uint16_t* first, const uint16_t* second, const size_t count, const char *label) { + + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + + uint16_t sum = 0 ; + for (size_t j = 0; j < count; ++j) { + sum += first[j] * second[j]; + } + + //check_sum( sum, label ); + uint16_t target = (uint16_t)(init_value_16)*(uint16_t)(init_value_16)*SIZE; + if ( ( sum - target ) > (uint16_t)(1.0e-6) ) + printf("test %s failed\n", label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_inner_product_32( const int32_t* first, const int32_t* second, const size_t count, const char *label) { + + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + + int32_t sum = 0 ; + for (size_t j = 0; j < count; ++j) { + sum += first[j] * second[j]; + } + + //check_sum( sum, label ); + int32_t target = (int32_t)(init_value_32)*(int32_t)(init_value_32)*SIZE; + if ( abs( sum - target ) > (int32_t)(1.0e-6) ) + printf("test %s failed\n", label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_inner_product_u32( const uint32_t* first, const uint32_t* second, const size_t count, const char *label) { + + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + + uint32_t sum = 0 ; + for (size_t j = 0; j < count; ++j) { + sum += first[j] * second[j]; + } + + //check_sum( sum, label ); + uint32_t target = (uint32_t)(init_value_32)*(uint32_t)(init_value_32)*SIZE; + if ( ( sum - target ) > (uint32_t)(1.0e-6) ) + printf("test %s failed\n", label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_inner_product_f16( const float* first, const float* second, const size_t count, const char *label) { + + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + + float sum = 0 ; + for (size_t j = 0; j < count; ++j) { + sum += first[j] * second[j]; + } + + //check_sum( sum, label ); + float target = (float)(init_value_f16)*(float)(init_value_f16)*SIZE; + if ( fabs( sum - target ) > (float)(1.0e-6) ) + printf("test %s failed\n", label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_inner_product_f32( const double* first, const double* second, const size_t count, const char *label) { + + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + + double sum = 0 ; + for (size_t j = 0; j < count; ++j) { + sum += first[j] * second[j]; + } + + //check_sum( sum, label ); + double target = (double)(init_value_f32)*(double)(init_value_f32)*SIZE; + if ( fabs( sum - target ) > (double)(1.0e-6) ) + printf("test %s failed\n", label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +/******************************************************************************/ +/******************************************************************************/ + +// NOTE - can't make generic template template argument without C++17 +// I would like to have TestOneFunction to handle all the types and if's, but need to use different types with it inside +// see sum_sequence.cpp + + +void TestOneType_8() +{ + int8_t data[SIZE]; + int8_t dataB[SIZE]; + + fill_8(data, data+SIZE, (int8_t)(init_value_8)); + fill_8(dataB, dataB+SIZE, (int8_t)(init_value_8)); + + test_inner_product_8( data, dataB, SIZE, "int_8 inner_product1 to int_8"); +} + +void TestOneType_u8() +{ + uint8_t data[SIZE]; + uint8_t dataB[SIZE]; + + fill_u8(data, data+SIZE, (uint8_t)(init_value_8)); + fill_u8(dataB, dataB+SIZE, (uint8_t)(init_value_8)); + + test_inner_product_u8( data, dataB, SIZE, "uint_8 inner_product1 to uint_8"); +} + + +void TestOneType_16() +{ + int16_t data[SIZE]; + int16_t dataB[SIZE]; + + fill_16(data, data+SIZE, (int16_t)(init_value_16)); + fill_16(dataB, dataB+SIZE, (int16_t)(init_value_16)); + + test_inner_product_16( data, dataB, SIZE, "int_16 inner_product1 to int_16"); +} + +void TestOneType_u16() +{ + uint16_t data[SIZE]; + uint16_t dataB[SIZE]; + + fill_u16(data, data+SIZE, (uint16_t)(init_value_16)); + fill_u16(dataB, dataB+SIZE, (uint16_t)(init_value_16)); + + test_inner_product_u16( data, dataB, SIZE, "uint_16 inner_product1 to uint_16"); +} + +void TestOneType_32() +{ + int32_t data[SIZE]; + int32_t dataB[SIZE]; + + fill_32(data, data+SIZE, (int32_t)(init_value_32)); + fill_32(dataB, dataB+SIZE, (int32_t)(init_value_32)); + + test_inner_product_32( data, dataB, SIZE, "int_32 inner_product1 to int_32"); +} + +void TestOneType_u32() +{ + uint32_t data[SIZE]; + uint32_t dataB[SIZE]; + + fill_u32(data, data+SIZE, (uint32_t)(init_value_32)); + fill_u32(dataB, dataB+SIZE, (uint32_t)(init_value_32)); + + test_inner_product_u32( data, dataB, SIZE, "uint_32 inner_product1 to uint_32"); +} + +void TestOneType_f16() +{ + float data[SIZE]; + float dataB[SIZE]; + + fill_f16(data, data+SIZE, (float)(init_value_f16)); + fill_f16(dataB, dataB+SIZE, (float)(init_value_f16)); + + test_inner_product_f16( data, dataB, SIZE, "float inner_product1 to float"); +} + +void TestOneType_f32() +{ + double data[SIZE]; + double dataB[SIZE]; + + fill_f32(data, data+SIZE, (double)(init_value_f32)); + fill_f32(dataB, dataB+SIZE, (double)(init_value_f32)); + + test_inner_product_f32( data, dataB, SIZE, "double inner_product1 to double"); +} +/******************************************************************************/ +/******************************************************************************/ + +int main(int argc, char** argv) { + + // output command for documentation: + int i; + // for (i = 0; i < argc; ++i) + // printf("%s ", argv[i] ); + // printf("\n"); + + if (argc > 1) iterations = atoi(argv[1]); + // if (argc > 2) init_value = (int32_t) atoi(argv[2]); + + + TestOneType_8(); + TestOneType_u8(); + TestOneType_16(); + TestOneType_u16(); + TestOneType_32(); + TestOneType_u32(); + + TestOneType_f16(); + TestOneType_f32(); + + return 0; +} + +// the end +/******************************************************************************/ +/******************************************************************************/ diff --git a/sdk/software/examples/c_prg/lookup_table/Makefile b/sdk/software/examples/c_prg/lookup_table/Makefile new file mode 100644 index 0000000..2bc1f33 --- /dev/null +++ b/sdk/software/examples/c_prg/lookup_table/Makefile @@ -0,0 +1,14 @@ +TARGET = lookup_table + +CFLAGS += -O3 -g + +#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真 +CFLAGS += -DSIMU=0 + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../../bsp +GCC_DIR=../../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../../toolchains/picolibc +include ../../../bsp/common.mk diff --git a/sdk/software/examples/c_prg/lookup_table/lookup_table.c b/sdk/software/examples/c_prg/lookup_table/lookup_table.c new file mode 100644 index 0000000..f6d6393 --- /dev/null +++ b/sdk/software/examples/c_prg/lookup_table/lookup_table.c @@ -0,0 +1,315 @@ +/* + Copyright 2008-2009 Adobe Systems Incorporated + Copyright 2018 Chris Cox + Distributed under the MIT License (see accompanying file LICENSE_1_0_0.txt + or a copy at http://stlab.adobe.com/licenses.html ) + + +Goal: Test performance of various idioms and optimizations for lookup tables. + + +Assumptions: + 1) The compiler will optimize lookup table operations. + Unrolling will usually be needed to hide read latencies. + + 2) The compiler should recognize ineffecient lookup table idioms and substitute efficient methods. + Many different CPU architecture issues will require reading and writing words for best performance. + CPUs with... + cache write-back/write-combine delays. + store forwarding delays. + slow cache access relative to shifts/masks. + slow partial word (byte) access. + fast shift/mask operations. + On some CPUs, a lookup can be handled with vector instructions. + On some CPUs, special cache handling is needed (especially 2way caches). + + + + +TODO - lookup and interpolate (int16_t, int32_t, int64_t, float, double) +TODO - 2D and 3D LUTs, simple and interpolated + +*/ + +/******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************/ +/******************************************************************************/ +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbfe001e0; //UART16550的虚地址 +unsigned long CONFREG_UART_BASE = 0xbfafff10; //CONFREG模拟UART的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbfafe000; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 100000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +clock_t start_time, end_time; + +// this constant may need to be adjusted to give reasonable minimum times +// For best results, times should be about 1.0 seconds for the minimum test run +int base_iterations = 1; +int iterations = 1; + +// 4000 items, or about 2..4k of data +// this is intended to remain within the L1 cache of most common CPUs +#define SIZE_SMALL 2000 + +// about 0.5..1M of data +// 没有那么大内存，这里给50KB到100KB +// this is intended to be outside the L2 cache of most common CPUs +#define SIZE 50000 + +// initial value for filling our arrays, may be changed from the command line +int32_t init_value = 3; + +/******************************************************************************/ + +// our global arrays of numbers + +uint8_t inputData8[SIZE]; +uint8_t resultData8[SIZE]; + +uint16_t inputData16[SIZE]; +uint16_t resultData16[SIZE]; + +/******************************************************************************/ +/******************************************************************************/ + + +void fill_8(uint8_t * first, uint8_t * last, uint8_t value) { + while (first != last) *first++ = (uint8_t)(value); +} + +void fill_16(uint16_t * first, uint16_t * last, uint16_t value) { + while (first != last) *first++ = (uint16_t)(value); +} + +void fill_random_8(uint8_t * first, uint8_t * last) { + srand((unsigned int)init_value + 123 ); + while (first != last) { + *first++ = (uint8_t)rand(); + } +} + +void fill_random_16(uint16_t * first, uint16_t * last) { + srand((unsigned int)init_value + 123 ); + while (first != last) { + *first++ = (uint16_t)rand(); + } +} + +int max(int a, int b){ + if(a > b) + return a; + else + return b; +} + +/******************************************************************************/ +/******************************************************************************/ + + + +// baseline - a trivial loop + +void test_lut1_u8(const uint8_t* input, uint8_t *result, const int count, const uint8_t* LUT, const char *label) { + + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + for (int j = 0; j < count; ++j) { + result[j] = LUT[ input[j] ]; + } + } + + end_time = clock(); + + int j; + + for (j = 0; j < count; ++j) { + if (result[j] != (uint8_t)(init_value)) { + printf("test %s failed (got %u, expected %u)\n", label, (unsigned)(result[j]), (unsigned)(init_value)); + break; + } + } + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %d times\" %f sec\n", + label, + count, + time_cost); + +} + +void test_lut1_8(const int8_t* input, int8_t *result, const int count, const int8_t* LUT, const char *label) { + + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + for (int j = 0; j < count; ++j) { + result[j] = LUT[ input[j] ]; + } + } + + end_time = clock(); + + int j; + + for (j = 0; j < count; ++j) { + if (result[j] != (int8_t)(init_value)) { + printf("test %s failed (got %u, expected %u)\n", label, (unsigned)(result[j]), (unsigned)(init_value)); + break; + } + } + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %d times\" %f sec\n", + label, + count, + time_cost); + +} + +void test_lut1_u16(const uint16_t* input, uint16_t *result, const int count, const uint16_t* LUT, const char *label) { + + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + for (int j = 0; j < count; ++j) { + result[j] = LUT[ input[j] ]; + } + } + + end_time = clock(); + + int j; + + for (j = 0; j < count; ++j) { + if (result[j] != (uint16_t)(init_value)) { + printf("test %s failed (got %u, expected %u)\n", label, (unsigned)(result[j]), (unsigned)(init_value)); + break; + } + } + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %d times\" %f sec\n", + label, + count, + time_cost); + +} + +void test_lut1_16(const int16_t* input, int16_t *result, const int count, const int16_t* LUT, const char *label) { + + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + for (int j = 0; j < count; ++j) { + result[j] = LUT[ input[j] ]; + } + } + + end_time = clock(); + + int j; + + for (j = 0; j < count; ++j) { + if (result[j] != (int16_t)(init_value)) { + printf("test %s failed (got %u, expected %u)\n", label, (unsigned)(result[j]), (unsigned)(init_value)); + break; + } + } + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %d times\" %f sec\n", + label, + count, + time_cost); + +} + +/******************************************************************************/ +/******************************************************************************/ + +int main(int argc, char** argv) { + + // output command for documentation: + int i; + // for (i = 0; i < argc; ++i) + // printf("%s ", argv[i] ); + // printf("\n"); + + if (argc > 1) base_iterations = atoi(argv[1]); + if (argc > 2) init_value = (int32_t) atoi(argv[2]); + + uint8_t myLUT8[ 256 ]; + uint16_t myLUT16[ 65536 ]; + + + fill_8(myLUT8, myLUT8+256, (uint8_t)(init_value)); + fill_16(myLUT16, myLUT16+65536, (uint16_t)(init_value)); + + fill_random_8( inputData8, inputData8+SIZE ); + fill_random_16( inputData16, inputData16+SIZE ); + + +// uint8_t + iterations = base_iterations; + + test_lut1_u8( inputData8, inputData8, SIZE_SMALL, myLUT8, "uint8_t lookup table1 small inplace"); + test_lut1_u8( inputData8, resultData8, SIZE_SMALL, myLUT8, "uint8_t lookup table1 small"); + + iterations = max( 1, (int)(((uint64_t)base_iterations * SIZE_SMALL) / SIZE) ); + + test_lut1_u8( inputData8, inputData8, SIZE, myLUT8, "uint8_t lookup table1 large inplace"); + test_lut1_u8( inputData8, resultData8, SIZE, myLUT8, "uint8_t lookup table1 large"); + + + +// int8_t + iterations = base_iterations; + + test_lut1_8( (int8_t*)inputData8, (int8_t*)inputData8, SIZE_SMALL, (int8_t*)(myLUT8+128), "int8_t lookup table1 small inplace"); + test_lut1_8( (int8_t*)inputData8, (int8_t*)resultData8, SIZE_SMALL, (int8_t*)(myLUT8+128), "int8_t lookup table1 small"); + + iterations = max( 1, (int)(((uint64_t)base_iterations * SIZE_SMALL) / SIZE) ); + + test_lut1_8( (int8_t*)inputData8, (int8_t*)inputData8, SIZE, (int8_t*)(myLUT8+128), "int8_t lookup table1 large inplace"); + test_lut1_8( (int8_t*)inputData8, (int8_t*)resultData8, SIZE, (int8_t*)(myLUT8+128), "int8_t lookup table1 large"); + + +// uint16_t + iterations = base_iterations; + + test_lut1_u16( inputData16, inputData16, SIZE_SMALL, myLUT16, "uint16_t lookup table1 small inplace"); + test_lut1_u16( inputData16, resultData16, SIZE_SMALL, myLUT16, "uint16_t lookup table1 small"); + + iterations = max( 1, (int)(((uint64_t)base_iterations * SIZE_SMALL) / SIZE) ); + + test_lut1_u16( inputData16, inputData16, SIZE, myLUT16, "uint16_t lookup table1 large inplace"); + test_lut1_u16( inputData16, resultData16, SIZE, myLUT16, "uint16_t lookup table1 large"); + +// int16_t + iterations = base_iterations; + + test_lut1_16( (int16_t*)inputData16, (int16_t*)inputData16, SIZE_SMALL, (int16_t*)(myLUT16+32768), "int16_t lookup table1 small inplace"); + test_lut1_16( (int16_t*)inputData16, (int16_t*)resultData16, SIZE_SMALL, (int16_t*)(myLUT16+32768), "int16_t lookup table1 small"); + + iterations = max( 1, (int)(((uint64_t)base_iterations * SIZE_SMALL) / SIZE) ); + + test_lut1_16( (int16_t*)inputData16, (int16_t*)inputData16, SIZE, (int16_t*)(myLUT16+32768), "int16_t lookup table1 large inplace"); + test_lut1_16( (int16_t*)inputData16, (int16_t*)resultData16, SIZE, (int16_t*)(myLUT16+32768), "int16_t lookup table1 large"); + + return 0; +} + +// the end +/******************************************************************************/ +/******************************************************************************/ diff --git a/sdk/software/examples/c_prg/loop_induction/Makefile b/sdk/software/examples/c_prg/loop_induction/Makefile new file mode 100644 index 0000000..9272f21 --- /dev/null +++ b/sdk/software/examples/c_prg/loop_induction/Makefile @@ -0,0 +1,14 @@ +TARGET = loop_induction + +CFLAGS += -O3 -g + +#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真 +CFLAGS += -DSIMU=0 + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../../bsp +GCC_DIR=../../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../../toolchains/picolibc +include ../../../bsp/common.mk diff --git a/sdk/software/examples/c_prg/loop_induction/loop_induction.c b/sdk/software/examples/c_prg/loop_induction/loop_induction.c new file mode 100644 index 0000000..95ba9e4 --- /dev/null +++ b/sdk/software/examples/c_prg/loop_induction/loop_induction.c @@ -0,0 +1,131 @@ +/* + Copyright 2018 Chris Cox + Distributed under the MIT License (see accompanying file LICENSE_1_0_0.txt + or a copy at http://stlab.adobe.com/licenses.html ) + + +Goal: Examine performance optimizations related to loop induction variables. + + +Assumptions: + 1) The compiler will normalize all loop types and optimize all equally. + (this is a necessary step before doing induction variable analysis) + + 2) The compiler will remove unused induction variables. + This could happen due to several optimizations. + + 2) The compiler will recognize induction variables with linear relations (x = a*b + c) + and optimize out redundant variables. + + 3) The compiler will apply strength reduction to induction variable usage. + + 4) The compiler will remove bounds checks by recognizing or adjusting loop limits. + (can be an explict loop optimization, or part of range propagation) + + +*/ + +#include +#include +#include +#include +#include +#include +#include + + +/******************************************************************************/ +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbfe001e0; //UART16550的虚地址 +unsigned long CONFREG_UART_BASE = 0xbfafff10; //CONFREG模拟UART的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbfafe000; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 100000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +clock_t start_time, end_time; + +/******************************************************************************/ + +// this constant may need to be adjusted to give reasonable minimum times +// For best results, times should be about 1.0 seconds for the minimum test run +int iterations = 10; + + +// 32000 items, or about 128k of data +// this is intended to remain within the L2 cache of most common CPUs +const int SIZE = 32000; + + +// initial value for filling our arrays, may be changed from the command line +int init_value = 3; + +/******************************************************************************/ + +void fill_random(int32_t * first, int32_t * last) { + while (first != last) { + *first++ = (int32_t)rand(); + } +} + +/******************************************************************************/ +/******************************************************************************/ + + +void test_copy(const int32_t *source, int32_t *dest, int count, const char *label) { + int i; + + fill_random( dest, dest+count ); + + start_time = clock(); + + for(i = 0; i < iterations; ++i) { + int i, j, k; + for ( i=0, j=0, k=0; k < count; ++i, ++j, ++k ) { + dest[i] = source[j]; + } + } + + end_time = clock(); + + if ( memcmp(dest, source, count*sizeof(int32_t)) != 0 ) + printf("test %s failed\n", label); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + + printf("\"%s, %d items\" %f sec\n", + label, + count, + time_cost); +} + +/******************************************************************************/ +/******************************************************************************/ + +int main(int argc, char** argv) { + + // output command for documentation: + int i; + // for (i = 0; i < argc; ++i) + // printf("%s ", argv[i] ); + // printf("\n"); + + if (argc > 1) iterations = atoi(argv[1]); + if (argc > 2) init_value = (int) atoi(argv[2]); + + int32_t intSrc[ SIZE ]; + int32_t intDst[ SIZE ]; + + + srand( (unsigned int)init_value + 123); + fill_random( intSrc, intSrc+SIZE ); + + + test_copy( &intSrc[0], &intDst[0], SIZE, "int32_t for induction copy" ); + + + return 0; +} + +// the end +/******************************************************************************/ +/******************************************************************************/ diff --git a/sdk/software/examples/c_prg/memcmp/Makefile b/sdk/software/examples/c_prg/memcmp/Makefile new file mode 100644 index 0000000..fa83170 --- /dev/null +++ b/sdk/software/examples/c_prg/memcmp/Makefile @@ -0,0 +1,14 @@ +TARGET = memcmp + +CFLAGS += -O3 -g + +#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真 +CFLAGS += -DSIMU=0 + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../../bsp +GCC_DIR=../../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../../toolchains/picolibc +include ../../../bsp/common.mk diff --git a/sdk/software/examples/c_prg/memcmp/memcmp.c b/sdk/software/examples/c_prg/memcmp/memcmp.c new file mode 100644 index 0000000..1fb0922 --- /dev/null +++ b/sdk/software/examples/c_prg/memcmp/memcmp.c @@ -0,0 +1,177 @@ +/* + Copyright 2008-2009 Adobe Systems Incorporated + Copyright 2018 Chris Cox + Distributed under the MIT License (see accompanying file LICENSE_1_0_0.txt + or a copy at http://stlab.adobe.com/licenses.html ) + + +Goal: Test compiler optimizations related to memcmp and hand coded memcmp loops. + + +Assumptions: + + 1) The compiler will recognize memcmp like loops and optimize appropriately. + This could be subtitution of calls to memcmp, + or it could be just optimizing the loop to get the best throughput. + On modern systems, cache hinting is usually required for best throughput. + + 2) The library function memcmp should be optimized for small, medium, and large buffers. + ie: low overhead for smaller buffer, highly hinted for large buffers. + + 3) The STL functions equal and mismatch should be optimized for small, medium, and large buffers. + ie: low overhead for smaller buffers, highly hinted for large buffers. + + + + +NOTE - on some OSes, memcmp calls into the VM system to test for shared pages + thus running faster than the DRAM bandwidth would allow on large arrays + + However, on those OSes, calling memcmp can hit mutexes and slow down + significantly when called from threads. + + +NOTE - Linux memcmp returns 0, +-1 instead of the actual difference +NOTE - and sometimes Linux memcmp returns 0, +-256 instead of the actual difference + + +TODO - test performance of unaligned buffers +*/ + +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************/ +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbfe001e0; //UART16550的虚地址 +unsigned long CONFREG_UART_BASE = 0xbfafff10; //CONFREG模拟UART的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbfafe000; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 100000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +clock_t start_time, end_time; + +// this constant may need to be adjusted to give reasonable minimum times +// For best results, times should be about 1.0 seconds for the minimum test run +int iterations = 1; + + +// 64 Megabytes, intended to be larger than L2 cache on common CPUs +// needs to be divisible by 8 +// 没有这么大内存，给30KB +#define SIZE_4K 4096 +// #define SIZE_3M 3145728 +#define SIZE_3M 30720 + +// initial value for filling our arrays, may be changed from the command line +uint8_t init_value = 3; + +/******************************************************************************/ +/******************************************************************************/ + +void fill(uint8_t * first, uint8_t * last, uint8_t value) { + while (first != last) *first++ = value; +} + + +int forloop_memcmp( const void *first, const void *second, size_t bytes ){ + const uint8_t *first_byte = (const uint8_t *)first; + const uint8_t *second_byte = (const uint8_t *)second; + int x; + + for (x = 0; x < bytes; ++x) { + if (first_byte[x] != second_byte[x]) { + return (first_byte[x] - second_byte[x]); + } + } + + return 0; +} + + +/******************************************************************************/ +/******************************************************************************/ + + +void test_memcmp(const uint8_t *first, const uint8_t *second, int count, bool expected_result) { + int i; + int bytes = count * sizeof(uint8_t); + + start_time = clock(); + + for(i = 0; i < iterations; ++i) { + // sigh, Linux memcmp is wonky - some return 1, some return 256 + bool result = (forloop_memcmp( first, second, bytes ) != 0) ; + + // moving this test out of the loop causes unwanted overoptimization + if ( result != expected_result ) + printf("test %s by %d failed (got %d instead of %d)\n", "for loop compare", count, (int)result, (int)expected_result ); + } + + end_time = clock(); +} + +/******************************************************************************/ + +void test_memcmp_sizes(const uint8_t *first, const uint8_t *second, int max_count, bool result) { + int i = max_count * sizeof(uint8_t); + + test_memcmp( first, second, max_count, result); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + + printf("\"%s %d bytes\" compare result: %s %f sec\n", + "for loop compare", + i, + result ? "false" : "true", + time_cost); + +} + +/******************************************************************************/ +/******************************************************************************/ + +// our global arrays of numbers to be operated upon + +uint8_t data8u[SIZE_3M/sizeof(uint8_t)]; +int alignment_pad = 1024; +uint8_t data8u_dest[SIZE_3M/sizeof(uint8_t) + 1024]; // leave some room for alignment testing + +/******************************************************************************/ +/******************************************************************************/ + + +int main(int argc, char** argv) { + + // output command for documentation: + int i; + + if (argc > 1) iterations = atoi(argv[1]); + if (argc > 2) init_value = (int32_t) atoi(argv[2]); + + + fill( data8u, data8u+(SIZE_3M/sizeof(uint8_t)), (uint8_t)(init_value) ); + fill( data8u_dest, data8u_dest+(SIZE_3M/sizeof(uint8_t) + alignment_pad), (uint8_t)(init_value) ); + test_memcmp_sizes( data8u, data8u_dest, SIZE_3M/sizeof(uint8_t), false); + data8u[(SIZE_3M/sizeof(uint8_t))-1] += 1; // last byte in the array + test_memcmp_sizes( data8u, data8u_dest, SIZE_3M/sizeof(uint8_t), true); +/* + test_memcmp_sizes( data8u, data8u_dest, SIZE_1M/sizeof(uint8_t), false); + data8u[(SIZE_1M/sizeof(uint8_t))-1] += 1; // last byte in the array + test_memcmp_sizes( data8u, data8u_dest, SIZE_1M/sizeof(uint8_t), true); +*/ + test_memcmp_sizes( data8u, data8u_dest, SIZE_4K/sizeof(uint8_t), false); + data8u[(SIZE_4K/sizeof(uint8_t))-1] += 1; // last byte in the array + test_memcmp_sizes( data8u, data8u_dest, SIZE_4K/sizeof(uint8_t), true); + + return 0; +} + +// the end +/******************************************************************************/ +/******************************************************************************/ diff --git a/sdk/software/examples/c_prg/minmax_sequence/Makefile b/sdk/software/examples/c_prg/minmax_sequence/Makefile new file mode 100644 index 0000000..c2e2a84 --- /dev/null +++ b/sdk/software/examples/c_prg/minmax_sequence/Makefile @@ -0,0 +1,14 @@ +TARGET = minmax_sequence + +CFLAGS += -O3 -g + +#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真 +CFLAGS += -DSIMU=0 + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../../bsp +GCC_DIR=../../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../../toolchains/picolibc +include ../../../bsp/common.mk diff --git a/sdk/software/examples/c_prg/minmax_sequence/minmax_sequence.c b/sdk/software/examples/c_prg/minmax_sequence/minmax_sequence.c new file mode 100644 index 0000000..e69bced --- /dev/null +++ b/sdk/software/examples/c_prg/minmax_sequence/minmax_sequence.c @@ -0,0 +1,1509 @@ +/* + Copyright 2008-2009 Adobe Systems Incorporated + Copyright 2018-2019 Chris Cox + Distributed under the MIT License (see accompanying file LICENSE_1_0_0.txt + or a copy at http://stlab.adobe.com/licenses.html ) + + +Goal: Test the performance of various idioms for finding maximum and maximum of a sequence. + + +Assumptions: + 1) The compiler will optimize minimum and maximum finding operations. + + 2) The compiler may recognize ineffecient minimum or maximum idioms and substitute efficient methods. + + + +NOTE - min or max between two sequences is tested in minmax.cpp. + +NOTE - pin values in sequence, see minmax.cpp + +*/ + +/******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************/ +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbfe001e0; //UART16550的虚地址 +unsigned long CONFREG_UART_BASE = 0xbfafff10; //CONFREG模拟UART的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbfafe000; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 100000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +clock_t start_time, end_time; + +/******************************************************************************/ + +// this constant may need to be adjusted to give reasonable minimum times +// For best results, times should be about 1.0 seconds for the minimum test run +int iterations = 5; + + +// 8000 items, or between 8 and 64k of data +// this is intended to remain within the L2 cache of most common CPUs +#define SIZE 8000 + + +// initial value for filling our arrays, may be changed from the command line +int32_t init_value = 3; + +/******************************************************************************/ + +double gMinResult = 0; +double gMaxResult = 0; + +size_t gMinPosition = 0; +size_t gMaxPosition = 0; + + +/******************************************************************************/ +/******************************************************************************/ + +void check_min_position(size_t result, const char * label) { + if (result != (size_t)(gMinPosition)) + printf("test %s failed (got %tu instead of %zu)\n", label, result, gMinPosition ); +} + +/******************************************************************************/ + +void check_max_position(size_t result, const char * label) { + if (result != (size_t)(gMaxPosition)) + printf("test %s failed (got %tu instead of %zu)\n", label, result, gMaxPosition ); +} + +/******************************************************************************/ +/******************************************************************************/ + +int8_t find_minimum_8( int8_t * first, int8_t * last ) { + int8_t min_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first < min_value) + min_value = *first; + ++first; + } + return min_value; +} + +uint8_t find_minimum_u8( uint8_t * first, uint8_t * last ) { + uint8_t min_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first < min_value) + min_value = *first; + ++first; + } + return min_value; +} + +int16_t find_minimum_16( int16_t * first, int16_t * last ) { + int16_t min_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first < min_value) + min_value = *first; + ++first; + } + return min_value; +} + +uint16_t find_minimum_u16( uint16_t * first, uint16_t * last ) { + uint16_t min_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first < min_value) + min_value = *first; + ++first; + } + return min_value; +} + +int32_t find_minimum_32( int32_t * first, int32_t * last ) { + int32_t min_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first < min_value) + min_value = *first; + ++first; + } + return min_value; +} + +uint32_t find_minimum_u32( uint32_t * first, uint32_t * last ) { + uint32_t min_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first < min_value) + min_value = *first; + ++first; + } + return min_value; +} + +float find_minimum_f16( float * first, float * last ) { + float min_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first < min_value) + min_value = *first; + ++first; + } + return min_value; +} + +double find_minimum_f32( double * first, double * last ) { + double min_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first < min_value) + min_value = *first; + ++first; + } + return min_value; +} + +/******************************************************************************/ +int8_t find_maximum_8( int8_t * first, int8_t * last ) { + int8_t max_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first > max_value) + max_value = *first; + ++first; + } + return max_value; +} + +uint8_t find_maximum_u8( uint8_t * first, uint8_t * last ) { + uint8_t max_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first > max_value) + max_value = *first; + ++first; + } + return max_value; +} + +int16_t find_maximum_16( int16_t * first, int16_t * last ) { + int16_t max_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first > max_value) + max_value = *first; + ++first; + } + return max_value; +} + +uint16_t find_maximum_u16( uint16_t * first, uint16_t * last ) { + uint16_t max_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first > max_value) + max_value = *first; + ++first; + } + return max_value; +} + +int32_t find_maximum_32( int32_t * first, int32_t * last ) { + int32_t max_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first > max_value) + max_value = *first; + ++first; + } + return max_value; +} + +uint32_t find_maximum_u32( uint32_t * first, uint32_t * last ) { + uint32_t max_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first > max_value) + max_value = *first; + ++first; + } + return max_value; +} + +float find_maximum_f16( float * first, float * last ) { + float max_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first > max_value) + max_value = *first; + ++first; + } + return max_value; +} + +double find_maximum_f32( double * first, double * last ) { + double max_value = *first; + if (first != last) + ++first; + while (first != last) { + if (*first > max_value) + max_value = *first; + ++first; + } + return max_value; +} + +/******************************************************************************/ +size_t find_minimum_position_8( int8_t * first, size_t count) { + int8_t min_value = first[0]; + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) { + min_value = first[k]; + minpos = k; + } + } + return minpos; +} + +size_t find_minimum_position_u8( uint8_t * first, size_t count) { + uint8_t min_value = first[0]; + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) { + min_value = first[k]; + minpos = k; + } + } + return minpos; +} + +size_t find_minimum_position_16( int16_t * first, size_t count) { + int16_t min_value = first[0]; + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) { + min_value = first[k]; + minpos = k; + } + } + return minpos; +} + +size_t find_minimum_position_u16( uint16_t * first, size_t count) { + uint16_t min_value = first[0]; + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) { + min_value = first[k]; + minpos = k; + } + } + return minpos; +} + +size_t find_minimum_position_32( int32_t * first, size_t count) { + int32_t min_value = first[0]; + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) { + min_value = first[k]; + minpos = k; + } + } + return minpos; +} + +size_t find_minimum_position_u32( uint32_t * first, size_t count) { + uint32_t min_value = first[0]; + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) { + min_value = first[k]; + minpos = k; + } + } + return minpos; +} + +size_t find_minimum_position_f16( float * first, size_t count) { + float min_value = first[0]; + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) { + min_value = first[k]; + minpos = k; + } + } + return minpos; +} + +size_t find_minimum_position_f32( double * first, size_t count) { + double min_value = first[0]; + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) { + min_value = first[k]; + minpos = k; + } + } + return minpos; +} + +/******************************************************************************/ +size_t find_maximum_position_8( int8_t * first, size_t count) { + int8_t max_value = first[0]; + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) { + max_value = first[k]; + maxpos = k; + } + } + return maxpos; +} + +size_t find_maximum_position_u8( uint8_t * first, size_t count) { + uint8_t max_value = first[0]; + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) { + max_value = first[k]; + maxpos = k; + } + } + return maxpos; +} + +size_t find_maximum_position_16( int16_t * first, size_t count) { + int16_t max_value = first[0]; + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) { + max_value = first[k]; + maxpos = k; + } + } + return maxpos; +} + +size_t find_maximum_position_u16( uint16_t * first, size_t count) { + uint16_t max_value = first[0]; + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) { + max_value = first[k]; + maxpos = k; + } + } + return maxpos; +} + +size_t find_maximum_position_32( int32_t * first, size_t count) { + int32_t max_value = first[0]; + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) { + max_value = first[k]; + maxpos = k; + } + } + return maxpos; +} + +size_t find_maximum_position_u32( uint32_t * first, size_t count) { + uint32_t max_value = first[0]; + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) { + max_value = first[k]; + maxpos = k; + } + } + return maxpos; +} + +size_t find_maximum_position_f16( float * first, size_t count) { + float max_value = first[0]; + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) { + max_value = first[k]; + maxpos = k; + } + } + return maxpos; +} + +size_t find_maximum_position_f32( double * first, size_t count) { + double max_value = first[0]; + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) { + max_value = first[k]; + maxpos = k; + } + } + return maxpos; +} + +/******************************************************************************/ +/******************************************************************************/ +void test_min_value2_8(int8_t* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + int8_t min_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) + min_value = first[k]; + } + + if (min_value != (int8_t)(gMinResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)min_value, gMinResult ); + + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_value2_u8(uint8_t* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + uint8_t min_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) + min_value = first[k]; + } + + if (min_value != (uint8_t)(gMinResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)min_value, gMinResult ); + + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_value2_16(int16_t* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + int16_t min_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) + min_value = first[k]; + } + + if (min_value != (int16_t)(gMinResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)min_value, gMinResult ); + + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_value2_u16(uint16_t* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + uint16_t min_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) + min_value = first[k]; + } + + if (min_value != (uint16_t)(gMinResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)min_value, gMinResult ); + + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_value2_32(int32_t* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + int32_t min_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) + min_value = first[k]; + } + + if (min_value != (int32_t)(gMinResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)min_value, gMinResult ); + + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_value2_u32(uint32_t* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + uint32_t min_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) + min_value = first[k]; + } + + if (min_value != (uint32_t)(gMinResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)min_value, gMinResult ); + + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_value2_f16(float* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + float min_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) + min_value = first[k]; + } + + if (min_value != (float)(gMinResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)min_value, gMinResult ); + + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_value2_f32(double* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + double min_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] < min_value) + min_value = first[k]; + } + + if (min_value != (double)(gMinResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)min_value, gMinResult ); + + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +/******************************************************************************/ + +void test_max_value2_8(int8_t* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + int8_t max_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) + max_value = first[k]; + } + + if (max_value != (int8_t)(gMaxResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)max_value, gMaxResult ); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_value2_u8(uint8_t* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + uint8_t max_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) + max_value = first[k]; + } + + if (max_value != (uint8_t)(gMaxResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)max_value, gMaxResult ); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_value2_16(int16_t* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + int16_t max_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) + max_value = first[k]; + } + + if (max_value != (int16_t)(gMaxResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)max_value, gMaxResult ); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_value2_u16(uint16_t* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + uint16_t max_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) + max_value = first[k]; + } + + if (max_value != (uint16_t)(gMaxResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)max_value, gMaxResult ); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_value2_32(int32_t* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + int32_t max_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) + max_value = first[k]; + } + + if (max_value != (int32_t)(gMaxResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)max_value, gMaxResult ); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_value2_u32(uint32_t* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + uint32_t max_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) + max_value = first[k]; + } + + if (max_value != (uint32_t)(gMaxResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)max_value, gMaxResult ); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_value2_f16(float* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + float max_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) + max_value = first[k]; + } + + if (max_value != (float)(gMaxResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)max_value, gMaxResult ); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_value2_f32(double* first, size_t count, const char * label) { + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + double max_value = first[0]; + for (size_t k = 1; k < count; ++k) { + if (first[k] > max_value) + max_value = first[k]; + } + + if (max_value != (double)(gMaxResult)) + printf("test %s failed (got %g instead of %g)\n", label, (double)max_value, gMaxResult ); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +/******************************************************************************/ + +/******************************************************************************/ +/******************************************************************************/ + +void test_min_position1_8(int8_t* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < first[minpos]) { + minpos = k; + } + } + check_min_position(minpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_position1_u8(uint8_t* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < first[minpos]) { + minpos = k; + } + } + check_min_position(minpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_position1_16(int16_t* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < first[minpos]) { + minpos = k; + } + } + check_min_position(minpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_position1_u16(uint16_t* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < first[minpos]) { + minpos = k; + } + } + check_min_position(minpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_position1_32(int32_t* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < first[minpos]) { + minpos = k; + } + } + check_min_position(minpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_position1_u32(uint32_t* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < first[minpos]) { + minpos = k; + } + } + check_min_position(minpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_position1_f16(float* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < first[minpos]) { + minpos = k; + } + } + check_min_position(minpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_min_position1_f32(double* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t minpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] < first[minpos]) { + minpos = k; + } + } + check_min_position(minpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +/******************************************************************************/ +/******************************************************************************/ + +void test_max_position1_8(int8_t* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > first[maxpos]) { + maxpos = k; + } + } + check_max_position(maxpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_position1_u8(uint8_t* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > first[maxpos]) { + maxpos = k; + } + } + check_max_position(maxpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_position1_16(int16_t* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > first[maxpos]) { + maxpos = k; + } + } + check_max_position(maxpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_position1_u16(uint16_t* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > first[maxpos]) { + maxpos = k; + } + } + check_max_position(maxpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_position1_32(int32_t* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > first[maxpos]) { + maxpos = k; + } + } + check_max_position(maxpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_position1_u32(uint32_t* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > first[maxpos]) { + maxpos = k; + } + } + check_max_position(maxpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_position1_f16(float* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > first[maxpos]) { + maxpos = k; + } + } + check_max_position(maxpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +void test_max_position1_f32(double* first, size_t count, const char * label) +{ + start_time = clock(); + + for(int i = 0; i < iterations; ++i) { + size_t maxpos = 0; + for (size_t k = 1; k < count; ++k) { + if (first[k] > first[maxpos]) { + maxpos = k; + } + } + check_max_position(maxpos, label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + printf("\"%s, %lu items\" %f sec\n", + label, + count, + time_cost); +} + +/******************************************************************************/ +/******************************************************************************/ + +/******************************************************************************/ +/******************************************************************************/ + +void TestOneType_8() +{ + int8_t data[SIZE]; + + srand( (unsigned int)init_value + 123 ); + int8_t * data_p = data; + while (data_p != (data+SIZE)) { + *data_p++ = (int8_t)rand(); + } + + gMinResult = find_minimum_8( data, data+SIZE ); + gMaxResult = find_maximum_8( data, data+SIZE ); + gMinPosition = find_minimum_position_8( data, SIZE ); + gMaxPosition = find_maximum_position_8( data, SIZE ); + + test_min_value2_8( data, SIZE, "int8_t minimum value sequence2"); + test_max_value2_8( data, SIZE, "int8_t maximum value sequence2"); + + // position tests are much slower, even at their best + int iterations_base = iterations; + iterations = iterations / 5; + + test_min_position1_8( data, SIZE, "int8_t minimum position sequence1"); + test_max_position1_8( data, SIZE, "int8_t maximum position sequence1"); + + iterations = iterations_base; +} + +void TestOneType_u8() +{ + uint8_t data[SIZE]; + + srand( (unsigned int)init_value + 123 ); + uint8_t * data_p = data; + while (data_p != (data+SIZE)) { + *data_p++ = (uint8_t)rand(); + } + + gMinResult = find_minimum_u8( data, data+SIZE ); + gMaxResult = find_maximum_u8( data, data+SIZE ); + gMinPosition = find_minimum_position_u8( data, SIZE ); + gMaxPosition = find_maximum_position_u8( data, SIZE ); + + test_min_value2_u8( data, SIZE, "uint8_t minimum value sequence2"); + test_max_value2_u8( data, SIZE, "uint8_t maximum value sequence2"); + + // position tests are much slower, even at their best + int iterations_base = iterations; + iterations = iterations / 5; + + test_min_position1_u8( data, SIZE, "uint8_t minimum position sequence1"); + test_max_position1_u8( data, SIZE, "uint8_t maximum position sequence1"); + + iterations = iterations_base; +} + +void TestOneType_16() +{ + int16_t data[SIZE]; + + srand( (unsigned int)init_value + 123 ); + int16_t * data_p = data; + while (data_p != (data+SIZE)) { + *data_p++ = (int16_t)rand(); + } + + gMinResult = find_minimum_16( data, data+SIZE ); + gMaxResult = find_maximum_16( data, data+SIZE ); + gMinPosition = find_minimum_position_16( data, SIZE ); + gMaxPosition = find_maximum_position_16( data, SIZE ); + + test_min_value2_16( data, SIZE, "int16_t minimum value sequence2"); + test_max_value2_16( data, SIZE, "int16_t maximum value sequence2"); + + // position tests are much slower, even at their best + int iterations_base = iterations; + iterations = iterations / 5; + + test_min_position1_16( data, SIZE, "int16_t minimum position sequence1"); + test_max_position1_16( data, SIZE, "int16_t maximum position sequence1"); + + iterations = iterations_base; +} + +void TestOneType_u16() +{ + uint16_t data[SIZE]; + + srand( (unsigned int)init_value + 123 ); + uint16_t * data_p = data; + while (data_p != (data+SIZE)) { + *data_p++ = (uint16_t)rand(); + } + + gMinResult = find_minimum_u16( data, data+SIZE ); + gMaxResult = find_maximum_u16( data, data+SIZE ); + gMinPosition = find_minimum_position_u16( data, SIZE ); + gMaxPosition = find_maximum_position_u16( data, SIZE ); + + test_min_value2_u16( data, SIZE, "uint16_t minimum value sequence2"); + test_max_value2_u16( data, SIZE, "uint16_t maximum value sequence2"); + + // position tests are much slower, even at their best + int iterations_base = iterations; + iterations = iterations / 5; + + test_min_position1_u16( data, SIZE, "uint16_t minimum position sequence1"); + test_max_position1_u16( data, SIZE, "uint16_t maximum position sequence1"); + + iterations = iterations_base; +} + +void TestOneType_32() +{ + int32_t data[SIZE]; + + srand( (unsigned int)init_value + 123 ); + int32_t * data_p = data; + while (data_p != (data+SIZE)) { + *data_p++ = (int32_t)rand(); + } + + gMinResult = find_minimum_32( data, data+SIZE ); + gMaxResult = find_maximum_32( data, data+SIZE ); + gMinPosition = find_minimum_position_32( data, SIZE ); + gMaxPosition = find_maximum_position_32( data, SIZE ); + + test_min_value2_32( data, SIZE, "int32_t minimum value sequence2"); + test_max_value2_32( data, SIZE, "int32_t maximum value sequence2"); + + // position tests are much slower, even at their best + int iterations_base = iterations; + iterations = iterations / 5; + + test_min_position1_32( data, SIZE, "int32_t minimum position sequence1"); + test_max_position1_32( data, SIZE, "int32_t maximum position sequence1"); + + iterations = iterations_base; +} + +void TestOneType_u32() +{ + uint32_t data[SIZE]; + + srand( (unsigned int)init_value + 123 ); + uint32_t * data_p = data; + while (data_p != (data+SIZE)) { + *data_p++ = (uint32_t)rand(); + } + + gMinResult = find_minimum_u32( data, data+SIZE ); + gMaxResult = find_maximum_u32( data, data+SIZE ); + gMinPosition = find_minimum_position_u32( data, SIZE ); + gMaxPosition = find_maximum_position_u32( data, SIZE ); + + test_min_value2_u32( data, SIZE, "uint32_t minimum value sequence2"); + test_max_value2_u32( data, SIZE, "uint32_t maximum value sequence2"); + + // position tests are much slower, even at their best + int iterations_base = iterations; + iterations = iterations / 5; + + test_min_position1_u32( data, SIZE, "uint32_t minimum position sequence1"); + test_max_position1_u32( data, SIZE, "uint32_t maximum position sequence1"); + + iterations = iterations_base; +} + +/******************************************************************************/ +/******************************************************************************/ + +void TestOneFloat_f16() +{ + float data[SIZE]; + + srand( (unsigned int)init_value + 123 ); + float * data_p = data; + while (data_p != (data+SIZE)) { + *data_p++ = (float)rand(); + } + + gMinResult = find_minimum_f16( data, data+SIZE ); + gMaxResult = find_maximum_f16( data, data+SIZE ); + gMinPosition = find_minimum_position_f16( data, SIZE ); + gMaxPosition = find_maximum_position_f16( data, SIZE ); + + test_min_value2_f16( data, SIZE, "float minimum value sequence2"); + test_max_value2_f16( data, SIZE, "float maximum value sequence2"); + + // position tests are much slower, even at their best + int iterations_base = iterations; + iterations = iterations / 5; + + test_min_position1_f16( data, SIZE, "float minimum position sequence1"); + test_max_position1_f16( data, SIZE, "float maximum position sequence1"); + + iterations = iterations_base; +} + +void TestOneFloat_f32() +{ + double data[SIZE]; + + srand( (unsigned int)init_value + 123 ); + double * data_p = data; + while (data_p != (data+SIZE)) { + *data_p++ = (double)rand(); + } + + gMinResult = find_minimum_f32( data, data+SIZE ); + gMaxResult = find_maximum_f32( data, data+SIZE ); + gMinPosition = find_minimum_position_f32( data, SIZE ); + gMaxPosition = find_maximum_position_f32( data, SIZE ); + + test_min_value2_f32( data, SIZE, "double minimum value sequence2"); + test_max_value2_f32( data, SIZE, "double maximum value sequence2"); + + // position tests are much slower, even at their best + int iterations_base = iterations; + iterations = iterations / 5; + + test_min_position1_f32( data, SIZE, "double minimum position sequence1"); + test_max_position1_f32( data, SIZE, "double maximum position sequence1"); + + iterations = iterations_base; +} + +/******************************************************************************/ +/******************************************************************************/ + +int main(int argc, char** argv) { + + // output command for documentation: + int i; + // for (i = 0; i < argc; ++i) + // printf("%s ", argv[i] ); + // printf("\n"); + + if (argc > 1) iterations = atoi(argv[1]); + if (argc > 2) init_value = (int32_t) atoi(argv[2]); + + + TestOneType_8(); + TestOneType_u8(); + TestOneType_16(); + TestOneType_u16(); + + TestOneType_32(); + TestOneType_u32(); + + TestOneFloat_f16(); + TestOneFloat_f32(); + + return 0; +} + +// the end +/******************************************************************************/ +/******************************************************************************/ diff --git a/sdk/software/examples/c_prg/product_sequence/Makefile b/sdk/software/examples/c_prg/product_sequence/Makefile new file mode 100644 index 0000000..b987045 --- /dev/null +++ b/sdk/software/examples/c_prg/product_sequence/Makefile @@ -0,0 +1,14 @@ +TARGET = product_sequence + +CFLAGS += -O3 -g + +#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真 +CFLAGS += -DSIMU=0 + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../../bsp +GCC_DIR=../../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../../toolchains/picolibc +include ../../../bsp/common.mk diff --git a/sdk/software/examples/c_prg/product_sequence/product_sequence.c b/sdk/software/examples/c_prg/product_sequence/product_sequence.c new file mode 100644 index 0000000..f747d17 --- /dev/null +++ b/sdk/software/examples/c_prg/product_sequence/product_sequence.c @@ -0,0 +1,169 @@ +/* + Copyright 2008 Adobe Systems Incorporated + Copyright 2019 Chris Cox + Distributed under the MIT License (see accompanying file LICENSE_1_0_0.txt + or a copy at http://stlab.adobe.com/licenses.html ) + + +Goal: Test performance of various idioms for calculating the product of a sequence. + + +Assumptions: + 1) The compiler will optimize product operations. + + 2) The compiler may recognize ineffecient product idioms and substitute efficient methods. + + +*/ + +/******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + + +/******************************************************************************/ +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbfe001e0; //UART16550的虚地址 +unsigned long CONFREG_UART_BASE = 0xbfafff10; //CONFREG模拟UART的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbfafe000; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 100000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +clock_t start_time, end_time; + +/******************************************************************************/ + +// this constant may need to be adjusted to give reasonable minimum times +// For best results, times should be about 1.0 seconds for the minimum test run +int iterations = 10; + + +// 4000 items, or about 32k of data +// this is intended to remain within the L2 cache of most common CPUs +const int SIZE = 4000; + + +// initial value for filling our arrays, may be changed from the command line +double init_value = 2.1; + +/******************************************************************************/ +/******************************************************************************/ + +void fill_f16(float * first, float * last, float value) { + while (first != last) *first++ = (float)(value); +} + +void fill_f32(double * first, double * last, double value) { + while (first != last) *first++ = (double)(value); +} + + +void testOneFunction_f16(const float* first, const int count, const char * label) { + int i; + + start_time = clock(); + + for(i = 0; i < iterations; ++i) { + + float result = (float)(1); + for (int j = 0; j < count; ++j) { + result = result * first[j]; + } + + if ( fabs( result - pow(init_value,(double)SIZE) ) > 1.0e-6 ) + printf("test %s failed\n", label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + + printf("\"%s, %d items\" %f sec\n", + label, + count, + time_cost); +} + +void testOneFunction_f32(const double* first, const int count, const char * label) { + int i; + + start_time = clock(); + + for(i = 0; i < iterations; ++i) { + + double result = (double)(1); + for (int j = 0; j < count; ++j) { + result = result * first[j]; + } + + if ( fabs( result - pow(init_value,(double)SIZE) ) > 1.0e-6 ) + printf("test %s failed\n", label); + } + + // need the labels to remain valid until we print the summary + end_time = clock(); + + double time_cost = (end_time - start_time)/ (double)(CLOCKS_PER_SEC); + + printf("\"%s, %d items\" %f sec\n", + label, + count, + time_cost); +} + +/******************************************************************************/ +void TestOneType_f16() +{ + + float data[SIZE]; + + fill_f16(data, data+SIZE, (float)(init_value)); + + testOneFunction_f16( data, SIZE, "float product sequence1" ); + +} + +void TestOneType_f32() +{ + + double data[SIZE]; + + fill_f32(data, data+SIZE, (double)(init_value)); + + testOneFunction_f32( data, SIZE, "double product sequence1" ); + +} + +/******************************************************************************/ +/******************************************************************************/ + +int main(int argc, char** argv) { + + // output command for documentation: + int i; + // for (i = 0; i < argc; ++i) + // printf("%s ", argv[i] ); + // printf("\n"); + + if (argc > 1) iterations = atoi(argv[1]); + if (argc > 2) init_value = (double) atof(argv[2]); + + + TestOneType_f16(); + + TestOneType_f32(); + + + return 0; +} + +// the end +/******************************************************************************/ +/******************************************************************************/ diff --git a/sdk/software/examples/coremark/LICENSE.md b/sdk/software/examples/coremark/LICENSE.md new file mode 100644 index 0000000..14e53e9 --- /dev/null +++ b/sdk/software/examples/coremark/LICENSE.md @@ -0,0 +1,100 @@ +# COREMARK® ACCEPTABLE USE AGREEMENT + +This ACCEPTABLE USE AGREEMENT (this “Agreement”) is offered by Embedded Microprocessor Benchmark Consortium, a California nonprofit corporation (“Licensor”), to users of its CoreMark® software (“Licensee”) exclusively on the following terms. + +Licensor offers benchmarking software (“Software”) pursuant to an open source license, but carefully controls use of its benchmarks and their associated goodwill. Licensor has registered its trademark in one of the benchmarks available through the Software, COREMARK, Ser. No. 85/487,290; Reg. No. 4,179,307 (the “Trademark”), and promotes the use of a standard metric as a benchmark for assessing the performance of embedded systems. Solely on the terms described herein, Licensee may use and display the Trademark in connection with the generation of data regarding measurement and analysis of computer and embedded system benchmarking via the Software (the “Licensed Use”). + +## Article 1 – License Grant. +1.1. License. Subject to the terms and conditions of this Agreement, Licensor hereby grants to Licensee, and Licensee hereby accepts from Licensor, a personal, non-exclusive, royalty-free, revocable right and license to use and display the Trademark during the term of this Agreement (the “Term”), solely and exclusively in connection with the Licensed Use. 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This Agreement is perpetual unless terminated by either of the parties. Licensee may terminate this Agreement for convenience, without cause or liability, for any reason or for no reason whatsoever, upon ten (10) business days written notice. Licensor may terminate this Agreement effective immediately upon notice of breach. Upon termination, Licensee shall immediately remove all implementations of the Trademark from the Licensed Use, and delete all digitals files and records of all materials related to the Trademark. + +## Article 2 – Ownership. +2.1. Ownership. Licensee acknowledges and agrees that Licensor is the owner of all right, title, and interest in and to the Trademark, and all such right, title, and interest shall remain with Licensor. Licensee shall not contest, dispute, challenge, oppose, or seek to cancel Licensor’s right, title, and interest in and to the Trademark. Licensee shall not prosecute any application for registration of the Trademark. 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However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS diff --git a/sdk/software/examples/coremark/Makefile b/sdk/software/examples/coremark/Makefile new file mode 100644 index 0000000..040f420 --- /dev/null +++ b/sdk/software/examples/coremark/Makefile @@ -0,0 +1,25 @@ +TARGET = coremark + +C_SRCS := \ + core_list_join.c \ + core_main.c \ + core_matrix.c \ + core_state.c \ + core_util.c \ + core_portme.c \ + +CFLAGS := -O3 -funroll-all-loops -finline-limit=200 -ftree-dominator-opts -fno-if-conversion2 -fselective-scheduling -fno-code-hoisting -fno-common -falign-functions=4 -falign-jumps=4 -falign-loops=4 + +#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真 +CFLAGS += -DSIMU=0 + +CFLAGS += -DFLAGS_STR=\""$(CFLAGS)"\" +CFLAGS += -g +#配置迭代次数 +CFLAGS += -DITERATIONS=1 + +OBJDIR = obj +COMMON_DIR = ../../bsp +GCC_DIR=../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../toolchains/picolibc +include ../../bsp/common.mk diff --git a/sdk/software/examples/coremark/README.md b/sdk/software/examples/coremark/README.md new file mode 100644 index 0000000..ce67229 --- /dev/null +++ b/sdk/software/examples/coremark/README.md @@ -0,0 +1,398 @@ + +# Introduction + +CoreMark's primary goals are simplicity and providing a method for testing only a processor's core features. For more information about EEMBC's comprehensive embedded benchmark suites, please see www.eembc.org. + +For a more compute-intensive version of CoreMark that uses larger datasets and execution loops taken from common applications, please check out EEMBC's [CoreMark-PRO](https://www.github.com/eembc/coremark-pro) benchmark, also on GitHub. + +# Building and Running + +To build and run the benchmark, type + +`> make` + +Full results are available in the files `run1.log` and `run2.log`. CoreMark result can be found in `run1.log`. + +## Cross Compiling + +For cross compile platforms please adjust `core_portme.mak`, `core_portme.h` (and possibly `core_portme.c`) according to the specific platform used. When porting to a new platform, it is recommended to copy one of the default port folders (e.g. `mkdir && cp linux/* `), adjust the porting files, and run: +~~~ +% make PORT_DIR= +~~~ + +## Make Targets +`run` - Default target, creates `run1.log` and `run2.log`. +`run1.log` - Run the benchmark with performance parameters, and output to `run1.log` +`run2.log` - Run the benchmark with validation parameters, and output to `run2.log` +`run3.log` - Run the benchmark with profile generation parameters, and output to `run3.log` +`compile` - compile the benchmark executable +`link` - link the benchmark executable +`check` - test MD5 of sources that may not be modified +`clean` - clean temporary files + +### Make flag: `ITERATIONS` +By default, the benchmark will run between 10-100 seconds. To override, use `ITERATIONS=N` +~~~ +% make ITERATIONS=10 +~~~ +Will run the benchmark for 10 iterations. It is recommended to set a specific number of iterations in certain situations e.g.: + +* Running with a simulator +* Measuring power/energy +* Timing cannot be restarted + +Minimum required run time: **Results are only valid for reporting if the benchmark ran for at least 10 secs!** + +### Make flag: `XCFLAGS` +To add compiler flags from the command line, use `XCFLAGS` e.g.: + +~~~ +% make XCFLAGS="-g -DMULTITHREAD=4 -DUSE_FORK=1" +~~~ + +### Make flag: `CORE_DEBUG` + +Define to compile for a debug run if you get incorrect CRC. + +~~~ +% make XCFLAGS="-DCORE_DEBUG=1" +~~~ + +### Make flag: `REBUILD` + +Force a rebuild of the executable. + +## Systems Without `make` +The following files need to be compiled: +* `core_list_join.c` +* `core_main.c` +* `core_matrix.c` +* `core_state.c` +* `core_util.c` +* `PORT_DIR/core_portme.c` + +For example: +~~~ +% gcc -O2 -o coremark.exe core_list_join.c core_main.c core_matrix.c core_state.c core_util.c simple/core_portme.c -DPERFORMANCE_RUN=1 -DITERATIONS=1000 +% ./coremark.exe > run1.log +~~~ +The above will compile the benchmark for a performance run and 1000 iterations. Output is redirected to `run1.log`. + +# Parallel Execution +Use `XCFLAGS=-DMULTITHREAD=N` where N is number of threads to run in parallel. Several implementations are available to execute in multiple contexts, or you can implement your own in `core_portme.c`. + +~~~ +% make XCFLAGS="-DMULTITHREAD=4 -DUSE_PTHREAD" +~~~ + +The above will compile the benchmark for execution on 4 cores, using POSIX Threads API. + +Note: linking may fail on the previous command if your linker does not automatically add the `pthread` library. If you encounter `undefined reference` errors, please modify the `core_portme.mak` file for your platform, (e.g. `linux64/core_portme.mak`) and add `-lpthread` to the `LFLAGS_END` parameter. + +# Run Parameters for the Benchmark Executable +CoreMark's executable takes several parameters as follows (but only if `main()` accepts arguments): +1st - A seed value used for initialization of data. +2nd - A seed value used for initialization of data. +3rd - A seed value used for initialization of data. +4th - Number of iterations (0 for auto : default value) +5th - Reserved for internal use. +6th - Reserved for internal use. +7th - For malloc users only, ovreride the size of the input data buffer. + +The run target from make will run coremark with 2 different data initialization seeds. + +## Alternative parameters: +If not using `malloc` or command line arguments are not supported, the buffer size +for the algorithms must be defined via the compiler define `TOTAL_DATA_SIZE`. +`TOTAL_DATA_SIZE` must be set to 2000 bytes (default) for standard runs. +The default for such a target when testing different configurations could be: + +~~~ +% make XCFLAGS="-DTOTAL_DATA_SIZE=6000 -DMAIN_HAS_NOARGC=1" +~~~ + +# Submitting Results + +CoreMark results can be submitted on the web. Open a web browser and go to the [submission page](https://www.eembc.org/coremark/submit.php). After registering an account you may enter a score. + +# Run Rules +What is and is not allowed. + +## Required +1. The benchmark needs to run for at least 10 seconds. +2. All validation must succeed for seeds `0,0,0x66` and `0x3415,0x3415,0x66`, buffer size of 2000 bytes total. + * If not using command line arguments to main: +~~~ + % make XCFLAGS="-DPERFORMANCE_RUN=1" REBUILD=1 run1.log + % make XCFLAGS="-DVALIDATION_RUN=1" REBUILD=1 run2.log +~~~ +3. If using profile guided optimization, profile must be generated using seeds of `8,8,8`, and buffer size of 1200 bytes total. +~~~ + % make XCFLAGS="-DTOTAL_DATA_SIZE=1200 -DPROFILE_RUN=1" REBUILD=1 run3.log +~~~ +4. All source files must be compiled with the same flags. +5. All data type sizes must match size in bits such that: + * `ee_u8` is an unsigned 8-bit datatype. + * `ee_s16` is a signed 16-bit datatype. + * `ee_u16` is an unsigned 16-bit datatype. + * `ee_s32` is a signed 32-bit datatype. + * `ee_u32` is an unsigned 32-bit datatype. + +## Allowed + +1. Changing number of iterations +2. Changing toolchain and build/load/run options +3. Changing method of acquiring a data memory block +5. Changing the method of acquiring seed values +6. Changing implementation `in core_portme.c` +7. Changing configuration values in `core_portme.h` +8. Changing `core_portme.mak` + +## NOT ALLOWED +1. Changing of source file other then `core_portme*` (use `make check` to validate) + +# Reporting rules +Use the following syntax to report results on a data sheet: + +CoreMark 1.0 : N / C [/ P] [/ M] + +N - Number of iterations per second with seeds 0,0,0x66,size=2000) + +C - Compiler version and flags + +P - Parameters such as data and code allocation specifics + +* This parameter *may* be omitted if all data was allocated on the heap in RAM. +* This parameter *may not* be omitted when reporting CoreMark/MHz + +M - Type of parallel execution (if used) and number of contexts +* This parameter may be omitted if parallel execution was not used. + +e.g.: + +~~~ +CoreMark 1.0 : 128 / GCC 4.1.2 -O2 -fprofile-use / Heap in TCRAM / FORK:2 +~~~ +or +~~~ +CoreMark 1.0 : 1400 / GCC 3.4 -O4 +~~~ + +If reporting scaling results, the results must be reported as follows: + +CoreMark/MHz 1.0 : N / C / P [/ M] + +P - When reporting scaling results, memory parameter must also indicate memory frequency:core frequency ratio. +1. If the core has cache and cache frequency to core frequency ratio is configurable, that must also be included. + +e.g.: + +~~~ +CoreMark/MHz 1.0 : 1.47 / GCC 4.1.2 -O2 / DDR3(Heap) 30:1 Memory 1:1 Cache +~~~ + +# Log File Format +The log files have the following format + +~~~ +2K performance run parameters for coremark. (Run type) +CoreMark Size : 666 (Buffer size) +Total ticks : 25875 (platform dependent value) +Total time (secs) : 25.875000 (actual time in seconds) +Iterations/Sec : 3864.734300 (Performance value to report) +Iterations : 100000 (number of iterations used) +Compiler version : GCC3.4.4 (Compiler and version) +Compiler flags : -O2 (Compiler and linker flags) +Memory location : Code in flash, data in on chip RAM +seedcrc : 0xe9f5 (identifier for the input seeds) +[0]crclist : 0xe714 (validation for list part) +[0]crcmatrix : 0x1fd7 (validation for matrix part) +[0]crcstate : 0x8e3a (validation for state part) +[0]crcfinal : 0x33ff (iteration dependent output) +Correct operation validated. See README.md for run and reporting rules. (*Only when run is successful*) +CoreMark 1.0 : 6508.490622 / GCC3.4.4 -O2 / Heap (*Only on a successful performance run*) +~~~ + +# Theory of Operation + +This section describes the initial goals of CoreMark and their implementation. + +## Small and easy to understand + +* X number of source code lines for timed portion of the benchmark. +* Meaningful names for variables and functions. +* Comments for each block of code more than 10 lines long. + +## Portability + +A thin abstraction layer will be provided for I/O and timing in a separate file. All I/O and timing of the benchmark will be done through this layer. + +### Code / data size + +* Compile with gcc on x86 and make sure all sizes are according to requirements. +* If dynamic memory allocation is used, take total memory allocated into account as well. +* Avoid recursive functions and keep track of stack usage. +* Use the same memory block as data site for all algorithms, and initialize the data before each algorithm – while this means that initialization with data happens during the timed portion, it will only happen once during the timed portion and so have negligible effect on the results. + +## Controlled output + +This may be the most difficult goal. Compilers are constantly improving and getting better at analyzing code. To create work that cannot be computed at compile time and must be computed at run time, we will rely on two assumptions: + +* Some system functions (e.g. time, scanf) and parameters cannot be computed at compile time. In most cases, marking a variable volatile means the compiler is force to read this variable every time it is read. This will be used to introduce a factor into the input that cannot be precomputed at compile time. Since the results are input dependent, that will make sure that computation has to happen at run time. + +* Either a system function or I/O (e.g. scanf) or command line parameters or volatile variables will be used before the timed portion to generate data which is not available at compile time. Specific method used is not relevant as long as it can be controlled, and that it cannot be computed or eliminated by the compiler at compile time. E.g. if the clock() functions is a compiler stub, it may not be used. The derived values will be reported on the output so that verification can be done on a different machine. + +* We cannot rely on command line parameters since some embedded systems do not have the capability to provide command line parameters. All 3 methods above will be implemented (time based, scanf and command line parameters) and all 3 are valid if the compiler cannot determine the value at compile time. + +* It is important to note that The actual values that are to be supplied at run time will be standardized. The methodology is not intended to provide random data, but simply to provide controlled data that cannot be precomputed at compile time. + +* Printed results must be valid at run time. This will be used to make sure the computation has been executed. + +* Some embedded systems do not provide “printf” or other I/O functionality. All I/O will be done through a thin abstraction interface to allow execution on such systems (e.g. allow output via JTAG). + +## Key Algorithms + +### Linked List + +The following linked list structure will be used: + +~~~ +typedef struct list_data_s { + ee_s16 data16; + ee_s16 idx; +} list_data; + +typedef struct list_head_s { + struct list_head_s *next; + struct list_data_s *info; +} list_head; +~~~ + +While adding a level of indirection accessing the data, this structure is realistic and used in many embedded applications for small to medium lists. + +The list itself will be initialized on a block of memory that will be passed in to the initialization function. While in general linked lists use malloc for new nodes, embedded applications sometime control the memory for small data structures such as arrays and lists directly to avoid the overhead of system calls, so this approach is realistic. + +The linked list will be initialized such that 1/4 of the list pointers point to sequential areas in memory, and 3/4 of the list pointers are distributed in a non sequential manner. This is done to emulate a linked list that had add/remove happen for a while disrupting the neat order, and then a series of adds that are likely to come from sequential memory locations. + +For the benchmark itself: +- Multiple find operations are going to be performed. These find operations may result in the whole list being traversed. The result of each find will become part of the output chain. +- The list will be sorted using merge sort based on the data16 value, and then derive CRC of the data16 item in order for part of the list. The CRC will become part of the output chain. +- The list will be sorted again using merge sort based on the idx value. This sort will guarantee that the list is returned to the primary state before leaving the function, so that multiple iterations of the function will have the same result. CRC of the data16 for part of the list will again be calculated and become part of the output chain. + +The actual `data16` in each cell will be pseudo random based on a single 16b input that cannot be determined at compile time. In addition, the part of the list which is used for CRC will also be passed to the function, and determined based on an input that cannot be determined at run time. + +### Matrix Multiply + +This very simple algorithm forms the basis of many more complex algorithms. The tight inner loop is the focus of many optimizations (compiler as well as hardware based) and is thus relevant for embedded processing. + +The total available data space will be divided to 3 parts: +1. NxN matrix A. +2. NxN matrix B. +3. NxN matrix C. + +E.g. for 2K we will have 3 12x12 matrices (assuming data type of 32b 12(len)*12(wid)*4(size)*3(num) =1728 bytes). + +Matrix A will be initialized with small values (upper 3/4 of the bits all zero). +Matrix B will be initialized with medium values (upper half of the bits all zero). +Matrix C will be used for the result. + +For the benchmark itself: +- Multiple A by a constant into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain. +- Multiple A by column X of B into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain. +- Multiple A by B into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain. + +The actual values for A and B must be derived based on input that is not available at compile time. + +### State Machine + +This part of the code needs to exercise switch and if statements. As such, we will use a small Moore state machine. In particular, this will be a state machine that identifies string input as numbers and divides them according to format. + +The state machine will parse the input string until either a “,” separator or end of input is encountered. An invalid number will cause the state machine to return invalid state and a valid number will cause the state machine to return with type of number format (int/float/scientific). + +This code will perform a realistic task, be small enough to easily understand, and exercise the required functionality. The other option used in embedded systems is a mealy based state machine, which is driven by a table. The table then determines the number of states and complexity of transitions. This approach, however, tests mainly the load/store and function call mechanisms and less the handling of branches. If analysis of the final results shows that the load/store functionality of the processor is not exercised thoroughly, it may be a good addition to the benchmark (codesize allowing). + +For input, the memory block will be initialized with comma separated values of mixed formats, as well as invalid inputs. + +For the benchmark itself: +- Invoke the state machine on all of the input and count final states and state transitions. CRC of all final states and transitions will become part of the output chain. +- Modify the input at intervals (inject errors) and repeat the state machine operation. +- Modify the input back to original form. + +The actual input must be initialized based on data that cannot be determined at compile time. In addition the intervals for modification of the input and the actual modification must be based on input that cannot be determined at compile time. + +# Validation + +This release was tested on the following platforms: +* x86 cygwin and gcc 3.4 (Quad, dual and single core systems) +* x86 linux (Ubuntu/Fedora) and gcc (4.2/4.1) (Quad and single core systems) +* MIPS64 BE linux and gcc 3.4 16 cores system +* MIPS32 BE linux with CodeSourcery compiler 4.2-177 on Malta/Linux with a 1004K 3-core system +* PPC simulator with gcc 4.2.2 (No OS) +* PPC 64b BE linux (yellowdog) with gcc 3.4 and 4.1 (Dual core system) +* BF533 with VDSP50 +* Renesas R8C/H8 MCU with HEW 4.05 +* NXP LPC1700 armcc v4.0.0.524 +* NEC 78K with IAR v4.61 +* ARM simulator with armcc v4 + +# Memory Analysis + +Valgrind 3.4.0 used and no errors reported. + +# Balance Analysis + +Number of instructions executed for each function tested with cachegrind and found balanced with gcc and -O0. + +# Statistics + +Lines: +~~~ +Lines Blank Cmnts Source AESL +===== ===== ===== ===== ========== ======================================= + 469 66 170 251 627.5 core_list_join.c (C) + 330 18 54 268 670.0 core_main.c (C) + 256 32 80 146 365.0 core_matrix.c (C) + 240 16 51 186 465.0 core_state.c (C) + 165 11 20 134 335.0 core_util.c (C) + 150 23 36 98 245.0 coremark.h (C) + 1610 166 411 1083 2707.5 ----- Benchmark ----- (6 files) + 293 15 74 212 530.0 linux/core_portme.c (C) + 235 30 104 104 260.0 linux/core_portme.h (C) + 528 45 178 316 790.0 ----- Porting ----- (2 files) + +* For comparison, here are the stats for Dhrystone +Lines Blank Cmnts Source AESL +===== ===== ===== ===== ========== ======================================= + 311 15 242 54 135.0 dhry.h (C) + 789 132 119 553 1382.5 dhry_1.c (C) + 186 26 68 107 267.5 dhry_2.c (C) + 1286 173 429 714 1785.0 ----- C ----- (3 files) +~~~ + +# Credits +Many thanks to all of the individuals who helped with the development or testing of CoreMark including (Sorted by company name; note that company names may no longer be accurate as this was written in 2009). +* Alan Anderson, ADI +* Adhikary Rajiv, ADI +* Elena Stohr, ARM +* Ian Rickards, ARM +* Andrew Pickard, ARM +* Trent Parker, CAVIUM +* Shay Gal-On, EEMBC +* Markus Levy, EEMBC +* Peter Torelli, EEMBC +* Ron Olson, IBM +* Eyal Barzilay, MIPS +* Jens Eltze, NEC +* Hirohiko Ono, NEC +* Ulrich Drees, NEC +* Frank Roscheda, NEC +* Rob Cosaro, NXP +* Shumpei Kawasaki, RENESAS + +# Legal +Please refer to LICENSE.md in this reposity for a description of your rights to use this code. + +# Copyright +Copyright © 2009 EEMBC All rights reserved. +CoreMark is a trademark of EEMBC and EEMBC is a registered trademark of the Embedded Microprocessor Benchmark Consortium. + diff --git a/sdk/software/examples/coremark/core_list_join.c b/sdk/software/examples/coremark/core_list_join.c new file mode 100644 index 0000000..588b103 --- /dev/null +++ b/sdk/software/examples/coremark/core_list_join.c @@ -0,0 +1,599 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +#include "coremark.h" +/* +Topic: Description + Benchmark using a linked list. + + Linked list is a common data structure used in many applications. + + For our purposes, this will excercise the memory units of the processor. + In particular, usage of the list pointers to find and alter data. + + We are not using Malloc since some platforms do not support this +library. + + Instead, the memory block being passed in is used to create a list, + and the benchmark takes care not to add more items then can be + accomodated by the memory block. The porting layer will make sure + that we have a valid memory block. + + All operations are done in place, without using any extra memory. + + The list itself contains list pointers and pointers to data items. + Data items contain the following: + + idx - An index that captures the initial order of the list. + data - Variable data initialized based on the input parameters. The 16b +are divided as follows: o Upper 8b are backup of original data. o Bit 7 +indicates if the lower 7 bits are to be used as is or calculated. o Bits 0-2 +indicate type of operation to perform to get a 7b value. o Bits 3-6 provide +input for the operation. + +*/ + +/* local functions */ + +list_head *core_list_find(list_head *list, list_data *info); +list_head *core_list_reverse(list_head *list); +list_head *core_list_remove(list_head *item); +list_head *core_list_undo_remove(list_head *item_removed, + list_head *item_modified); +list_head *core_list_insert_new(list_head * insert_point, + list_data * info, + list_head **memblock, + list_data **datablock, + list_head * memblock_end, + list_data * datablock_end); +typedef ee_s32 (*list_cmp)(list_data *a, list_data *b, core_results *res); +list_head *core_list_mergesort(list_head * list, + list_cmp cmp, + core_results *res); + +ee_s16 +calc_func(ee_s16 *pdata, core_results *res) +{ + ee_s16 data = *pdata; + ee_s16 retval; + ee_u8 optype + = (data >> 7) + & 1; /* bit 7 indicates if the function result has been cached */ + if (optype) /* if cached, use cache */ + return (data & 0x007f); + else + { /* otherwise calculate and cache the result */ + ee_s16 flag = data & 0x7; /* bits 0-2 is type of function to perform */ + ee_s16 dtype + = ((data >> 3) + & 0xf); /* bits 3-6 is specific data for the operation */ + dtype |= dtype << 4; /* replicate the lower 4 bits to get an 8b value */ + switch (flag) + { + case 0: + if (dtype < 0x22) /* set min period for bit corruption */ + dtype = 0x22; + retval = core_bench_state(res->size, + res->memblock[3], + res->seed1, + res->seed2, + dtype, + res->crc); + if (res->crcstate == 0) + res->crcstate = retval; + break; + case 1: + retval = core_bench_matrix(&(res->mat), dtype, res->crc); + if (res->crcmatrix == 0) + res->crcmatrix = retval; + break; + default: + retval = data; + break; + } + res->crc = crcu16(retval, res->crc); + retval &= 0x007f; + *pdata = (data & 0xff00) | 0x0080 | retval; /* cache the result */ + return retval; + } +} +/* Function: cmp_complex + Compare the data item in a list cell. + + Can be used by mergesort. +*/ +ee_s32 +cmp_complex(list_data *a, list_data *b, core_results *res) +{ + ee_s16 val1 = calc_func(&(a->data16), res); + ee_s16 val2 = calc_func(&(b->data16), res); + return val1 - val2; +} + +/* Function: cmp_idx + Compare the idx item in a list cell, and regen the data. + + Can be used by mergesort. +*/ +ee_s32 +cmp_idx(list_data *a, list_data *b, core_results *res) +{ + if (res == NULL) + { + a->data16 = (a->data16 & 0xff00) | (0x00ff & (a->data16 >> 8)); + b->data16 = (b->data16 & 0xff00) | (0x00ff & (b->data16 >> 8)); + } + return a->idx - b->idx; +} + +void +copy_info(list_data *to, list_data *from) +{ + to->data16 = from->data16; + to->idx = from->idx; +} + +/* Benchmark for linked list: + - Try to find multiple data items. + - List sort + - Operate on data from list (crc) + - Single remove/reinsert + * At the end of this function, the list is back to original state +*/ +ee_u16 +core_bench_list(core_results *res, ee_s16 finder_idx) +{ + ee_u16 retval = 0; + ee_u16 found = 0, missed = 0; + list_head *list = res->list; + ee_s16 find_num = res->seed3; + list_head *this_find; + list_head *finder, *remover; + list_data info; + ee_s16 i; + + info.idx = finder_idx; + /* find values in the list, and change the list each time + * (reverse and cache if value found) */ + for (i = 0; i < find_num; i++) + { + info.data16 = (i & 0xff); + this_find = core_list_find(list, &info); + list = core_list_reverse(list); + if (this_find == NULL) + { + missed++; + retval += (list->next->info->data16 >> 8) & 1; + } + else + { + found++; + if (this_find->info->data16 & 0x1) /* use found value */ + retval += (this_find->info->data16 >> 9) & 1; + /* and cache next item at the head of the list (if any) */ + if (this_find->next != NULL) + { + finder = this_find->next; + this_find->next = finder->next; + finder->next = list->next; + list->next = finder; + } + } + if (info.idx >= 0) + info.idx++; +#if CORE_DEBUG + ee_printf("List find %d: [%d,%d,%d]\n", i, retval, missed, found); +#endif + } + retval += found * 4 - missed; + /* sort the list by data content and remove one item*/ + if (finder_idx > 0) + list = core_list_mergesort(list, cmp_complex, res); + remover = core_list_remove(list->next); + /* CRC data content of list from location of index N forward, and then undo + * remove */ + finder = core_list_find(list, &info); + if (!finder) + finder = list->next; + while (finder) + { + retval = crc16(list->info->data16, retval); + finder = finder->next; + } +#if CORE_DEBUG + ee_printf("List sort 1: %04x\n", retval); +#endif + remover = core_list_undo_remove(remover, list->next); + /* sort the list by index, in effect returning the list to original state */ + list = core_list_mergesort(list, cmp_idx, NULL); + /* CRC data content of list */ + finder = list->next; + while (finder) + { + retval = crc16(list->info->data16, retval); + finder = finder->next; + } +#if CORE_DEBUG + ee_printf("List sort 2: %04x\n", retval); +#endif + return retval; +} +/* Function: core_list_init + Initialize list with data. + + Parameters: + blksize - Size of memory to be initialized. + memblock - Pointer to memory block. + seed - Actual values chosen depend on the seed parameter. + The seed parameter MUST be supplied from a source that cannot be + determined at compile time + + Returns: + Pointer to the head of the list. + +*/ +list_head * +core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed) +{ + /* calculated pointers for the list */ + ee_u32 per_item = 16 + sizeof(struct list_data_s); + ee_u32 size = (blksize / per_item) + - 2; /* to accomodate systems with 64b pointers, and make sure + same code is executed, set max list elements */ + list_head *memblock_end = memblock + size; + list_data *datablock = (list_data *)(memblock_end); + list_data *datablock_end = datablock + size; + /* some useful variables */ + ee_u32 i; + list_head *finder, *list = memblock; + list_data info; + + /* create a fake items for the list head and tail */ + list->next = NULL; + list->info = datablock; + list->info->idx = 0x0000; + list->info->data16 = (ee_s16)0x8080; + memblock++; + datablock++; + info.idx = 0x7fff; + info.data16 = (ee_s16)0xffff; + core_list_insert_new( + list, &info, &memblock, &datablock, memblock_end, datablock_end); + + /* then insert size items */ + for (i = 0; i < size; i++) + { + ee_u16 datpat = ((ee_u16)(seed ^ i) & 0xf); + ee_u16 dat + = (datpat << 3) | (i & 0x7); /* alternate between algorithms */ + info.data16 = (dat << 8) | dat; /* fill the data with actual data and + upper bits with rebuild value */ + core_list_insert_new( + list, &info, &memblock, &datablock, memblock_end, datablock_end); + } + /* and now index the list so we know initial seed order of the list */ + finder = list->next; + i = 1; + while (finder->next != NULL) + { + if (i < size / 5) /* first 20% of the list in order */ + finder->info->idx = i++; + else + { + volatile ee_u16 pat = (ee_u16)(i++ ^ seed); /* get a pseudo random number */ + finder->info->idx = 0x3fff & (((i & 0x07) << 8)| pat); /* make sure the mixed items end up after the ones in sequence */ + //*( volatile int * ) ( 0x40000000 ) = pat; + //*( volatile int * ) ( 0x40000004 ) = ((i & 0x07) << 8) | pat; + //*( volatile int * ) ( 0x40000008 ) = finder->info->idx; + //ee_printf("pat = %x\n",pat); + //ee_printf("((i & 0x07) << 8) | pat = %x\n",((i & 0x07) << 8) | pat); + //ee_printf("finder->info->idx = %d\n",finder->info->idx); + } + finder = finder->next; + } + list = core_list_mergesort(list, cmp_idx, NULL); + +#if CORE_DEBUG + ee_printf("Initialized list:\n"); + finder = list; + while (finder) + { + ee_printf( + "[%04x,%04x]", finder->info->idx, (ee_u16)finder->info->data16); + finder = finder->next; + } + ee_printf("\n"); +#endif + return list; +} + +/* Function: core_list_insert + Insert an item to the list + + Parameters: + insert_point - where to insert the item. + info - data for the cell. + memblock - pointer for the list header + datablock - pointer for the list data + memblock_end - end of region for list headers + datablock_end - end of region for list data + + Returns: + Pointer to new item. +*/ +list_head * +core_list_insert_new(list_head * insert_point, + list_data * info, + list_head **memblock, + list_data **datablock, + list_head * memblock_end, + list_data * datablock_end) +{ + list_head *newitem; + + if ((*memblock + 1) >= memblock_end) + return NULL; + if ((*datablock + 1) >= datablock_end) + return NULL; + + newitem = *memblock; + (*memblock)++; + newitem->next = insert_point->next; + insert_point->next = newitem; + + newitem->info = *datablock; + (*datablock)++; + copy_info(newitem->info, info); + + return newitem; +} + +/* Function: core_list_remove + Remove an item from the list. + + Operation: + For a singly linked list, remove by copying the data from the next item + over to the current cell, and unlinking the next item. + + Note: + since there is always a fake item at the end of the list, no need to + check for NULL. + + Returns: + Removed item. +*/ +list_head * +core_list_remove(list_head *item) +{ + list_data *tmp; + list_head *ret = item->next; + /* swap data pointers */ + tmp = item->info; + item->info = ret->info; + ret->info = tmp; + /* and eliminate item */ + item->next = item->next->next; + ret->next = NULL; + return ret; +} + +/* Function: core_list_undo_remove + Undo a remove operation. + + Operation: + Since we want each iteration of the benchmark to be exactly the same, + we need to be able to undo a remove. + Link the removed item back into the list, and switch the info items. + + Parameters: + item_removed - Return value from the + item_modified - List item that was modified during + + Returns: + The item that was linked back to the list. + +*/ +list_head * +core_list_undo_remove(list_head *item_removed, list_head *item_modified) +{ + list_data *tmp; + /* swap data pointers */ + tmp = item_removed->info; + item_removed->info = item_modified->info; + item_modified->info = tmp; + /* and insert item */ + item_removed->next = item_modified->next; + item_modified->next = item_removed; + return item_removed; +} + +/* Function: core_list_find + Find an item in the list + + Operation: + Find an item by idx (if not 0) or specific data value + + Parameters: + list - list head + info - idx or data to find + + Returns: + Found item, or NULL if not found. +*/ +list_head * +core_list_find(list_head *list, list_data *info) +{ + if (info->idx >= 0) + { + while (list && (list->info->idx != info->idx)) + list = list->next; + return list; + } + else + { + while (list && ((list->info->data16 & 0xff) != info->data16)) + list = list->next; + return list; + } +} +/* Function: core_list_reverse + Reverse a list + + Operation: + Rearrange the pointers so the list is reversed. + + Parameters: + list - list head + info - idx or data to find + + Returns: + Found item, or NULL if not found. +*/ + +list_head * +core_list_reverse(list_head *list) +{ + list_head *next = NULL, *tmp; + while (list) + { + tmp = list->next; + list->next = next; + next = list; + list = tmp; + } + return next; +} +/* Function: core_list_mergesort + Sort the list in place without recursion. + + Description: + Use mergesort, as for linked list this is a realistic solution. + Also, since this is aimed at embedded, care was taken to use iterative + rather then recursive algorithm. The sort can either return the list to + original order (by idx) , or use the data item to invoke other other + algorithms and change the order of the list. + + Parameters: + list - list to be sorted. + cmp - cmp function to use + + Returns: + New head of the list. + + Note: + We have a special header for the list that will always be first, + but the algorithm could theoretically modify where the list starts. + + */ +list_head * +core_list_mergesort(list_head *list, list_cmp cmp, core_results *res) +{ + list_head *p, *q, *e, *tail; + ee_s32 insize, nmerges, psize, qsize, i; + + insize = 1; + + while (1) + { + p = list; + list = NULL; + tail = NULL; + + nmerges = 0; /* count number of merges we do in this pass */ + + while (p) + { + nmerges++; /* there exists a merge to be done */ + /* step `insize' places along from p */ + q = p; + psize = 0; + for (i = 0; i < insize; i++) + { + psize++; + q = q->next; + if (!q) + break; + } + + /* if q hasn't fallen off end, we have two lists to merge */ + qsize = insize; + + /* now we have two lists; merge them */ + while (psize > 0 || (qsize > 0 && q)) + { + + /* decide whether next element of merge comes from p or q */ + if (psize == 0) + { + /* p is empty; e must come from q. */ + e = q; + q = q->next; + qsize--; + } + else if (qsize == 0 || !q) + { + /* q is empty; e must come from p. */ + e = p; + p = p->next; + psize--; + } + else if (cmp(p->info, q->info, res) <= 0) + { + /* First element of p is lower (or same); e must come from + * p. */ + e = p; + p = p->next; + psize--; + } + else + { + /* First element of q is lower; e must come from q. */ + e = q; + q = q->next; + qsize--; + } + + /* add the next element to the merged list */ + if (tail) + { + tail->next = e; + } + else + { + list = e; + } + tail = e; + } + + /* now p has stepped `insize' places along, and q has too */ + p = q; + } + + tail->next = NULL; + + /* If we have done only one merge, we're finished. */ + if (nmerges <= 1) /* allow for nmerges==0, the empty list case */ + return list; + + /* Otherwise repeat, merging lists twice the size */ + insize *= 2; + } +#if COMPILER_REQUIRES_SORT_RETURN + return list; +#endif +} diff --git a/sdk/software/examples/coremark/core_main.c b/sdk/software/examples/coremark/core_main.c new file mode 100644 index 0000000..d70050e --- /dev/null +++ b/sdk/software/examples/coremark/core_main.c @@ -0,0 +1,422 @@ +/* +Author : Shay Gal-On, EEMBC + +This file is part of EEMBC(R) and CoreMark(TM), which are Copyright (C) 2009 +All rights reserved. + +EEMBC CoreMark Software is a product of EEMBC and is provided under the terms of the +CoreMark License that is distributed with the official EEMBC COREMARK Software release. +If you received this EEMBC CoreMark Software without the accompanying CoreMark License, +you must discontinue use and download the official release from www.coremark.org. + +Also, if you are publicly displaying scores generated from the EEMBC CoreMark software, +make sure that you are in compliance with Run and Reporting rules specified in the accompanying readme.txt file. + +EEMBC +4354 Town Center Blvd. Suite 114-200 +El Dorado Hills, CA, 95762 +*/ +/* File: core_main.c + This file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results. +*/ +#include "coremark.h" + +/* Function: iterate + Run the benchmark for a specified number of iterations. + + Operation: + For each type of benchmarked algorithm: + a - Initialize the data block for the algorithm. + b - Execute the algorithm N times. + + Returns: + NULL. +*/ + +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbf000000; //UART16550的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbf20f100; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +static ee_u16 list_known_crc[] = {(ee_u16)0xd4b0,(ee_u16)0x3340,(ee_u16)0x6a79,(ee_u16)0xe714,(ee_u16)0xe3c1}; +static ee_u16 matrix_known_crc[] = {(ee_u16)0xbe52,(ee_u16)0x1199,(ee_u16)0x5608,(ee_u16)0x1fd7,(ee_u16)0x0747}; +static ee_u16 state_known_crc[] = {(ee_u16)0x5e47,(ee_u16)0x39bf,(ee_u16)0xe5a4,(ee_u16)0x8e3a,(ee_u16)0x8d84}; +void *iterate(void *pres) { + ee_u32 i; + ee_u16 crc; + core_results *res=(core_results *)pres; + ee_u32 iterations=res->iterations; + res->crc=0; + res->crclist=0; + res->crcmatrix=0; + res->crcstate=0; + + for (i=0; icrc=crcu16(crc,res->crc); + crc=core_bench_list(res,-1); + res->crc=crcu16(crc,res->crc); + if (i==0) res->crclist=res->crc; + } + return NULL; +} + +#if (SEED_METHOD==SEED_ARG) +ee_s32 get_seed_args(int i, int argc, char *argv[]); +#define get_seed(x) (ee_s16)get_seed_args(x,argc,argv) +#define get_seed_32(x) get_seed_args(x,argc,argv) +#else /* via function or volatile */ +ee_s32 get_seed_32(int i); +#define get_seed(x) (ee_s16)get_seed_32(x) +#endif + +#if (MEM_METHOD==MEM_STATIC) +ee_u8 static_memblk[TOTAL_DATA_SIZE]; +#endif +char *mem_name[3] = {"Static","Heap","Stack"}; +/* Function: main + Main entry routine for the benchmark. + This function is responsible for the following steps: + + 1 - Initialize input seeds from a source that cannot be determined at compile time. + 2 - Initialize memory block for use. + 3 - Run and time the benchmark. + 4 - Report results, testing the validity of the output if the seeds are known. + + Arguments: + 1 - first seed : Any value + 2 - second seed : Must be identical to first for iterations to be identical + 3 - third seed : Any value, should be at least an order of magnitude less then the input size, but bigger then 32. + 4 - Iterations : Special, if set to 0, iterations will be automatically determined such that the benchmark will run between 10 to 100 secs + +*/ + +#if MAIN_HAS_NOARGC +MAIN_RETURN_TYPE main(void) { + int argc=0; + char *argv[1]; +#else +MAIN_RETURN_TYPE main(int argc, char *argv[]) { +#endif + ee_u16 i,j=0,num_algorithms=0; + ee_s16 known_id=-1,total_errors=0; + ee_u16 seedcrc=0; + CORE_TICKS total_time; + core_results results[MULTITHREAD]; +#if (MEM_METHOD==MEM_STACK) + ee_u8 stack_memblock[TOTAL_DATA_SIZE*MULTITHREAD]; +#endif + /* first call any initializations needed */ + //portable_init(&(results[0].port), &argc, argv); + /* First some checks to make sure benchmark will run ok */ + if (sizeof(struct list_head_s)>128) { + + return MAIN_RETURN_VAL; + } + results[0].seed1=get_seed(1); + results[0].seed2=get_seed(2); + results[0].seed3=get_seed(3); + results[0].iterations=get_seed_32(4); +#if CORE_DEBUG + results[0].iterations=1; +#endif + // Bob: change the interation times to make it faster + /* Initializations */ + // UART_INIT(UART, 3, CCLK, BAUD); + + results[0].execs=get_seed_32(5); + if (results[0].execs==0) { /* if not supplied, execute all algorithms */ + results[0].execs=ALL_ALGORITHMS_MASK; + } + /* put in some default values based on one seed only for easy testing */ + if ((results[0].seed1==0) && (results[0].seed2==0) && (results[0].seed3==0)) { /* validation run */ + results[0].seed1=0; + results[0].seed2=0; + results[0].seed3=0x66; + } + if ((results[0].seed1==1) && (results[0].seed2==0) && (results[0].seed3==0)) { /* perfromance run */ + results[0].seed1=0x3415; + results[0].seed2=0x3415; + results[0].seed3=0x66; + } +#if (MEM_METHOD==MEM_STATIC) + results[0].memblock[0]=(void *)static_memblk; + results[0].size=TOTAL_DATA_SIZE; + results[0].err=0; + #if (MULTITHREAD>1) + #error "Cannot use a static data area with multiple contexts!" + #endif +#elif (MEM_METHOD==MEM_MALLOC) + for (i=0 ; i1) + if (default_num_contexts>MULTITHREAD) { + default_num_contexts=MULTITHREAD; + } + for (i=0 ; i= 0) + { + for (i = 0; i < default_num_contexts; i++) + { + results[i].err = 0; + if ((results[i].execs & ID_LIST) + && (results[i].crclist != list_known_crc[known_id])) + { + ee_printf("[%u]ERROR! list crc 0x%04x - should be 0x%04x\n", + i, + results[i].crclist, + list_known_crc[known_id]); + results[i].err++; + } + if ((results[i].execs & ID_MATRIX) + && (results[i].crcmatrix != matrix_known_crc[known_id])) + { + ee_printf("[%u]ERROR! matrix crc 0x%04x - should be 0x%04x\n", + i, + results[i].crcmatrix, + matrix_known_crc[known_id]); + results[i].err++; + } + if ((results[i].execs & ID_STATE) + && (results[i].crcstate != state_known_crc[known_id])) + { + ee_printf("[%u]ERROR! state crc 0x%04x - should be 0x%04x\n", + i, + results[i].crcstate, + state_known_crc[known_id]); + results[i].err++; + } + total_errors += results[i].err; + } + } + total_errors += check_data_types(); + + /* and report results */ + ee_printf("CoreMark Size : %lu\n", (long unsigned)results[0].size); + ee_printf("Total ticks : %lu\n", (long unsigned)total_time); +#if HAS_FLOAT + ee_printf("Total time (secs): %f\n", time_in_secs(total_time)); + if (time_in_secs(total_time) > 0) + ee_printf("Iterations/Sec : %f\n", + default_num_contexts * results[0].iterations + / time_in_secs(total_time)); +#else + ee_printf("Total time (secs): %d\n", time_in_secs(total_time)); + if (time_in_secs(total_time) > 0) + ee_printf("Iterations/Sec : %d\n", + default_num_contexts * results[0].iterations + / time_in_secs(total_time)); +#endif + // if (time_in_secs(total_time) < 10) + // { + // ee_printf( + // "ERROR! Must execute for at least 10 secs for a valid result!\n"); + // total_errors++; + // } + + ee_printf("Iterations : %lu\n", + (long unsigned)default_num_contexts * results[0].iterations); + ee_printf("Compiler version : %s\n", COMPILER_VERSION); + ee_printf("Compiler flags : %s\n", COMPILER_FLAGS); +#if (MULTITHREAD > 1) + ee_printf("Parallel %s : %d\n", PARALLEL_METHOD, default_num_contexts); +#endif + ee_printf("Memory location : %s\n", MEM_LOCATION); + /* output for verification */ + ee_printf("seedcrc : 0x%04x\n", seedcrc); + if (results[0].execs & ID_LIST) + for (i = 0; i < default_num_contexts; i++) + ee_printf("[%d]crclist : 0x%04x\n", i, results[i].crclist); + if (results[0].execs & ID_MATRIX) + for (i = 0; i < default_num_contexts; i++) + ee_printf("[%d]crcmatrix : 0x%04x\n", i, results[i].crcmatrix); + if (results[0].execs & ID_STATE) + for (i = 0; i < default_num_contexts; i++) + ee_printf("[%d]crcstate : 0x%04x\n", i, results[i].crcstate); + for (i = 0; i < default_num_contexts; i++) + ee_printf("[%d]crcfinal : 0x%04x\n", i, results[i].crc); + if (total_errors == 0) + { + ee_printf( + "Correct operation validated. See README.md for run and reporting " + "rules.\n"); +#if HAS_FLOAT + if (known_id == 3) + { + ee_printf("CoreMark 1.0 : %f / %s %s", + default_num_contexts * results[0].iterations + / time_in_secs(total_time), + COMPILER_VERSION, + COMPILER_FLAGS); +#if defined(MEM_LOCATION) && !defined(MEM_LOCATION_UNSPEC) + ee_printf(" / %s", MEM_LOCATION); +#else + ee_printf(" / %s", mem_name[MEM_METHOD]); +#endif + +#if (MULTITHREAD > 1) + ee_printf(" / %d:%s", default_num_contexts, PARALLEL_METHOD); +#endif + ee_printf("\n"); + } +#endif + } + if (total_errors > 0) + ee_printf("Errors detected\n"); + if (total_errors < 0) + ee_printf( + "Cannot validate operation for these seed values, please compare " + "with results on a known platform.\n"); + + float coremark_dmips = (results[0].iterations*1000000)/(float)total_time; +#if HAS_FLOAT + ee_printf ("\n"); + ee_printf ("\n"); + ee_printf ("Print Personal Added Addtional Info to Easy Visual Analysis\n"); + ee_printf ("\n"); + ee_printf (" (*) Assume the core running at %d MHz\n",CORE_CLOCKS_PER_SEC/1000000); + ee_printf (" So the CoreMark/MHz can be caculated by: \n"); + ee_printf (" (Iterations*1000000/total_ticks) = %2.6f CoreMark/MHz\n", coremark_dmips); + ee_printf ("\n"); +#endif + + return MAIN_RETURN_VAL; +} + + + diff --git a/sdk/software/examples/coremark/core_matrix.c b/sdk/software/examples/coremark/core_matrix.c new file mode 100644 index 0000000..29fd8ab --- /dev/null +++ b/sdk/software/examples/coremark/core_matrix.c @@ -0,0 +1,359 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +#include "coremark.h" +/* +Topic: Description + Matrix manipulation benchmark + + This very simple algorithm forms the basis of many more complex +algorithms. + + The tight inner loop is the focus of many optimizations (compiler as +well as hardware based) and is thus relevant for embedded processing. + + The total available data space will be divided to 3 parts: + NxN Matrix A - initialized with small values (upper 3/4 of the bits all +zero). NxN Matrix B - initialized with medium values (upper half of the bits all +zero). NxN Matrix C - used for the result. + + The actual values for A and B must be derived based on input that is not +available at compile time. +*/ +ee_s16 matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val); +ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval); +void matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val); +void matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B); +void matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B); +void matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B); +void matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val); + +#define matrix_test_next(x) (x + 1) +#define matrix_clip(x, y) ((y) ? (x)&0x0ff : (x)&0x0ffff) +#define matrix_big(x) (0xf000 | (x)) +#define bit_extract(x, from, to) (((x) >> (from)) & (~(0xffffffff << (to)))) + +#if CORE_DEBUG +void +printmat(MATDAT *A, ee_u32 N, char *name) +{ + ee_u32 i, j; + ee_printf("Matrix %s [%dx%d]:\n", name, N, N); + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + if (j != 0) + ee_printf(","); + ee_printf("%d", A[i * N + j]); + } + ee_printf("\n"); + } +} +void +printmatC(MATRES *C, ee_u32 N, char *name) +{ + ee_u32 i, j; + ee_printf("Matrix %s [%dx%d]:\n", name, N, N); + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + if (j != 0) + ee_printf(","); + ee_printf("%d", C[i * N + j]); + } + ee_printf("\n"); + } +} +#endif +/* Function: core_bench_matrix + Benchmark function + + Iterate N times, + changing the matrix values slightly by a constant amount each time. +*/ +ee_u16 +core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc) +{ + ee_u32 N = p->N; + MATRES *C = p->C; + MATDAT *A = p->A; + MATDAT *B = p->B; + MATDAT val = (MATDAT)seed; + + crc = crc16(matrix_test(N, C, A, B, val), crc); + + return crc; +} + +/* Function: matrix_test + Perform matrix manipulation. + + Parameters: + N - Dimensions of the matrix. + C - memory for result matrix. + A - input matrix + B - operator matrix (not changed during operations) + + Returns: + A CRC value that captures all results calculated in the function. + In particular, crc of the value calculated on the result matrix + after each step by . + + Operation: + + 1 - Add a constant value to all elements of a matrix. + 2 - Multiply a matrix by a constant. + 3 - Multiply a matrix by a vector. + 4 - Multiply a matrix by a matrix. + 5 - Add a constant value to all elements of a matrix. + + After the last step, matrix A is back to original contents. +*/ +ee_s16 +matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val) +{ + ee_u16 crc = 0; + MATDAT clipval = matrix_big(val); + + matrix_add_const(N, A, val); /* make sure data changes */ +#if CORE_DEBUG + printmat(A, N, "matrix_add_const"); +#endif + matrix_mul_const(N, C, A, val); + crc = crc16(matrix_sum(N, C, clipval), crc); +#if CORE_DEBUG + printmatC(C, N, "matrix_mul_const"); +#endif + matrix_mul_vect(N, C, A, B); + crc = crc16(matrix_sum(N, C, clipval), crc); +#if CORE_DEBUG + printmatC(C, N, "matrix_mul_vect"); +#endif + matrix_mul_matrix(N, C, A, B); + crc = crc16(matrix_sum(N, C, clipval), crc); +#if CORE_DEBUG + printmatC(C, N, "matrix_mul_matrix"); +#endif + matrix_mul_matrix_bitextract(N, C, A, B); + crc = crc16(matrix_sum(N, C, clipval), crc); +#if CORE_DEBUG + printmatC(C, N, "matrix_mul_matrix_bitextract"); +#endif + + matrix_add_const(N, A, -val); /* return matrix to initial value */ + return crc; +} + +/* Function : matrix_init + Initialize the memory block for matrix benchmarking. + + Parameters: + blksize - Size of memory to be initialized. + memblk - Pointer to memory block. + seed - Actual values chosen depend on the seed parameter. + p - pointers to containing initialized matrixes. + + Returns: + Matrix dimensions. + + Note: + The seed parameter MUST be supplied from a source that cannot be + determined at compile time +*/ +ee_u32 +core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p) +{ + ee_u32 N = 0; + MATDAT *A; + MATDAT *B; + ee_s32 order = 1; + MATDAT val; + ee_u32 i = 0, j = 0; + if (seed == 0) + seed = 1; + while (j < blksize) + { + i++; + j = i * i * 2 * 4; + } + N = i - 1; + A = (MATDAT *)align_mem(memblk); + B = A + N * N; + + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + seed = ((order * seed) % 65536); + val = (seed + order); + val = matrix_clip(val, 0); + B[i * N + j] = val; + val = (val + order); + val = matrix_clip(val, 1); + A[i * N + j] = val; + order++; + } + } + + p->A = A; + p->B = B; + p->C = (MATRES *)align_mem(B + N * N); + p->N = N; +#if CORE_DEBUG + printmat(A, N, "A"); + printmat(B, N, "B"); +#endif + return N; +} + +/* Function: matrix_sum + Calculate a function that depends on the values of elements in the + matrix. + + For each element, accumulate into a temporary variable. + + As long as this value is under the parameter clipval, + add 1 to the result if the element is bigger then the previous. + + Otherwise, reset the accumulator and add 10 to the result. +*/ +ee_s16 +matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval) +{ + MATRES tmp = 0, prev = 0, cur = 0; + ee_s16 ret = 0; + ee_u32 i, j; + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + cur = C[i * N + j]; + tmp += cur; + if (tmp > clipval) + { + ret += 10; + tmp = 0; + } + else + { + ret += (cur > prev) ? 1 : 0; + } + prev = cur; + } + } + return ret; +} + +/* Function: matrix_mul_const + Multiply a matrix by a constant. + This could be used as a scaler for instance. +*/ +void +matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val) +{ + ee_u32 i, j; + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + C[i * N + j] = (MATRES)A[i * N + j] * (MATRES)val; + } + } +} + +/* Function: matrix_add_const + Add a constant value to all elements of a matrix. +*/ +void +matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val) +{ + ee_u32 i, j; + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + A[i * N + j] += val; + } + } +} + +/* Function: matrix_mul_vect + Multiply a matrix by a vector. + This is common in many simple filters (e.g. fir where a vector of + coefficients is applied to the matrix.) +*/ +void +matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) +{ + ee_u32 i, j; + for (i = 0; i < N; i++) + { + C[i] = 0; + for (j = 0; j < N; j++) + { + C[i] += (MATRES)A[i * N + j] * (MATRES)B[j]; + } + } +} + +/* Function: matrix_mul_matrix + Multiply a matrix by a matrix. + Basic code is used in many algorithms, mostly with minor changes such as + scaling. +*/ +void +matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) +{ + ee_u32 i, j, k; + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + C[i * N + j] = 0; + for (k = 0; k < N; k++) + { + C[i * N + j] += (MATRES)A[i * N + k] * (MATRES)B[k * N + j]; + } + } + } +} + +/* Function: matrix_mul_matrix_bitextract + Multiply a matrix by a matrix, and extract some bits from the result. + Basic code is used in many algorithms, mostly with minor changes such as + scaling. +*/ +void +matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) +{ + ee_u32 i, j, k; + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + C[i * N + j] = 0; + for (k = 0; k < N; k++) + { + MATRES tmp = (MATRES)A[i * N + k] * (MATRES)B[k * N + j]; + C[i * N + j] += bit_extract(tmp, 2, 4) * bit_extract(tmp, 5, 7); + } + } + } +} diff --git a/sdk/software/examples/coremark/core_portme.c b/sdk/software/examples/coremark/core_portme.c new file mode 100644 index 0000000..94a328f --- /dev/null +++ b/sdk/software/examples/coremark/core_portme.c @@ -0,0 +1,53 @@ +//#include +//#include +#include "coremark.h" +//#include "platform.h" +//#include "encoding.h" + +#if VALIDATION_RUN + volatile ee_s32 seed1_volatile=0x3415; + volatile ee_s32 seed2_volatile=0x3415; + volatile ee_s32 seed3_volatile=0x66; +#endif + +#if PERFORMANCE_RUN + volatile ee_s32 seed1_volatile=0x0; + volatile ee_s32 seed2_volatile=0x0; + volatile ee_s32 seed3_volatile=0x66; +#endif + +#if PROFILE_RUN + volatile ee_s32 seed1_volatile=0x8; + volatile ee_s32 seed2_volatile=0x8; + volatile ee_s32 seed3_volatile=0x8; +#endif + +volatile ee_s32 seed4_volatile=ITERATIONS; +volatile ee_s32 seed5_volatile=0; + +static CORE_TICKS t0, t1; + +void start_time(void) +{ + t0 = get_clock_count(); +} + +void stop_time(void) +{ + t1 = get_clock_count(); +} + +CORE_TICKS get_time(void) +{ + return t1 - t0; +} + +secs_ret time_in_secs(CORE_TICKS ticks) +{ +#ifdef USE_CPU_CLOCK_COUNT + secs_ret retval = ((secs_ret)ticks) / (secs_ret)CORE_CLOCKS_PER_SEC; +#else + secs_ret retval = ((secs_ret)ticks) / (secs_ret)CONFREG_CLOCKS_PER_SEC; +#endif + return retval; +} diff --git a/sdk/software/examples/coremark/core_portme.h b/sdk/software/examples/coremark/core_portme.h new file mode 100644 index 0000000..0d7cb67 --- /dev/null +++ b/sdk/software/examples/coremark/core_portme.h @@ -0,0 +1,64 @@ +//Bob: put some macro here such that the IDE SDK do not need to specify the macro specially +// #define FLAGS_STR "-O3 -fno-common -funroll-all-loops -finline-limit=600 -ftree-dominator-opts -fno-if-conversion2 -fselective-scheduling -fno-code-hoisting --param max-inline-insns-auto=20 -falign-functions=4 -falign-jumps=4 -falign-loops=4" +#define PERFORMANCE_RUN 1 + +#ifndef FESDK_CORE_PORTME_H +#define FESDK_CORE_PORTME_H + +#include +#include +#include "confreg_time.h" + +//#define CORE_DEBUG 1 +#define HAS_FLOAT 1 +#define HAS_TIME_H 1 +#define USE_CLOCK 1 +#define HAS_STDIO 1 +#define HAS_PRINTF 1 +#define SEED_METHOD SEED_VOLATILE +#define CORE_TICKS uint64_t +#define ee_u8 uint8_t +#define ee_u16 uint16_t +#define ee_u32 uint32_t +#define ee_s16 int16_t +#define ee_s32 int32_t +#define ee_ptr_int uintptr_t +#define ee_size_t size_t +#define COMPILER_FLAGS FLAGS_STR + +#define align_mem(x) (void *)(((ee_ptr_int)(x) + sizeof(ee_u32) - 1) & -sizeof(ee_u32)) + +#ifdef __GNUC__ +# define COMPILER_VERSION "GCC8.3.0" +#else +# error +#endif + +#define MEM_METHOD MEM_STACK +#define MEM_LOCATION "STACK" + +#define MAIN_HAS_NOARGC 0 +#define MAIN_HAS_NORETURN 0 + +#define MULTITHREAD 1 +#define USE_PTHREAD 0 +#define USE_FORK 0 +#define USE_SOCKET 0 + +#define default_num_contexts MULTITHREAD + +typedef int core_portable; +//static void portable_init(core_portable *p, int *argc, char *argv[]) {} +//static void portable_fini(core_portable *p) {} + +#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) && !defined(VALIDATION_RUN) +#if (TOTAL_DATA_SIZE==1200) +#define PROFILE_RUN 1 +#elif (TOTAL_DATA_SIZE==2000) +#define PERFORMANCE_RUN 1 +#else +#define VALIDATION_RUN 1 +#endif +#endif + +#endif diff --git a/sdk/software/examples/coremark/core_state.c b/sdk/software/examples/coremark/core_state.c new file mode 100644 index 0000000..6dbab9d --- /dev/null +++ b/sdk/software/examples/coremark/core_state.c @@ -0,0 +1,330 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +#include "coremark.h" +/* local functions */ +enum CORE_STATE core_state_transition(ee_u8 **instr, ee_u32 *transition_count); + +/* +Topic: Description + Simple state machines like this one are used in many embedded products. + + For more complex state machines, sometimes a state transition table +implementation is used instead, trading speed of direct coding for ease of +maintenance. + + Since the main goal of using a state machine in CoreMark is to excercise +the switch/if behaviour, we are using a small moore machine. + + In particular, this machine tests type of string input, + trying to determine whether the input is a number or something else. + (see core_state.png). +*/ + +/* Function: core_bench_state + Benchmark function + + Go over the input twice, once direct, and once after introducing some + corruption. +*/ +ee_u16 +core_bench_state(ee_u32 blksize, + ee_u8 *memblock, + ee_s16 seed1, + ee_s16 seed2, + ee_s16 step, + ee_u16 crc) +{ + ee_u32 final_counts[NUM_CORE_STATES]; + ee_u32 track_counts[NUM_CORE_STATES]; + ee_u8 *p = memblock; + ee_u32 i; + +#if CORE_DEBUG + ee_printf("State Bench: %d,%d,%d,%04x\n", seed1, seed2, step, crc); +#endif + for (i = 0; i < NUM_CORE_STATES; i++) + { + final_counts[i] = track_counts[i] = 0; + } + /* run the state machine over the input */ + while (*p != 0) + { + enum CORE_STATE fstate = core_state_transition(&p, track_counts); + final_counts[fstate]++; +#if CORE_DEBUG + ee_printf("%d,", fstate); + } + ee_printf("\n"); +#else + } +#endif + p = memblock; + while (p < (memblock + blksize)) + { /* insert some corruption */ + if (*p != ',') + *p ^= (ee_u8)seed1; + p += step; + } + p = memblock; + /* run the state machine over the input again */ + while (*p != 0) + { + enum CORE_STATE fstate = core_state_transition(&p, track_counts); + final_counts[fstate]++; +#if CORE_DEBUG + ee_printf("%d,", fstate); + } + ee_printf("\n"); +#else + } +#endif + p = memblock; + while (p < (memblock + blksize)) + { /* undo corruption is seed1 and seed2 are equal */ + if (*p != ',') + *p ^= (ee_u8)seed2; + p += step; + } + /* end timing */ + for (i = 0; i < NUM_CORE_STATES; i++) + { + crc = crcu32(final_counts[i], crc); + crc = crcu32(track_counts[i], crc); + } + return crc; +} + +/* Default initialization patterns */ +static ee_u8 *intpat[4] + = { (ee_u8 *)"5012", (ee_u8 *)"1234", (ee_u8 *)"-874", (ee_u8 *)"+122" }; +static ee_u8 *floatpat[4] = { (ee_u8 *)"35.54400", + (ee_u8 *)".1234500", + (ee_u8 *)"-110.700", + (ee_u8 *)"+0.64400" }; +static ee_u8 *scipat[4] = { (ee_u8 *)"5.500e+3", + (ee_u8 *)"-.123e-2", + (ee_u8 *)"-87e+832", + (ee_u8 *)"+0.6e-12" }; +static ee_u8 *errpat[4] = { (ee_u8 *)"T0.3e-1F", + (ee_u8 *)"-T.T++Tq", + (ee_u8 *)"1T3.4e4z", + (ee_u8 *)"34.0e-T^" }; + +/* Function: core_init_state + Initialize the input data for the state machine. + + Populate the input with several predetermined strings, interspersed. + Actual patterns chosen depend on the seed parameter. + + Note: + The seed parameter MUST be supplied from a source that cannot be + determined at compile time +*/ +void +core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p) +{ + ee_u32 total = 0, next = 0, i; + ee_u8 *buf = 0; +#if CORE_DEBUG + ee_u8 *start = p; + ee_printf("State: %d,%d\n", size, seed); +#endif + size--; + next = 0; + while ((total + next + 1) < size) + { + if (next > 0) + { + for (i = 0; i < next; i++) + *(p + total + i) = buf[i]; + *(p + total + i) = ','; + total += next + 1; + } + seed++; + switch (seed & 0x7) + { + case 0: /* int */ + case 1: /* int */ + case 2: /* int */ + buf = intpat[(seed >> 3) & 0x3]; + next = 4; + break; + case 3: /* float */ + case 4: /* float */ + buf = floatpat[(seed >> 3) & 0x3]; + next = 8; + break; + case 5: /* scientific */ + case 6: /* scientific */ + buf = scipat[(seed >> 3) & 0x3]; + next = 8; + break; + case 7: /* invalid */ + buf = errpat[(seed >> 3) & 0x3]; + next = 8; + break; + default: /* Never happen, just to make some compilers happy */ + break; + } + } + size++; + while (total < size) + { /* fill the rest with 0 */ + *(p + total) = 0; + total++; + } +#if CORE_DEBUG + ee_printf("State Input: %s\n", start); +#endif +} + +static ee_u8 +ee_isdigit(ee_u8 c) +{ + ee_u8 retval; + retval = ((c >= '0') & (c <= '9')) ? 1 : 0; + return retval; +} + +/* Function: core_state_transition + Actual state machine. + + The state machine will continue scanning until either: + 1 - an invalid input is detcted. + 2 - a valid number has been detected. + + The input pointer is updated to point to the end of the token, and the + end state is returned (either specific format determined or invalid). +*/ + +enum CORE_STATE +core_state_transition(ee_u8 **instr, ee_u32 *transition_count) +{ + ee_u8 * str = *instr; + ee_u8 NEXT_SYMBOL; + enum CORE_STATE state = CORE_START; + for (; *str && state != CORE_INVALID; str++) + { + NEXT_SYMBOL = *str; + if (NEXT_SYMBOL == ',') /* end of this input */ + { + str++; + break; + } + switch (state) + { + case CORE_START: + if (ee_isdigit(NEXT_SYMBOL)) + { + state = CORE_INT; + } + else if (NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-') + { + state = CORE_S1; + } + else if (NEXT_SYMBOL == '.') + { + state = CORE_FLOAT; + } + else + { + state = CORE_INVALID; + transition_count[CORE_INVALID]++; + } + transition_count[CORE_START]++; + break; + case CORE_S1: + if (ee_isdigit(NEXT_SYMBOL)) + { + state = CORE_INT; + transition_count[CORE_S1]++; + } + else if (NEXT_SYMBOL == '.') + { + state = CORE_FLOAT; + transition_count[CORE_S1]++; + } + else + { + state = CORE_INVALID; + transition_count[CORE_S1]++; + } + break; + case CORE_INT: + if (NEXT_SYMBOL == '.') + { + state = CORE_FLOAT; + transition_count[CORE_INT]++; + } + else if (!ee_isdigit(NEXT_SYMBOL)) + { + state = CORE_INVALID; + transition_count[CORE_INT]++; + } + break; + case CORE_FLOAT: + if (NEXT_SYMBOL == 'E' || NEXT_SYMBOL == 'e') + { + state = CORE_S2; + transition_count[CORE_FLOAT]++; + } + else if (!ee_isdigit(NEXT_SYMBOL)) + { + state = CORE_INVALID; + transition_count[CORE_FLOAT]++; + } + break; + case CORE_S2: + if (NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-') + { + state = CORE_EXPONENT; + transition_count[CORE_S2]++; + } + else + { + state = CORE_INVALID; + transition_count[CORE_S2]++; + } + break; + case CORE_EXPONENT: + if (ee_isdigit(NEXT_SYMBOL)) + { + state = CORE_SCIENTIFIC; + transition_count[CORE_EXPONENT]++; + } + else + { + state = CORE_INVALID; + transition_count[CORE_EXPONENT]++; + } + break; + case CORE_SCIENTIFIC: + if (!ee_isdigit(NEXT_SYMBOL)) + { + state = CORE_INVALID; + transition_count[CORE_INVALID]++; + } + break; + default: + break; + } + } + *instr = str; + return state; +} diff --git a/sdk/software/examples/coremark/core_util.c b/sdk/software/examples/coremark/core_util.c new file mode 100644 index 0000000..67c5d77 --- /dev/null +++ b/sdk/software/examples/coremark/core_util.c @@ -0,0 +1,249 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +#include "coremark.h" +/* Function: get_seed + Get a values that cannot be determined at compile time. + + Since different embedded systems and compilers are used, 3 different + methods are provided: 1 - Using a volatile variable. This method is only + valid if the compiler is forced to generate code that reads the value of a + volatile variable from memory at run time. Please note, if using this method, + you would need to modify core_portme.c to generate training profile. 2 - + Command line arguments. This is the preferred method if command line + arguments are supported. 3 - System function. If none of the first 2 methods + is available on the platform, a system function which is not a stub can be + used. + + e.g. read the value on GPIO pins connected to switches, or invoke + special simulator functions. +*/ +#if (SEED_METHOD == SEED_VOLATILE) +extern volatile ee_s32 seed1_volatile; +extern volatile ee_s32 seed2_volatile; +extern volatile ee_s32 seed3_volatile; +extern volatile ee_s32 seed4_volatile; +extern volatile ee_s32 seed5_volatile; +ee_s32 +get_seed_32(int i) +{ + ee_s32 retval; + switch (i) + { + case 1: + retval = seed1_volatile; + break; + case 2: + retval = seed2_volatile; + break; + case 3: + retval = seed3_volatile; + break; + case 4: + retval = seed4_volatile; + break; + case 5: + retval = seed5_volatile; + break; + default: + retval = 0; + break; + } + return retval; +} +#elif (SEED_METHOD == SEED_ARG) +ee_s32 +parseval(char *valstring) +{ + ee_s32 retval = 0; + ee_s32 neg = 1; + int hexmode = 0; + if (*valstring == '-') + { + neg = -1; + valstring++; + } + if ((valstring[0] == '0') && (valstring[1] == 'x')) + { + hexmode = 1; + valstring += 2; + } + /* first look for digits */ + if (hexmode) + { + while (((*valstring >= '0') && (*valstring <= '9')) + || ((*valstring >= 'a') && (*valstring <= 'f'))) + { + ee_s32 digit = *valstring - '0'; + if (digit > 9) + digit = 10 + *valstring - 'a'; + retval *= 16; + retval += digit; + valstring++; + } + } + else + { + while ((*valstring >= '0') && (*valstring <= '9')) + { + ee_s32 digit = *valstring - '0'; + retval *= 10; + retval += digit; + valstring++; + } + } + /* now add qualifiers */ + if (*valstring == 'K') + retval *= 1024; + if (*valstring == 'M') + retval *= 1024 * 1024; + + retval *= neg; + return retval; +} + +ee_s32 +get_seed_args(int i, int argc, char *argv[]) +{ + if (argc > i) + return parseval(argv[i]); + return 0; +} + +#elif (SEED_METHOD == SEED_FUNC) +/* If using OS based function, you must define and implement the functions below + * in core_portme.h and core_portme.c ! */ +ee_s32 +get_seed_32(int i) +{ + ee_s32 retval; + switch (i) + { + case 1: + retval = portme_sys1(); + break; + case 2: + retval = portme_sys2(); + break; + case 3: + retval = portme_sys3(); + break; + case 4: + retval = portme_sys4(); + break; + case 5: + retval = portme_sys5(); + break; + default: + retval = 0; + break; + } + return retval; +} +#endif + +/* Function: crc* + Service functions to calculate 16b CRC code. + +*/ +ee_u16 +crcu8(ee_u8 data, ee_u16 crc) +{ + ee_u8 i = 0, x16 = 0, carry = 0; + + for (i = 0; i < 8; i++) + { + x16 = (ee_u8)((data & 1) ^ ((ee_u8)crc & 1)); + data >>= 1; + + if (x16 == 1) + { + crc ^= 0x4002; + carry = 1; + } + else + carry = 0; + crc >>= 1; + if (carry) + crc |= 0x8000; + else + crc &= 0x7fff; + } + return crc; +} +ee_u16 +crcu16(ee_u16 newval, ee_u16 crc) +{ + crc = crcu8((ee_u8)(newval), crc); + crc = crcu8((ee_u8)((newval) >> 8), crc); + return crc; +} +ee_u16 +crcu32(ee_u32 newval, ee_u16 crc) +{ + crc = crc16((ee_s16)newval, crc); + crc = crc16((ee_s16)(newval >> 16), crc); + return crc; +} +ee_u16 +crc16(ee_s16 newval, ee_u16 crc) +{ + return crcu16((ee_u16)newval, crc); +} + +ee_u8 +check_data_types() +{ + ee_u8 retval = 0; + if (sizeof(ee_u8) != 1) + { + ee_printf("ERROR: ee_u8 is not an 8b datatype!\n"); + retval++; + } + if (sizeof(ee_u16) != 2) + { + ee_printf("ERROR: ee_u16 is not a 16b datatype!\n"); + retval++; + } + if (sizeof(ee_s16) != 2) + { + ee_printf("ERROR: ee_s16 is not a 16b datatype!\n"); + retval++; + } + if (sizeof(ee_s32) != 4) + { + ee_printf("ERROR: ee_s32 is not a 32b datatype!\n"); + retval++; + } + if (sizeof(ee_u32) != 4) + { + ee_printf("ERROR: ee_u32 is not a 32b datatype!\n"); + retval++; + } + if (sizeof(ee_ptr_int) != sizeof(int *)) + { + ee_printf( + "ERROR: ee_ptr_int is not a datatype that holds an int pointer!\n"); + retval++; + } + if (retval > 0) + { + ee_printf("ERROR: Please modify the datatypes in core_portme.h!\n"); + } + return retval; +} diff --git a/sdk/software/examples/coremark/coremark.h b/sdk/software/examples/coremark/coremark.h new file mode 100644 index 0000000..a40511e --- /dev/null +++ b/sdk/software/examples/coremark/coremark.h @@ -0,0 +1,173 @@ +/* +Author : Shay Gal-On, EEMBC + +This file is part of EEMBC(R) and CoreMark(TM), which are Copyright (C) 2009 +All rights reserved. + +EEMBC CoreMark Software is a product of EEMBC and is provided under the terms of the +CoreMark License that is distributed with the official EEMBC COREMARK Software release. +If you received this EEMBC CoreMark Software without the accompanying CoreMark License, +you must discontinue use and download the official release from www.coremark.org. + +Also, if you are publicly displaying scores generated from the EEMBC CoreMark software, +make sure that you are in compliance with Run and Reporting rules specified in the accompanying readme.txt file. + +EEMBC +4354 Town Center Blvd. Suite 114-200 +El Dorado Hills, CA, 95762 +*/ +/* Topic: Description + This file contains declarations of the various benchmark functions. +*/ + +/* Configuration: TOTAL_DATA_SIZE + Define total size for data algorithms will operate on +*/ +#ifndef TOTAL_DATA_SIZE +#define TOTAL_DATA_SIZE 2*1000 +#endif + +#define SEED_ARG 0 +#define SEED_FUNC 1 +#define SEED_VOLATILE 2 + +#define MEM_STATIC 0 +#define MEM_MALLOC 1 +#define MEM_STACK 2 + +//void uart_initial(); +#include "core_portme.h" + +#if HAS_STDIO +#include +#endif + +#define ee_printf printf +/* Actual benchmark execution in iterate */ +void *iterate(void *pres); + +/* Typedef: secs_ret + For machines that have floating point support, get number of seconds as a double. + Otherwise an unsigned int. +*/ +#if HAS_FLOAT +typedef double secs_ret; +#else +typedef ee_u32 secs_ret; +#endif + +#if MAIN_HAS_NORETURN +#define MAIN_RETURN_VAL +#define MAIN_RETURN_TYPE void +#else +#define MAIN_RETURN_VAL 0 +#define MAIN_RETURN_TYPE int +#endif + +void start_time(void); +void stop_time(void); +CORE_TICKS get_time(void); +secs_ret time_in_secs(CORE_TICKS ticks); + +/* Misc useful functions */ +ee_u16 crcu8(ee_u8 data, ee_u16 crc); +ee_u16 crc16(ee_s16 newval, ee_u16 crc); +ee_u16 crcu16(ee_u16 newval, ee_u16 crc); +ee_u16 crcu32(ee_u32 newval, ee_u16 crc); +ee_u8 check_data_types(); +void *portable_malloc(ee_size_t size); +void portable_free(void *p); +ee_s32 parseval(char *valstring); + +/* Algorithm IDS */ +#define ID_LIST (1<<0) +#define ID_MATRIX (1<<1) +#define ID_STATE (1<<2) +#define ALL_ALGORITHMS_MASK (ID_LIST|ID_MATRIX|ID_STATE) +#define NUM_ALGORITHMS 3 + +/* list data structures */ +typedef struct list_data_s { + ee_s16 data16; + ee_s16 idx; +} list_data; + +typedef struct list_head_s { + struct list_head_s *next; + struct list_data_s *info; +} list_head; + + +/*matrix benchmark related stuff */ +#define MATDAT_INT 1 +#if MATDAT_INT +typedef ee_s16 MATDAT; +typedef ee_s32 MATRES; +#else +typedef ee_f16 MATDAT; +typedef ee_f32 MATRES; +#endif + +typedef struct MAT_PARAMS_S { + int N; + MATDAT *A; + MATDAT *B; + MATRES *C; +} mat_params; + +/* state machine related stuff */ +/* List of all the possible states for the FSM */ +typedef enum CORE_STATE { + CORE_START=0, + CORE_INVALID, + CORE_S1, + CORE_S2, + CORE_INT, + CORE_FLOAT, + CORE_EXPONENT, + CORE_SCIENTIFIC, + NUM_CORE_STATES +} core_state_e ; + + +/* Helper structure to hold results */ +typedef struct RESULTS_S { + /* inputs */ + ee_s16 seed1; /* Initializing seed */ + ee_s16 seed2; /* Initializing seed */ + ee_s16 seed3; /* Initializing seed */ + void *memblock[4]; /* Pointer to safe memory location */ + ee_u32 size; /* Size of the data */ + ee_u32 iterations; /* Number of iterations to execute */ + ee_u32 execs; /* Bitmask of operations to execute */ + struct list_head_s *list; + mat_params mat; + /* outputs */ + ee_u16 crc; + ee_u16 crclist; + ee_u16 crcmatrix; + ee_u16 crcstate; + ee_s16 err; + /* ultithread specific */ + core_portable port; +} core_results; + +/* Multicore execution handling */ +#if (MULTITHREAD>1) +ee_u8 core_start_parallel(core_results *res); +ee_u8 core_stop_parallel(core_results *res); +#endif + +/* list benchmark functions */ +list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed); +ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx); + +/* state benchmark functions */ +void core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p); +ee_u16 core_bench_state(ee_u32 blksize, ee_u8 *memblock, + ee_s16 seed1, ee_s16 seed2, ee_s16 step, ee_u16 crc); + +/* matrix benchmark functions */ +ee_u32 core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p); +ee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc); + diff --git a/sdk/software/examples/dhrystone/Makefile b/sdk/software/examples/dhrystone/Makefile new file mode 100644 index 0000000..ccc9685 --- /dev/null +++ b/sdk/software/examples/dhrystone/Makefile @@ -0,0 +1,16 @@ +TARGET = dhrystone + +CFLAGS += -O3 -g -G8 -DTIME -DNumber_Of_Runs=1 + +#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真 +CFLAGS += -DSIMU=0 + +C_SRCS := $(wildcard ./*.c ) + +INCLUDES := -I. + +OBJDIR = obj +COMMON_DIR = ../../bsp +GCC_DIR=../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../toolchains/picolibc +include ../../bsp/common.mk diff --git a/sdk/software/examples/dhrystone/README.md b/sdk/software/examples/dhrystone/README.md new file mode 100644 index 0000000..52fc469 --- /dev/null +++ b/sdk/software/examples/dhrystone/README.md @@ -0,0 +1,10 @@ +Multiple versions of Reinhold P. Weicker's **Dhrystone** benchmark + +Sources downloaded and extracted from old Usenet postings and from +sites linked from http://en.wikipedia.org/wiki/Dhrystone + +The `original-sources` directory contains the raw sources. Each +subdirectory `v1`, `v2.0`, `v2.1`, `v2.2` contains an extracted +version; see the `_README` file in each directory. + +version in this dir is v2.1 diff --git a/sdk/software/examples/dhrystone/dhry.h b/sdk/software/examples/dhrystone/dhry.h new file mode 100644 index 0000000..c1b7410 --- /dev/null +++ b/sdk/software/examples/dhrystone/dhry.h @@ -0,0 +1,420 @@ +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry.h (part 1 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * Siemens AG, AUT E 51 + * Postfach 3220 + * 8520 Erlangen + * Germany (West) + * Phone: [+49]-9131-7-20330 + * (8-17 Central European Time) + * Usenet: ..!mcsun!unido!estevax!weicker + * + * Original Version (in Ada) published in + * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), + * pp. 1013 - 1030, together with the statistics + * on which the distribution of statements etc. is based. + * + * In this C version, the following C library functions are used: + * - strcpy, strcmp (inside the measurement loop) + * - printf, scanf (outside the measurement loop) + * In addition, Berkeley UNIX system calls "times ()" or "time ()" + * are used for execution time measurement. For measurements + * on other systems, these calls have to be changed. + * + * Collection of Results: + * Reinhold Weicker (address see above) and + * + * Rick Richardson + * PC Research. Inc. + * 94 Apple Orchard Drive + * Tinton Falls, NJ 07724 + * Phone: (201) 389-8963 (9-17 EST) + * Usenet: ...!uunet!pcrat!rick + * + * Please send results to Rick Richardson and/or Reinhold Weicker. + * Complete information should be given on hardware and software used. + * Hardware information includes: Machine type, CPU, type and size + * of caches; for microprocessors: clock frequency, memory speed + * (number of wait states). + * Software information includes: Compiler (and runtime library) + * manufacturer and version, compilation switches, OS version. + * The Operating System version may give an indication about the + * compiler; Dhrystone itself performs no OS calls in the measurement loop. + * + * The complete output generated by the program should be mailed + * such that at least some checks for correctness can be made. + * + *************************************************************************** + * + * History: This version C/2.1 has been made for two reasons: + * + * 1) There is an obvious need for a common C version of + * Dhrystone, since C is at present the most popular system + * programming language for the class of processors + * (microcomputers, minicomputers) where Dhrystone is used most. + * There should be, as far as possible, only one C version of + * Dhrystone such that results can be compared without + * restrictions. In the past, the C versions distributed + * by Rick Richardson (Version 1.1) and by Reinhold Weicker + * had small (though not significant) differences. + * + * 2) As far as it is possible without changes to the Dhrystone + * statistics, optimizing compilers should be prevented from + * removing significant statements. + * + * This C version has been developed in cooperation with + * Rick Richardson (Tinton Falls, NJ), it incorporates many + * ideas from the "Version 1.1" distributed previously by + * him over the UNIX network Usenet. + * I also thank Chaim Benedelac (National Semiconductor), + * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), + * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) + * for their help with comments on earlier versions of the + * benchmark. + * + * Changes: In the initialization part, this version follows mostly + * Rick Richardson's version distributed via Usenet, not the + * version distributed earlier via floppy disk by Reinhold Weicker. + * As a concession to older compilers, names have been made + * unique within the first 8 characters. + * Inside the measurement loop, this version follows the + * version previously distributed by Reinhold Weicker. + * + * At several places in the benchmark, code has been added, + * but within the measurement loop only in branches that + * are not executed. The intention is that optimizing compilers + * should be prevented from moving code out of the measurement + * loop, or from removing code altogether. Since the statements + * that are executed within the measurement loop have NOT been + * changed, the numbers defining the "Dhrystone distribution" + * (distribution of statements, operand types and locality) + * still hold. Except for sophisticated optimizing compilers, + * execution times for this version should be the same as + * for previous versions. + * + * Since it has proven difficult to subtract the time for the + * measurement loop overhead in a correct way, the loop check + * has been made a part of the benchmark. This does have + * an impact - though a very minor one - on the distribution + * statistics which have been updated for this version. + * + * All changes within the measurement loop are described + * and discussed in the companion paper "Rationale for + * Dhrystone version 2". + * + * Because of the self-imposed limitation that the order and + * distribution of the executed statements should not be + * changed, there are still cases where optimizing compilers + * may not generate code for some statements. To a certain + * degree, this is unavoidable for small synthetic benchmarks. + * Users of the benchmark are advised to check code listings + * whether code is generated for all statements of Dhrystone. + * + * Version 2.1 is identical to version 2.0 distributed via + * the UNIX network Usenet in March 1988 except that it corrects + * some minor deficiencies that were found by users of version 2.0. + * The only change within the measurement loop is that a + * non-executed "else" part was added to the "if" statement in + * Func_3, and a non-executed "else" part removed from Proc_3. + * + *************************************************************************** + * + * Defines: The following "Defines" are possible: + * -DREG=register (default: Not defined) + * As an approximation to what an average C programmer + * might do, the "register" storage class is applied + * (if enabled by -DREG=register) + * - for local variables, if they are used (dynamically) + * five or more times + * - for parameters if they are used (dynamically) + * six or more times + * Note that an optimal "register" strategy is + * compiler-dependent, and that "register" declarations + * do not necessarily lead to faster execution. + * -DNOSTRUCTASSIGN (default: Not defined) + * Define if the C compiler does not support + * assignment of structures. + * -DNOENUMS (default: Not defined) + * Define if the C compiler does not support + * enumeration types. + * -DTIMES (default) + * -DTIME + * The "times" function of UNIX (returning process times) + * or the "time" function (returning wallclock time) + * is used for measurement. + * For single user machines, "time ()" is adequate. For + * multi-user machines where you cannot get single-user + * access, use the "times ()" function. If you have + * neither, use a stopwatch in the dead of night. + * "printf"s are provided marking the points "Start Timer" + * and "Stop Timer". DO NOT use the UNIX "time(1)" + * command, as this will measure the total time to + * run this program, which will (erroneously) include + * the time to allocate storage (malloc) and to perform + * the initialization. + * -DHZ=nnn + * In Berkeley UNIX, the function "times" returns process + * time in 1/HZ seconds, with HZ = 60 for most systems. + * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY + * A VALUE. + * + *************************************************************************** + * + * Compilation model and measurement (IMPORTANT): + * + * This C version of Dhrystone consists of three files: + * - dhry.h (this file, containing global definitions and comments) + * - dhry_1.c (containing the code corresponding to Ada package Pack_1) + * - dhry_2.c (containing the code corresponding to Ada package Pack_2) + * + * The following "ground rules" apply for measurements: + * - Separate compilation + * - No procedure merging + * - Otherwise, compiler optimizations are allowed but should be indicated + * - Default results are those without register declarations + * See the companion paper "Rationale for Dhrystone Version 2" for a more + * detailed discussion of these ground rules. + * + * For 16-Bit processors (e.g. 80186, 80286), times for all compilation + * models ("small", "medium", "large" etc.) should be given if possible, + * together with a definition of these models for the compiler system used. + * + ************************************************************************** + * + * Dhrystone (C version) statistics: + * + * [Comment from the first distribution, updated for version 2. + * Note that because of language differences, the numbers are slightly + * different from the Ada version.] + * + * The following program contains statements of a high level programming + * language (here: C) in a distribution considered representative: + * + * assignments 52 (51.0 %) + * control statements 33 (32.4 %) + * procedure, function calls 17 (16.7 %) + * + * 103 statements are dynamically executed. The program is balanced with + * respect to the three aspects: + * + * - statement type + * - operand type + * - operand locality + * operand global, local, parameter, or constant. + * + * The combination of these three aspects is balanced only approximately. + * + * 1. Statement Type: + * ----------------- number + * + * V1 = V2 9 + * (incl. V1 = F(..) + * V = Constant 12 + * Assignment, 7 + * with array element + * Assignment, 6 + * with record component + * -- + * 34 34 + * + * X = Y +|-|"&&"|"|" Z 5 + * X = Y +|-|"==" Constant 6 + * X = X +|- 1 3 + * X = Y *|/ Z 2 + * X = Expression, 1 + * two operators + * X = Expression, 1 + * three operators + * -- + * 18 18 + * + * if .... 14 + * with "else" 7 + * without "else" 7 + * executed 3 + * not executed 4 + * for ... 7 | counted every time + * while ... 4 | the loop condition + * do ... while 1 | is evaluated + * switch ... 1 + * break 1 + * declaration with 1 + * initialization + * -- + * 34 34 + * + * P (...) procedure call 11 + * user procedure 10 + * library procedure 1 + * X = F (...) + * function call 6 + * user function 5 + * library function 1 + * -- + * 17 17 + * --- + * 103 + * + * The average number of parameters in procedure or function calls + * is 1.82 (not counting the function values as implicit parameters). + * + * + * 2. Operators + * ------------ + * number approximate + * percentage + * + * Arithmetic 32 50.8 + * + * + 21 33.3 + * - 7 11.1 + * * 3 4.8 + * / (int div) 1 1.6 + * + * Comparison 27 42.8 + * + * == 9 14.3 + * /= 4 6.3 + * > 1 1.6 + * < 3 4.8 + * >= 1 1.6 + * <= 9 14.3 + * + * Logic 4 6.3 + * + * && (AND-THEN) 1 1.6 + * | (OR) 1 1.6 + * ! (NOT) 2 3.2 + * + * -- ----- + * 63 100.1 + * + * + * 3. Operand Type (counted once per operand reference): + * --------------- + * number approximate + * percentage + * + * Integer 175 72.3 % + * Character 45 18.6 % + * Pointer 12 5.0 % + * String30 6 2.5 % + * Array 2 0.8 % + * Record 2 0.8 % + * --- ------- + * 242 100.0 % + * + * When there is an access path leading to the final operand (e.g. a record + * component), only the final data type on the access path is counted. + * + * + * 4. Operand Locality: + * ------------------- + * number approximate + * percentage + * + * local variable 114 47.1 % + * global variable 22 9.1 % + * parameter 45 18.6 % + * value 23 9.5 % + * reference 22 9.1 % + * function result 6 2.5 % + * constant 55 22.7 % + * --- ------- + * 242 100.0 % + * + * + * The program does not compute anything meaningful, but it is syntactically + * and semantically correct. All variables have a value assigned to them + * before they are used as a source operand. + * + * There has been no explicit effort to account for the effects of a + * cache, or to balance the use of long or short displacements for code or + * data. + * + *************************************************************************** + */ + +/* Compiler and system dependent definitions: */ + +#ifndef TIME +#define TIMES +#endif + /* Use times(2) time function unless */ + /* explicitly defined otherwise */ + + +#define Mic_secs_Per_Second 1000000 + /* Berkeley UNIX C returns process times in seconds/HZ */ + +#ifdef NOSTRUCTASSIGN +#define structassign(d, s) memcpy(&(d), &(s), sizeof(d)) +#else +#define structassign(d, s) d = s +#endif + +#ifdef NOENUM +#define Ident_1 0 +#define Ident_2 1 +#define Ident_3 2 +#define Ident_4 3 +#define Ident_5 4 + typedef int Enumeration; +#else + typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} + Enumeration; +#endif + /* for boolean and enumeration types in Ada, Pascal */ + +/* General definitions: */ + +#include +#include +#include "confreg_time.h" + /* for strcpy, strcmp */ + +#define Null 0 + /* Value of a Null pointer */ +#define true 1 +#define false 0 + +typedef int One_Thirty; +typedef int One_Fifty; +typedef char Capital_Letter; +typedef int Boolean; +typedef char Str_30 [31]; +typedef int Arr_1_Dim [50]; +typedef int Arr_2_Dim [50] [50]; + +typedef struct record + { + struct record *Ptr_Comp; + Enumeration Discr; + union { + struct { + Enumeration Enum_Comp; + int Int_Comp; + char Str_Comp [31]; + } var_1; + struct { + Enumeration E_Comp_2; + char Str_2_Comp [31]; + } var_2; + struct { + char Ch_1_Comp; + char Ch_2_Comp; + } var_3; + } variant; + } Rec_Type, *Rec_Pointer; + + diff --git a/sdk/software/examples/dhrystone/dhry_1.c b/sdk/software/examples/dhrystone/dhry_1.c new file mode 100644 index 0000000..a69c15a --- /dev/null +++ b/sdk/software/examples/dhrystone/dhry_1.c @@ -0,0 +1,392 @@ +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry_1.c (part 2 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * + **************************************************************************** + */ + +#include "dhry.h" + +/* Global Variables: */ + +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbfe001e0; //UART16550的虚地址 +unsigned long CONFREG_UART_BASE = 0xbfafff10; //CONFREG模拟UART的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbfafe000; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 100000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +Rec_Pointer Ptr_Glob, + Next_Ptr_Glob; +int Int_Glob; +Boolean Bool_Glob; +char Ch_1_Glob, + Ch_2_Glob; +int Arr_1_Glob [50]; +int Arr_2_Glob [50] [50]; + +Enumeration Func_1 (); + + /* forward declaration necessary since Enumeration may not simply be int */ + +#ifndef REG + Boolean Reg = false; +#define REG + /* REG becomes defined as empty */ + /* i.e. no register variables */ +#else + Boolean Reg = true; +#endif + +/* variables for time measurement: */ + + /* see library function "times" */ +#define Too_Small_Time 120 + /* Measurements should last at least about 2 seconds */ + +long Begin_Time, + End_Time, + User_Time; + +float Microseconds, + Dhrystones_Per_Second; + +Rec_Type Next_Rec_Glob; +Rec_Type Rec_Glob; +/* end of variables for time measurement */ + +void* malloc(size_t); + +int main (int argc, char** argv) +/*****/ + + /* main program, corresponds to procedures */ + /* Main and Proc_0 in the Ada version */ +{ + One_Fifty Int_1_Loc; + REG One_Fifty Int_2_Loc; + One_Fifty Int_3_Loc; + REG char Ch_Index; + Enumeration Enum_Loc; + Str_30 Str_1_Loc; + Str_30 Str_2_Loc; + REG int Run_Index; + + /* Initializations */ + printf ("\n"); + printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); + printf ("\n"); + +// Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); +// Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); + Next_Ptr_Glob = (Rec_Pointer)&Next_Rec_Glob; + Ptr_Glob = (Rec_Pointer)&Rec_Glob; + + Ptr_Glob->Ptr_Comp = Next_Ptr_Glob; + Ptr_Glob->Discr = Ident_1; + Ptr_Glob->variant.var_1.Enum_Comp = Ident_3; + Ptr_Glob->variant.var_1.Int_Comp = 40; + strcpy (Ptr_Glob->variant.var_1.Str_Comp, + "DHRYSTONE PROGRAM, SOME STRING"); + strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING"); + + Arr_2_Glob [8][7] = 10; + /* Was missing in published program. Without this statement, */ + /* Arr_2_Glob [8][7] would have an undefined value. */ + /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ + /* overflow may occur for this array element. */ + + printf("\n"); + printf("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); + printf("\n"); + if (Reg) + { + printf ("Program compiled with 'register' attribute\n"); + printf ("\n"); + } + else + { + printf ("Program compiled without 'register' attribute\n"); + printf ("\n"); + } + + printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs); + + /***************/ + /* Start timer */ + /***************/ + + Begin_Time = get_ns(); + + for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index) + { + + Proc_5(); + Proc_4(); + /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */ + Int_1_Loc = 2; + Int_2_Loc = 3; + strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING"); + Enum_Loc = Ident_2; + Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc); + /* Bool_Glob == 1 */ + while (Int_1_Loc < Int_2_Loc) /* loop body executed once */ + { + Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc; + /* Int_3_Loc == 7 */ + Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc); + /* Int_3_Loc == 7 */ + Int_1_Loc += 1; + } /* while */ + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc); + /* Int_Glob == 5 */ + Proc_1 (Ptr_Glob); + for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index) + /* loop body executed twice */ + { + if (Enum_Loc == Func_1 (Ch_Index, 'C')) + /* then, not executed */ + { + Proc_6 (Ident_1, &Enum_Loc); + strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING"); + Int_2_Loc = Run_Index; + Int_Glob = Run_Index; + } + } + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Int_2_Loc = Int_2_Loc * Int_1_Loc; + Int_1_Loc = Int_2_Loc / Int_3_Loc; + Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; + /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */ + Proc_2 (&Int_1_Loc); + /* Int_1_Loc == 5 */ + + } /* loop "for Run_Index" */ + + /**************/ + /* Stop timer */ + /**************/ + + End_Time = get_ns(); + + printf ("Execution ends\n"); + printf ("\n"); + printf ("Final values of the variables used in the benchmark:\n"); + printf ("\n"); + printf ("Int_Glob: %d\n", Int_Glob); + printf (" should be: %d\n", 5); + printf ("Bool_Glob: %d\n", Bool_Glob); + printf (" should be: %d\n", 1); + printf ("Ch_1_Glob: %c\n", Ch_1_Glob); + printf (" should be: %c\n", 'A'); + printf ("Ch_2_Glob: %c\n", Ch_2_Glob); + printf (" should be: %c\n", 'B'); + printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]); + printf (" should be: %d\n", 7); + printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); + printf (" should be: %d\n", Number_Of_Runs + 10); + printf ("Ptr_Glob->\n"); + printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); + printf (" should be: (implementation-dependent)\n"); + printf (" Discr: %d\n", Ptr_Glob->Discr); + printf (" should be: %d\n", 0); + printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp); + printf (" should be: %d\n", 2); + printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); + printf (" should be: %d\n", 17); + printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); + printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + printf ("Next_Ptr_Glob->\n"); + printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); + printf (" should be: (implementation-dependent), same as above\n"); + printf (" Discr: %d\n", Next_Ptr_Glob->Discr); + printf (" should be: %d\n", 0); + printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp); + printf (" should be: %d\n", 1); + printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); + printf (" should be: %d\n", 18); + printf (" Str_Comp: %s\n", + Next_Ptr_Glob->variant.var_1.Str_Comp); + printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + printf ("Int_1_Loc: %d\n", Int_1_Loc); + printf (" should be: %d\n", 5); + printf ("Int_2_Loc: %d\n", Int_2_Loc); + printf (" should be: %d\n", 13); + printf ("Int_3_Loc: %d\n", Int_3_Loc); + printf (" should be: %d\n", 7); + printf ("Enum_Loc: %d\n", Enum_Loc); + printf (" should be: %d\n", 1); + printf ("Str_1_Loc: %s\n", Str_1_Loc); + printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n"); + printf ("Str_2_Loc: %s\n", Str_2_Loc); + printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n"); + printf ("\n"); + + int pass = 0; + if (Int_Glob == 5) ; else pass = 1; + if (Bool_Glob == 1) ; else pass = 1; + if (Ch_1_Glob == 'A') ; else pass = 1; + if (Ch_2_Glob == 'B') ; else pass = 1; + if (Arr_1_Glob[8] == 7) ; else pass = 1; + if ((Arr_2_Glob[8][7] == Number_Of_Runs + 10)) ; else pass = 1; + if ((int) Ptr_Glob->Ptr_Comp == (int) Next_Ptr_Glob->Ptr_Comp) ; else pass = 1; + if (Ptr_Glob->Discr == 0) ; else pass = 1; + if (Ptr_Glob->variant.var_1.Enum_Comp == 2) ; else pass = 1; + if (Ptr_Glob->variant.var_1.Int_Comp == 17) ; else pass = 1; + if (strcmp(Ptr_Glob->variant.var_1.Str_Comp, "DHRYSTONE PROGRAM, SOME STRING") == 0) ; else pass = 1; + if (Next_Ptr_Glob->Discr == 0) ; else pass = 1; + if (Next_Ptr_Glob->variant.var_1.Enum_Comp == 1) ; else pass = 1; + if (Next_Ptr_Glob->variant.var_1.Int_Comp == 18) ; else pass = 1; + if (strcmp(Next_Ptr_Glob->variant.var_1.Str_Comp, "DHRYSTONE PROGRAM, SOME STRING") == 0) ; else pass = 1; + if (Int_1_Loc == 5) ; else pass = 1; + if (Int_2_Loc == 13) ; else pass = 1; + if (Int_3_Loc == 7) ; else pass = 1; + if (Enum_Loc == 1) ; else pass = 1; + if (strcmp(Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING") == 0) ; else pass = 1; + if (strcmp(Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING") == 0) ; else pass = 1; + + User_Time = End_Time - Begin_Time; + printf ("Begin ns: %lu\n",Begin_Time); + printf ("End ns: %lu\n",End_Time); + printf ("Total ns: %lu\n",User_Time); + + + if (User_Time < Too_Small_Time) + { + printf ("Measured time too small to obtain meaningful results\n"); + printf ("Please increase number of runs\n"); + printf ("\n"); + } + else + { + Microseconds = (float) User_Time /(float) Number_Of_Runs/(float)1000000; + Dhrystones_Per_Second = ((float) 1000000000 * (float) Number_Of_Runs) + / (float) User_Time; + + printf ("Microseconds for one run through Dhrystone: "); + printf ("%10.1f \n", Microseconds); + printf ("Dhrystones per Second: "); + printf ("%10.0f \n", Dhrystones_Per_Second); + printf ("\n"); + } + return pass; +} + + +Proc_1 (Ptr_Val_Par) +/******************/ + +REG Rec_Pointer Ptr_Val_Par; + /* executed once */ +{ + REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; + /* == Ptr_Glob_Next */ + /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ + /* corresponds to "rename" in Ada, "with" in Pascal */ + + structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); + Ptr_Val_Par->variant.var_1.Int_Comp = 5; + Next_Record->variant.var_1.Int_Comp + = Ptr_Val_Par->variant.var_1.Int_Comp; + Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; + Proc_3 (&Next_Record->Ptr_Comp); + /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp + == Ptr_Glob->Ptr_Comp */ + if (Next_Record->Discr == Ident_1) + /* then, executed */ + { + Next_Record->variant.var_1.Int_Comp = 6; + Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, + &Next_Record->variant.var_1.Enum_Comp); + Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; + Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, + &Next_Record->variant.var_1.Int_Comp); + } + else /* not executed */ + structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); +} /* Proc_1 */ + + +Proc_2 (Int_Par_Ref) +/******************/ + /* executed once */ + /* *Int_Par_Ref == 1, becomes 4 */ + +One_Fifty *Int_Par_Ref; +{ + One_Fifty Int_Loc; + Enumeration Enum_Loc; + + Int_Loc = *Int_Par_Ref + 10; + do /* executed once */ + if (Ch_1_Glob == 'A') + /* then, executed */ + { + Int_Loc -= 1; + *Int_Par_Ref = Int_Loc - Int_Glob; + Enum_Loc = Ident_1; + } /* if */ + while (Enum_Loc != Ident_1); /* true */ +} /* Proc_2 */ + + +Proc_3 (Ptr_Ref_Par) +/******************/ + /* executed once */ + /* Ptr_Ref_Par becomes Ptr_Glob */ + +Rec_Pointer *Ptr_Ref_Par; + +{ + if (Ptr_Glob != Null) + /* then, executed */ + *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; + Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); +} /* Proc_3 */ + + +Proc_4 () /* without parameters */ +/*******/ + /* executed once */ +{ + Boolean Bool_Loc; + + Bool_Loc = Ch_1_Glob == 'A'; + Bool_Glob = Bool_Loc | Bool_Glob; + Ch_2_Glob = 'B'; +} /* Proc_4 */ + + +Proc_5 () /* without parameters */ +/*******/ + /* executed once */ +{ + Ch_1_Glob = 'A'; + Bool_Glob = false; +} /* Proc_5 */ + + + /* Procedure for the assignment of structures, */ + /* if the C compiler doesn't support this feature */ +#ifdef NOSTRUCTASSIGN +memcpy (d, s, l) +register char *d; +register char *s; +register int l; +{ + while (l--) *d++ = *s++; +} +#endif + + diff --git a/sdk/software/examples/dhrystone/dhry_2.c b/sdk/software/examples/dhrystone/dhry_2.c new file mode 100644 index 0000000..63a3d3e --- /dev/null +++ b/sdk/software/examples/dhrystone/dhry_2.c @@ -0,0 +1,192 @@ +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry_2.c (part 3 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * + **************************************************************************** + */ + +#include "dhry.h" + +#ifndef REG +#define REG + /* REG becomes defined as empty */ + /* i.e. no register variables */ +#endif + +extern int Int_Glob; +extern char Ch_1_Glob; + + +Proc_6 (Enum_Val_Par, Enum_Ref_Par) +/*********************************/ + /* executed once */ + /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */ + +Enumeration Enum_Val_Par; +Enumeration *Enum_Ref_Par; +{ + *Enum_Ref_Par = Enum_Val_Par; + if (! Func_3 (Enum_Val_Par)) + /* then, not executed */ + *Enum_Ref_Par = Ident_4; + switch (Enum_Val_Par) + { + case Ident_1: + *Enum_Ref_Par = Ident_1; + break; + case Ident_2: + if (Int_Glob > 100) + /* then */ + *Enum_Ref_Par = Ident_1; + else *Enum_Ref_Par = Ident_4; + break; + case Ident_3: /* executed */ + *Enum_Ref_Par = Ident_2; + break; + case Ident_4: break; + case Ident_5: + *Enum_Ref_Par = Ident_3; + break; + } /* switch */ +} /* Proc_6 */ + + +Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref) +/**********************************************/ + /* executed three times */ + /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */ + /* Int_Par_Ref becomes 7 */ + /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */ + /* Int_Par_Ref becomes 17 */ + /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */ + /* Int_Par_Ref becomes 18 */ +One_Fifty Int_1_Par_Val; +One_Fifty Int_2_Par_Val; +One_Fifty *Int_Par_Ref; +{ + One_Fifty Int_Loc; + + Int_Loc = Int_1_Par_Val + 2; + *Int_Par_Ref = Int_2_Par_Val + Int_Loc; +} /* Proc_7 */ + + +Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val) +/*********************************************************************/ + /* executed once */ + /* Int_Par_Val_1 == 3 */ + /* Int_Par_Val_2 == 7 */ +Arr_1_Dim Arr_1_Par_Ref; +Arr_2_Dim Arr_2_Par_Ref; +int Int_1_Par_Val; +int Int_2_Par_Val; +{ + REG One_Fifty Int_Index; + REG One_Fifty Int_Loc; + + Int_Loc = Int_1_Par_Val + 5; + Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val; + Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc]; + Arr_1_Par_Ref [Int_Loc+30] = Int_Loc; + for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index) + Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc; + Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1; + Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc]; + Int_Glob = 5; +} /* Proc_8 */ + + +Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val) +/*************************************************/ + /* executed three times */ + /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */ + /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */ + /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */ + +Capital_Letter Ch_1_Par_Val; +Capital_Letter Ch_2_Par_Val; +{ + Capital_Letter Ch_1_Loc; + Capital_Letter Ch_2_Loc; + + Ch_1_Loc = Ch_1_Par_Val; + Ch_2_Loc = Ch_1_Loc; + if (Ch_2_Loc != Ch_2_Par_Val) + /* then, executed */ + return (Ident_1); + else /* not executed */ + { + Ch_1_Glob = Ch_1_Loc; + return (Ident_2); + } +} /* Func_1 */ + + +Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref) +/*************************************************/ + /* executed once */ + /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */ + /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */ + +Str_30 Str_1_Par_Ref; +Str_30 Str_2_Par_Ref; +{ + REG One_Thirty Int_Loc; + Capital_Letter Ch_Loc; + + Int_Loc = 2; + while (Int_Loc <= 2) /* loop body executed once */ + if (Func_1 (Str_1_Par_Ref[Int_Loc], + Str_2_Par_Ref[Int_Loc+1]) == Ident_1) + /* then, executed */ + { + Ch_Loc = 'A'; + Int_Loc += 1; + } /* if, while */ + if (Ch_Loc >= 'W' && Ch_Loc < 'Z') + /* then, not executed */ + Int_Loc = 7; + if (Ch_Loc == 'R') + /* then, not executed */ + return (true); + else /* executed */ + { + if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0) + /* then, not executed */ + { + Int_Loc += 7; + Int_Glob = Int_Loc; + return (true); + } + else /* executed */ + return (false); + } /* if Ch_Loc */ +} /* Func_2 */ + + +Boolean Func_3 (Enum_Par_Val) +/***************************/ + /* executed once */ + /* Enum_Par_Val == Ident_3 */ +Enumeration Enum_Par_Val; +{ + Enumeration Enum_Loc; + + Enum_Loc = Enum_Par_Val; + if (Enum_Loc == Ident_3) + /* then, executed */ + return (true); + else /* not executed */ + return (false); +} /* Func_3 */ + diff --git a/sdk/software/examples/fireye/A0/A0.c b/sdk/software/examples/fireye/A0/A0.c new file mode 100644 index 0000000..09f6654 --- /dev/null +++ b/sdk/software/examples/fireye/A0/A0.c @@ -0,0 +1,35 @@ +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbfe001e0; //UART16550的虚地址 +unsigned long CONFREG_UART_BASE = 0xbfafff10; //CONFREG模拟UART的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbfafe000; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 100000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +int A0_n = 10000; +int A0_k = 20; +int data[20] = {207, 47, 368, 668, 655, 560, 8, 820, 11, 723, 396, 310, 268, 572, 45, 84, 229, 5, 92, 475}; +#define LOOP 1 + +#include + +#define KN 10000 + +int pos[KN] = {1}; + +int A0_max(int a, int b) { return a > b ? a : b; } + +int main() { + pos[0] = 0; + + int ans = 0; + for(int i = 0; i < A0_k; i++) { + int x = data[i]; + for(int j = x; j <= A0_n; j += x) pos[j] ^= 1; + int tmp = 0; + for(int j = 1; j <= A0_n; j++) tmp += pos[j]; + ans = A0_max(ans, tmp); + } + + printf("%d\n", ans); + return (ans == 3367) ? 0 : 1; +} diff --git a/sdk/software/examples/fireye/A0/Makefile b/sdk/software/examples/fireye/A0/Makefile new file mode 100644 index 0000000..5be849f --- /dev/null +++ b/sdk/software/examples/fireye/A0/Makefile @@ -0,0 +1,14 @@ +TARGET = fireye_A0 + +CFLAGS += -O3 -g + +#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真 +CFLAGS += -DSIMU=0 + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../../bsp +GCC_DIR=../../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../../toolchains/picolibc +include ../../../bsp/common.mk diff --git a/sdk/software/examples/fireye/B2/B2.c b/sdk/software/examples/fireye/B2/B2.c new file mode 100644 index 0000000..76e95f9 --- /dev/null +++ b/sdk/software/examples/fireye/B2/B2.c @@ -0,0 +1,61 @@ +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbfe001e0; //UART16550的虚地址 +unsigned long CONFREG_UART_BASE = 0xbfafff10; //CONFREG模拟UART的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbfafe000; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 100000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +int B2_n = 100; +int L[100] = {48, 47, 40, 40, 36, 31, 25, 25, 25, 24, 14, 13, 13, 10, 10, 10, 10, 10, 10, 8, 5, 5, 5, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 21, 21, 21, 21, 21, 23, 23, 23, 23, 26, 29, 29, 32, 32, 32, 32, 33, 33, 33, 33, 38, 38, 38, 38, 38, 38, 38, 39, 40, 40, 40, 42, 43, 48}; +int R[100] = {48, 48, 53, 53, 53, 54, 55, 57, 59, 66, 66, 66, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 98, 98, 98, 98, 98, 98, 98, 98, 98, 98, 96, 96, 96, 96, 96, 96, 96, 96, 95, 95, 95, 95, 94, 94, 93, 93, 93, 92, 92, 89, 89, 83, 80, 79, 78, 77, 77, 76, 76, 71, 71, 71, 71, 70, 70, 69, 69, 69, 68, 57, 51, 48}; + +#define LOOP 2 + +#include + +#define KN 100 + +int log_2(int x) { int ans = 0; while(x >>= 1) ans++; return ans; } +int B2_max(int a, int b) { return a > b ? a : b; } +int B2_min(int a, int b) { return a < b ? a : b; } + +int query(int d[][KN], int l, int r, int maxx) { + int t = log_2(r - l + 1); + if (maxx) return B2_max(d[t][l], d[t][r - (1 << t) + 1]); + return B2_min(d[t][l], d[t][r - (1 << t) + 1]); +} + +void init(int d[][KN], int a[], int len, int maxx) { + for (int i = 0; i < len; i++) d[0][i] = a[i]; + int t = 1; + for (int i = 1; t <= len; i++) { + for (int j = 0; j + t < len; j++) + if (maxx)d[i][j] = B2_max(d[i - 1][j], d[i - 1][j + t]); + else d[i][j] = B2_min(d[i - 1][j], d[i - 1][j + t]); + t <<= 1; + } +} + +int main() { + int dl[20][KN], dr[20][KN]; + + init(dl, L, B2_n, 1); + init(dr, R, B2_n, 0); + + int ans; + for (int var = 0; var < LOOP; var++) { + ans = 1; + for (int i = 1; i <= B2_n; i++) { + int l = ans, r = B2_n - i + 1; + while (l <= r) { + int mid = l + r >> 1; + if (query(dr, i - 1, i + mid - 2, 0) - query(dl, i - 1, i + mid - 2, 1) + 1 >= mid) { + ans = B2_max(ans, mid); l = mid + 1; + } else r = mid - 1; + } + } + } + + printf("%d\n", ans); + return (ans == 64) ? 0 : 1; +} diff --git a/sdk/software/examples/fireye/B2/Makefile b/sdk/software/examples/fireye/B2/Makefile new file mode 100644 index 0000000..7993184 --- /dev/null +++ b/sdk/software/examples/fireye/B2/Makefile @@ -0,0 +1,14 @@ +TARGET = fireye_B2 + +CFLAGS += -O3 -g + +#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真 +CFLAGS += -DSIMU=0 + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../../bsp +GCC_DIR=../../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../../toolchains/picolibc +include ../../../bsp/common.mk diff --git a/sdk/software/examples/fireye/C0/C0.c b/sdk/software/examples/fireye/C0/C0.c new file mode 100644 index 0000000..fd1c1c0 --- /dev/null +++ b/sdk/software/examples/fireye/C0/C0.c @@ -0,0 +1,74 @@ +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbfe001e0; //UART16550的虚地址 +unsigned long CONFREG_UART_BASE = 0xbfafff10; //CONFREG模拟UART的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbfafe000; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 100000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +int C0_n = 2, A = 50, C0_m = 2, B = 50; +char C0_data0[50][3] = {"of", "to", "in", "is", "it", "on", "be", "as", "at", "by", "he", "or", "an", "we", "up", "so", "if", "do", "no", "me", "my", "go", "er", "us", "am", "oh", "de", "mm", "et", "al", "la", "ah", "ha", "eh", "ad", "ya", "en", "re", "ye", "ex", "yo", "ma", "na", "ta", "ed", "sh", "ho", "um", "em", "un"}; +char C0_data1[50][3] = {"lo", "wo", "hi", "li", "ti", "ne", "ba", "pa", "si", "id", "mi", "mo", "fe", "el", "ox", "ab", "ar", "es", "ow", "pe", "bo", "oi", "op", "fa", "uh", "bi", "pi", "mu", "hm", "ay", "xi", "ki", "nu", "os", "aa", "ai", "ag", "ae", "ut", "aw", "oy", "ka", "ax", "od", "qi", "om", "jo", "za", "ef", "oe"}; + +#define LOOP 2 + +#include + +#define N 100 + +int mpN[6][6], mpM[6][6]; +int ans; + +struct Trie { + int ch[N][26]; + int tot; +} t[2] = {{{1}, 0}, {{1}, 0}}; + +void insert(struct Trie *t, char *s) { + int x = 0; + for (int i = 0; s[i] != '\0'; i++) { + if (!t->ch[x][s[i] - 'a']) + t->ch[x][s[i] - 'a'] = ++t->tot; + x = t->ch[x][s[i] - 'a']; + } +} + +void dfs(int x, int y) { + if (x == C0_n + 1) { + ++ans; + return; + } + for (int i = 0; i < 26; i++) { + int lastN = mpN[x - 1][y], lastM = mpM[x][y - 1]; + int nx = t[0].ch[lastN][i], ny = t[1].ch[lastM][i]; + if (!(nx && ny)) continue; + mpN[x][y] = nx; + mpM[x][y] = ny; + + nx = x, ny = y + 1; + if (ny > C0_m) ++nx, ny = 1; + dfs(nx, ny); + } +} + +void run() { + for (int i = 0; i < A; i++) { + insert(&t[0], C0_data0[i]); + } + for (int i = 0; i < B; i++) { + insert(&t[1], C0_data1[i]); + } + for (int i = 0; i < LOOP; i++) { + ans = 0; + dfs(1, 1); + } +} + +int main() { + t[0].ch[0][0] = 0; + t[1].ch[0][0] = 0; + + run(); + printf("%d\n", ans); + + return (ans == 62) ? 0 : 1; +} diff --git a/sdk/software/examples/fireye/C0/Makefile b/sdk/software/examples/fireye/C0/Makefile new file mode 100644 index 0000000..1cbbece --- /dev/null +++ b/sdk/software/examples/fireye/C0/Makefile @@ -0,0 +1,14 @@ +TARGET = fireye_C0 + +CFLAGS += -O3 -g + +#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真 +CFLAGS += -DSIMU=0 + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../../bsp +GCC_DIR=../../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../../toolchains/picolibc +include ../../../bsp/common.mk diff --git a/sdk/software/examples/fireye/D1/D1.c b/sdk/software/examples/fireye/D1/D1.c new file mode 100644 index 0000000..103393a --- /dev/null +++ b/sdk/software/examples/fireye/D1/D1.c @@ -0,0 +1,76 @@ +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbfe001e0; //UART16550的虚地址 +unsigned long CONFREG_UART_BASE = 0xbfafff10; //CONFREG模拟UART的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbfafe000; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 100000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +int x = 1000, y = 1000, D1_n = 492; +int D1_data0[492] = {595, 982, 328, 543, 646, 541, 484, 344, 862, 393, 378, 997, 699, 264, 128, 565, 582, 136, 768, 872, 967, 769, 979, 439, 892, 174, 779, 339, 520, 175, 931, 606, 146, 430, 661, 877, 950, 103, 563, 903, 681, 921, 924, 186, 20, 591, 953, 962, 253, 882, 141, 413, 845, 337, 465, 735, 659, 750, 821, 853, 100, 521, 16, 740, 580, 468, 562, 206, 476, 682, 68, 634, 126, 895, 947, 696, 246, 511, 38, 356, 319, 291, 519, 367, 164, 279, 330, 560, 137, 350, 564, 51, 332, 256, 657, 455, 459, 242, 537, 23, 526, 714, 10, 412, 630, 287, 410, 840, 987, 99, 98, 311, 235, 198, 588, 977, 282, 6, 841, 719, 598, 259, 207, 255, 720, 664, 766, 501, 671, 323, 937, 949, 392, 14, 739, 217, 228, 592, 957, 556, 406, 376, 94, 518, 669, 315, 223, 22, 483, 625, 780, 990, 748, 172, 33, 884, 341, 972, 426, 831, 529, 724, 787, 241, 628, 744, 461, 12, 763, 850, 973, 247, 403, 195, 790, 290, 856, 764, 331, 796, 69, 677, 754, 102, 355, 804, 738, 46, 920, 566, 795, 989, 803, 514, 742, 364, 125, 629, 889, 570, 776, 161, 24, 885, 601, 948, 822, 761, 805, 495, 326, 871, 911, 952, 651, 153, 858, 506, 913, 919, 799, 236, 737, 559, 249, 965, 729, 208, 202, 615, 833, 417, 340, 440, 834, 257, 741, 700, 122, 158, 452, 116, 215, 755, 851, 283, 276, 618, 36, 819, 133, 600, 645, 148, 583, 983, 115, 929, 313, 63, 405, 181, 534, 785, 767, 945, 351, 303, 797, 415, 930, 204, 400, 467, 727, 690, 854, 268, 789, 728, 602, 307, 976, 360, 444, 552, 144, 41, 384, 706, 905, 899, 828, 510, 694, 245, 62, 670, 425, 597, 394, 551, 607, 273, 117, 42, 839, 500, 686, 879, 986, 423, 486, 532, 745, 294, 65, 544, 916, 286, 284, 120, 383, 170, 179, 868, 818, 90, 616, 936, 823, 807, 568, 233, 447, 557, 722, 723, 297, 448, 656, 642, 266, 433, 808, 830, 280, 361, 185, 708, 293, 545, 225, 956, 567, 229, 917, 398, 673, 718, 281, 586, 60, 5, 352, 270, 149, 594, 775, 676, 458, 436, 2, 528, 451, 244, 975, 366, 162, 93, 298, 274, 810, 852, 37, 131, 826, 631, 349, 701, 784, 915, 89, 34, 814, 512, 372, 497, 316, 912, 209, 614, 231, 189, 984, 132, 407, 946, 308, 301, 166, 83, 58, 357, 914, 427, 44, 715, 434, 968, 887, 7, 505, 396, 214, 420, 674, 620, 477, 792, 760, 925, 961, 666, 991, 944, 637, 542, 698, 442, 865, 110, 730, 933, 875, 498, 783, 234, 765, 399, 88, 704, 535, 707, 18, 992, 445, 716, 310, 891, 32, 277, 824, 938, 751, 91, 391, 675, 385, 82, 842, 70, 324, 612, 558, 112, 581, 359, 752, 999, 424, 832, 782, 299, 288, 746, 438, 599, 414, 487, 201, 464}; +int D1_data1[492] = {29, 951, 39, 276, 380, 861, 357, 324, 624, 363, 758, 792, 233, 752, 950, 894, 215, 23, 525, 414, 933, 547, 364, 155, 256, 953, 749, 833, 344, 792, 614, 633, 325, 744, 872, 239, 317, 77, 29, 20, 545, 601, 168, 369, 124, 760, 727, 515, 49, 7, 292, 631, 384, 262, 665, 430, 403, 304, 458, 541, 314, 998, 324, 578, 27, 607, 245, 38, 851, 874, 478, 900, 370, 175, 514, 13, 845, 717, 67, 723, 901, 828, 936, 891, 72, 952, 762, 536, 985, 488, 229, 81, 909, 613, 840, 66, 901, 79, 813, 59, 212, 502, 985, 317, 112, 161, 941, 880, 150, 599, 730, 378, 847, 367, 901, 155, 982, 340, 97, 957, 78, 138, 359, 29, 950, 578, 626, 548, 80, 703, 674, 80, 869, 941, 324, 893, 76, 263, 836, 365, 453, 270, 507, 530, 865, 982, 493, 868, 148, 869, 675, 470, 440, 512, 797, 929, 897, 224, 619, 666, 251, 485, 707, 680, 281, 990, 435, 675, 189, 463, 743, 489, 662, 223, 155, 25, 476, 862, 870, 284, 445, 191, 297, 181, 900, 288, 249, 371, 533, 929, 159, 30, 89, 986, 33, 547, 178, 949, 964, 130, 700, 840, 124, 242, 376, 879, 746, 295, 450, 784, 844, 753, 38, 434, 403, 439, 598, 713, 480, 589, 742, 234, 650, 922, 3, 771, 16, 498, 371, 956, 747, 848, 30, 769, 483, 810, 683, 600, 981, 168, 127, 325, 324, 255, 446, 33, 281, 786, 896, 383, 387, 823, 302, 314, 437, 102, 629, 272, 478, 419, 375, 549, 425, 27, 410, 532, 44, 988, 198, 187, 504, 37, 837, 257, 338, 660, 124, 978, 813, 52, 521, 329, 388, 855, 729, 117, 314, 769, 127, 191, 292, 21, 895, 37, 718, 250, 514, 779, 326, 577, 306, 757, 34, 363, 786, 809, 153, 70, 714, 610, 575, 213, 611, 20, 958, 615, 985, 251, 181, 7, 569, 307, 91, 996, 93, 105, 143, 944, 864, 546, 444, 453, 318, 514, 383, 546, 81, 128, 780, 35, 521, 714, 288, 14, 622, 621, 701, 445, 187, 246, 593, 674, 331, 38, 120, 898, 366, 429, 291, 221, 553, 59, 326, 558, 565, 393, 991, 549, 232, 80, 935, 330, 491, 632, 478, 58, 396, 183, 205, 769, 236, 537, 92, 516, 379, 90, 796, 248, 418, 230, 368, 666, 608, 993, 219, 700, 456, 294, 917, 482, 613, 662, 390, 2, 947, 11, 81, 607, 898, 855, 18, 857, 310, 811, 666, 940, 359, 199, 148, 476, 315, 890, 310, 968, 979, 174, 895, 632, 597, 759, 255, 1, 133, 763, 788, 136, 256, 335, 325, 766, 901, 280, 254, 688, 731, 793, 996, 288, 80, 80, 842, 584, 951, 600, 818, 323, 303, 303, 318, 807, 47, 864, 63, 140, 450, 231, 905, 200, 247, 725, 4, 714, 122, 298, 60, 547, 433, 328, 666, 606, 143, 643, 689, 716, 425, 737, 594, 255, 243, 931, 537, 358}; +#define LOOP 2 + +#include +#include + +#define MAXN 10000 + +int in[MAXN] = {1}, out[MAXN] = {1}; +int mn[MAXN] = {1}, mx [MAXN] = {1}; + +int D1_max(int a, int b) { return a > b ? a : b; } +int D1_min(int a, int b) { return a < b ? a : b; } + +int main() { + int ans; + + for (int l = 0; l < LOOP; l++) { + memset(mn, -1, (D1_max(x, y) + 1) * sizeof(int)); + memset(mx, -1, (D1_max(x, y) + 1) * sizeof(int)); + memset(in, 0, (D1_max(x, y) + 1) * sizeof(int)); + memset(out, 0, (D1_max(x, y) + 1) * sizeof(int)); + + int a, b; + for (int i = 0; i < D1_n; i++) { + a = D1_data0[i]; + b = D1_data1[i]; + if (mn[a] == -1) + mn[a] = b; + else + mn[a] = D1_min(mn[a], b); + mx[a] = D1_max(mx[a], b); + } + + int reduce = 0; + int down = 0; + int sum = 0; + + for (int i = 0; i < y + 1; i++) { + if (mx[i] != -1){ + in[mx[i]]++; + + out[mn[i]]++; + sum += mn[i]; + down++; + } + } + + ans = 0x7fffffff; + int up = 0, upsum = 0; + for (int p = y + 1; p >= 0; p--){ + if (in[p] > 0){ + up += in[p]; + upsum += in[p] * p; + } + if (out[p] > 0){ + down -= out[p]; + sum -= out[p] * p; + } + int df = 2 * ((upsum - up * p) + (down * p - sum)); + ans = D1_min(ans, df); + } + } + + printf("%d\n", ans + x - 1); + return (ans + x - 1 == 253649) ? 0 : 1; +} diff --git a/sdk/software/examples/fireye/D1/Makefile b/sdk/software/examples/fireye/D1/Makefile new file mode 100644 index 0000000..41a7f6c --- /dev/null +++ b/sdk/software/examples/fireye/D1/Makefile @@ -0,0 +1,14 @@ +TARGET = fireye_D1 + +CFLAGS += -O3 -g + +#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真 +CFLAGS += -DSIMU=0 + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../../bsp +GCC_DIR=../../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../../toolchains/picolibc +include ../../../bsp/common.mk diff --git a/sdk/software/examples/fireye/I2/I2.c b/sdk/software/examples/fireye/I2/I2.c new file mode 100644 index 0000000..8a5838c --- /dev/null +++ b/sdk/software/examples/fireye/I2/I2.c @@ -0,0 +1,122 @@ +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbfe001e0; //UART16550的虚地址 +unsigned long CONFREG_UART_BASE = 0xbfafff10; //CONFREG模拟UART的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbfafe000; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 100000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +int I2_m = 19, I2_n = 32; +char s[32][21] = {" ###################", " #.................#", " #.###############.#", " #.###############.#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.##..............#", " #.###############.#", " #.###############.#", " #.................#", " ###################"}; +int vis[32][19] = {1}; + +#define LOOP 10 + +#include +#include + +int dd[8][2] = {{-1, 0}, {-1, -1}, {-1, 1}, {0, 1}, {0, -1}, {1, 0}, {1, -1}, {1, 1}}; +int abc[3][15] = {{1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1}, + {1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1}, + {1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 1, 1} +}; +int add1[20], add2[20]; + +int check(int x, int y, int I2_n, int I2_m, char cur) { + for (int i = x; i < x + I2_n; i++) + for (int j = y; j < y + I2_m; j++) + if (s[i][j] != cur || vis[i][j])return 1; + return 0; +} + +int find(int stx, int sty, int x, int y, int cur) { + add1[0] = 0, add1[1] = x, add1[2] = x + y; + for (int i = 3; i < 15; i++)add1[i] = add1[i % 3]; + add2[0] = 0, add2[3] = x, add2[6] = x + y, add2[9] = 2 * x + y, add2[12] = 2 * x + 2 * y; + for (int i = 0; i < 5; i++) + for (int j = 1; j < 3; j++)add2[3 * i + j] = add2[3 * i + j - 1]; + + for (int i = 0; i < 15; i++) { + int addn = 0, addm = 0; + if (i / 3 % 2 == 0)addn = x; else addn = y; + if (i % 3 % 2 == 0)addm = x; else addm = y; + + char findchar = '.'; + if (abc[cur][i])findchar = '#'; + if (check(stx + add2[i], sty + add1[i], addn, addm, findchar)) { + return 0; + } + } + return 1; +} + +int main() { + + int ansa = 0, ansb = 0, ansc = 0; + + for (int l = 0; l < LOOP; l++) { + + ansa = ansb = ansc = 0; + memset(vis, 0, sizeof(vis)); + + for (int i = 2; i <= I2_n - 1; i++) + for (int j = 2; j <= I2_m - 1; j++) + if (s[i][j] == '#') { + int gg = 0; + for (int k = 0; k < 8; k++) + if (s[i + dd[k][0]][j + dd[k][1]] == '#') { + gg++; + break; + } + if (!gg)s[i][j] = '.'; + } + + for (int i = 2; i <= I2_n - 1; i++) + for (int j = 2; j <= I2_m - 2; j++) + if (s[i][j] == '.' && s[i][j + 1] == '#' && !vis[i][j]) { + int a = 1, b = 1; + for (int k = j + 2; k <= I2_m - 2; k++) + if (s[i][k] == '#')a++; + else break; + for (int k = i + 1; k <= I2_n - 2; k++) + if (s[k][j + 1] == '#')b++; + else break; + + int x = 2 * a - b, y = 2 * b - 3 * a; + if (x <= 0 || y <= 0)continue; + + int gg = 0; + for (int k = j; k <= j + a + 1; k++) + if (s[i - 1][k] == '#' || s[i + b][k] == '#') { + gg++; + break; + } + if (gg)continue; + for (int k = i; k <= i + b - 1; k++) + if (s[k][j] == '#' || s[k][j + a + 1] == '#') { + gg++; + break; + } + if (gg)continue; + + int cur = 0; + if (s[i][j + x + 1] == '#' && s[i + x + y][j + x + 1] == '#' && s[i + 2 * (x + y)][j + x + 1] == '.')cur = 1; + if (s[i][j + x + 1] == '#' && s[i + x + y][j + x + 1] == '#' && s[i + 2 * (x + y)][j + x + 1] == '#')cur = 2; + if (s[i][j + x + 1] == '#' && s[i + x + y][j + x + 1] == '.' && s[i + 2 * (x + y)][j + x + 1] == '#')cur = 3; + + if (!cur)continue; + + if (find(i, j + 1, x, y, cur - 1)) { + for (int visx = i - 1; visx <= i + b; visx++) + for (int visy = j; visy <= j + a + 1; visy++) + vis[visx][visy]++; + if (cur == 1)ansa++; + else if (cur == 2)ansb++; + else ansc++; + } + + } + } + + printf("%d %d %d\n", ansa, ansb, ansc); + return (ansa == 0 && ansb == 0 && ansc == 1) ? 0 : 1; +} diff --git a/sdk/software/examples/fireye/I2/Makefile b/sdk/software/examples/fireye/I2/Makefile new file mode 100644 index 0000000..ab031e0 --- /dev/null +++ b/sdk/software/examples/fireye/I2/Makefile @@ -0,0 +1,14 @@ +TARGET = fireye_I2 + +CFLAGS += -O3 -g + +C_SRCS := $(wildcard ./*.c ) + +#根据SIMU宏选择串口波特率,0：FPGA上板；1：仿真 +CFLAGS += -DSIMU=0 + +OBJDIR = obj +COMMON_DIR = ../../../bsp +GCC_DIR=../../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../../toolchains/picolibc +include ../../../bsp/common.mk diff --git a/sdk/software/examples/hello_world/Makefile b/sdk/software/examples/hello_world/Makefile new file mode 100644 index 0000000..89c3964 --- /dev/null +++ b/sdk/software/examples/hello_world/Makefile @@ -0,0 +1,11 @@ +TARGET = hello_world + +CFLAGS += -O3 -g + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../bsp +GCC_DIR=../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../toolchains/picolibc +include ../../bsp/common.mk diff --git a/sdk/software/examples/hello_world/main.c b/sdk/software/examples/hello_world/main.c new file mode 100644 index 0000000..ac2afec --- /dev/null +++ b/sdk/software/examples/hello_world/main.c @@ -0,0 +1,36 @@ +#include +#include +#include +#include + +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbf000000; //UART16550的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbf20f100; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +#define CPSIZE 12 +char src[CPSIZE] = "this is src"; +char dst[CPSIZE] = "this is dst"; + +int main(int argc, char** argv) +{ + int a = 100; + float b = 3.2564; + double c = 5478.47563; + char *str; + + printf("Hello Loongarch32r!\n"); + printf("a = %d\n", a); + printf("b = %f\n", b); + printf("c = %lf\n", c); + + str = (char *)malloc(6); + strcpy(str, "ABCDE"); + printf("String = %s, Address = 0x%x\n", str, str); + + memcpy(dst, src, CPSIZE); + printf("%s\n", dst); + + return 0; +} \ No newline at end of file diff --git a/sdk/software/examples/int_test/Makefile b/sdk/software/examples/int_test/Makefile new file mode 100644 index 0000000..64dcd00 --- /dev/null +++ b/sdk/software/examples/int_test/Makefile @@ -0,0 +1,11 @@ +TARGET = int_test + +CFLAGS += -O3 -g + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../bsp +GCC_DIR=../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../toolchains/picolibc +include ../../bsp/common.mk diff --git a/sdk/software/examples/int_test/main.c b/sdk/software/examples/int_test/main.c new file mode 100644 index 0000000..54095cb --- /dev/null +++ b/sdk/software/examples/int_test/main.c @@ -0,0 +1,96 @@ +#include +#include +#include +#include + +#include "common_func.h" + +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbf000000; //UART16550的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbf20f100; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + + +int Ball_x = 400; +int Ball_y = 100; +int Ball_r = 5; + +int Plane_x = 400; +int Plane_y = 400; +int Plane_l = 100; +int Plane_w = 5; + +int simu_flag; +volatile unsigned char int_flag; + +void Timer_IntrHandler(void); +void Button_IntrHandler(unsigned char button_state); + +int main(int argc, char** argv) +{ + int_flag = 0; + DVI_Draw_Rect(Plane_x,Plane_y,Plane_l,Plane_w); + DVI_Draw_SQU(Ball_x,Ball_y,Ball_r); + + simu_flag = RegRead(0xbf20f500); + RegWrite(0xbf20f004,0x0f);//edge + RegWrite(0xbf20f008,0x1f);//pol + RegWrite(0xbf20f00c,0x1f);//clr + RegWrite(0xbf20f000,0x1f);//en + if(simu_flag){ + RegWrite(0xbf20f104,5000);//timercmp 0.1ms + } + else{ + RegWrite(0xbf20f104,50000000);//timercmp 1s + } + RegWrite(0xbf20f108,0x1);//timeren + + while(int_flag == 0) + { + + } + + return 0; +} + +void HWI0_IntrHandler(void) +{ + unsigned int int_state; + int_state = RegRead(0xbf20f014); + + if((int_state & 0x10) == 0x10){ + Timer_IntrHandler(); + } + else if(int_state & 0xf){ + Button_IntrHandler(int_state & 0xf); + } +} + +void Timer_IntrHandler(void) +{ + RegWrite(0xbf20f108,0);//timeren + RegWrite(0xbf20f108,1);//timeren + printf("timer int\n"); +} + +void Button_IntrHandler(unsigned char button_state) +{ + if((button_state & 0b1000) == 0b1000){ + printf("button4 int\n"); + int_flag = 1; + RegWrite(0xbf20f00c,0x8);//clr + } + else if((button_state & 0b0100) == 0b0100){ + printf("button3 int\n"); + RegWrite(0xbf20f00c,0x4);//clr + } + else if((button_state & 0b0010) == 0b0010){ + printf("button2 int\n"); + RegWrite(0xbf20f00c,0x2);//clr + } + else if((button_state & 0b0001) == 0b0001){ + printf("button1 int\n"); + RegWrite(0xbf20f00c,0x1);//clr + } +} \ No newline at end of file diff --git a/sdk/software/examples/lenet/AccelConvFuncs.c b/sdk/software/examples/lenet/AccelConvFuncs.c new file mode 100644 index 0000000..89e9d63 --- /dev/null +++ b/sdk/software/examples/lenet/AccelConvFuncs.c @@ -0,0 +1,179 @@ +#include "AccelConvFuncs.h" + +void accel_conv_func(int8_t* d_i, int8_t* weight, int32_t* bias, int32_t* d_o, int8_t di_type, + int height, int width, int padding, int channel, int out_channel, + int kernel_width, int kernel_height, int with_relu) { + accel_conf_t accel_conf; + accel_conf.buf_size = di_type; + accel_conf.weight_size = 0; + accel_conf.padding = padding; + accel_conf.stride = 1; + accel_conf.kernel_height = kernel_height; + accel_conf.kernel_width = kernel_width; + + int size_mul = di_type == 0b10 ? 4 : + di_type == 0b01 ? 2 : 1; + int buf_mul = di_type == 0b10 ? 1 : + di_type == 0b01 ? 2 : 4; + + int del_h = kernel_height - 1; + int del_w = (kernel_width - 1) * size_mul; + + int size_sft = size_mul >> 1; + int buf_sft = buf_mul >> 1; + int width_i = width * size_mul; + int height_o = (height - kernel_height + padding * 2) + 1; + int width_o = ((width - kernel_width + padding * 2) + 1); + + + int h_append = 0; + int res_h = 0; + for (int h = 0; h < height; h += h_append) { + int h_eq_0 = h == 0; + h_append = h_eq_0 ? MAX_BUF_HEIGHT : MAX_BUF_HEIGHT - del_h; + int h_remain = height - h; + int buf_h_end = h_remain <= h_append; + int buf_h; + int begin_h = h_eq_0 ? 0 : h - del_h; + if (buf_h_end) { + if (h_eq_0) buf_h = h_remain; + else buf_h = h_remain + del_h; + } else { + buf_h = MAX_BUF_HEIGHT; + } + accel_conf.buf_height = buf_h - 1; + int res_h_append = (buf_h - kernel_height + (h_eq_0 + buf_h_end) * padding) + 1; + + int w_append = 0; + int res_w = 0; + for (int w = 0; w < width_i; w += w_append) { + int w_eq_0 = w == 0; + w_append = w_eq_0 ? MAX_BUF_WIDTH : MAX_BUF_WIDTH - del_w; + int w_remain = width_i - w; + int buf_w_end = w_remain <= w_append; + int buf_w; + int begin_w = w_eq_0 ? 0 : w - del_w; + if (buf_w_end) { + if (w_eq_0) { + buf_w = w_remain; + } else { + buf_w = (w_remain + del_w); + } + } else { + buf_w = MAX_BUF_WIDTH; + } + int padding_valid = (w_eq_0) | + (buf_w_end << 1) | + (h_eq_0 << 2) | + (buf_h_end << 3); + int buf_offset = width_i - buf_w; + int res_w_append = ((buf_w >> size_sft) - kernel_width + (w_eq_0 + buf_w_end) * padding) + 1; + int res_offset = (width_o - res_w_append) << size_sft; + int res_buf_info = ((res_w_append - 1) << 16) | res_offset; + inst_conf_offset(buf_offset, res_buf_info); + + accel_conf.buf_width = buf_w - 1; + accel_conf.padding_valid = padding_valid; + for (int k = 0; k < channel; k++) { + accel_conf.buf_refresh = 1; + accel_conf.wadd = k != 0; + for (int c = 0; c < out_channel; c += MAX_KERNEL_NUM) { + int valid_kernel_num = c + MAX_KERNEL_NUM > out_channel ? out_channel - c : MAX_KERNEL_NUM; + accel_conf.kernel_num = valid_kernel_num - 1; + inst_conf_buf((uint32_t)&d_i[(k * height + begin_h) * width_i + begin_w], accel_conf.val); + for (int vc = 0; vc < valid_kernel_num; vc++) { + int ca = c + vc; + inst_conf_res_addr(&d_o[(ca * height_o + res_h) * width_o + res_w], vc); + + if (k == 0) { + inst_conf_res_bias(bias[ca], vc); + // for (int m = 0; m < res_h_append; m++) { + // for (int n = 0; n < res_w_append; n++) { + // d_o[(ca * height_o + res_h + m) * width_o + res_w + n] = bias[ca]; + // } + // } + } + } + if (k == channel - 1 && with_relu) { + inst_conv_relu(&weight[(k * out_channel + c) * kernel_height * kernel_width]); + } else { + inst_conv(&weight[(k * out_channel + c) * kernel_height * kernel_width]); + } + accel_conf.buf_refresh = 0; + } + } + res_w += res_w_append; + } + res_h += res_h_append; + } +} + +// height and width must align 2 +void accel_pool_func(int32_t* d_i, int32_t* d_o, int pool_mode, int channel, int height, int width) { + accel_conf_t conf; + conf.buf_refresh = 1; + conf.wadd = 0; + conf.padding_valid = 0; + conf.weight_size = 2; + conf.buf_size = 2; + conf.kernel_width = 2; + conf.kernel_height = 2; + conf.stride = 2; + conf.kernel_num = 0; + conf.padding = 0; + + int max_width_word = MAX_BUF_WIDTH >> 2; + + // for (int i = 0; i < height; i++) { + // for(int j = 0; j < width; j++) { + // printf("%x ", d_i[i * width + j]); + // } + // printf("\n"); + // } + + int width_o = width >> 1; + int height_o = height >> 1; + + for (int c = 0; c < channel; c++) { + int h_append; + int res_h = 0; + for (int h = 0; h < height; h += h_append) { + h_append = height - h < MAX_BUF_HEIGHT ? height - h : MAX_BUF_HEIGHT; + int buf_h = h_append; + conf.buf_height = buf_h - 1; + int res_h_append = buf_h >> 1; + + int w_append; + int res_w = 0; + for (int w = 0; w < width; w += w_append) { + int w_remain = width - w; + w_append = w_remain < max_width_word ? w_remain : max_width_word; + int buf_w = w_append; + conf.buf_width = (buf_w << 2) - 1; + + inst_conf_buf((uint32_t)&d_i[(c * height + h) * width + w], conf.val); + inst_conf_res_addr((uint32_t)&d_o[(c * height_o + res_h) * width_o + res_w], 0); + int buf_offset = (width - buf_w) << 2; + int res_w_append = (buf_w >> 1); + int res_offset = (width_o - res_w_append) << 2; + int res_buf_info = ((res_w_append - 1) << 16) | res_offset; + inst_conf_offset(buf_offset, res_buf_info); + inst_pool(pool_mode); + + res_w += res_w_append; + } + res_h += res_h_append; + } + } +} + +void accel_linear_func(int32_t* d_i, int8_t* weight, int32_t* bias, + int32_t* output, int input_size, int output_size) { + // 线性层的瓶颈在于访存，cpu可以处理计算 + for (int i = 0; i < output_size; i++) { + output[i] = bias[i]; + for (int j = 0; j < input_size; j++) { + output[i] += d_i[j] * weight[i * input_size + j]; + } + } +} \ No newline at end of file diff --git a/sdk/software/examples/lenet/AccelConvFuncs.h b/sdk/software/examples/lenet/AccelConvFuncs.h new file mode 100644 index 0000000..d8ce398 --- /dev/null +++ b/sdk/software/examples/lenet/AccelConvFuncs.h @@ -0,0 +1,14 @@ +#ifndef __ACCEL__CONV__FUNCS__H__ +#define __ACCEL__CONV__FUNCS__H__ +#include "Accelop.h" + +void accel_conv_func(int8_t* d_i, int8_t* weight, int32_t* bias, int32_t* d_o, int8_t di_type, + int height, int width, int padding, int channel, int out_channel, + int kernel_width, int kernel_height, int with_relu); + +void accel_pool_func(int32_t* d_i, int32_t* d_o, int pool_mode, int channel, int height, int width); + +void accel_linear_func(int32_t* d_i, int8_t* weight, int32_t* bias, + int32_t* output, int input_size, int output_size); + +#endif \ No newline at end of file diff --git a/sdk/software/examples/lenet/Accelop.h b/sdk/software/examples/lenet/Accelop.h new file mode 100644 index 0000000..60688b7 --- /dev/null +++ b/sdk/software/examples/lenet/Accelop.h @@ -0,0 +1,154 @@ +#ifndef __ACCEL__OP__H__ +#define __ACCEL__OP__H__ +#include +// #define LACC_OP + +typedef struct { + union { + struct { + uint32_t buf_refresh: 1; + uint32_t wadd: 1; + uint32_t padding_valid: 4; + uint32_t weight_size: 2; + uint32_t buf_size: 2; + uint32_t kernel_width: 3; + uint32_t kernel_height: 3; + uint32_t buf_width: 5; + uint32_t buf_height: 4; + uint32_t stride: 2; + uint32_t kernel_num: 3; + uint32_t padding: 2; + }; + uint32_t val; + }; +}accel_conf_t; + +#define MAX_KERNEL_NUM 3 +#define MAx_KERNEL_WIDTH 3 +#define MAX_KERNEL_HEIGHT 3 +#define MAX_BUF_WIDTH 32 +#define MAX_BUF_HEIGHT 8 + +void inst_conf_buf(uint32_t addr, uint32_t para) { +#ifdef LACC_OP + asm volatile ( + "lacc 0x0, $r0, %[addr], %[para], 0x0\n\t" + ::[addr]"r"(addr), [para]"r"(para) + ); +#else + asm volatile ( + "move $r5, %[addr]\n\t" + "move $r6, %[para]\n\t" + ".word 0xc00018a0\n\t" + ::[addr]"r"(addr),[para]"r"(para) + :"$r5", "$r6" + ); +#endif +} + +void inst_conf_res_addr(uint32_t waddr, uint32_t idx) { +#ifdef LACC_OP + asm volatile ( + "lacc 0x1, $r0, %[addr], %[idx], 0x5\n\t" + ::[addr]"r"(waddr), [idx]"r"(idx) + ); +#else + asm volatile ( + "move $r5, %[addr]\n\t" + "move $r6, %[idx]\n\t" + ".word 0xc04298a0\n\t" + ::[addr]"r"(waddr), [idx]"r"(idx) + :"$r5", "$r6" + ); +#endif +} + +void inst_conf_res_bias(uint32_t bias, uint32_t idx) { +#ifdef LACC_OP + asm volatile ( + "lacc 0x1, $r0, %[bias], %[idx], 0x2\n\t" + ::[bias]"r"(bias), [idx]"r"(idx) + ); +#else + asm volatile ( + "move $r5, %[addr]\n\t" + "move $r6, %[idx]\n\t" + ".word 0xc04118a0\n\t" + ::[addr]"r"(bias), [idx]"r"(idx) + :"$r5", "$r6" + ); +#endif +} + +typedef void (*inst_conv_ptr_t)(uint32_t); + +void inst_conv(uint32_t weight_addr) { +#ifdef LACC_OP + asm volatile ( + "lacc 0x2, $r0, %[addr], $r0, 0x1\n\t" + ::[addr]"r"(weight_addr) + ); +#else + asm volatile ( + "move $r5, %[addr]\n\t" + ".word 0xc08080a0\n\t" + ::[addr]"r"(weight_addr) + : "$r5" + ); +#endif +} + +void inst_conv_relu(uint32_t weight_addr) { +#ifdef LACC_OP + asm volatile ( + "lacc 0x2, $r0, %[addr], $r0, 0x5\n\t" + ::[addr]"r"(weight_addr) + ); +#else + asm volatile ( + "move $r5, %[addr]\n\t" + ".word 0xc08280a0\n\t" + ::[addr]"r"(weight_addr) + : "$r5" + ); +#endif +} + +#define POOL_MODE_MIN 0 +#define POOL_MODE_MAX 1 +#define POOL_MODE_AVG 2 + +void inst_pool(int pool_mode) { +#ifdef LACC_OP + asm volatile ( + "lacc 0x2, $r0, %[pool_mode], $r0, 0x2\n\t" + ::[pool_mode]"r"(pool_mode) + ); +#else + asm volatile ( + "move $r5, %[pool_mode]\n\t" + ".word 0xc08100a0\n\t" + ::[pool_mode]"r"(pool_mode) + :"$r5" + ); +#endif +} + +void inst_conf_offset(uint32_t buf_offset, uint32_t res_offset) { +#ifdef LACC_OP + asm volatile ( + "lacc 0x3, $r0, %[buf_offset], %[res_offset], 0x0\n\t" + ::[buf_offset]"r"(buf_offset), [res_offset]"r"(res_offset) + ); +#else + asm volatile ( + "move $r5, %[buf_offset]\n\t" + "move $r6, %[res_offset]\n\t" + ".word 0xc0c018a0" + ::[buf_offset]"r"(buf_offset),[res_offset]"r"(res_offset) + :"$r5", "$r6" + ); +#endif +} + +#endif \ No newline at end of file diff --git a/sdk/software/examples/lenet/ConvFuncs.c b/sdk/software/examples/lenet/ConvFuncs.c new file mode 100644 index 0000000..8afb0f4 --- /dev/null +++ b/sdk/software/examples/lenet/ConvFuncs.c @@ -0,0 +1,97 @@ +#include "ConvFuncs.h" + +void conv_func(int8_t* d_i, int8_t* weight, int32_t* bias, int32_t* d_o, int8_t di_type, + int height, int width, int padding, int channel, int out_channel, + int kernel_width, int kernel_height) { + // 使用多重循环卷积(BUF_HEIGHT - KERNEL_SIZE + PADDING * 2) / STRIDE + 1 + int16_t* d_16 = (int16_t*)d_i; + int32_t* d_32 = (int32_t*)d_i; + int height_o = (height - kernel_height + padding * 2) + 1; + int width_o = (width - kernel_width + padding * 2) + 1; + for (int c = 0; c < out_channel; c++) { + for (int h = -padding; h < (height - kernel_height + padding) + 1; h++) { + for (int w = -padding; w < (width - kernel_width + padding) + 1; w++) { + int32_t sum = 0; + for(int k = 0; k < channel; k++) { + for (int m = 0; m < kernel_height; m++) { + for (int n = 0; n < kernel_width; n++) { + int h_m = h + m; + int w_n = w + n; + if (h_m >= 0 && h_m < height && w_n >= 0 && w_n < width) { + if(di_type == 0){ + sum += d_i[(k * height + h_m) * width + w_n] * + weight[((c * channel + k) * kernel_height + m) * kernel_width + n]; + } else if (di_type == 1) { + sum += d_16[(k * height + h_m) * width + w_n] * + weight[((c * channel + k) * kernel_height + m) * kernel_width + n]; + } else if (di_type == 2) { + sum += d_32[(k * height + h_m) * width + w_n] * + weight[((c * channel + k) * kernel_height + m) * kernel_width + n]; + } + } + } + } + } + d_o[c * height_o * width_o + (h+padding) * width_o + w + padding] = sum + bias[c]; + } + } + } +} + +void pool_func(int32_t* d_i, int32_t* d_o, int channel, int height, int width) { + for (int c = 0; c < channel; c++) { + for (int h = 0; h < height / 2; h++) { + for (int w = 0; w < width / 2; w++) { + int32_t sum = d_i[(c * height + (h << 1)) * width + (w << 1)] + + d_i[(c * height + (h << 1) + 1) * width + (w << 1)] + + d_i[(c * height + (h << 1)) * width + (w << 1) + 1] + + d_i[(c * height + (h << 1) + 1) * width + (w << 1) + 1]; + if(sum > 0) d_o[(c * height / 2 + h) * (width / 2) + w] = sum >> 2; + else d_o[(c * height / 2 + h) * (width / 2) + w] = 0; + } + } + } +} + +void linear_func( + int32_t* d_i, + int8_t* weight, + int32_t* bias, + int32_t* output, + int input_size, + int output_size) { + + for (int i = 0; i < output_size; i++) { + output[i] = bias[i]; + for (int j = 0; j < input_size; j++) { + output[i] += d_i[j] * weight[i * input_size + j]; + } + } +} + +void relu_int(int32_t *x, int size) { + for (int i = 0; i < size; i++) { + if (x[i] < 0) { + x[i] = 0; + } + } +} + +void softmax(int32_t *x, float *output, int size) { + int32_t max = x[0]; + for (int i = 1; i < size; i++) { + if (x[i] > max) { + max = x[i]; + } + } + + float sum = 0; + for (int i = 0; i < size; i++) { + output[i] = exp((float)(x[i] - max)) ; + sum += output[i]; + } + + for (int i = 0; i < size; i++) { + output[i] /= sum; + } +} \ No newline at end of file diff --git a/sdk/software/examples/lenet/ConvFuncs.h b/sdk/software/examples/lenet/ConvFuncs.h new file mode 100644 index 0000000..84cd58f --- /dev/null +++ b/sdk/software/examples/lenet/ConvFuncs.h @@ -0,0 +1,16 @@ +#ifndef __CONV_FUNCS_H__ +#define __CONV_FUNCS_H__ +#include + +void conv_func(int8_t* d_i, int8_t* weight, int32_t* bias, int32_t* d_o, int8_t di_type, + int height, int width, int padding, int channel, int out_channel, + int kernel_width, int kernel_height); + +void pool_func(int32_t* d_i, int32_t* d_o, int channel, int height, int width); + +void linear_func(int32_t* d_i, int8_t* weight, int32_t* bias, int32_t* output, int input_size, int output_size); + +void relu_int(int32_t *x, int size); + +void softmax(int32_t *x, float *output, int size); +#endif \ No newline at end of file diff --git a/sdk/software/examples/lenet/Makefile b/sdk/software/examples/lenet/Makefile new file mode 100644 index 0000000..db3f5f3 --- /dev/null +++ b/sdk/software/examples/lenet/Makefile @@ -0,0 +1,11 @@ +TARGET = lenet + +CFLAGS += -O3 -g + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../bsp +GCC_DIR=../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../toolchains/picolibc +include ../../bsp/common.mk diff --git a/sdk/software/examples/lenet/main.c b/sdk/software/examples/lenet/main.c new file mode 100644 index 0000000..7be5437 --- /dev/null +++ b/sdk/software/examples/lenet/main.c @@ -0,0 +1,160 @@ +#include +#include +#include +#include +#include +#include +#include "ConvFuncs.h" +#include "weights.h" +#include "test_image.h" +#include "common_func.h" + + +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbf000000; //UART16550的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbf20f100; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + +int start = 0; + + +void InterruptInit(void) +{ + // Enable button and timer Interrupt + RegWrite(0xbf20f004,0x0f);//edge + RegWrite(0xbf20f008,0x1f);//pol + RegWrite(0xbf20f00c,0x1f);//clr + RegWrite(0xbf20f000,0x1f);//en +} + +void HWI0_IntrHandler(void) +{ + unsigned int int_state; + int_state = RegRead(0xbf20f014); + + if(int_state & 0xf){ + Button_IntrHandler(int_state & 0xf); + } +} + +void Button_IntrHandler(unsigned char button_state) +{ + if((button_state & 0b0001) == 0b0001){ + start = 1; + RegWrite(0xbf20f00c,0x1);//clr + } +} + + +int compare(int32_t* dut, int32_t* ref, int size) { + for (int i = 0; i < size; i++) { + if (dut[i] != ref[i]) { + printf("Error at index %d: expected %d, got %d, %x\n", i, ref[i], dut[i], (uint32_t)&dut[i]); + return 1; + } + } + return 0; +} + +void printImage(int8_t* image, int height, int width) { + for (int i = 0; i < height; i++) { + for (int j = 0; j < width; j++) { + printf("%d ", image[i * width + j] != -1); + } + printf("\n"); + } + printf("\n"); +} + +void flush_dcache(int size) { + for (int i = 0; i < size; i++) { + int index = size << 4; + init_dcache_line(index); + } +} + +int simu_flag; + +int main(int argc, char** argv) { + InterruptInit(); + simu_flag = RegRead(0xbf20f500); + + int32_t conv1_out[6][28][28] = { 0 }; + int32_t pool1_out[6][14][14] = { 0 }; + int32_t conv2_out[16][12][12] = { 0 }; + int32_t pool2_out[16][6][6] = { 0 }; + int32_t fc1_out[10] = { 0 }; + int acc = 0; + int begin_clk, end_clk; + + int32_t accel_conv1_out[6][28][28]; + int32_t accel_pool1_out[6][14][14] = { 0 }; + int32_t accel_conv2_out[16][12][12] = { 0 }; + int32_t accel_pool2_out[16][6][6] = { 0 }; + int32_t accel_fc1_out[10] = { 0 }; + + int test_idx = 0; + int test_num = 0; + + printf("image num: %d\n", TEST_IMAGE_SIZE); + + int clk, ret; + while (1) { + if(!simu_flag) delay_ms(200); + if (start | simu_flag) { + start = 0; + printf("start\n"); + int gold_clk = 0; + if (!simu_flag) { + printImage(test_image[test_idx], 28, 28); + + flush_dcache(256); + + gold_clk = clock(); + conv_func(test_image[test_idx], w_conv1, b_conv1, conv1_out, 0, 28, 28, 1, 1, 6, 3, 3); + relu_int(&conv1_out, 6 * 28 * 28); + pool_func(conv1_out, pool1_out, 6, 28, 28); + conv_func(pool1_out, w_conv2, b_conv2, conv2_out, 2, 14, 14, 0, 6, 16, 3, 3); + relu_int(&conv2_out, 16 * 12 * 12); + pool_func(conv2_out, pool2_out, 16, 12, 12); + linear_func(pool2_out, w_fc1, b_fc1, fc1_out, 576, 10); + gold_clk = clock() - gold_clk; + + flush_dcache(256); + + } + + clk = clock(); + accel_conv_func(test_image[test_idx], w_conv1, b_conv1, accel_conv1_out, 0, 28, 28, 1, 1, 6, 3, 3, 1); + accel_pool_func(accel_conv1_out, accel_pool1_out, 2, 6, 28, 28); + accel_conv_func(accel_pool1_out, w_conv2_rev, b_conv2, accel_conv2_out, 2, 14, 14, 0, 6, 16, 3, 3, 1); + accel_pool_func(accel_conv2_out, accel_pool2_out, 2, 16, 12, 12); + accel_linear_func(accel_pool2_out, w_fc1, b_fc1, accel_fc1_out, 576, 10); + clk = clock() - clk; + + int index = 0; + float max = accel_fc1_out[0]; + for (int j = 1; j < 10; j++) { + if (accel_fc1_out[j] > max) { + index = j; + max = accel_fc1_out[j]; + } + } + printf("recognized number: %d\n", index); + if (index == test_target[test_idx]) acc++; + test_num++; + test_idx = (test_idx + 1) % TEST_IMAGE_SIZE; + if (simu_flag) { + printf("Accuracy: %d/%d, clk: %d\n", + acc, test_num, clk); + } else { + printf("Accuracy: %d/%d, gold_clk: %d, clk: %d speedup: %f\n", + acc, test_num, gold_clk, clk, (float)gold_clk/(float)clk); + } + if (simu_flag) break; + } + } + + return 0; +} \ No newline at end of file diff --git a/sdk/software/examples/lenet/test_image.h b/sdk/software/examples/lenet/test_image.h new file mode 100644 index 0000000..ed2afc9 --- /dev/null +++ b/sdk/software/examples/lenet/test_image.h @@ -0,0 +1,23 @@ +#ifndef __TEST_IMAGE__H__ +#define __TEST_IMAGE__H__ + +#include + +#define TEST_IMAGE_SIZE 10 + +int8_t test_image[TEST_IMAGE_SIZE][28][28] = { + {{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 6, 4, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, 8, 7, 0, -1, -1, -1, -1, 0, 7, 5, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 6, 8, 5, -1, -1, -1, -1, -1, 5, 8, 2, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 8, 8, 3, -1, -1, -1, -1, 0, 8, 7, 0, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 8, 7, 0, -1, -1, -1, -1, 2, 8, 5, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, 3, 8, 7, -1, -1, -1, -1, 0, 8, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, 5, 8, 4, -1, -1, -1, -1, 1, 8, 8, 0, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, 5, 8, 7, 0, -1, -1, -1, 3, 8, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, 2, 8, 8, 4, -1, -1, -1, 4, 8, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 6, 8, 8, 6, 6, 7, 8, 8, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 4, 7, 8, 8, 8, 8, 8, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 0, 0, 2, 8, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 8, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, 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-1, -1, -1, -1, -1, -1, 0, 1, 5, 8, 8, 8, 5, 0, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 4, 0, -1, -1, -1, 0, 7, 8, 8, 8, 0, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, 3, 7, 8, 7, 3, 0, -1, -1, 1, 8, 8, 8, 2, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, 3, 8, 8, 8, 8, 6, 2, 3, 7, 8, 8, 8, 3, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, 3, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 0, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, 0, 6, 8, 8, 8, 8, 8, 8, 8, 8, 8, 3, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 4, 8, 8, 8, 8, 8, 8, 4, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 3, 3, 3, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}} +}; + +int test_target[TEST_IMAGE_SIZE] = {4, 2, 0, 6, 3, 8, 7, 8, 3, 5}; + +#endif // __TEST_IMAGE__H__ diff --git a/sdk/software/examples/lenet/weights.h b/sdk/software/examples/lenet/weights.h new file mode 100644 index 0000000..79f59d4 --- /dev/null +++ b/sdk/software/examples/lenet/weights.h @@ -0,0 +1,62 @@ +#ifndef __WEIGHTS__H__ +#define __WEIGHTS__H__ + +#include + +int8_t w_conv1[6][3][3] = { + {{-43, -52, -8}, {15, -8, 91}, {32, 101, 91}}, + {{-17, 33, -10}, {109, 106, 69}, {64, 89, 14}}, + {{0, -51, -93}, {-80, -43, -26}, {40, 78, 114}}, + {{75, 6, 83}, {34, 75, 65}, {-114, -120, -74}}, + {{60, 36, 44}, {34, 127, 9}, {75, 40, -49}}, + {{4, 7, 25}, {-91, -44, -109}, {-79, -28, -87}} +}; + +int8_t w_conv2[16][6][3][3] = { + {{{12, 13, -12}, {46, -29, -42}, {15, -25, -25}}, {{-8, 40, -29}, {27, 25, -42}, {15, 18, -23}}, {{-66, -41, -10}, {-58, -45, 6}, {-38, -50, -2}}, {{-9, -41, 1}, {-10, -72, -30}, {-26, -81, -65}}, {{27, 45, -23}, {13, 58, -45}, {23, 26, -57}}, {{-61, 15, 29}, {-39, 9, 44}, {0, 42, 13}}}, + {{{18, -67, -47}, {-49, -30, 46}, {-34, 33, 56}}, {{29, 14, -83}, {-79, -85, 9}, {-39, -14, 33}}, {{-2, -6, 58}, {23, 79, 108}, {8, 5, 3}}, {{58, 41, 45}, {45, -66, -13}, {-49, -2, 88}}, {{43, 41, -50}, {-37, -127, -40}, {-93, -16, 58}}, {{-20, -7, 31}, {22, 27, -32}, {15, -27, -46}}}, + {{{-69, -37, -1}, {13, -20, -71}, {64, 56, 34}}, {{-26, -19, 46}, {-15, -64, -87}, {50, 12, 42}}, {{-51, -52, -26}, {8, 18, -29}, {-18, -19, 14}}, {{20, 65, 75}, {-44, -11, 3}, {-7, 28, -84}}, {{-4, 7, 27}, {-23, -67, -47}, {55, 21, -27}}, {{38, 26, 28}, {28, -1, 28}, {-8, -30, 29}}}, + {{{-2, -1, 9}, {-32, -5, 15}, {30, -1, -20}}, {{-15, 21, -24}, {-18, 9, -19}, {18, -5, -46}}, {{-10, 16, 42}, {-11, -20, 5}, {-17, -13, 1}}, {{71, 49, -18}, {54, 63, 45}, {-81, -21, -14}}, {{9, 1, 10}, {21, 0, 34}, {-3, -40, -9}}, {{-45, 3, -20}, {13, 7, -1}, {30, 3, -2}}}, + {{{-42, -10, 0}, {-3, 26, -9}, {46, -26, -73}}, {{27, -44, 21}, {-19, 20, 10}, {-3, 20, -27}}, {{-17, 9, 5}, {55, 29, -61}, {43, -41, 9}}, {{49, 12, -34}, {-19, -28, 6}, {19, 21, -7}}, {{8, -28, 26}, {-46, 10, 41}, {29, 34, -30}}, {{-2, -14, -84}, {19, -46, -74}, {-33, -50, 18}}}, + {{{-22, -12, 50}, {-61, -3, 4}, {-35, -7, 6}}, {{48, -50, 9}, {11, -15, 18}, {-18, -22, 3}}, {{-41, -34, -26}, {0, -31, -69}, {25, 0, -40}}, {{11, -2, 7}, {-48, -92, -8}, {-74, -65, -38}}, {{20, -55, 54}, {13, -75, 50}, {-22, -14, 35}}, {{19, 13, -12}, {30, 29, -42}, {3, 32, -43}}}, + {{{9, 41, 25}, {-18, -26, -6}, {4, 7, 14}}, {{0, 32, 3}, {7, -1, 27}, {-10, -48, -4}}, {{1, -16, 4}, {-46, -24, -21}, {66, 51, 59}}, {{40, 53, -3}, {62, 72, 50}, {-50, -66, -35}}, {{-20, 19, 3}, {7, -3, 25}, {-47, -58, -15}}, {{-29, -31, -28}, {9, 10, 0}, {-3, 33, 13}}}, + {{{24, -14, -41}, {14, -12, 3}, {-2, 24, 27}}, {{20, -37, -70}, {-10, 19, -6}, {-27, 39, 32}}, {{-41, -30, 2}, {-31, 4, -23}, {16, -6, 19}}, {{-8, -68, -13}, {49, -14, -26}, {21, 94, 62}}, {{45, 7, -67}, {11, 21, -52}, {-18, -1, 10}}, {{-43, 21, 15}, {-75, -16, 8}, {12, -23, -53}}}, + {{{2, -9, 32}, {-23, 29, -9}, {-55, 26, -9}}, {{0, -43, 25}, {7, -33, 23}, {-55, 4, 27}}, {{1, 3, -61}, {17, -14, -120}, {-15, -63, -124}}, {{18, -46, -47}, {-2, -32, -58}, {-51, -28, -65}}, {{0, -49, 68}, {12, -14, 66}, {-36, -29, 62}}, {{21, 9, -19}, {48, 9, -70}, {32, -4, -57}}}, + {{{-38, 41, -14}, {38, 33, -58}, {23, -72, -33}}, {{-16, 20, -4}, {-36, 17, -30}, {2, -11, -49}}, {{11, 11, -35}, {54, 18, -21}, {33, -21, 9}}, {{-3, -34, -20}, {-32, -24, 27}, {3, 50, -8}}, {{-18, 33, 27}, {-27, 33, 18}, {38, 38, -37}}, {{15, -42, -52}, {-29, -55, -25}, {-60, -17, 45}}}, + {{{0, -33, -29}, {16, -7, -20}, {8, 22, -21}}, {{-6, -43, -36}, {2, -10, -7}, {8, 0, 9}}, {{52, 16, -14}, {-1, 30, 20}, {17, 16, 0}}, {{22, 60, 93}, {107, 51, -2}, {62, 41, 46}}, {{-24, -49, -29}, {-4, -23, -27}, {26, 18, 22}}, {{27, 9, 50}, {-37, -7, -9}, {-3, -23, -12}}}, + {{{-28, -79, -65}, {-18, 15, 36}, {-4, 55, 20}}, {{17, -12, -64}, {-32, -56, -15}, {-26, 26, 27}}, {{-45, 6, 27}, {40, 45, 46}, {56, 9, 48}}, {{93, 6, -28}, {14, -76, -29}, {-67, -12, 43}}, {{60, -33, -69}, {-48, -79, -12}, {-7, 7, 68}}, {{-6, -12, 9}, {-2, 14, -1}, {-24, -18, -5}}}, + {{{15, -4, -30}, {-3, 36, -29}, {-3, 23, 14}}, {{-5, 11, -30}, {-5, 36, -3}, {-30, 36, 29}}, {{-22, -35, -23}, {-38, -41, 1}, {-27, -63, 23}}, {{0, -50, -83}, {-25, -75, -111}, {-50, -26, -29}}, {{-37, 20, 4}, {1, 38, -8}, {9, 49, 27}}, {{-48, -80, -20}, {6, -33, -30}, {1, -51, -39}}}, + {{{15, -22, -26}, {21, -1, 11}, {-23, 6, -13}}, {{-10, -41, -15}, {25, -5, -4}, {-31, -26, -19}}, {{-17, 7, 10}, {0, -21, -8}, {-5, 10, 47}}, {{5, -55, -38}, {55, 62, 45}, {54, 55, 14}}, {{-17, -28, -12}, {31, 35, 30}, {-17, -6, 2}}, {{2, -20, -6}, {-10, -22, 12}, {27, 14, 25}}}, + {{{-8, -27, 36}, {-31, 37, 50}, {-57, 28, 12}}, {{24, -67, -46}, {-18, -24, 30}, {-41, 1, -4}}, {{12, 18, 92}, {-27, 12, 33}, {7, -11, -27}}, {{29, -33, -123}, {-61, -85, 4}, {-44, -75, -35}}, {{21, -68, -77}, {1, -60, 14}, {-77, -22, 52}}, {{5, 0, 31}, {7, 20, -13}, {-2, 5, 5}}}, + {{{-28, -15, -5}, {16, 16, 14}, {-25, -8, -37}}, {{-18, -30, -30}, {28, 23, 30}, {-14, 16, 8}}, {{0, 3, 6}, {-7, 4, -5}, {-27, -44, -41}}, {{5, 23, 16}, {11, -5, 9}, {50, 71, 40}}, {{-7, -22, -36}, {37, 0, 20}, {27, 39, 10}}, {{10, 30, 3}, {-24, -17, -16}, {2, -29, 3}}} +}; + +int8_t w_conv2_rev[6][16][3][3] = { + {{{12, 13, -12}, {46, -29, -42}, {15, -25, -25}}, {{18, -67, -47}, {-49, -30, 46}, {-34, 33, 56}}, {{-69, -37, -1}, {13, -20, -71}, {64, 56, 34}}, {{-2, -1, 9}, {-32, -5, 15}, {30, -1, -20}}, {{-42, -10, 0}, {-3, 26, -9}, {46, -26, -73}}, {{-22, -12, 50}, {-61, -3, 4}, {-35, -7, 6}}, {{9, 41, 25}, {-18, -26, -6}, {4, 7, 14}}, {{24, -14, -41}, {14, -12, 3}, {-2, 24, 27}}, {{2, -9, 32}, {-23, 29, -9}, {-55, 26, -9}}, {{-38, 41, -14}, {38, 33, -58}, {23, -72, -33}}, {{0, -33, -29}, {16, -7, -20}, {8, 22, -21}}, {{-28, -79, -65}, {-18, 15, 36}, {-4, 55, 20}}, {{15, -4, -30}, {-3, 36, -29}, {-3, 23, 14}}, {{15, -22, -26}, {21, -1, 11}, {-23, 6, -13}}, {{-8, -27, 36}, {-31, 37, 50}, {-57, 28, 12}}, {{-28, -15, -5}, {16, 16, 14}, {-25, -8, -37}}}, + {{{-8, 40, -29}, {27, 25, -42}, {15, 18, -23}}, {{29, 14, -83}, {-79, -85, 9}, {-39, -14, 33}}, {{-26, -19, 46}, {-15, -64, -87}, {50, 12, 42}}, {{-15, 21, -24}, {-18, 9, -19}, {18, -5, -46}}, {{27, -44, 21}, {-19, 20, 10}, {-3, 20, -27}}, {{48, -50, 9}, {11, -15, 18}, {-18, -22, 3}}, {{0, 32, 3}, {7, -1, 27}, {-10, -48, -4}}, {{20, -37, -70}, {-10, 19, -6}, {-27, 39, 32}}, {{0, -43, 25}, {7, -33, 23}, {-55, 4, 27}}, {{-16, 20, -4}, {-36, 17, -30}, {2, -11, -49}}, {{-6, -43, -36}, {2, -10, -7}, {8, 0, 9}}, {{17, -12, -64}, {-32, -56, -15}, {-26, 26, 27}}, {{-5, 11, -30}, {-5, 36, -3}, {-30, 36, 29}}, {{-10, -41, -15}, {25, -5, -4}, {-31, -26, -19}}, {{24, -67, -46}, {-18, -24, 30}, {-41, 1, -4}}, {{-18, -30, -30}, {28, 23, 30}, {-14, 16, 8}}}, + {{{-66, -41, -10}, {-58, -45, 6}, {-38, -50, -2}}, {{-2, -6, 58}, {23, 79, 108}, {8, 5, 3}}, {{-51, -52, -26}, {8, 18, -29}, {-18, -19, 14}}, {{-10, 16, 42}, {-11, -20, 5}, {-17, -13, 1}}, {{-17, 9, 5}, {55, 29, -61}, {43, -41, 9}}, {{-41, -34, -26}, {0, -31, -69}, {25, 0, -40}}, {{1, -16, 4}, {-46, -24, -21}, {66, 51, 59}}, {{-41, -30, 2}, {-31, 4, -23}, {16, -6, 19}}, {{1, 3, -61}, {17, -14, -120}, {-15, -63, -124}}, {{11, 11, -35}, {54, 18, -21}, {33, -21, 9}}, {{52, 16, -14}, {-1, 30, 20}, {17, 16, 0}}, {{-45, 6, 27}, {40, 45, 46}, {56, 9, 48}}, {{-22, -35, -23}, {-38, -41, 1}, {-27, -63, 23}}, {{-17, 7, 10}, {0, -21, -8}, {-5, 10, 47}}, {{12, 18, 92}, {-27, 12, 33}, {7, -11, -27}}, {{0, 3, 6}, {-7, 4, -5}, {-27, -44, -41}}}, + {{{-9, -41, 1}, {-10, -72, -30}, {-26, -81, -65}}, {{58, 41, 45}, {45, -66, -13}, {-49, -2, 88}}, {{20, 65, 75}, {-44, -11, 3}, {-7, 28, -84}}, {{71, 49, -18}, {54, 63, 45}, {-81, -21, -14}}, {{49, 12, -34}, {-19, -28, 6}, {19, 21, -7}}, {{11, -2, 7}, {-48, -92, -8}, {-74, -65, -38}}, {{40, 53, -3}, {62, 72, 50}, {-50, -66, -35}}, {{-8, -68, -13}, {49, -14, -26}, {21, 94, 62}}, {{18, -46, -47}, {-2, -32, -58}, {-51, -28, -65}}, {{-3, -34, -20}, {-32, -24, 27}, {3, 50, -8}}, {{22, 60, 93}, {107, 51, -2}, {62, 41, 46}}, {{93, 6, -28}, {14, -76, -29}, {-67, -12, 43}}, {{0, -50, -83}, {-25, -75, -111}, {-50, -26, -29}}, {{5, -55, -38}, {55, 62, 45}, {54, 55, 14}}, {{29, -33, -123}, {-61, -85, 4}, {-44, -75, -35}}, {{5, 23, 16}, {11, -5, 9}, {50, 71, 40}}}, + {{{27, 45, -23}, {13, 58, -45}, {23, 26, -57}}, {{43, 41, -50}, {-37, -127, -40}, {-93, -16, 58}}, {{-4, 7, 27}, {-23, -67, -47}, {55, 21, -27}}, {{9, 1, 10}, {21, 0, 34}, {-3, -40, -9}}, {{8, -28, 26}, {-46, 10, 41}, {29, 34, -30}}, {{20, -55, 54}, {13, -75, 50}, {-22, -14, 35}}, {{-20, 19, 3}, {7, -3, 25}, {-47, -58, -15}}, {{45, 7, -67}, {11, 21, -52}, {-18, -1, 10}}, {{0, -49, 68}, {12, -14, 66}, {-36, -29, 62}}, {{-18, 33, 27}, {-27, 33, 18}, {38, 38, -37}}, {{-24, -49, -29}, {-4, -23, -27}, {26, 18, 22}}, {{60, -33, -69}, {-48, -79, -12}, {-7, 7, 68}}, {{-37, 20, 4}, {1, 38, -8}, {9, 49, 27}}, {{-17, -28, -12}, {31, 35, 30}, {-17, -6, 2}}, {{21, -68, -77}, {1, -60, 14}, {-77, -22, 52}}, {{-7, -22, -36}, {37, 0, 20}, {27, 39, 10}}}, + {{{-61, 15, 29}, {-39, 9, 44}, {0, 42, 13}}, {{-20, -7, 31}, {22, 27, -32}, {15, -27, -46}}, {{38, 26, 28}, {28, -1, 28}, {-8, -30, 29}}, {{-45, 3, -20}, {13, 7, -1}, {30, 3, -2}}, {{-2, -14, -84}, {19, -46, -74}, {-33, -50, 18}}, {{19, 13, -12}, {30, 29, -42}, {3, 32, -43}}, {{-29, -31, -28}, {9, 10, 0}, {-3, 33, 13}}, {{-43, 21, 15}, {-75, -16, 8}, {12, -23, -53}}, {{21, 9, -19}, {48, 9, -70}, {32, -4, -57}}, {{15, -42, -52}, {-29, -55, -25}, {-60, -17, 45}}, {{27, 9, 50}, {-37, -7, -9}, {-3, -23, -12}}, {{-6, -12, 9}, {-2, 14, -1}, {-24, -18, -5}}, {{-48, -80, -20}, {6, -33, -30}, {1, -51, -39}}, {{2, -20, -6}, {-10, -22, 12}, {27, 14, 25}}, {{5, 0, 31}, {7, 20, -13}, {-2, 5, 5}}, {{10, 30, 3}, {-24, -17, -16}, {2, -29, 3}}} +}; + +int8_t w_fc1[10][576] = { + {-6, -4, -15, -14, -18, 2, -7, -15, 0, -10, -5, -2, -6, 21, 14, -15, 11, 11, -1, 13, 21, -61, -12, -4, 3, 21, -18, -26, -15, -12, 4, 0, -13, -25, -30, -27, -12, -10, -15, -15, -7, -4, 0, -6, -8, -13, -34, -3, -7, 5, -8, -31, -6, -15, -24, -3, -4, -12, 4, 0, -23, -51, -28, -3, 20, 6, -13, -28, -17, 0, 5, 1, 4, 4, -8, 0, -7, -6, -3, -18, -10, -2, -1, -12, -9, -28, -21, -32, -39, -16, -24, -58, -24, -10, -30, -22, -14, -13, -25, 0, -5, 1, -10, -1, 5, 4, 5, 1, -1, -10, -10, -5, 4, -1, -4, -16, 2, 11, -8, -10, -5, -11, -28, -5, -18, -24, -3, -23, -73, -69, -2, 9, -18, -13, -23, -16, 0, -1, 5, -8, 11, -6, -18, -10, 4, -15, -16, -18, -21, 2, -4, -1, -12, -25, -37, -26, -6, 10, 0, -51, -2, 1, 14, 7, -34, 4, 12, 14, 5, -9, -14, 3, 5, 1, 7, 2, -18, -45, -16, -1, -4, -5, -9, -2, -7, -5, -11, -11, -19, -3, -3, -2, -5, -1, -20, 7, 39, 0, 1, 17, -29, 24, 41, -4, -10, 15, -35, -20, -6, -14, -16, -4, -28, -61, -26, -8, 4, -11, -21, -16, -13, -1, -2, -24, -24, 8, -5, -22, -11, -22, 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21, 27, -9, 9, 5, -8, 9, -6, 3, -15, -64, -8, 6, 0, -17, -10, -41, -4, -8, -14, -45, -14, -13, 0, 10, -42, -30, -16, 15, 13, -22, -22, -24, -25, -17, -25, -29, -18, -5, -1, 3, 24, 9, -6, -3, -13, -47, -40, 9, 4, 0, -7, 3, -20, -8, -4, 8, -9, 23, -2, -5, 7, 1, -6, -8, -11, -28, -8, -14, 6, -15, 6, 0, -2, 8, -7, -1, -60, -70, -30, 0, 3, -5, -40, -56, -45, -9, 5, -1, -29, -19, -3, -5, -15, -15, -52, 0, 3, 2, -24, -40, -22, 11, 2, 4, 1, 1, 21, 33, 23, 5, -2, -13, 5, -19, -25, -13, 0, 21, -2, -26, -19, -34, 2, -17, -36, 22, -6, -15, -13, -31, -52, 13, 8, -30, -3, -5, -17, -10, -6, -14, -4, 8, -5, -11, -21, -1, -11, -19, 12, 10, -2, -25, -4, -5, -4, 7, 12, -7, -26, -36, -21, -11, -22, -31, -47, -27, 14, -7, -61, -48, -24, 5, 11, -22, -62, 4, 11, 4, -30, -12, 21, 10, -2, 0, 4, -12, -21, -13, 9, 5, 12, -28, -58, -17, -16, -31, -36, 6, -8, -17, -43, -57, -27, -13, -2, -10, -18, 7, 11, 4, 1, -11, 8, 20, 1, -18, -10, -20, -7, -16, -18, -31, -14, -9, -17, -49, -66, -4, 10, -8, 5, 0, -20, 25, 16, -2, 1, 11, -40, -5, 7, -18, -1, -17, -45, -19, -1, -14, 1, -4, 5, 22, 10, 11, 3, -17, -9, -4, -16, -9, -13, -15, 1, 0, 8, -21, -4, -13, 14, 15, -16, -18, -17, -1, 22, -7, -62, -38, -11, -5, 1, -46, -48, -20, -4, -6, -21, -19, -4, 5, -2, -3, -18, -20, -18, -11, 5, 16, 8, -61, -62, -3, 0, -8, -53, -8, -14, -1, -19, -79, -86, -29, 22, 5, -3, -12, -15, -24, 35, 1, 5, 15, 19, -2, -10, -14, -3, -17, 12, 13, -10, -26, -5, 2, -13, 4, 9, 2, -18, -27, -13, 27, 4, -19, -53, -29, 10, -31, -44, -37, -24, 9, 8, -48, -42, -8, 9, 9, -28, -28, 13, 22} +}; + +int32_t b_conv1[6] = {101, 113, 26, 14, 127, 61}; + +int32_t b_conv2[16] = {70, -89, 4, 48, 24, 127, -12, -74, 77, 36, -15, 13, -45, 21, 30, -28}; + +int32_t b_fc1[10] = {-77, -48, -24, -90, -35, -48, -89, -44, 127, 10}; + +#endif // __WEIGHTS__H__ diff --git a/sdk/software/examples/matmul_test/Makefile b/sdk/software/examples/matmul_test/Makefile new file mode 100644 index 0000000..79cb285 --- /dev/null +++ b/sdk/software/examples/matmul_test/Makefile @@ -0,0 +1,11 @@ +TARGET = matmul_test + +CFLAGS += -O3 -g + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../bsp +GCC_DIR=../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../toolchains/picolibc +include ../../bsp/common.mk diff --git a/sdk/software/examples/matmul_test/main.c b/sdk/software/examples/matmul_test/main.c new file mode 100644 index 0000000..fc36f77 --- /dev/null +++ b/sdk/software/examples/matmul_test/main.c @@ -0,0 +1,253 @@ +/** + * matmul_test - Standalone test example for matmul_axi_slave IP + * + * Tests the 4x4 matrix multiplier IP at 0x1f500000 (axiOut_7). + * Computes C = A x B using register-level access, then verifies + * against a software reference matmul. + * + * Register map (byte offsets from MATMUL_BASE): + * 0x000 CTRL [W] bit0=1 starts computation + * 0x004 STATUS [R] bit2=error, bit1=done, bit0=busy + * 0x008 SRC_BASE [R/W] source data base address + * 0x00c DST_BASE [R/W] result data base address + * 0x010 GROUP_NUM [R/W] number of matrix groups + * 0x020 A_BASE [R/W] 16 words of matrix A (row-major) + * 0x060 B_BASE [R/W] 16 words of matrix B (row-major) + * 0x0a0 C_BASE [R] 48 words of result C (3 words per element) + */ + +#include +#include + +/* ─── BSP globals (required by common.mk / picolibc) ─────────────── */ +unsigned long UART_BASE = 0xbf000000; +unsigned long CONFREG_TIMER_BASE = 0xbf20f100; +unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L; +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; + +/* ─── MATMUL IP register map ─────────────────────────────────────── */ +#define MATMUL_BASE 0x1f500000 + +#define MATMUL_CTRL (MATMUL_BASE + 0x000) +#define MATMUL_STATUS (MATMUL_BASE + 0x004) +#define MATMUL_SRC_BASE (MATMUL_BASE + 0x008) +#define MATMUL_DST_BASE (MATMUL_BASE + 0x00c) +#define MATMUL_GROUP_NUM (MATMUL_BASE + 0x010) +#define MATMUL_A_BASE (MATMUL_BASE + 0x020) +#define MATMUL_B_BASE (MATMUL_BASE + 0x060) +#define MATMUL_C_BASE (MATMUL_BASE + 0x0a0) + +/* CTRL bits */ +#define CTRL_START 0x1 + +/* STATUS bits */ +#define STATUS_BUSY 0x1 +#define STATUS_DONE 0x2 +#define STATUS_ERROR 0x4 + +/* ─── Convenience macros ─────────────────────────────────────────── */ +#define REG_WR(addr, val) (*(volatile uint32_t *)(addr) = (uint32_t)(val)) +#define REG_RD(addr) (*(volatile uint32_t *)(addr)) + +/* ─── Test data ───────────────────────────────────────────────────── + * Test group 0: + * A = identity (4x4) + * B = diagonal {2, 3, 4, 5} + * Expected C = B (since identity * X = X) + * + * Test group 1: + * A = [[1,2,0,0], [0,0,3,0], [0,0,0,4], [0,0,0,0]] + * B = [[5,0,0,0], [6,0,0,0], [0,7,0,0], [0,0,8,0]] + * Expected C computed by software reference below + * + * Each A/B is 16 uint32_t, row-major. Unused slots in sub-4x4 matrices + * are 0 as specified. + */ + +#define N_GROUPS 2 + +static const uint32_t test_a[N_GROUPS][16] = { + /* group 0: identity */ + { 1, 0, 0, 0, + 0, 1, 0, 0, + 0, 0, 1, 0, + 0, 0, 0, 1 }, + /* group 1 */ + { 1, 2, 0, 0, + 0, 0, 3, 0, + 0, 0, 0, 4, + 0, 0, 0, 0 }, +}; + +static const uint32_t test_b[N_GROUPS][16] = { + /* group 0: diagonal */ + { 2, 0, 0, 0, + 0, 3, 0, 0, + 0, 0, 4, 0, + 0, 0, 0, 5 }, + /* group 1 */ + { 5, 0, 0, 0, + 6, 0, 0, 0, + 0, 7, 0, 0, + 0, 0, 8, 0 }, +}; + +/* ─── Software reference matmul ───────────────────────────────────── + * Returns the 66-bit result element as two 32-bit halves: + * words[0] = result[31:0] + * words[1] = result[63:32] + * words[2] = result[65:64] (only 2 bits, zero-extended to 32) + */ +static void matmul_ref_u32( + const uint32_t a[16], + const uint32_t b[16], + uint32_t c_words[48]) +{ + int row, col, k; + for (row = 0; row < 4; row++) { + for (col = 0; col < 4; col++) { + uint64_t acc = 0; + for (k = 0; k < 4; k++) { + acc += (uint64_t)a[row * 4 + k] * (uint64_t)b[k * 4 + col]; + } + int idx = (row * 4 + col) * 3; + c_words[idx + 0] = (uint32_t)(acc & 0xFFFFFFFFULL); + c_words[idx + 1] = (uint32_t)((acc >> 32) & 0xFFFFFFFFULL); + c_words[idx + 2] = (uint32_t)((acc >> 64) & 0x3ULL); + } + } +} + +/* ─── Write 16 words of matrix data to the IP ────────────────────── */ +static void write_matrix(uint32_t base_addr, const uint32_t data[16]) +{ + int i; + for (i = 0; i < 16; i++) { + REG_WR(base_addr + i * 4, data[i]); + } +} + +/* ─── Read 48 words of result C from the IP ──────────────────────── */ +static void read_result(uint32_t c_words[48]) +{ + int i; + for (i = 0; i < 48; i++) { + c_words[i] = REG_RD(MATMUL_C_BASE + i * 4); + } +} + +/* ─── Wait until IP is done, return 0 on success, -1 on error ────── */ +static int wait_done(void) +{ + while (1) { + uint32_t status = REG_RD(MATMUL_STATUS); + if (status & STATUS_ERROR) { + printf("[ERROR] matmul IP reports error (status=0x%08lx)\n", + (unsigned long)status); + return -1; + } + if (status & STATUS_DONE) { + return 0; + } + } +} + +/* ─── Verify group result against expected C words ───────────────── */ +static int verify_group(int group, const uint32_t got[48], + const uint32_t expected[48]) +{ + int i, errors = 0; + for (i = 0; i < 48; i++) { + if (got[i] != expected[i]) { + if (errors < 8) { + int elem = i / 3; + int sub = i % 3; /* 0=low, 1=high, 2=overflow */ + const char *sub_name[] = {"low", "high", "ovf"}; + printf(" group%d C[%d][%d].%s: got 0x%08lx exp 0x%08lx\n", + group, elem / 4, elem % 4, sub_name[sub], + (unsigned long)got[i], (unsigned long)expected[i]); + } + errors++; + } + } + if (errors > 8) { + printf(" ... and %d more mismatches\n", errors - 8); + } + return errors; +} + +/* ─── Main ────────────────────────────────────────────────────────── */ +int main(void) +{ + int g, pass_count = 0, fail_count = 0; + + printf("\n===== MATMUL IP Test =====\n"); + printf("Base addr : 0x%08lx\n", (unsigned long)MATMUL_BASE); + printf("Groups : %d\n", N_GROUPS); + printf("===========================\n"); + + /* Write group count */ + REG_WR(MATMUL_GROUP_NUM, N_GROUPS); + + /* For this register-level example, SRC_BASE / DST_BASE are + * informational only (no DMA). Set them to 0. */ + REG_WR(MATMUL_SRC_BASE, 0); + REG_WR(MATMUL_DST_BASE, 0); + + /* ── Run each test group ──────────────────────────────────── */ + for (g = 0; g < N_GROUPS; g++) { + uint32_t expected_c[48]; + uint32_t got_c[48]; + int errs; + + printf("\n--- Group %d ---\n", g); + printf("Loading A[16] and B[16] into IP...\n"); + + write_matrix(MATMUL_A_BASE, test_a[g]); + write_matrix(MATMUL_B_BASE, test_b[g]); + + /* Clear any stale done/error flags */ + REG_WR(MATMUL_STATUS, STATUS_DONE | STATUS_ERROR); + + printf("Starting computation (CTRL=0x%x)...\n", CTRL_START); + REG_WR(MATMUL_CTRL, CTRL_START); + + printf("Waiting for done...\n"); + if (wait_done() != 0) { + fail_count++; + continue; + } + + printf("Reading C[48] from IP...\n"); + read_result(got_c); + + printf("Computing software reference...\n"); + matmul_ref_u32(test_a[g], test_b[g], expected_c); + + printf("Verifying...\n"); + errs = verify_group(g, got_c, expected_c); + + if (errs == 0) { + printf("Group %d: PASS\n", g); + pass_count++; + } else { + printf("Group %d: FAIL (%d mismatches)\n", g, errs); + fail_count++; + } + } + + /* ── Final report ─────────────────────────────────────────── */ + printf("\n============================\n"); + printf("RESULTS: %d passed, %d failed\n", pass_count, fail_count); + if (fail_count == 0) { + printf("ALL TESTS PASSED\n"); + } else { + printf("SOME TESTS FAILED\n"); + } + printf("============================\n"); + + /* Signal completion to testbench via UART */ + printf("MATMUL_DONE\n"); + + return (fail_count == 0) ? 0 : 1; +} diff --git a/sdk/software/examples/pinball_game/Makefile b/sdk/software/examples/pinball_game/Makefile new file mode 100644 index 0000000..31b0ccc --- /dev/null +++ b/sdk/software/examples/pinball_game/Makefile @@ -0,0 +1,11 @@ +TARGET = pinball_game + +CFLAGS += -O3 -g + +C_SRCS := $(wildcard ./*.c ) + +OBJDIR = obj +COMMON_DIR = ../../bsp +GCC_DIR=../../../toolchains/loongson-gnu-toolchain-8.3-x86_64-loongarch32r-linux-gnusf-v2.0 +PICOLIBC_DIR=../../../toolchains/picolibc +include ../../bsp/common.mk diff --git a/sdk/software/examples/pinball_game/main.c b/sdk/software/examples/pinball_game/main.c new file mode 100644 index 0000000..739ce6f --- /dev/null +++ b/sdk/software/examples/pinball_game/main.c @@ -0,0 +1,249 @@ +#include +#include +#include +#include + +#include "common_func.h" +#include "dvi.h" +#include "seg7.h" +#include "led.h" +#include "core_time.h" + +//BSP板级支持包所需全局变量 +unsigned long UART_BASE = 0xbf000000; //UART16550的虚地址 +unsigned long CONFREG_TIMER_BASE = 0xbf20f100; //CONFREG计数器的虚地址 +unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L; //CONFREG时钟频率 +unsigned long CORE_CLOCKS_PER_SEC = 33000000L; //处理器核时钟频率 + + +int Ball_x = 400; +int Ball_y = 100; +int Ball_r = 5; + +volatile int Plane_x = 400; +int Plane_y = 400; +int Plane_l = 100; +int Plane_w = 5; + +// ball move direction +int Ball_dx = 2; +int Ball_dy = 2; + +// ball move direction +int Plane_dx = 20; + +int score = 0; + +volatile int delay_time = 0; + +void Timer_IntrHandler(void); +void Button_IntrHandler(unsigned char button_state); + +void showGameOver(void); + +int chooseFlag = 1; + +volatile int flag = 1; + +void InterruptInit(void) +{ + // Enable button and timer Interrupt + RegWrite(0xbf20f004,0x0f);//edge + RegWrite(0xbf20f008,0x1f);//pol + RegWrite(0xbf20f00c,0x1f);//clr + RegWrite(0xbf20f000,0x1f);//en + + RegWrite(0xbf20f104,25000000);//timercmp 500ms + RegWrite(0xbf20f108,0x1);//timeren +} + +void showGameOver(void); + +void chooseTime(void) +{ + printf("Please Choosetime !!\n"); + while (flag); + printf("Choosetime:%d\n",delay_time); + chooseFlag = 0; + setSegNum(0,0,0,0); +} + +int main(int argc, char** argv) +{ + InterruptInit(); + + chooseTime(); + + while (1) { + + DVI_Draw_Rect(Plane_x,Plane_y,Plane_l,Plane_w); + + DVI_Draw_SQU(Ball_x,Ball_y,Ball_r); + + delay_ms(delay_time); + + // refresh place + Ball_x += Ball_dx; + Ball_y += Ball_dy; + + delay_ms(delay_time); + + if(Ball_y < 2) + { + Ball_y = 2; + Ball_dy = -Ball_dy; + } + + if(Ball_y > 600) + { + Ball_y = 600; + Ball_dy = -Ball_dy; + } + + if(Ball_x < 2) + { + Ball_x = 2; + Ball_dx = -Ball_dx; + } + + if(Ball_x > 800) + { + Ball_x = 800; + Ball_dx = -Ball_dx; + } + + if( Ball_y > 410 ) + break; + + if((Plane_y - Ball_y) < 2 && (Ball_x > (Plane_x - Plane_l)) && (Ball_x < (Plane_x + Plane_l))) + { + Ball_dy = -Ball_dy; + score++; + } + + } + + showGameOver(); + + return 0; + +} + +void HWI0_IntrHandler(void) +{ + unsigned int int_state; + int_state = RegRead(0xbf20f014); + + if((int_state & 0x10) == 0x10){ + Timer_IntrHandler(); + } + else if(int_state & 0xf){ + Button_IntrHandler(int_state & 0xf); + } +} + +void Timer_IntrHandler(void) +{ + if (!chooseFlag) + { + // refreshing the DVI output + if (score > 9) + { + setSegNum(1,score/10,1,score%10); + }else{ + setSegNum(0,0,1,score); + } + } + RegWrite(0xbf20f108,0); + RegWrite(0xbf20f108,1); +} + +void Button_IntrHandler(unsigned char button_state) +{ + if (chooseFlag) + { + if (button_state & 0b1) + { + delay_time++; + + if (delay_time > 20) + { + delay_time = 20; + } + printf("button1\n"); + RegWrite(0xbf20f00c,0x1);//clr + + }else if (button_state & 0b1000) + { + delay_time--; + if (delay_time < 1) + { + delay_time = 1; + } + printf("button4\n"); + RegWrite(0xbf20f00c,0x8);//clr + }else if (button_state & 0b100) + { + flag = 0; + printf("button3\n"); + RegWrite(0xbf20f00c,0x4);//clr + }else{ + printf("button2\n"); + RegWrite(0xbf20f00c,0x2);//clr + } + + setSegNum(1,delay_time/10,1,delay_time%10); + + } + + if (!chooseFlag) + { + + if (button_state & 0b1) + { + Plane_x += Plane_dx; + if (Plane_x + Plane_l > 800) + { + Plane_x = 800 - Plane_l; + } + RegWrite(0xbf20f00c,0x1);//clr + }else if (button_state & 0b1000) + { + Plane_x -= Plane_dx; + if (Plane_x - Plane_l < 0) + { + Plane_x = Plane_l; + } + RegWrite(0xbf20f00c,0x8);//clr + }else if (button_state & 0b0100){ + RegWrite(0xbf20f00c,0x4);//clr + }else if (button_state & 0b0010){ + RegWrite(0xbf20f00c,0x2);//clr + } + } +} + +void showGameOver(void) +{ + + printf("GameOver\n"); + + while (1) + { + setLedPin(0b1000000000000001);delay_ms(50); + setLedPin(0b1100000000000011);delay_ms(50); + setLedPin(0b1110000000000111);delay_ms(50); + setLedPin(0b1111000000001111);delay_ms(50); + setLedPin(0b1111100000011111);delay_ms(50); + setLedPin(0b1111110000111111);delay_ms(50); + setLedPin(0b1111111001111111);delay_ms(50); + setLedPin(0b1111111111111111);delay_ms(50); + setLedPin(0b1111111001111111);delay_ms(50); + setLedPin(0b1111110000111111);delay_ms(50); + setLedPin(0b1111100000011111);delay_ms(50); + setLedPin(0b1111000000001111);delay_ms(50); + setLedPin(0b1110000000000111);delay_ms(50); + setLedPin(0b1100000000000011);delay_ms(50); + setLedPin(0b1000000000000001);delay_ms(50); + } +} diff --git a/sdk/toolchains b/sdk/toolchains new file mode 120000 index 0000000..f2b6cdc --- /dev/null +++ b/sdk/toolchains @@ -0,0 +1 @@ +/opt/la32r-toolchain \ No newline at end of file diff --git a/sim/matmul_flow_tb.v b/sim/matmul_flow_tb.v new file mode 100644 index 0000000..3d23c00 --- /dev/null +++ b/sim/matmul_flow_tb.v @@ -0,0 +1,396 @@ +`timescale 1ns / 1ps +`include "config.h" + +`define UART_PSEL u_soc_top.u_axi_uart_controller.uart0.PSEL +`define UART_PENABLE u_soc_top.u_axi_uart_controller.uart0.PENABLE +`define UART_PWRITE u_soc_top.u_axi_uart_controller.uart0.PWRITE +`define UART_WADDR u_soc_top.u_axi_uart_controller.uart0.PADDR[7:0] +`define UART_WDATA u_soc_top.u_axi_uart_controller.uart0.PWDATA[7:0] + +module tb_matmul_flow; + +localparam EXTRAM_WORDS = 1048576; +localparam DONE_LEN = 11; +localparam PC_CALL_MAIN = 32'h1c0001bc; +localparam PC_MAIN_ENTRY = 32'h1c000240; +localparam PC_MATMUL_INIT = 32'h1c000274; +localparam PC_MATMUL_LOAD_LOOP = 32'h1c0002f0; +localparam PC_MATMUL_WAIT = 32'h1c00045c; +localparam PC_MATMUL_STORE = 32'h1c000480; +localparam PC_DONE_PRINTF = 32'h1c0004a8; + +reg reset; +reg clk; +reg [3:0] touch_btn; +reg [31:0] dip_sw; + +wire UART_RX; +wire UART_TX; +wire [2:0] video_red; +wire [2:0] video_green; +wire [1:0] video_blue; +wire video_hsync; +wire video_vsync; +wire video_clk; +wire video_de; +wire [15:0] leds; +wire [7:0] dpy0; +wire [7:0] dpy1; +wire [19:0] base_ram_addr; +wire [3:0] base_ram_be_n; +wire base_ram_ce_n; +wire base_ram_oe_n; +wire base_ram_we_n; +wire [19:0] ext_ram_addr; +wire [3:0] ext_ram_be_n; +wire ext_ram_ce_n; +wire ext_ram_oe_n; +wire ext_ram_we_n; +wire [31:0] base_ram_data; +wire [31:0] ext_ram_data; + +reg [31:0] expected_mem [0:EXTRAM_WORDS-1]; +reg [8*256-1:0] input_hex; +reg [8*256-1:0] expected_hex; +reg [31:0] group_num; +reg [31:0] timeout_cycles; +reg [31:0] progress_cycles; +reg [31:0] uart_shift [0:DONE_LEN-1]; +reg done_seen; +integer i; +integer err_count; +integer check_words; +integer timeout_count; +integer uart_count; +integer matmul_write_rsp_count; +integer matmul_read_rsp_count; +integer ram_read_rsp_count; +integer cpu_read_req_count; +integer cpu_write_rsp_count; +reg [31:0] last_debug_pc; +reg [31:0] same_pc_cycles; +reg main_seen; +reg matmul_access_seen; +reg done_printf_seen; +reg [8*32-1:0] phase_text; + +initial begin + clk = 1'b0; + forever #10 clk = ~clk; +end + +initial begin + input_hex = "../../../../../../tools/matmul_testdata/extram_input_4mb.hex"; + expected_hex = "../../../../../../tools/matmul_testdata/extram_expected_4mb.hex"; + group_num = 32'd10; + timeout_cycles = 32'd5000000; + progress_cycles = 32'd500000; + + if (!$value$plusargs("INPUT_HEX=%s", input_hex)) begin + end + if (!$value$plusargs("EXPECTED_HEX=%s", expected_hex)) begin + end + if (!$value$plusargs("GROUPS=%d", group_num)) begin + end + if (!$value$plusargs("TIMEOUT_CYCLES=%d", timeout_cycles)) begin + end + if (!$value$plusargs("PROGRESS_CYCLES=%d", progress_cycles)) begin + end + + reset = 1'b1; + touch_btn = 4'h0; + dip_sw = 32'h0000_abcd; + done_seen = 1'b0; + timeout_count = 0; + uart_count = 0; + matmul_write_rsp_count = 0; + matmul_read_rsp_count = 0; + ram_read_rsp_count = 0; + cpu_read_req_count = 0; + cpu_write_rsp_count = 0; + last_debug_pc = 32'b0; + same_pc_cycles = 32'b0; + main_seen = 1'b0; + matmul_access_seen = 1'b0; + done_printf_seen = 1'b0; + + for (i = 0; i < DONE_LEN; i = i + 1) begin + uart_shift[i] = 32'b0; + end + + $display("[MATMUL_TB] load ExtRAM input: %0s", input_hex); + $display("[MATMUL_TB] load expected image: %0s", expected_hex); + $display("[MATMUL_TB] groups: %0d", group_num); + $readmemh(input_hex, ext_sram_sp.BRAM); + $readmemh(expected_hex, expected_mem); + + #2000; + $display("[MATMUL_TB] release reset and start timing"); + reset = 1'b0; +end + +always @(posedge clk) begin + if (!reset && !done_seen) begin + timeout_count <= timeout_count + 1; + + if (u_soc_top.debug_wb_pc == last_debug_pc) begin + same_pc_cycles <= same_pc_cycles + 1; + end else begin + last_debug_pc <= u_soc_top.debug_wb_pc; + same_pc_cycles <= 32'b0; + end + + if (u_soc_top.cpu_arvalid && u_soc_top.cpu_arready) begin + cpu_read_req_count <= cpu_read_req_count + 1; + end + if (u_soc_top.cpu_bvalid && u_soc_top.cpu_bready) begin + cpu_write_rsp_count <= cpu_write_rsp_count + 1; + end + if (u_soc_top.ram_rvalid && u_soc_top.ram_rready) begin + ram_read_rsp_count <= ram_read_rsp_count + 1; + end + if (u_soc_top.axiOut_7_bvalid && u_soc_top.axiOut_7_bready) begin + matmul_write_rsp_count <= matmul_write_rsp_count + 1; + matmul_access_seen <= 1'b1; + end + if (u_soc_top.axiOut_7_rvalid && u_soc_top.axiOut_7_rready) begin + matmul_read_rsp_count <= matmul_read_rsp_count + 1; + matmul_access_seen <= 1'b1; + end + + if (!main_seen && (u_soc_top.debug_wb_pc >= PC_MAIN_ENTRY)) begin + main_seen <= 1'b1; + $display("[MATMUL_TB] stage: entered main at cycles=%0d pc=%08x inst=%08x", + timeout_count, u_soc_top.debug_wb_pc, u_soc_top.debug_wb_inst); + end + if (!done_printf_seen && (u_soc_top.debug_wb_pc >= PC_DONE_PRINTF) && + (u_soc_top.debug_wb_pc < 32'h1c000780)) begin + done_printf_seen <= 1'b1; + $display("[MATMUL_TB] stage: software reached MATMUL_DONE printf path at cycles=%0d pc=%08x", + timeout_count, u_soc_top.debug_wb_pc); + end + + if ((progress_cycles != 0) && (timeout_count != 0) && + ((timeout_count % progress_cycles) == 0)) begin + print_progress; + end + if (timeout_count >= timeout_cycles) begin + $display(""); + $display("[MATMUL_TB] TIMEOUT: MATMUL_DONE was not printed"); + $display("[MATMUL_TB] debug_wb_pc = %08x", u_soc_top.debug_wb_pc); + print_progress; + $display("[MATMUL_TB] matmul busy=%0d done=%0d error=%0d", + u_soc_top.u_matmul_axi_slave.busy, + u_soc_top.u_matmul_axi_slave.done, + u_soc_top.u_matmul_axi_slave.error); + $finish; + end + end +end + +soc_top #(.SIMULATION(1'b1)) u_soc_top ( + .clk (clk), + .reset (reset), + .touch_btn (touch_btn), + .dip_sw (dip_sw), + .video_red (video_red), + .video_green (video_green), + .video_blue (video_blue), + .video_hsync (video_hsync), + .video_vsync (video_vsync), + .video_clk (video_clk), + .video_de (video_de), + .leds (leds), + .dpy0 (dpy0), + .dpy1 (dpy1), + .base_ram_addr (base_ram_addr), + .base_ram_be_n (base_ram_be_n), + .base_ram_ce_n (base_ram_ce_n), + .base_ram_oe_n (base_ram_oe_n), + .base_ram_we_n (base_ram_we_n), + .ext_ram_addr (ext_ram_addr), + .ext_ram_be_n (ext_ram_be_n), + .ext_ram_ce_n (ext_ram_ce_n), + .ext_ram_oe_n (ext_ram_oe_n), + .ext_ram_we_n (ext_ram_we_n), + .base_ram_data (base_ram_data), + .ext_ram_data (ext_ram_data), + .UART_RX (UART_RX), + .UART_TX (UART_TX) +); + +sram_sp #( + .AW(20), + .Init_File(`SRAM_Init_File) +) base_sram_sp ( + .ram_addr (base_ram_addr), + .ram_be_n (base_ram_be_n), + .ram_ce_n (base_ram_ce_n), + .ram_oe_n (base_ram_oe_n), + .ram_we_n (base_ram_we_n), + .ram_data (base_ram_data) +); + +sram_sp #( + .AW(20), + .Init_File("none") +) ext_sram_sp ( + .ram_addr (ext_ram_addr), + .ram_be_n (ext_ram_be_n), + .ram_ce_n (ext_ram_ce_n), + .ram_oe_n (ext_ram_oe_n), + .ram_we_n (ext_ram_we_n), + .ram_data (ext_ram_data) +); + +wire uart_wen; +wire uart_display; +wire [7:0] uart_data; +assign uart_wen = (`UART_PSEL == 1'b1) && (`UART_PENABLE == 1'b1) && (`UART_PWRITE == 1'b1); +assign uart_display = uart_wen && (`UART_WADDR == 8'h0); +assign uart_data = `UART_WDATA; + +always @(posedge clk) begin + if (uart_display) begin + uart_count <= uart_count + 1; + $write("%c", uart_data); + for (i = 0; i < DONE_LEN-1; i = i + 1) begin + uart_shift[i] <= uart_shift[i+1]; + end + uart_shift[DONE_LEN-1] <= {24'b0, uart_data}; + + if ((uart_shift[1][7:0] == "M") && + (uart_shift[2][7:0] == "A") && + (uart_shift[3][7:0] == "T") && + (uart_shift[4][7:0] == "M") && + (uart_shift[5][7:0] == "U") && + (uart_shift[6][7:0] == "L") && + (uart_shift[7][7:0] == "_") && + (uart_shift[8][7:0] == "D") && + (uart_shift[9][7:0] == "O") && + (uart_shift[10][7:0] == "N") && + (uart_data == "E")) begin + done_seen <= 1'b1; + check_result; + end + end +end + +task update_phase_text; + begin + if (u_soc_top.debug_wb_pc == PC_CALL_MAIN) begin + if (same_pc_cycles >= progress_cycles) begin + phase_text = "STUCK_AT_CALL_MAIN"; + end else begin + phase_text = "BOOT_CALL_MAIN"; + end + end else if (u_soc_top.debug_wb_pc < PC_MAIN_ENTRY) begin + phase_text = "BOOT"; + end else if (u_soc_top.debug_wb_pc < PC_MATMUL_INIT) begin + phase_text = "MAIN_PROLOGUE"; + end else if (u_soc_top.debug_wb_pc < PC_MATMUL_LOAD_LOOP) begin + phase_text = "MATMUL_REG_INIT"; + end else if (u_soc_top.debug_wb_pc < PC_MATMUL_WAIT) begin + phase_text = "LOAD_A_B_START_HW"; + end else if (u_soc_top.debug_wb_pc < PC_MATMUL_STORE) begin + phase_text = "POLL_MATMUL_DONE"; + end else if (u_soc_top.debug_wb_pc < PC_DONE_PRINTF) begin + phase_text = "STORE_RESULTS"; + end else if (u_soc_top.debug_wb_pc < 32'h1c000780) begin + phase_text = "PRINT_DONE"; + end else begin + phase_text = "LIB_OR_TRAP"; + end + end +endtask + +task print_progress; + begin + update_phase_text; + $display("[MATMUL_TB] progress cycles=%0d phase=%0s pc=%08x inst=%08x same_pc_cycles=%0d uart_bytes=%0d", + timeout_count, phase_text, u_soc_top.debug_wb_pc, + u_soc_top.debug_wb_inst, same_pc_cycles, uart_count); + $display("[MATMUL_TB] bus cpu_ar=%0d/%0d addr=%08x cpu_aw=%0d/%0d addr=%08x cpu_w=%0d/%0d cpu_b=%0d/%0d cpu_reads=%0d cpu_write_rsps=%0d ram_r_rsps=%0d", + u_soc_top.cpu_arvalid, u_soc_top.cpu_arready, u_soc_top.cpu_araddr, + u_soc_top.cpu_awvalid, u_soc_top.cpu_awready, u_soc_top.cpu_awaddr, + u_soc_top.cpu_wvalid, u_soc_top.cpu_wready, + u_soc_top.cpu_bvalid, u_soc_top.cpu_bready, + cpu_read_req_count, cpu_write_rsp_count, ram_read_rsp_count); + $display("[MATMUL_TB] cpu_bridge ws_valid=%0d inst_req=%0d/%0d inst_addr=%08x inst_ret=%0d data_wr=%0d/%0d data_wr_addr=%08x write_state=%0d write_wait=%0d read_state=%0d b=%0d/%0d", + u_soc_top.u_cpu.ws_valid, + u_soc_top.u_cpu.inst_rd_req, + u_soc_top.u_cpu.inst_rd_rdy, + u_soc_top.u_cpu.inst_rd_addr, + u_soc_top.u_cpu.inst_ret_valid, + u_soc_top.u_cpu.data_wr_req, + u_soc_top.u_cpu.data_wr_rdy, + u_soc_top.u_cpu.data_wr_addr, + u_soc_top.u_cpu.axi_bridge.write_requst_state, + u_soc_top.u_cpu.axi_bridge.write_wait_enable, + u_soc_top.u_cpu.axi_bridge.read_requst_state, + u_soc_top.u_cpu.bvalid, + u_soc_top.u_cpu.bready); + $display("[MATMUL_TB] uart_axi aw=%0d/%0d addr=%08x w=%0d/%0d strb=%x data=%08x b=%0d/%0d sel_wr=%0d apb_psel=%0d penable=%0d pwrite=%0d paddr=%02x", + u_soc_top.u_axi_uart_controller.axi_s_awvalid, + u_soc_top.u_axi_uart_controller.axi_s_awready, + u_soc_top.u_axi_uart_controller.axi_s_awaddr, + u_soc_top.u_axi_uart_controller.axi_s_wvalid, + u_soc_top.u_axi_uart_controller.axi_s_wready, + u_soc_top.u_axi_uart_controller.axi_s_wstrb, + u_soc_top.u_axi_uart_controller.axi_s_wdata, + u_soc_top.u_axi_uart_controller.axi_s_bvalid, + u_soc_top.u_axi_uart_controller.axi_s_bready, + u_soc_top.u_axi_uart_controller.AA_axi2apb_bridge_cpu.axi_s_sel_wr, + u_soc_top.u_axi_uart_controller.uart0.PSEL, + u_soc_top.u_axi_uart_controller.uart0.PENABLE, + u_soc_top.u_axi_uart_controller.uart0.PWRITE, + u_soc_top.u_axi_uart_controller.uart0.PADDR); + $display("[MATMUL_TB] matmul busy=%0d done=%0d error=%0d access_seen=%0d write_rsps=%0d read_rsps=%0d axi7_aw=%0d/%0d addr=%08x axi7_w=%0d/%0d axi7_b=%0d/%0d axi7_ar=%0d/%0d addr=%08x axi7_r=%0d/%0d", + u_soc_top.u_matmul_axi_slave.busy, + u_soc_top.u_matmul_axi_slave.done, + u_soc_top.u_matmul_axi_slave.error, + matmul_access_seen, + matmul_write_rsp_count, + matmul_read_rsp_count, + u_soc_top.axiOut_7_awvalid, + u_soc_top.axiOut_7_awready, + u_soc_top.axiOut_7_awaddr, + u_soc_top.axiOut_7_wvalid, + u_soc_top.axiOut_7_wready, + u_soc_top.axiOut_7_bvalid, + u_soc_top.axiOut_7_bready, + u_soc_top.axiOut_7_arvalid, + u_soc_top.axiOut_7_arready, + u_soc_top.axiOut_7_araddr, + u_soc_top.axiOut_7_rvalid, + u_soc_top.axiOut_7_rready); + end +endtask + +task check_result; + begin + $display(""); + $display("[MATMUL_TB] MATMUL_DONE captured after %0d clk cycles", timeout_count); + + err_count = 0; + check_words = group_num * 80; + for (i = 0; i < check_words; i = i + 1) begin + if (ext_sram_sp.BRAM[i] !== expected_mem[i]) begin + if (err_count < 16) begin + $display("[MATMUL_TB] mismatch word[%0d]: got=%08x expected=%08x", + i, ext_sram_sp.BRAM[i], expected_mem[i]); + end + err_count = err_count + 1; + end + end + + if (err_count == 0) begin + $display("[MATMUL_TB] PASS: source and result regions match expected image"); + end else begin + $display("[MATMUL_TB] FAIL: %0d mismatched words", err_count); + end + $finish; + end +endtask + +endmodule diff --git a/sim/mycpu_tb.v b/sim/mycpu_tb.v new file mode 100644 index 0000000..fc29a0b --- /dev/null +++ b/sim/mycpu_tb.v @@ -0,0 +1,230 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ +`timescale 1ns / 1ps +`include "config.h" +// `define FFT_OUTPUT_TXT + +`define UART_PSEL u_soc_top.u_axi_uart_controller.uart0.PSEL +`define UART_PENBLE u_soc_top.u_axi_uart_controller.uart0.PENABLE +`define UART_PWRITE u_soc_top.u_axi_uart_controller.uart0.PWRITE +`define UART_WADDR u_soc_top.u_axi_uart_controller.uart0.PADDR[7:0] +`define UART_WDATA u_soc_top.u_axi_uart_controller.uart0.PWDATA[7:0] +`define END_PC 32'h1c000200 + +module tb_top( ); +reg reset; +reg clk; +reg [3:0] touch_btn; +reg [31:0] dip_sw; + +wire UART_RX; +wire UART_TX; +wire [2:0] video_red; +wire [2:0] video_green; +wire [1:0] video_blue; +wire video_hsync; +wire video_vsync; +wire video_clk; +wire video_de; +wire [15:0] leds; +wire [7:0] dpy0; +wire [7:0] dpy1; +wire [19:0] base_ram_addr; +wire [ 3:0] base_ram_be_n; +wire base_ram_ce_n; +wire base_ram_oe_n; +wire base_ram_we_n; +wire [19:0] ext_ram_addr; +wire [ 3:0] ext_ram_be_n; +wire ext_ram_ce_n; +wire ext_ram_oe_n; +wire ext_ram_we_n; +wire [31:0] base_ram_data; +wire [31:0] ext_ram_data; + +//产生时钟与复位信号 +initial begin + clk = 1'b0; + reset = 1'b1; + dip_sw = 32'h0; + #2000; + reset = 1'b0; +end +always #10 clk=~clk; + +//产生按键信号 +initial begin + touch_btn = 4'h0; + dip_sw = 32'h0000_abcd; + + #3000000; + + #100000 + touch_btn = 4'b0001; + #50 + touch_btn = 4'b0000; + + #100000 + touch_btn = 4'b0010; + #50 + touch_btn = 4'b0000; + + #100000 + touch_btn = 4'b0100; + #50 + touch_btn = 4'b0000; + + #100000 + touch_btn = 4'b1000; + #50 + touch_btn = 4'b0000; + +end + +soc_top #(.SIMULATION(1'b1)) u_soc_top ( + .clk ( clk ), + .reset ( reset ), + .touch_btn ( touch_btn ), + .dip_sw ( dip_sw ), + + .video_red ( video_red ), + .video_green ( video_green ), + .video_blue ( video_blue ), + .video_hsync ( video_hsync ), + .video_vsync ( video_vsync ), + .video_clk ( video_clk ), + .video_de ( video_de ), + .leds ( leds ), + .dpy0 ( dpy0 ), + .dpy1 ( dpy1 ), + + .base_ram_addr ( base_ram_addr ), + .base_ram_be_n ( base_ram_be_n ), + .base_ram_ce_n ( base_ram_ce_n ), + .base_ram_oe_n ( base_ram_oe_n ), + .base_ram_we_n ( base_ram_we_n ), + .ext_ram_addr ( ext_ram_addr ), + .ext_ram_be_n ( ext_ram_be_n ), + .ext_ram_ce_n ( ext_ram_ce_n ), + .ext_ram_oe_n ( ext_ram_oe_n ), + .ext_ram_we_n ( ext_ram_we_n ), + + .base_ram_data ( base_ram_data ), + .ext_ram_data ( ext_ram_data ), + + .UART_RX ( UART_RX ), + .UART_TX ( UART_TX ) +); + +sram_sp #( + .AW ( 18 ), + .Init_File(`SRAM_Init_File)) +base_sram_sp ( + .ram_addr ( base_ram_addr ), + .ram_be_n ( base_ram_be_n ), + .ram_ce_n ( base_ram_ce_n ), + .ram_oe_n ( base_ram_oe_n ), + .ram_we_n ( base_ram_we_n ), + + .ram_data ( base_ram_data ) +); + +sram_sp #( + .AW ( 18 ), + .Init_File(`SRAM_Init_File)) +ext_sram_sp ( + .ram_addr ( ext_ram_addr ), + .ram_be_n ( ext_ram_be_n ), + .ram_ce_n ( ext_ram_ce_n ), + .ram_oe_n ( ext_ram_oe_n ), + .ram_we_n ( ext_ram_we_n ), + + .ram_data ( ext_ram_data ) +); + +//模拟串口打印 +wire uart_display; +wire [7:0] uart_data; +wire uart_wen; +assign uart_wen = (`UART_PSEL == 1'b1) && (`UART_PENBLE == 1'b1) && (`UART_PWRITE == 1'b1); +assign uart_display = (uart_wen == 1'b1) && (`UART_WADDR == 8'h0); +assign uart_data = `UART_WDATA; + +always @(posedge clk) +begin + if(uart_display) + begin + if(uart_data==8'hff) + begin + ;//$finish; + end + else + begin + $write("%c",uart_data); + end + end +end + +//仿真结束 +wire [31:0] debug_wb_pc; +assign debug_wb_pc = u_soc_top.debug_wb_pc; +wire test_end = debug_wb_pc==`END_PC; +always @(posedge u_soc_top.cpu_clk) +begin + if (!u_soc_top.cpu_resetn) begin + end + else if(test_end) begin + $display("=============================================================="); + $display("Test end!"); + $finish; + end +end + +//FFT测试结果输出 +`ifdef FFT_OUTPUT_TXT + integer fft_output_re; + integer fft_output_im; + initial begin + fft_output_re = $fopen("../../../../../../python/fft512_output_re.txt", "w"); + fft_output_im = $fopen("../../../../../../python/fft512_output_im.txt", "w"); + forever begin + @(posedge u_soc_top.u_axi_fft_top.u_axi_fft_wrap.aclk); + if(u_soc_top.u_axi_fft_top.u_axi_fft_wrap.valid_out) begin + $fwrite(fft_output_re, "%04h\n", u_soc_top.u_axi_fft_top.u_axi_fft_wrap.y_re); + $fwrite(fft_output_im, "%04h\n", u_soc_top.u_axi_fft_top.u_axi_fft_wrap.y_im); + end + end + end +`endif + +endmodule diff --git a/sim/sram.v b/sim/sram.v new file mode 100644 index 0000000..8f2ace7 --- /dev/null +++ b/sim/sram.v @@ -0,0 +1,52 @@ +`timescale 1ns/100ps +module sram_sp #( + parameter AW = 16, + parameter Init_File = "none" +) +( + inout [31:0] ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享 + input [19:0] ram_addr, //BaseRAM地址 + input [ 3:0] ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0 + input ram_ce_n, //BaseRAM片选，低有效 + input ram_oe_n, //BaseRAM读使能，低有效 + input ram_we_n //BaseRAM写使能，低有效 + +); + localparam AWT = ((1<<(AW-0))-1); + + reg [31:0] BRAM [AWT:0]; + + initial begin + if(Init_File != "none") begin + $readmemb(Init_File,BRAM); + end + end + + reg [AW-1:0] addr_q1; + wire [3:0] write_enable; + + assign write_enable[3:0] = (~ram_be_n) & {4{(~ram_ce_n) & (~ram_we_n)}}; + + + always@(posedge write_enable[0]) begin + #10; + if(~ram_be_n[0]) BRAM[ram_addr][7:0] <= ram_data[7:0]; + end + always@(posedge write_enable[1]) begin + #10; + if(~ram_be_n[1]) BRAM[ram_addr][15:8] <= ram_data[15:8]; + end + always@(posedge write_enable[2]) begin + #10; + if(~ram_be_n[2]) BRAM[ram_addr][23:16] <= ram_data[23:16]; + end + always@(posedge write_enable[3]) begin + #10; + if(~ram_be_n[3]) BRAM[ram_addr][31:24] <= ram_data[31:24]; + end + + wire [31:0] RDATA = BRAM[ram_addr]; + + assign ram_data = ((~ram_ce_n) & (~ram_oe_n)) ? RDATA : 32'hzzzzzzzz; + +endmodule diff --git a/tools/generate_matmul_testdata.py b/tools/generate_matmul_testdata.py new file mode 100644 index 0000000..bbcdf81 --- /dev/null +++ b/tools/generate_matmul_testdata.py @@ -0,0 +1,164 @@ +#!/usr/bin/env python3 +import argparse +import json +import random +import struct +from pathlib import Path + + +def u32(value): + return value & 0xFFFFFFFF + + +def split_u66(value): + return [ + value & 0xFFFFFFFF, + (value >> 32) & 0xFFFFFFFF, + (value >> 64) & 0x3, + ] + + +def matmul4x4(a, b): + c = [] + for row in range(4): + for col in range(4): + acc = 0 + for k in range(4): + acc += a[row * 4 + k] * b[k * 4 + col] + c.append(acc) + return c + + +def write_words_bin(path, words): + with path.open("wb") as f: + for word in words: + f.write(struct.pack(" max_groups: + raise SystemExit(f"--groups={args.groups} does not fit in {args.memory_bytes} bytes; max is {max_groups}") + if args.max_value < 0 or args.max_value > 0xFFFFFFFF: + raise SystemExit("--max-value must be in range 0..0xffffffff") + + rng = random.Random(args.seed) + vectors, source_words, result_words = build_vectors( + args.groups, rng, args.max_value, args.dump_vectors, not args.no_zero_matrix + ) + dst_base_word = len(source_words) + result_end_word = dst_base_word + len(result_words) + + input_image_words = [0] * memory_words + expected_image_words = [0] * memory_words + input_image_words[0:len(source_words)] = source_words + expected_image_words[0:len(source_words)] = source_words + expected_image_words[dst_base_word:result_end_word] = result_words + + args.out_dir.mkdir(parents=True, exist_ok=True) + write_words_bin(args.out_dir / "matmul_source_ab.bin", source_words) + write_words_bin(args.out_dir / "matmul_expected_c.bin", result_words) + write_words_bin(args.out_dir / "extram_input_4mb.bin", input_image_words) + write_words_bin(args.out_dir / "extram_expected_4mb.bin", expected_image_words) + write_words_hex(args.out_dir / "matmul_source_ab.hex", source_words) + write_words_hex(args.out_dir / "matmul_expected_c.hex", result_words) + write_words_hex(args.out_dir / "extram_input_4mb.hex", input_image_words) + write_words_hex(args.out_dir / "extram_expected_4mb.hex", expected_image_words) + + metadata = { + "groups": args.groups, + "seed": args.seed, + "max_value": args.max_value, + "zero_matrix_group": None if args.no_zero_matrix else 0, + "memory_bytes": args.memory_bytes, + "memory_words": memory_words, + "max_groups_for_memory": max_groups, + "source_words": len(source_words), + "result_words": len(result_words), + "src_base_offset": 0, + "dst_base_offset": dst_base_word * 4, + "unused_tail_words": memory_words - result_end_word, + "bytes_per_source_group": 128, + "bytes_per_result_group": 192, + "input_image": "source region filled, result region and unused tail filled with 0", + "expected_image": "source region preserved, result region filled, unused tail filled with 0", + "layout": "A0,B0,A1,B1,...,A(n-1),B(n-1),C0,C1,...,C(n-1),zero padding", + } + if args.dump_vectors: + metadata["vectors"] = vectors + (args.out_dir / "matmul_vectors.json").write_text( + json.dumps(metadata, indent=2), encoding="utf-8" + ) + + print(f"generated {args.groups} groups in {args.out_dir}") + print(f"memory size: {args.memory_bytes} bytes ({memory_words} words)") + print("SRC_BASE offset: 0") + print(f"DST_BASE offset: {dst_base_word * 4}") + print(f"unused tail: {memory_words - result_end_word} words") + print("input image: extram_input_4mb.bin / extram_input_4mb.hex") + print("expected image: extram_expected_4mb.bin / extram_expected_4mb.hex") + + +if __name__ == "__main__": + main()

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DaJB$o literal 0 HcmV?d00001 diff --git a/doc/matmul_ip_spec.md b/doc/matmul_ip_spec.md new file mode 100644 index 0000000..61c68b1 --- /dev/null +++ b/doc/matmul_ip_spec.md @@ -0,0 +1,137 @@ +# 集成电路创新创业大赛 龙芯中科杯 阶段任务三 矩阵乘法器 IP 设计说明 + +## 1. 参赛任务与设计自由度 + +本题希望参赛者在保证测试流程能够正确运行的前提下，获得尽可能大的设计自由度。参赛者可以自行决定矩阵乘法器的内部微结构、是否实现 DMA、CPU 与加速器之间的数据搬运方式、批量计算调度方式以及 C 程序中的驱动策略。 + +参赛者至少需要设计两部分内容： + +1. **乘法加速器**：在 `rtl/` 中实现并接入 SoC 的矩阵乘法硬件 IP。 +2. **C 程序**：运行在 SoC CPU 上，负责按数据布局读取输入、配置并启动加速器、等待计算完成，并将结果写回 ExtRAM 中的指定结果区域。 + +无论内部实现如何，最终都必须满足本文定义的数据布局、结果格式和测试流程要求。测试只关心程序能否在解除复位后正确运行，并在串口输出完成标志后，从 ExtRAM 中读取到正确结果。 + +## 2. 设计目标与接口 + +参赛者需要设计一个矩阵乘法器 IP，用于完成： + +```text +C = A x B +``` + +矩阵最大规模为 `4x4 * 4x4`。对于较小规模矩阵，例如 `2x3 * 3x2`，仍使用 4x4 数据槽位存储，未使用位置填 0，硬件可按统一的 4x4 规则计算，不影响有效结果。 + +每个输入元素为 32 bit。若采用无符号计算，每个输出元素为 4 项 32x32 乘积累加结果，结果宽度为 66 bit。实现中不得使用 FPGA DSP 资源，乘法运算应由 LUT、寄存器、加法器、移位器等基础逻辑构成。 + +矩阵乘法器 IP 固定作为 AXI slave 外设接入 SoC 的 `axiOut_7` 位置，由 CPU 通过 memory-mapped register 方式进行配置、启动和查询。寄存器接口可以按参赛者实现需要进行扩展或调整，但软件程序必须能够配合该接口完成测试任务。 + +## 3. RAM 数据布局 + +测试使用 ExtRAM 存放源矩阵和结果矩阵。数据采用“源数据连续区 + 结果连续区”的批量布局：前部连续存放 n 组源矩阵 A/B，排列方式为 `A0, B0, A1, B1, ... A(n-1), B(n-1)`；后部连续存放 n 组结果矩阵 C。 + +每组源数据占： + +```text +A: 16 word = 64 Byte +B: 16 word = 64 Byte +A + B: 32 word = 128 Byte +``` + +每组结果数据占： + +```text +C: 16 * 3 word = 48 word = 192 Byte +``` + +因此每组完整数据总占用： + +```text +(1 + 1 + 3) * 16 * 32 bit = 80 word = 320 Byte +``` + +批量布局如下： + +```text +SRC_BASE + 0 * 128: + group0_A[16] + group0_B[16] + +SRC_BASE + 1 * 128: + group1_A[16] + group1_B[16] + +... + +SRC_BASE + (n - 1) * 128: + group(n-1)_A[16] + group(n-1)_B[16] + +DST_BASE: + group0_C[48] + group1_C[48] + ... + group(n-1)_C[48] +``` + +第 i 组矩阵的地址计算规则为： + +```text +A_i = SRC_BASE + i * 128 +B_i = SRC_BASE + i * 128 + 64 +C_i = DST_BASE + i * 192 +``` + +默认可令： + +```text +DST_BASE = SRC_BASE + n * 128 +``` + +即结果区紧跟在 n 组源数据之后。IP 不应假设源区和结果区必须相邻，DMA 模式下应以 `SRC_BASE` 和 `DST_BASE` 寄存器为准。 + +矩阵 A、B 均按 row-major 存储，每个元素占 1 个 32 bit word： + +```text +A[0][0], A[0][1], A[0][2], A[0][3], +A[1][0], ... +A[3][3] +``` + +矩阵 C 同样按 row-major 存储，每个元素占 3 个 32 bit word，用于保存 66 bit 结果： + +```text +C[i][j] word0 = result[31:0] +C[i][j] word1 = result[63:32] +C[i][j] word2 = {30'b0, result[65:64]} +``` + +## 4. 测试流程 + +测试流程如下： + +1. 保持 SoC 处于复位状态。 +2. 测试平台向存储器写入待运行程序和矩阵输入数据。 +3. 解除 SoC 复位，同时开始计时。 +4. SoC CPU 运行参赛者编写的 C 程序。程序应完成输入数据读取、加速器配置、矩阵乘法计算调度、结果写回以及完成通知。 +5. 测试平台监听串口输出。当串口输出约定的特定字符串时，停止计时。 +6. 停止计时后，测试平台读取 ExtRAM 中的结果数据，并按本文定义的结果布局进行校验。 + +因此，C 程序必须在所有矩阵结果已经写回 ExtRAM 后，再通过串口输出完成标志。若提前输出完成标志，测试平台会立即停止计时并读取结果，可能导致校验失败。 + +## 5. 发布包环境修改 + +发布包工程保持统一顶层引脚约束，使用提供的 `fpga/constraints/soc.xdc`。参赛者不需要、也不应修改板级引脚约束。 + +工程需要在 SoC 顶层中为矩阵乘法器预留接入点： + +1. 将矩阵乘法器 IP 的 AXI slave 接口连接到 `AxiCrossbar_2x8` 的 `axiOut_7`。 +2. 为矩阵乘法器分配地址空间 `0x1f50_0000`，对应 crossbar slave7。 +3. 若支持 DMA，可将矩阵乘法器的 AXI master 接口连接到当前预留的 master1 通路。 +4. 保留 BaseRAM/ExtRAM 的统一连接方式。BaseRAM 可用于存放程序指令，ExtRAM 用于存放源矩阵和结果矩阵。 +5. 软件 BSP 中增加矩阵乘法器寄存器基地址和驱动接口，例如： + +```c +#define MATMUL_BASE 0x1f500000 +``` + +硬件部分建议限制为 `rtl/` 目录内文件替换或新增；软件部分应提供用于运行矩阵任务的 C 程序及必要的 BSP/驱动适配。工程、引脚约束、测试框架和资源检查流程保持统一，以保证结果可复现。 diff --git a/fpga/check_dsp.py b/fpga/check_dsp.py new file mode 100644 index 0000000..b0ff3a7 --- /dev/null +++ b/fpga/check_dsp.py @@ -0,0 +1,59 @@ +#!/usr/bin/env python3 +import os +import re +import sys +from pathlib import Path +from typing import List + + +def usage() -> None: + print("Usage: python3 check_dsp.py [max-dsp]", file=sys.stderr) + + +def extract_dsp_used(report: Path) -> int: + if not report.is_file(): + raise FileNotFoundError(f"DSP utilization report not found: {report}") + + used_values = [] + for line in report.read_text(errors="replace").splitlines(): + stripped = line.strip() + if not stripped.startswith("|") or "DSP" not in stripped.upper(): + continue + + columns = [col.strip() for col in stripped.strip("|").split("|")] + if len(columns) < 2: + continue + if not re.fullmatch(r"DSPs?", columns[0], re.IGNORECASE): + continue + + match = re.fullmatch(r"\d+", columns[1]) + if match: + used_values.append(int(match.group(0))) + + if not used_values: + raise ValueError(f"No DSP utilization row found in {report}") + + return max(used_values) + + +def main(argv: List[str]) -> int: + if len(argv) not in (2, 3): + usage() + return 2 + + report = Path(argv[1]) + max_allowed = int(argv[2]) if len(argv) == 3 else int(os.environ.get("DSP_MAX", "0")) + used = extract_dsp_used(report) + print(f"DSP used: {used}, allowed: {max_allowed}") + if used > max_allowed: + print(f"ERROR: DSP usage {used} exceeds allowed limit {max_allowed}", file=sys.stderr) + return 1 + return 0 + + +if __name__ == "__main__": + try: + sys.exit(main(sys.argv)) + except Exception as exc: + print(f"ERROR: {exc}", file=sys.stderr) + sys.exit(1) diff --git a/fpga/create_project.tcl b/fpga/create_project.tcl new file mode 100644 index 0000000..b7f5988 --- /dev/null +++ b/fpga/create_project.tcl @@ -0,0 +1,24 @@ +# SET PROJECT NAME +set project_name Loongson_Soc +set project_path ./project +set project_part xc7a200tfbg676-1 +# CLEAR +file delete -force $project_path + +create_project -force $project_name $project_path -part $project_part + +# Add conventional sources +add_files -scan_for_includes ../rtl + +# Add IPs +add_files -norecurse -scan_for_includes ../rtl/ip/PLL_2019_2/clk_pll.xci + +# Add simulation files +add_files -fileset sim_1 ../sim/ + +# Add constraints +add_files -fileset constrs_1 -quiet ./constraints + +set_property top soc_top [current_fileset] +set_property -name "top" -value "tb_top" -objects [get_filesets sim_1] +set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1] diff --git a/fpga/generate_bit.tcl b/fpga/generate_bit.tcl new file mode 100644 index 0000000..a3d8ee9 --- /dev/null +++ b/fpga/generate_bit.tcl @@ -0,0 +1,26 @@ +# open project +open_project project/Loongson_Soc.xpr + +# generate Bitstream +launch_runs impl_1 -to_step write_bitstream +wait_on_run impl_1 + +set impl_run [get_runs impl_1] +set impl_progress [get_property PROGRESS $impl_run] +set impl_status [get_property STATUS $impl_run] +puts "impl_1 progress: $impl_progress" +puts "impl_1 status: $impl_status" + +set bit_files [glob -nocomplain project/Loongson_Soc.runs/impl_1/*.bit] +if {[llength $bit_files] == 0} { + puts "ERROR: Bitstream file was not generated!" + exit 1 +} + +puts "Generated bitstream files:" +foreach bit_file $bit_files { + puts " $bit_file" +} + +close_project +exit 0 diff --git a/fpga/run-linter.py b/fpga/run-linter.py new file mode 100644 index 0000000..1959d92 --- /dev/null +++ b/fpga/run-linter.py @@ -0,0 +1,288 @@ +#!/usr/bin/env python3 +from lxml import etree +import chardet +import sys +import os +from pathlib import Path +from typing import Tuple, List, Set +import shutil +import subprocess +import tempfile +import traceback +import re + +def usage(): + print("Usage: python3 run-linter.py ", file=sys.stderr) + +def is_header(f: Path): + with f.open('rb') as fd: + return -1 == fd.read().find(b'endmodule') + +def transcoding(src: Path, target: Path): + with src.open("rb") as fd: + rawdata = fd.read() + res = chardet.detect(rawdata) + detected = res['encoding'] if res['confidence'] > 0.5 else None + encodings = ["utf-8", "gb18030"] + if detected and detected.lower() not in ("utf-8", "gb18030"): + encodings.append(detected) + + for encoding in encodings: + try: + s = rawdata.decode(encoding) + break + except UnicodeDecodeError: + continue + else: + print("Transcoding", src, "with replacement characters") + s = rawdata.decode("utf-8", "replace") + with target.open("wb") as wfd: + wfd.write(s.encode('utf-8')) + +def parse_project(xpr: Path) -> Tuple[str, Set[str], Set[str], Set[str]]: + prjname = os.path.splitext(xpr.name)[0] + prjdir = xpr.parent.resolve() + repo_root = prjdir.parent.parent + srcdir = prjdir / (prjname + ".srcs") + topname = '' + target = prjdir / '.lint' + + tree = etree.parse(str(xpr)) + srclist = set() + headerlist = set() + inclist = set() + skipped_ip_count = 0 + for fileset in tree.xpath("/Project/FileSets/FileSet"): + if fileset.attrib['Type'] != 'DesignSrcs' and \ + fileset.attrib['Type'] != 'BlockSrcs': + continue + for child in fileset: + if child.tag == 'File': + tmp = child.attrib['Path'] + if tmp.endswith((".xci", ".xcix")): + skipped_ip_count += 1 + continue + tmp = tmp.replace('$PSRCDIR', str(srcdir)) + tmp = tmp.replace('$PPRDIR', str(prjdir)) + vlog = Path(tmp).resolve() + if not vlog.is_file(): + print("Source file", vlog, "does not exist") + continue + vlog_target = target / vlog.relative_to(repo_root) + vlog_target.parent.mkdir(exist_ok=True, parents=True) + # shutil.copy(vlog, vlog_target) + transcoding(vlog, vlog_target) + inclist.add(str(vlog_target.parent)) + if is_header(vlog_target): + headerlist.add(str(vlog_target)) + else: + srclist.add(str(vlog_target)) + elif child.tag == 'Config' and fileset.attrib['Type'] == 'DesignSrcs': + topname = child.xpath("./Option[@Name='TopModule']")[0].attrib['Val'] + + return (topname, headerlist, srclist, inclist) + +def verilator_supports_warning(verilator: str, env, warning: str) -> bool: + with tempfile.TemporaryDirectory() as tmpdir: + probe = Path(tmpdir) / "verilator_warning_probe.v" + probe.write_text("module verilator_warning_probe; endmodule\n", encoding="utf-8") + res = subprocess.run( + [verilator, "--lint-only", "-Wno-" + warning, str(probe)], + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + universal_newlines=True, + env=env, + ) + return "Unknown warning specified" not in res.stdout + +def strip_verilog_comments(text: str) -> str: + text = re.sub(r"/\*.*?\*/", "", text, flags=re.S) + return re.sub(r"//.*", "", text) + +def find_module_body(text: str, module_name: str) -> str: + pattern = re.compile(r"\bmodule\s+" + re.escape(module_name) + r"\b.*?\bendmodule\b", re.S) + m = pattern.search(text) + return m.group(0) if m else "" + +def find_top_source(topname: str, srclist: Set[str]) -> Tuple[Path, str]: + module_re = re.compile(r"\bmodule\s+" + re.escape(topname) + r"\b") + for src in sorted(srclist): + path = Path(src) + text = path.read_text(encoding="utf-8", errors="replace") + if module_re.search(strip_verilog_comments(text)): + return path, text + return Path(), "" + +def module_is_instantiated(module_name: str, text: str) -> bool: + code = strip_verilog_comments(text) + pattern = re.compile( + r"(? Tuple[dict, dict]: + module_sources = {} + module_bodies = {} + for src in sorted(sources): + path = Path(src) + text = path.read_text(encoding="utf-8", errors="replace") + code = strip_verilog_comments(text) + for m in re.finditer(r"\bmodule\s+([A-Za-z_][A-Za-z0-9_$]*)\b.*?\bendmodule\b", code, re.S): + name = m.group(1) + module_sources.setdefault(name, path) + module_bodies.setdefault(name, m.group(0)) + return module_sources, module_bodies + +def find_instantiated_modules(text: str, module_names: Set[str]) -> Set[str]: + return { + module + for module in module_names + if module_is_instantiated(module, text) + } + +def find_reachable_modules(topname: str, module_bodies: dict) -> Set[str]: + reachable = set() + pending = [topname] + module_names = set(module_bodies) + while pending: + module = pending.pop() + if module in reachable: + continue + reachable.add(module) + body = module_bodies.get(module, "") + for child in find_instantiated_modules(body, module_names - reachable): + pending.append(child) + return reachable + +def run_design_sanity_checks(prjdir: Path, topname: str, srclist: Set[str]): + issues = [] + top_source, top_text = find_top_source(topname, srclist) + if not top_text: + issues.append("Top module '{}' was not found in lint source set.".format(topname)) + else: + for lineno, line in enumerate(top_text.splitlines(), start=1): + if "add your code" in line.lower(): + issues.append( + "{}:{}: template placeholder remains in top module; the SoC integration is likely incomplete.".format( + top_source, lineno + ) + ) + + module_sources, module_bodies = extract_module_definitions(srclist) + reachable_modules = find_reachable_modules(topname, module_bodies) + unreachable_modules = sorted(set(module_bodies) - reachable_modules) + if len(module_bodies) >= 20 and len(unreachable_modules) > len(module_bodies) // 2: + shown_modules = ", ".join(unreachable_modules[:12]) + if len(unreachable_modules) > 12: + shown_modules += ", ..." + issues.append( + "{}: only {} of {} project modules are reachable from top '{}'; unreachable modules include: {}.".format( + top_source, + len(reachable_modules & set(module_bodies)), + len(module_bodies), + topname, + shown_modules, + ) + ) + + if issues: + sanity_log = prjdir / "linter-sanity.log" + sanity_log.write_text("\n".join(issues) + "\n", encoding="utf-8") + print("HDL sanity check failed.") + for issue in issues: + print(issue) + print("Full log:", sanity_log) + sys.exit(1) + +def run_linter(prjdir: Path, topname: str, headerlist: Set[str], srclist: Set[str], inclist: Set[str]): + linter_log = prjdir / "linter.log" + linter_args = prjdir / "linter.args" + verilator = os.environ.get("VERILATOR") or shutil.which("verilator") or shutil.which("verilator_bin.exe") + if not verilator: + print("ERROR: verilator was not found in PATH.", file=sys.stderr) + print("Install verilator in the CI image, set VERILATOR, or remove the HDL lint step from .gitlab-ci.yml.", file=sys.stderr) + sys.exit(127) + + env = os.environ.copy() + if os.name == "nt" and "VERILATOR_ROOT" not in env: + verilator_root = Path(verilator).resolve().parent.parent / "share" / "verilator" + if verilator_root.is_dir(): + env["VERILATOR_ROOT"] = str(verilator_root) + + timescale_warning = None + for warning in ("TIMESCALEMOD", "TIMESCALE"): + if verilator_supports_warning(verilator, env, warning): + timescale_warning = warning + break + + args = [ + verilator, + "--lint-only", + "-Wall", + "-Wno-fatal", + "-Wno-DECLFILENAME", + "-Wno-PINCONNECTEMPTY", + "-Wno-UNUSED", + "-GSIMULATION=1", + ] + if timescale_warning: + args.append("-Wno-" + timescale_warning) + args += ['--top-module', topname] + incargs = [ '-I' + i for i in inclist] + args += incargs + args += sorted(headerlist) + args += srclist + + if os.name == "nt": + response_args = [str(arg).replace("\\", "/") for arg in args[1:]] + linter_args.write_text("\n".join(response_args) + "\n", encoding="utf-8") + run_args = [verilator, "-f", str(linter_args)] + else: + run_args = args + + with linter_log.open("w", encoding="utf-8") as log: + res = subprocess.run(run_args, stdout=log, stderr=subprocess.STDOUT, env=env) + if res.returncode != 0: + log_text = linter_log.read_text(encoding="utf-8", errors="replace") + error_lines = [ + line for line in log_text.splitlines() + if "%Error" in line or "Error:" in line or "ERROR:" in line + ] + print("HDL lint failed.") + if error_lines: + print("Key errors:") + for line in error_lines[:20]: + print(line) + if len(error_lines) > 20: + print("... {} more error lines omitted".format(len(error_lines) - 20)) + else: + print("No explicit error line found in Verilator output.") + print("Return code:", res.returncode) + print("Full log:", linter_log) + sys.exit(res.returncode) + print("HDL lint passed.") + +if __name__ == "__main__": + try: + if len(sys.argv) != 2: + usage() + sys.exit(2) + xpr = Path(sys.argv[1]) + if not xpr.is_file(): + print("Vivado project file does not exist:", xpr, file=sys.stderr) + sys.exit(2) + topname, headerlist, srclist, inclist = parse_project(xpr) + if not topname: + print("Top module was not found in project:", xpr, file=sys.stderr) + sys.exit(1) + if not srclist: + print("No Verilog source files were found in project:", xpr, file=sys.stderr) + sys.exit(1) + run_design_sanity_checks(xpr.parent, topname, srclist) + run_linter(xpr.parent, topname, headerlist, srclist, inclist) + except Exception: + traceback.print_exc() + sys.exit(1) diff --git a/fpga/run_impl.tcl b/fpga/run_impl.tcl new file mode 100644 index 0000000..7182fed --- /dev/null +++ b/fpga/run_impl.tcl @@ -0,0 +1,32 @@ +# bit.tcl +open_project project/Loongson_Soc.xpr + +# Add myCPU +# add_files -scan_for_includes mysrc + +# Add xilinx_ip in myCPU +# add_files -quiet [glob -nocomplain mysrc/xilinx_ip/*/*.xci] +# add_files -quiet [glob -nocomplain mysrc/xilinx_ip/*/*.xcix] + +# Upgrade IPs +upgrade_ip -quiet [get_ips] + +# run_impl +launch_runs impl_1 +wait_on_run impl_1 + +# check impl status +if {[get_property PROGRESS [get_runs impl_1]] != "100%"} { + puts "ERROR: Implementation failed!" + exit 1 +} + +# open_run impl_1 +open_run impl_1 +report_utilization -file project/dsp_utilization.rpt -pb project/dsp_utilization.pb + +# report_timing_summary -delay_type min_max -report_unconstrained \ +# -file lab/lab1.runs/impl_1/timing_summary.rpt + +close_project +exit 0 \ No newline at end of file diff --git a/rtl/config.h b/rtl/config.h new file mode 100644 index 0000000..5e0bd9f --- /dev/null +++ b/rtl/config.h @@ -0,0 +1,94 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +`define SRAM_Init_File "../../../../../../sdk/axi_ram.mif" + +`define USE_CACHE + +`define Lawcmd 4 +`define Lawdirqid 4 +`define Lawstate 2 +`define Lawscseti 2 +`define Lawid 4 +`define Lawaddr 32 +`define Lawlen 8 +`define Lawsize 3 +`define Lawburst 2 +`define Lawlock 2 +`define Lawcache 4 +`define Lawprot 3 +`define Lawvalid 1 +`define Lawready 1 +`define Lwid 4 +`define Lwdata 32 +`define Lwstrb 4 +`define Lwlast 1 +`define Lwvalid 1 +`define Lwready 1 +`define Lbid 4 +`define Lbresp 2 +`define Lbvalid 1 +`define Lbready 1 +`define Larcmd 4 +`define Larcpuno 10 +`define Larid 4 +`define Laraddr 32 +`define Larlen 8 +`define Larsize 3 +`define Larburst 2 +`define Larlock 2 +`define Larcache 4 +`define Larprot 3 +`define Larvalid 1 +`define Larready 1 +`define Lrstate 2 +`define Lrscseti 2 +`define Lrid 4 +`define Lrdata 32 +`define Lrresp 2 +`define Lrlast 1 +`define Lrvalid 1 +`define Lrready 1 +`define Lrrequest 1 + +`define LID 4 +`define LADDR 32 +`define LLEN 8 +`define LSIZE 3 +`define LDATA 32 +`define LSTRB 4 +`define LBURST 2 +`define LLOCK 2 +`define LCACHE 4 +`define LPROT 3 +`define LRESP 2 diff --git a/rtl/ip/APB_UART/URT/raminfr.v b/rtl/ip/APB_UART/URT/raminfr.v new file mode 100644 index 0000000..a7e8677 --- /dev/null +++ b/rtl/ip/APB_UART/URT/raminfr.v @@ -0,0 +1,62 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +module raminfr(clk, we, a, dpra, di, dpo); + +parameter addr_width = 4; +parameter data_width = 8; +parameter depth = 16; + +input clk; +input we; +input [addr_width-1:0] a; +input [addr_width-1:0] dpra; +input [data_width-1:0] di; +output [data_width-1:0] dpo; +reg [data_width-1:0] ram [depth-1:0]; + +wire [data_width-1:0] di; +wire [addr_width-1:0] a; +wire [addr_width-1:0] dpra; + +always @(posedge clk) begin + if (we) + ram[a] <= di; +end +reg [data_width-1:0] dpo; + +always @(posedge clk) + dpo <= ram[dpra]; + +endmodule + diff --git a/rtl/ip/APB_UART/URT/uart_defines.h b/rtl/ip/APB_UART/URT/uart_defines.h new file mode 100644 index 0000000..02bc376 --- /dev/null +++ b/rtl/ip/APB_UART/URT/uart_defines.h @@ -0,0 +1,119 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +`define UART_ADDR_WIDTH 3 +`define UART_DATA_WIDTH 8 + +// Register addresses +`define UART_REG_RB `UART_ADDR_WIDTH'd0 // receiver buffer +`define UART_REG_TR `UART_ADDR_WIDTH'd0 // transmitter +`define UART_REG_IE `UART_ADDR_WIDTH'd1 // Interrupt enable +`define UART_REG_II `UART_ADDR_WIDTH'd2 // Interrupt identification +`define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control +`define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control +`define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control +`define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status +`define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status +`define UART_REG_SR `UART_ADDR_WIDTH'd7 // Scratch register +`define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2) +`define UART_REG_DL2 `UART_ADDR_WIDTH'd1 + +// Interrupt Enable register bits +`define UART_IE_RDA 0 // Received Data available interrupt +`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt +`define UART_IE_RLS 2 // Receiver Line Status Interrupt +`define UART_IE_MS 3 // Modem Status Interrupt + +// Interrupt Identification register bits +`define UART_II_IP 0 // Interrupt pending when 0 +`define UART_II_II 3:1 // Interrupt identification + +// Interrupt identification values for bits 3:1 +`define UART_II_RLS 3'b011 // Receiver Line Status +`define UART_II_RDA 3'b010 // Receiver Data available +`define UART_II_TI 3'b110 // Timeout Indication +`define UART_II_THRE 3'b001 // Transmitter Holding Register empty +`define UART_II_MS 3'b000 // Modem Status + +// FIFO Control Register bits +`define UART_FC_TL 1:0 // Trigger level + +// FIFO trigger level values +`define UART_FC_1 2'b00 +`define UART_FC_4 2'b01 +`define UART_FC_8 2'b10 +`define UART_FC_14 2'b11 + +// Line Control register bits +`define UART_LC_BITS 1:0 // bits in character +`define UART_LC_SB 2 // stop bits +`define UART_LC_PE 3 // parity enable +`define UART_LC_EP 4 // even parity +`define UART_LC_SP 5 // stick parity +`define UART_LC_BC 6 // Break control +`define UART_LC_DL 7 // Divisor Latch access bit + +// Modem Control register bits +`define UART_MC_DTR 0 +`define UART_MC_RTS 1 +`define UART_MC_OUT1 2 +`define UART_MC_OUT2 3 +`define UART_MC_LB 4 // Loopback mode + +// Line Status Register bits +`define UART_LS_DR 0 // Data ready +`define UART_LS_OE 1 // Overrun Error +`define UART_LS_PE 2 // Parity Error +`define UART_LS_FE 3 // Framing Error +`define UART_LS_BI 4 // Break interrupt +`define UART_LS_TFE 5 // Transmit FIFO is empty +`define UART_LS_TE 6 // Transmitter Empty indicator +`define UART_LS_EI 7 // Error indicator + +// Modem Status Register bits +`define UART_MS_DCTS 0 // Delta signals +`define UART_MS_DDSR 1 +`define UART_MS_TERI 2 +`define UART_MS_DDCD 3 +`define UART_MS_CCTS 4 // Complement signals +`define UART_MS_CDSR 5 +`define UART_MS_CRI 6 +`define UART_MS_CDCD 7 + +// FIFO parameter defines + +`define UART_FIFO_WIDTH 8 +`define UART_FIFO_DEPTH 16 +`define UART_FIFO_POINTER_W 4 +`define UART_FIFO_COUNTER_W 5 +`define UART_FIFO_REC_WIDTH 11 diff --git a/rtl/ip/APB_UART/URT/uart_receiver.v b/rtl/ip/APB_UART/URT/uart_receiver.v new file mode 100644 index 0000000..da5ace6 --- /dev/null +++ b/rtl/ip/APB_UART/URT/uart_receiver.v @@ -0,0 +1,288 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +`include "uart_defines.h" + +module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, + counter_t, rf_count, rf_data_out, rf_error_bit, + rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); + +input clk; +input wb_rst_i; +input [7:0] lcr; +input rf_pop; +input srx_pad_i; +input enable; +input rx_reset; +input lsr_mask; + +output [9:0] counter_t; +output [`UART_FIFO_COUNTER_W-1:0] rf_count; +output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; +output rf_overrun; +output rf_error_bit; +output [3:0] rstate; +output rf_push_pulse; + +reg [3:0] rstate; +reg [3:0] rcounter16; +reg [2:0] rbit_counter; +reg [7:0] rshift; +reg rparity; +reg rparity_error; +reg rframing_error; +reg rbit_in; +reg rparity_xor; +reg [7:0] counter_b; +reg rf_push_q; + +reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in; +wire[`UART_FIFO_REC_WIDTH-1:0] rf_data_out; +wire rf_push_pulse; +reg rf_push; +wire rf_pop; +wire rf_overrun; +wire[`UART_FIFO_COUNTER_W-1:0] rf_count; +wire rf_error_bit; +wire break_error = (counter_b == 0); + +uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx( + .clk ( clk ), + .wb_rst_i ( wb_rst_i ), + .data_in ( rf_data_in ), + .data_out ( rf_data_out ), + .push ( rf_push_pulse), + .pop ( rf_pop ), + .overrun ( rf_overrun ), + .count ( rf_count ), + .error_bit ( rf_error_bit ), + .fifo_reset ( rx_reset ), + .reset_status( lsr_mask ) +); + +wire rcounter16_eq_7 = (rcounter16 == 4'd7); +wire rcounter16_eq_0 = (rcounter16 == 4'd0); +wire rcounter16_eq_1 = (rcounter16 == 4'd1); + +wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1; + +parameter sr_idle = 4'd0; +parameter sr_rec_start = 4'd1; +parameter sr_rec_bit = 4'd2; +parameter sr_rec_parity = 4'd3; +parameter sr_rec_stop = 4'd4; +parameter sr_check_parity = 4'd5; +parameter sr_rec_prepare = 4'd6; +parameter sr_end_bit = 4'd7; +parameter sr_ca_lc_parity = 4'd8; +parameter sr_wait1 = 4'd9; +parameter sr_push = 4'd10; + + +always @(posedge clk ) begin + if (wb_rst_i) begin + rstate <= sr_idle; + rbit_in <= 1'b0; + rcounter16 <= 0; + rbit_counter <= 0; + rparity_xor <= 1'b0; + rframing_error <= 1'b0; + rparity_error <= 1'b0; + rparity <= 1'b0; + rshift <= 0; + rf_push <= 1'b0; + rf_data_in <= 0; + end + else if (enable) begin + case (rstate) + sr_idle : begin + rf_push <= 1'b0; + rf_data_in <= 0; + rcounter16 <= 4'b1110; + if (srx_pad_i==1'b0 & ~break_error) begin + rstate <= sr_rec_start; + end + end + sr_rec_start : begin + rf_push <= 1'b0; + if (rcounter16_eq_7) + if (srx_pad_i==1'b1) + rstate <= sr_idle; + else + rstate <= sr_rec_prepare; + else rstate<=rstate; + rcounter16 <= rcounter16_minus_1; + end + sr_rec_prepare: begin + case (lcr[1:0]) + 2'b00 : rbit_counter <= 3'b100; + 2'b01 : rbit_counter <= 3'b101; + 2'b10 : rbit_counter <= 3'b110; + 2'b11 : rbit_counter <= 3'b111; + endcase + if (rcounter16_eq_0) begin + rstate <= sr_rec_bit; + rcounter16 <= 4'b1110; + rshift <= 0; + end + else + rstate <= sr_rec_prepare; + rcounter16 <= rcounter16_minus_1; + end + sr_rec_bit : begin + if (rcounter16_eq_0) rstate <= sr_end_bit; + if (rcounter16_eq_7) + case (lcr[1:0]) + 2'b00 : rshift[4:0] <= {srx_pad_i, rshift[4:1]}; + 2'b01 : rshift[5:0] <= {srx_pad_i, rshift[5:1]}; + 2'b10 : rshift[6:0] <= {srx_pad_i, rshift[6:1]}; + 2'b11 : rshift[7:0] <= {srx_pad_i, rshift[7:1]}; + endcase + rcounter16 <= rcounter16_minus_1; + end + sr_end_bit : begin + if (rbit_counter==3'b0) + if (lcr[`UART_LC_PE]) + rstate <= sr_rec_parity; + else begin + rstate <= sr_rec_stop; + rparity_error<= 1'b0; + end + else begin + rstate <= sr_rec_bit; + rbit_counter <= rbit_counter - 1'b1; + end + rcounter16 <= 4'b1110; + end + sr_rec_parity : begin + if (rcounter16_eq_7) begin + rparity <= srx_pad_i; + rstate <= sr_ca_lc_parity; + end + rcounter16 <= rcounter16_minus_1; + end + sr_ca_lc_parity:begin + rcounter16 <= rcounter16_minus_1; + rparity_xor <= ^{rshift,rparity}; + rstate <= sr_check_parity; + end + sr_check_parity: begin + case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) + 2'b00: rparity_error <= rparity_xor == 0; + 2'b01: rparity_error <= ~rparity; + 2'b10: rparity_error <= rparity_xor == 1; + 2'b11: rparity_error <= rparity; + endcase + rcounter16 <= rcounter16_minus_1; + rstate <= sr_wait1; + end + sr_wait1 : + if (rcounter16_eq_0) begin + rstate <= sr_rec_stop; + rcounter16 <= 4'b1110; + end + else rcounter16 <= rcounter16_minus_1; + sr_rec_stop : begin + if (rcounter16_eq_7) begin + rframing_error <= !srx_pad_i; + rstate <= sr_push; + end + rcounter16 <= rcounter16_minus_1; + end + sr_push : begin + if(srx_pad_i | break_error) begin + if(break_error) + rf_data_in <= {8'b0, 3'b100}; + else + rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error}; + rf_push <= 1'b1; + rstate <= sr_idle; + end + else if(~rframing_error) begin + rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error}; + rf_push <= 1'b1; + rcounter16 <= 4'b1110; + rstate <= sr_rec_start; + end + + end + default : rstate <= sr_idle; + endcase + end +end + +always @ (posedge clk ) begin + if(wb_rst_i) rf_push_q <= 0; + else rf_push_q <= rf_push; +end + +assign rf_push_pulse = rf_push & ~rf_push_q; + + +reg [9:0] toc_value; + +always @(lcr) + case (lcr[3:0]) + 4'b0000 : toc_value = 447; + 4'b0100 : toc_value = 479; + 4'b0001, 4'b1000 : toc_value = 511; + 4'b1100 : toc_value = 543; + 4'b0010, 4'b0101, 4'b1001 : toc_value = 575; + 4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; + 4'b0111, 4'b1011, 4'b1110 : toc_value = 703; + 4'b1111 : toc_value = 767; + endcase + +wire [7:0] brc_value; +assign brc_value = toc_value[9:2]; + +always @(posedge clk ) begin + if (wb_rst_i) counter_b <= 8'd159; + else if (srx_pad_i) counter_b <= brc_value; + else if (enable & counter_b != 8'b0) + counter_b <= counter_b - 1; +end + + +reg [9:0] counter_t; + +always @(posedge clk ) begin + if (wb_rst_i) counter_t <= 10'd639; + else if(rf_push_pulse || rf_pop || rf_count == 0) + counter_t <= toc_value; + else if (enable && counter_t != 10'b0) + counter_t <= counter_t - 1; +end + +endmodule + diff --git a/rtl/ip/APB_UART/URT/uart_regs.v b/rtl/ip/APB_UART/URT/uart_regs.v new file mode 100644 index 0000000..443ea93 --- /dev/null +++ b/rtl/ip/APB_UART/URT/uart_regs.v @@ -0,0 +1,711 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +`include "uart_defines.h" + +`define UART_DL1 7:0 +`define UART_DL2 15:8 +`define UART_DL3 23:16 +module uart_regs (clk, rst, clk_carrier, + addr, dat_i, dat_o, we, re, + + modem_inputs, + rts_pad_o, dtr_pad_o, + stx_pad_o,TXD_i,srx_pad_i,RXD_o, + int_o, + usart_mode, + rx_en, + tx2rx_en +); +input clk; +input rst ; +input clk_carrier; +input [2:0] addr; +input [7:0] dat_i; +output [7:0] dat_o; +input we; +input re; + +output stx_pad_o; +input srx_pad_i; +input TXD_i; +output RXD_o; + +input [3:0] modem_inputs; +output rts_pad_o; +output dtr_pad_o; +output int_o; + +output usart_mode; +output tx2rx_en; +output rx_en; + +wire [3:0] modem_inputs; +reg enable; + +wire stx_pad_o; +wire srx_pad_i; +wire srx_pad; + +reg [7:0] dat_o; + +wire [2:0] addr; +wire [7:0] dat_i; + +reg [3:0] ier; +reg [3:0] iir; +reg [1:0] fcr; +reg [4:0] mcr; +reg infrared; +reg rx_pol; +reg [7:0] lcr; +reg [7:0] msr; +reg [23:0] dl; +reg start_dlc; +reg lsr_mask_d; +reg msi_reset; + +reg [15:0] dlc; +reg int_o; + +reg [3:0] trigger_level; +reg rx_reset; +reg tx_reset; +wire dlab; + +wire usart_mode; +wire usart_rx_en; +wire usart_tx_en; +wire tx2rx_en; +reg sclk_reg; +reg sclk_en_reg; +reg [7:0] mode_reg; +reg [7:0] fi_di_reg; +reg [7:0] sclk_count; +reg [2:0] repeat_reg; + +wire usart_normal; +wire usart_irda; +wire usart_t0; +wire usart_t1; +wire rx_en; +wire tx_en; +wire sclk_por; + +assign usart_normal = mode_reg[1:0]==2'h0; +assign usart_irda = mode_reg[1:0]==2'h1; +assign usart_t0 = mode_reg[1:0]==2'h2; +assign usart_t1 = mode_reg[1:0]==2'h3; +assign usart_tx_en = mode_reg[2]==1'b0; +assign usart_rx_en = mode_reg[2]==1'b1; +assign sclk_por = mode_reg[3]; +assign RXD_o = sclk_reg^sclk_por; + +assign usart_mode = usart_t0 || usart_t1; +assign rx_en = usart_normal || usart_irda || usart_mode && usart_rx_en; +assign tx_en = usart_normal || usart_irda || usart_mode && usart_tx_en; + + +always @(posedge clk ) +begin + if (rst) begin + mode_reg <= 8'h0; + fi_di_reg <= 8'h0; + repeat_reg<= 3'h4; + sclk_en_reg<= 1'b0; + end + else if (we && addr==`UART_REG_SR)begin + if(dlab) + fi_di_reg <= dat_i; + else + mode_reg <= dat_i; + end + else begin + if(enable) sclk_en_reg <= mode_reg[4]; + repeat_reg <= mode_reg[7:5]; + end +end + +always @(posedge clk) +begin + if(rst) begin + sclk_count <= 8'b0; + sclk_reg <=1'b0; + end + else if(usart_mode&&(fi_di_reg>8'h1)&&sclk_en_reg) begin + if(sclk_count == fi_di_reg[7:1]) begin + sclk_reg <= 1'b1; + sclk_count <= sclk_count + 1'b1; + end + else if(sclk_count == fi_di_reg) begin + sclk_reg <= 1'b0; + sclk_count <= 8'b0; + end + else begin + sclk_count <= sclk_count + 1'b1; + end + end + else begin + sclk_reg <=1'b0; + sclk_count <= 8'b0; + end +end + +wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; +wire loopback; +wire cts, dsr, ri, dcd; +wire cts_c, dsr_c, ri_c, dcd_c; +wire rts_pad_o, dtr_pad_o; + +wire [7:0] lsr; +wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7; +reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r; +wire lsr_mask; + +assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r }; + +assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs; +assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; + +assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]} + : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; + +assign dlab = lcr[`UART_LC_DL]; +assign loopback = mcr[4]; + +assign rts_pad_o = mcr[`UART_MC_RTS]; +assign dtr_pad_o = mcr[`UART_MC_DTR]; + +wire rls_int; +wire rda_int; +wire ti_int; +wire thre_int; +wire ms_int; + +wire tf_push; +reg rf_pop; +wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; +wire rf_error_bit; +wire [`UART_FIFO_COUNTER_W-1:0] rf_count; +wire [`UART_FIFO_COUNTER_W-1:0] tf_count; +wire [2:0] tstate; +wire [3:0] rstate; +wire [9:0] counter_t; + +wire thre_set_en; +reg [7:0] block_cnt; +reg [7:0] block_value; +wire current_finish; +wire max_repeat_time; + +wire serial_out; +wire serial_out_modulated = ~ (clk_carrier & serial_out); + +uart_transmitter transmitter(.clk(clk), .wb_rst_i(rst), .lcr(lcr), .tf_push(tf_push), .wb_dat_i(dat_i), + + .tx2rx_en (tx2rx_en), + .usart_mode(usart_mode), + .srx_pad_i(TXD_i), + .enable (enable && tx_en), + .usart_t0(usart_t0), + .repeat_time(repeat_reg ), + .current_finish(current_finish), + .max_repeat_time(max_repeat_time), + + .stx_pad_o(serial_out), .tstate(tstate), .tf_count(tf_count), + .tx_reset(tx_reset), .lsr_mask(lsr_mask)); +wire rcv_pad_i; +assign rcv_pad_i = ~usart_mode ? srx_pad_i : (rx_en ? TXD_i : 1'b1); + +uart_sync_flops i_uart_sync_flops( + .rst_i (rst), + .clk_i (clk), + .stage1_rst_i (1'b0), + .stage1_clk_en_i (1'b1), + .async_dat_i (rcv_pad_i), + .sync_dat_o (srx_pad) + ); + + defparam i_uart_sync_flops.width = 1; + defparam i_uart_sync_flops.init_value = 1'b1; +wire serial_in = loopback ? serial_out : rx_pol ? ~srx_pad : srx_pad; +assign stx_pad_o = loopback ? 1'b1 : infrared ? serial_out_modulated : serial_out; + +wire rf_overrun; +wire rf_push_pulse; +uart_receiver receiver(.clk(clk), .wb_rst_i(rst), .lcr(lcr), .rf_pop(rf_pop), .srx_pad_i(serial_in), + .enable(enable && rx_en), + .counter_t(counter_t), .rf_count(rf_count), .rf_data_out(rf_data_out), .rf_error_bit(rf_error_bit), + .rf_overrun(rf_overrun), .rx_reset(rx_reset), .lsr_mask(lsr_mask), .rstate(rstate), .rf_push_pulse(rf_push_pulse)); + + +always @(dl or dlab or ier or iir or fi_di_reg or mode_reg + or lcr or lsr or msr or rf_data_out or addr ) +begin + case (addr) + `UART_REG_RB : dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3]; + `UART_REG_IE : dat_o = dlab ? dl[`UART_DL2] : ier; + `UART_REG_II : dat_o = dlab ? dl[`UART_DL3] : {4'b1100,iir}; + `UART_REG_LC : dat_o = lcr; + `UART_REG_LS : dat_o = lsr; + `UART_REG_MS : dat_o = msr; + `UART_REG_SR : dat_o = dlab ? fi_di_reg : mode_reg; + default : dat_o = 8'b0; + endcase +end + +always @(posedge clk ) +begin + if (rst) + rf_pop <= 0; + else + if (rf_pop) + rf_pop <= 0; + else + if (re && addr == `UART_REG_RB && !dlab) + rf_pop <= 1; +end + +wire lsr_mask_condition; +wire iir_read; +wire msr_read; +wire fifo_read; +wire fifo_write; + +assign lsr_mask_condition = (re && addr == `UART_REG_LS && !dlab); +assign iir_read = (re && addr == `UART_REG_II && !dlab); +assign msr_read = (re && addr == `UART_REG_MS && !dlab); +assign fifo_read = (re && addr == `UART_REG_RB && !dlab); +assign fifo_write = (we && addr == `UART_REG_TR && !dlab); + +always @(posedge clk ) +begin + if (rst) + lsr_mask_d <= 0; + else + lsr_mask_d <= lsr_mask_condition; +end + +assign lsr_mask = lsr_mask_condition && ~lsr_mask_d; + +always @(posedge clk ) +begin + if (rst) + msi_reset <= 1; + else + if (msi_reset) + msi_reset <= 0; + else + if (msr_read) + msi_reset <= 1; +end + +always @(posedge clk ) + if (rst) + lcr <= 8'b00000011; + else + if (we && addr==`UART_REG_LC) + lcr <= dat_i; + +always @(posedge clk ) + if (rst) + begin + ier <= 4'b0000; + dl[`UART_DL2] <= 8'b0; + end + else + if (we && addr==`UART_REG_IE) + if (dlab) + begin + dl[`UART_DL2] <= dat_i; + end + else + ier <= dat_i[3:0]; + else + ier<= ier; + +always @(posedge clk ) + if (rst) begin + fcr <= 2'b11; + rx_reset <= 0; + tx_reset <= 0; + dl[`UART_DL3] <= 8'h0; + end else + if (we && addr==`UART_REG_FC) begin + if(dlab) dl[`UART_DL3] <= dat_i; + else begin + fcr <= dat_i[7:6]; + rx_reset <= dat_i[1]; + tx_reset <= dat_i[2]; + end + end else begin + rx_reset <= 0; + tx_reset <= 0; + end + +always @(posedge clk ) + if (rst) begin + mcr <= 5'b0; + infrared <= 1'b0; + rx_pol <= 1'b0; end + else + if(we && addr==`UART_REG_MC) begin + mcr <= dat_i[4:0]; + infrared <= dat_i[7]; + rx_pol <= dat_i[6]; end + +assign tf_push = we & addr==`UART_REG_TR & !dlab; +always @(posedge clk ) + if (rst) + begin + dl[`UART_DL1] <= 8'b0; + start_dlc <= 1'b0; + end + else + if (we && addr==`UART_REG_TR) + if (dlab) + begin + dl[`UART_DL1] <= dat_i; + start_dlc <= 1'b1; + end + else + begin + start_dlc <= 1'b0; + end + else + begin + start_dlc <= 1'b0; + end + +always @(fcr) + case (fcr[`UART_FC_TL]) + 2'b00 : trigger_level = 1; + 2'b01 : trigger_level = 4; + 2'b10 : trigger_level = 8; + 2'b11 : trigger_level = 14; + endcase + +reg [3:0] delayed_modem_signals; +always @(posedge clk ) +begin + if (rst) + begin + msr <= 0; + delayed_modem_signals[3:0] <= 0; + end + else begin + msr[`UART_MS_DDCD:`UART_MS_DCTS] <= msi_reset ? 4'b0 : + msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]); + msr[`UART_MS_CDCD:`UART_MS_CCTS] <= {dcd_c, ri_c, dsr_c, cts_c}; + delayed_modem_signals[3:0] <= {dcd, ri, dsr, cts}; + end +end + +assign lsr0 = (rf_count==0 && rf_push_pulse); +assign lsr1 = rf_overrun; +assign lsr2 = rf_data_out[1]; +assign lsr3 = rf_data_out[0]; +assign lsr4 = rf_data_out[2]; +assign lsr5 = current_finish && (tf_count==5'b0 && thre_set_en); +assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == 3'd0)); +assign lsr7 = rf_error_bit | rf_overrun; + +reg lsr0_d; + +always @(posedge clk ) + if (rst) lsr0_d <= 0; + else lsr0_d <= lsr0; + +always @(posedge clk ) + if (rst) lsr0r <= 0; + else lsr0r <= (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : + lsr0r || (lsr0 && ~lsr0_d); + +reg lsr1_d; + +always @(posedge clk ) + if (rst) lsr1_d <= 0; + else lsr1_d <= lsr1; + +always @(posedge clk ) + if (rst) lsr1r <= 0; + else lsr1r <= lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); + +reg lsr2_d; + +always @(posedge clk ) + if (rst) lsr2_d <= 0; + else lsr2_d <= lsr2; + +always @(posedge clk ) + if (rst) lsr2r <= 0; + else lsr2r <= lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); + +reg lsr3_d; + +always @(posedge clk ) + if (rst) lsr3_d <= 0; + else lsr3_d <= lsr3; + +always @(posedge clk ) + if (rst) lsr3r <= 0; + else lsr3r <= lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); + +reg lsr4_d; + +always @(posedge clk ) + if (rst) lsr4_d <= 0; + else lsr4_d <= lsr4; + +always @(posedge clk ) + if (rst) lsr4r <= 0; + else lsr4r <= lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d); + +reg lsr5_d; +always @(posedge clk ) + if (rst) lsr5_d <= 1; + else lsr5_d <= lsr5; + +always @(posedge clk ) + if (rst) lsr5r <= 1; + else lsr5r <= (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d); + +reg lsr6_d; + +always @(posedge clk ) + if (rst) lsr6_d <= 1; + else lsr6_d <= lsr6; + +always @(posedge clk ) + if (rst) lsr6r <= 1; + else lsr6r <= (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d); + +reg lsr7_d; + +always @(posedge clk ) + if (rst) lsr7_d <= 0; + else lsr7_d <= lsr7; + +always @(posedge clk ) + if (rst) lsr7r <= 0; + else lsr7r <= lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d); + +reg [8:0] M_cnt; +wire [8:0] M_next = M_cnt + dl[`UART_DL3]; +wire M_toggle = M_cnt[8] ^ M_next[8]; + +always @(posedge clk ) +begin + if (rst) begin + dlc <= 0; + M_cnt <= 8'h0; + end + else if (start_dlc | ~ (|dlc)) begin + dlc <= dl - 1 + M_toggle; + M_cnt <= M_next; + end + else + dlc <= dlc - 1; +end + +always @(posedge clk ) +begin + if (rst) + enable <= 1'b0; + else if (|dl & ~(|dlc)) + enable <= 1'b1; + else + enable <= 1'b0; +end + +always @(lcr) + case (lcr[3:0]) + 4'b0000 : block_value = 95; + 4'b0100 : block_value = 103; + 4'b0001, 4'b1000 : block_value = 111; + 4'b1100 : block_value = 119; + 4'b0010, 4'b0101, 4'b1001 : block_value = 127; + 4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; + 4'b0111, 4'b1011, 4'b1110 : block_value = 159; + 4'b1111 : block_value = 175; + endcase + +always @(posedge clk ) +begin + if (rst) + block_cnt <= 8'd0; + else + if(lsr5r & fifo_write) + block_cnt <= usart_t0 ? (block_value + 8'h16) : block_value; + else + if (enable & block_cnt != 8'b0) + block_cnt <= block_cnt - 1; +end + +assign thre_set_en = ~(|block_cnt); + +assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]); +assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level}); +assign thre_int = ier[`UART_IE_THRE]&& lsr[`UART_LS_TFE]; +assign ms_int = ier[`UART_IE_MS] && (usart_t0 ? max_repeat_time : (| msr[3:0])); +assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count); + +reg rls_int_d; +reg thre_int_d; +reg ms_int_d; +reg ti_int_d; +reg rda_int_d; + +always @(posedge clk ) + if (rst) rls_int_d <= 0; + else rls_int_d <= rls_int; + +always @(posedge clk ) + if (rst) rda_int_d <= 0; + else rda_int_d <= rda_int; + +always @(posedge clk ) + if (rst) thre_int_d <= 0; + else thre_int_d <= thre_int; + +always @(posedge clk ) + if (rst) ms_int_d <= 0; + else ms_int_d <= ms_int; + +always @(posedge clk ) + if (rst) ti_int_d <= 0; + else ti_int_d <= ti_int; + + +wire rls_int_rise; +wire thre_int_rise; +wire ms_int_rise; +wire ti_int_rise; +wire rda_int_rise; + +assign rda_int_rise = rda_int & ~rda_int_d; +assign rls_int_rise = rls_int & ~rls_int_d; +assign thre_int_rise = thre_int & ~thre_int_d; +assign ms_int_rise = ms_int & ~ms_int_d; +assign ti_int_rise = ti_int & ~ti_int_d; + +reg rls_int_pnd; +reg rda_int_pnd; +reg thre_int_pnd; +reg ms_int_pnd; +reg ti_int_pnd; + +always @(posedge clk ) + if (rst) rls_int_pnd <= 0; + else + rls_int_pnd <= lsr_mask ? 0 : + rls_int_rise ? 1 : + rls_int_pnd && ier[`UART_IE_RLS]; + +reg d1_fifo_read; +always @( posedge clk ) d1_fifo_read <= fifo_read; + +always @(posedge clk) + if (rst) rda_int_pnd <= 0; + else rda_int_pnd <= ((rf_count == {1'b0,trigger_level}) && d1_fifo_read) ? 0 : + rda_int_rise ? 1 : + rda_int_pnd && ier[`UART_IE_RDA]; + +always @(posedge clk ) + if (rst) thre_int_pnd <= 0; + else + thre_int_pnd <= fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 : + thre_int_rise ? 1 : + thre_int_pnd && ier[`UART_IE_THRE]; + +always @(posedge clk ) + if (rst) ms_int_pnd <= 0; + else + ms_int_pnd <= msr_read ? 0 : ms_int_rise ? 1 : + ms_int_pnd && ier[`UART_IE_MS]; + +always @(posedge clk ) + if (rst) ti_int_pnd <= 0; + else + ti_int_pnd <= fifo_read ? 0 : ti_int_rise ? 1 : + ti_int_pnd && ier[`UART_IE_RDA]; + +always @(posedge clk ) +begin + if (rst) int_o <= 1'b0; + else int_o <= rls_int_pnd ? ~lsr_mask : + rda_int_pnd ? 1 : + ti_int_pnd ? ~fifo_read: + thre_int_pnd? !(fifo_write & iir_read) : + ms_int_pnd ? ~msr_read : + 0; +end + + +always @(posedge clk ) +begin + if (rst) + iir <= 1; + else + if (rls_int_pnd) + begin + iir[`UART_II_II] <= `UART_II_RLS; + iir[`UART_II_IP] <= 1'b0; + end else + if (rda_int_pnd) + begin + iir[`UART_II_II] <= `UART_II_RDA; + iir[`UART_II_IP] <= 1'b0; + end + else if (ti_int_pnd) + begin + iir[`UART_II_II] <= `UART_II_TI; + iir[`UART_II_IP] <= 1'b0; + end + else if (thre_int_pnd) + begin + iir[`UART_II_II] <= `UART_II_THRE; + iir[`UART_II_IP] <= 1'b0; + end + else if (ms_int_pnd) + begin + iir[`UART_II_II] <= `UART_II_MS; + iir[`UART_II_IP] <= 1'b0; + end else + begin + iir[`UART_II_II] <= 0; + iir[`UART_II_IP] <= 1'b1; + end +end + +endmodule diff --git a/rtl/ip/APB_UART/URT/uart_rfifo.v b/rtl/ip/APB_UART/URT/uart_rfifo.v new file mode 100644 index 0000000..c53db74 --- /dev/null +++ b/rtl/ip/APB_UART/URT/uart_rfifo.v @@ -0,0 +1,193 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +`include "uart_defines.h" + +module uart_rfifo (clk, + wb_rst_i, data_in, data_out, + push, + pop, + overrun, + count, + error_bit, + fifo_reset, + reset_status +); + +parameter fifo_width = `UART_FIFO_WIDTH; +parameter fifo_depth = `UART_FIFO_DEPTH; +parameter fifo_pointer_w = `UART_FIFO_POINTER_W; +parameter fifo_counter_w = `UART_FIFO_COUNTER_W; + +input clk; +input wb_rst_i; +input push; +input pop; +input [fifo_width-1:0] data_in; +input fifo_reset; +input reset_status; + +output [fifo_width-1:0] data_out; +output overrun; +output [fifo_counter_w-1:0] count; +output error_bit; + +wire [fifo_width-1:0] data_out; +wire [7:0] data8_out; +reg [2:0] fifo[fifo_depth-1:0]; + +reg [fifo_pointer_w-1:0] top; +reg [fifo_pointer_w-1:0] bottom; + +reg [fifo_counter_w-1:0] count; +reg overrun; + +wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1; + +raminfr #(fifo_pointer_w,8,fifo_depth) rfifo (.clk(clk), + .we(push), + .a(top), + .dpra(bottom), + .di(data_in[fifo_width-1:fifo_width-8]), + .dpo(data8_out) +); + +always @(posedge clk) +begin + if (wb_rst_i) + begin + top <= 0; + bottom <= 1'b0; + count <= 0; + fifo[0] <= 0; + fifo[1] <= 0; + fifo[2] <= 0; + fifo[3] <= 0; + fifo[4] <= 0; + fifo[5] <= 0; + fifo[6] <= 0; + fifo[7] <= 0; + fifo[8] <= 0; + fifo[9] <= 0; + fifo[10]<= 0; + fifo[11]<= 0; + fifo[12]<= 0; + fifo[13]<= 0; + fifo[14]<= 0; + fifo[15]<= 0; + end + else + if (fifo_reset) begin + top <= 0; + bottom <= 1'b0; + count <= 0; + fifo[0] <= 0; + fifo[1] <= 0; + fifo[2] <= 0; + fifo[3] <= 0; + fifo[4] <= 0; + fifo[5] <= 0; + fifo[6] <= 0; + fifo[7] <= 0; + fifo[8] <= 0; + fifo[9] <= 0; + fifo[10]<= 0; + fifo[11]<= 0; + fifo[12]<= 0; + fifo[13]<= 0; + fifo[14]<= 0; + fifo[15]<= 0; + end + else + begin + case ({push, pop}) + 2'b10 : if (count0) + begin + fifo[bottom] <= 0; + bottom <= bottom + 1'b1; + count <= count - 1'b1; + end + 2'b11 : begin + bottom <= bottom + 1'b1; + top <= top_plus_1; + fifo[top] <= data_in[2:0]; + end + default: ; + endcase + end +end + +always @(posedge clk) +begin + if (wb_rst_i) + overrun <= 1'b0; + else + if(fifo_reset | reset_status) + overrun <= 1'b0; + else + if(push & ~pop & (count==fifo_depth)) + overrun <= 1'b1; +end + +assign data_out = {data8_out,fifo[bottom]}; + +wire [2:0] word0 = fifo[0]; +wire [2:0] word1 = fifo[1]; +wire [2:0] word2 = fifo[2]; +wire [2:0] word3 = fifo[3]; +wire [2:0] word4 = fifo[4]; +wire [2:0] word5 = fifo[5]; +wire [2:0] word6 = fifo[6]; +wire [2:0] word7 = fifo[7]; + +wire [2:0] word8 = fifo[8]; +wire [2:0] word9 = fifo[9]; +wire [2:0] word10 = fifo[10]; +wire [2:0] word11 = fifo[11]; +wire [2:0] word12 = fifo[12]; +wire [2:0] word13 = fifo[13]; +wire [2:0] word14 = fifo[14]; +wire [2:0] word15 = fifo[15]; + +assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] | + word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] | + word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] | + word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] ); + +endmodule diff --git a/rtl/ip/APB_UART/URT/uart_sync_flops.v b/rtl/ip/APB_UART/URT/uart_sync_flops.v new file mode 100644 index 0000000..99cdeb4 --- /dev/null +++ b/rtl/ip/APB_UART/URT/uart_sync_flops.v @@ -0,0 +1,76 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +module uart_sync_flops +( + rst_i, + clk_i, + stage1_rst_i, + stage1_clk_en_i, + async_dat_i, + sync_dat_o +); + +parameter Tp = 1; +parameter width = 1; +parameter init_value = 1'b0; + +input rst_i; +input clk_i; +input stage1_rst_i; +input stage1_clk_en_i; +input [width-1:0] async_dat_i; +output [width-1:0] sync_dat_o; + +reg [width-1:0] sync_dat_o; +reg [width-1:0] flop_0; + +always @ (posedge clk_i) +begin + if (rst_i) + flop_0 <= {width{init_value}}; + else + flop_0 <= async_dat_i; +end + +always @ (posedge clk_i) +begin + if (rst_i) + sync_dat_o <= {width{init_value}}; + else if (stage1_rst_i) + sync_dat_o <= {width{init_value}}; + else if (stage1_clk_en_i) + sync_dat_o <= flop_0; +end + +endmodule diff --git a/rtl/ip/APB_UART/URT/uart_tfifo.v b/rtl/ip/APB_UART/URT/uart_tfifo.v new file mode 100644 index 0000000..824da97 --- /dev/null +++ b/rtl/ip/APB_UART/URT/uart_tfifo.v @@ -0,0 +1,129 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +`include "uart_defines.h" + +module uart_tfifo (clk, + wb_rst_i, data_in, data_out, + push, + pop, + overrun, + count, + fifo_reset, + reset_status +); + +parameter fifo_width = `UART_FIFO_WIDTH; +parameter fifo_depth = `UART_FIFO_DEPTH; +parameter fifo_pointer_w = `UART_FIFO_POINTER_W; +parameter fifo_counter_w = `UART_FIFO_COUNTER_W; + +input clk; +input wb_rst_i; +input push; +input pop; +input [fifo_width-1:0] data_in; +input fifo_reset; +input reset_status; + +output [fifo_width-1:0] data_out; +output overrun; +output [fifo_counter_w-1:0] count; + +wire [fifo_width-1:0] data_out; + +reg [fifo_pointer_w-1:0] top; +reg [fifo_pointer_w-1:0] bottom; + +reg [fifo_counter_w-1:0] count; +reg overrun; +wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1; + +raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo (.clk(clk), + .we(push), + .a(top), + .dpra(bottom), + .di(data_in), + .dpo(data_out) +); + + +always @(posedge clk) +begin + if (wb_rst_i) + begin + top <= 0; + bottom <= 1'b0; + count <= 0; + end + else + if (fifo_reset) begin + top <= 0; + bottom <= 1'b0; + count <= 0; + end + else + begin + case ({push, pop}) + 2'b10 : if (count0) + begin + bottom <= bottom + 1'b1; + count <= count - 1'b1; + end + 2'b11 : begin + bottom <= bottom + 1'b1; + top <= top_plus_1; + end + default: ; + endcase + end +end + +always @(posedge clk) +begin + if (wb_rst_i) + overrun <= 1'b0; + else + if(fifo_reset | reset_status) + overrun <= 1'b0; + else + if(push & (count==fifo_depth)) + overrun <= 1'b1; +end + +endmodule diff --git a/rtl/ip/APB_UART/URT/uart_top.v b/rtl/ip/APB_UART/URT/uart_top.v new file mode 100644 index 0000000..8e8662b --- /dev/null +++ b/rtl/ip/APB_UART/URT/uart_top.v @@ -0,0 +1,107 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +`include "uart_defines.h" + +module UART_TOP( + PCLK, PRST_, + PSEL, PENABLE, PADDR, PWRITE, + PWDATA, URT_PRDATA, + + INT, clk_carrier, + + TXD_i, TXD_o, TXD_oe, + RXD_i, RXD_o, RXD_oe, + + RTS, CTS, DSR, + DCD, DTR, RI + ); + +input PCLK, PRST_; +input PSEL, PENABLE, PWRITE; +input [7:0] PADDR; +input [7:0] PWDATA; +output [7:0] URT_PRDATA; + +output INT; +input clk_carrier; + +input TXD_i; +output TXD_o; +output TXD_oe; +input RXD_i; +output RXD_o; +output RXD_oe; + +output RTS; +input CTS, DSR, DCD; +output DTR; +input RI; + +wire prst = !PRST_; +wire we = PSEL & PENABLE & PWRITE; +wire re = PSEL & PENABLE & !PWRITE; + +wire rx_en; +wire tx2rx_en; +wire isomode; + +assign TXD_oe = isomode&&(rx_en||tx2rx_en) ? 1'b1:1'b0; +assign RXD_oe =~isomode; + +uart_regs regs( + .clk (PCLK ), + .rst (prst ), + .clk_carrier (clk_carrier), + .addr (PADDR[2:0] ), + .dat_i (PWDATA ), + .dat_o (URT_PRDATA ), + .we (we ), + .re (re ), + + .modem_inputs({ CTS, DSR, RI, DCD } ), + .rts_pad_o (RTS ), + .dtr_pad_o (DTR ), + .stx_pad_o (TXD_o ), + .TXD_i (TXD_i ), + .srx_pad_i (RXD_i ), + .RXD_o (RXD_o ), + .int_o ( INT ), + .tx2rx_en (tx2rx_en ), + .rx_en (rx_en ), + .usart_mode (isomode ) + +); + + +endmodule diff --git a/rtl/ip/APB_UART/URT/uart_transmitter.v b/rtl/ip/APB_UART/URT/uart_transmitter.v new file mode 100644 index 0000000..1e8daeb --- /dev/null +++ b/rtl/ip/APB_UART/URT/uart_transmitter.v @@ -0,0 +1,281 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +`include "uart_defines.h" + +module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, + enable,stx_pad_o, tstate, tf_count, tx_reset, lsr_mask, + usart_t0,srx_pad_i,repeat_time,max_repeat_time,current_finish, + usart_mode,tx2rx_en); + +input clk; +input wb_rst_i; +input [7:0] lcr; +input tf_push; +input [7:0] wb_dat_i; +input enable; +input tx_reset; +input lsr_mask; +input usart_mode; +input usart_t0,srx_pad_i; +input [2:0] repeat_time; +output current_finish; +output max_repeat_time; + +output tx2rx_en; +reg tx2rx_en; +output stx_pad_o; +output [2:0] tstate; +output [`UART_FIFO_COUNTER_W-1:0] tf_count; + +reg [2:0] tstate; +reg [4:0] counter; +reg [2:0] bit_counter; +reg [6:0] shift_out; +reg stx_o_tmp; +reg parity_xor; +reg tf_pop; +reg bit_out; +reg tx_error; +reg [2:0] error_time; + +wire [`UART_FIFO_WIDTH-1:0] tf_data_in; +wire [`UART_FIFO_WIDTH-1:0] tf_data_out; +wire tf_push; +wire tf_overrun; +wire [`UART_FIFO_COUNTER_W-1:0]tf_count; + +assign tf_data_in = wb_dat_i; + +uart_tfifo fifo_tx( + .clk ( clk ), + .wb_rst_i( wb_rst_i ), + .data_in ( tf_data_in ), + .data_out( tf_data_out ), + .push ( tf_push ), + .pop ( tf_pop ), + .overrun ( tf_overrun ), + .count ( tf_count ), + .fifo_reset ( tx_reset), + .reset_status(lsr_mask ) +); + +parameter s_idle = 3'd0; +parameter s_send_start = 3'd1; +parameter s_send_byte = 3'd2; +parameter s_send_parity = 3'd3; +parameter s_send_stop = 3'd4; +parameter s_pop_byte = 3'd5; +parameter s_send_guard1 = 3'd6; +reg [7:0]tf_data_bak; + +wire max_repeat_time = (error_time==(repeat_time+1'b1)) & usart_mode & usart_t0; + +always @(posedge clk ) +begin + if (wb_rst_i) + begin + tx_error <= 1'b0; + error_time <= 3'b0; + tstate <= s_idle; + stx_o_tmp <= 1'b1; + counter <= 5'b0; + shift_out <= 7'b0; + bit_out <= 1'b0; + parity_xor <= 1'b0; + tf_pop <= 1'b0; + bit_counter <= 3'b0; + tx2rx_en <= 1'b0; + tf_data_bak <= 8'h0; + end + else + if (enable) + begin + case (tstate) + s_idle :if ((~|tf_count)&(error_time==(repeat_time+1'b1)||~tx_error||~usart_mode)) + begin + tstate <= s_idle; + stx_o_tmp <= 1'b1; + tx_error <= 1'b0; + end + else begin + tf_pop <= 1'b0; + stx_o_tmp <= 1'b1; + tstate <= s_pop_byte; + end + s_pop_byte : begin + + if(tx_error&(error_time !=(repeat_time+1'b1))) + begin + tf_pop <= 1'b0; + case (lcr[1:0]) + 2'b00 : begin + bit_counter <= 3'b100; + parity_xor <= ^tf_data_bak[4:0]; + end + 2'b01 : begin + bit_counter <= 3'b101; + parity_xor <= ^tf_data_bak[5:0]; + end + 2'b10 : begin + bit_counter <= 3'b110; + parity_xor <= ^tf_data_bak[6:0]; + end + 2'b11 : begin + bit_counter <= 3'b111; + parity_xor <= ^tf_data_bak[7:0]; + end + endcase + {shift_out[6:0], bit_out} <= tf_data_bak; + end + else begin + tf_pop <= 1'b1; + error_time <= 3'h0; + case (lcr[1:0]) + 2'b00 : begin + bit_counter <= 3'b100; + parity_xor <= ^tf_data_out[4:0]; + end + 2'b01 : begin + bit_counter <= 3'b101; + parity_xor <= ^tf_data_out[5:0]; + end + 2'b10 : begin + bit_counter <= 3'b110; + parity_xor <= ^tf_data_out[6:0]; + end + 2'b11 : begin + bit_counter <= 3'b111; + parity_xor <= ^tf_data_out[7:0]; + end + endcase + {shift_out[6:0], bit_out} <= tf_data_out; + tf_data_bak <= tf_data_out; + end + tstate <= s_send_start; + end + s_send_start : begin + tf_pop <= 1'b0; + if (~|counter) + counter <= 5'b01111; + else if (counter == 5'b00001) + begin + counter <= 0; + tstate <= s_send_byte; + end + else + counter <= counter - 1'b1; + stx_o_tmp <= 1'b0; + end + s_send_byte : begin + if (~|counter) + counter <= 5'b01111; + else if (counter == 5'b00001) + begin + if (bit_counter > 3'b0) begin + bit_counter <= bit_counter - 1'b1; + {shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]}; + tstate <= s_send_byte; + end + else + if (~lcr[`UART_LC_PE]) begin + tstate <= s_send_stop; + end + else begin + case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) + 2'b00: bit_out <= ~parity_xor; + 2'b01: bit_out <= 1'b1; + 2'b10: bit_out <= parity_xor; + 2'b11: bit_out <= 1'b0; + endcase + tstate <= s_send_parity; + end + counter <= 0; + end + else counter <= counter - 1'b1; + stx_o_tmp <= bit_out; + end + s_send_parity : begin + if (~|counter) counter <= 5'b01111; + else if (counter == 5'b00001) begin + counter <= 4'b0; + tstate <= usart_mode ? s_send_guard1 : s_send_stop; + end + else counter <= counter - 1'b1; + stx_o_tmp <= bit_out; + end + s_send_stop : begin + if (~|counter) begin + if(usart_t0) + counter <= tx_error ? 5'b11101 : 5'b01101; + else + casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]}) + 3'b0xx: counter <= 5'b01101; + 3'b100: counter <= 5'b10101; + default: counter <= 5'b11101; + endcase + end + else if (counter == 5'b00001) begin + counter <= 5'b0; + tx2rx_en<= 1'b0; + tstate <= s_idle; + end + else counter <= counter - 1'b1; + stx_o_tmp <= 1'b1; + end + s_send_guard1:begin + if (~|counter) begin + tx2rx_en <= 1'b1; + counter <= usart_t0 ? 5'b01111:5'b01101; + end + else if (counter == 5'b00001) begin + counter <= 5'b0; + tx_error <= !srx_pad_i; + error_time<= error_time + !srx_pad_i; + tx2rx_en <= usart_t0 ? 1'b1 : 1'b0; + tstate <= usart_t0 ? s_send_stop : s_idle; + end + else counter <= counter - 1'b1; + stx_o_tmp <= 1'b1; + end + default : + tstate <= s_idle; + endcase + end + else tf_pop <= 1'b0; +end + +assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; +assign current_finish = usart_mode ? ( (tstate==3'b0)&(tx_error & (error_time ==repeat_time+1'b1) |~tx_error) ) : 1'b1; + +endmodule diff --git a/rtl/ip/APB_UART/apb_mux2.v b/rtl/ip/APB_UART/apb_mux2.v new file mode 100644 index 0000000..7b585e5 --- /dev/null +++ b/rtl/ip/APB_UART/apb_mux2.v @@ -0,0 +1,206 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +`define APB_DEV0 6'h00 + +`define APB_DEV1 6'h1e + +module apb_mux2 ( +clk, +rst_n, +apb_ack_cpu, +apb_rw_cpu, +apb_psel_cpu, +apb_enab_cpu, +apb_addr_cpu, +apb_datai_cpu, +apb_datao_cpu, +apb_high_24b_rd, +apb_high_24b_wr, +apb_word_trans_cpu, + +apb_ready_dma, +apb_rw_dma, +apb_psel_dma, +apb_enab_dma, +apb_addr_dma, +apb_wdata_dma, +apb_rdata_dma, +apb_valid_dma, +apb_valid_cpu, +dma_grant, + +apb0_req, +apb0_ack, +apb0_rw, +apb0_psel, +apb0_enab, +apb0_addr, +apb0_datai, +apb0_datao, + +apb1_req, +apb1_ack, +apb1_rw, +apb1_psel, +apb1_enab, +apb1_addr, +apb1_datai, +apb1_datao +); + +parameter ADDR_APB = 20, + DATA_APB = 8, + DATA_APB_32 = 32; +input clk,rst_n; +output apb_ready_dma; +input apb_rw_dma; +input apb_psel_dma; +input apb_enab_dma; +input [ADDR_APB-1:0] apb_addr_dma; +input [31:0] apb_wdata_dma; +output[31:0] apb_rdata_dma; +output dma_grant; +input apb_valid_dma; +input apb_valid_cpu; + +output apb_ack_cpu; +input apb_rw_cpu; +input apb_psel_cpu; +input apb_enab_cpu; +input [ADDR_APB-1:0] apb_addr_cpu; +input [DATA_APB-1:0] apb_datai_cpu; +output[DATA_APB-1:0] apb_datao_cpu; +output [23:0] apb_high_24b_rd; +input [23:0] apb_high_24b_wr; + +output apb_word_trans_cpu; +output apb0_req; +input apb0_ack; +output apb0_rw; +output apb0_psel; +output apb0_enab; +output[ADDR_APB-1:0] apb0_addr; +output[DATA_APB-1:0] apb0_datai; +input [DATA_APB-1:0] apb0_datao; + +output apb1_req; +input apb1_ack; +output apb1_rw; +output apb1_psel; +output apb1_enab; +output[ADDR_APB-1:0] apb1_addr; +output[31:0] apb1_datai; +input [31:0] apb1_datao; + +wire apb_ack; +wire apb_rw; +wire apb_psel; +wire apb_enab; +wire [ADDR_APB-1:0] apb_addr; +wire [DATA_APB-1:0] apb_datai; +wire [23:0]high_24b_wr; +wire [23:0]high_24b_rd; +wire [7:0]apb_datao ; +wire dma_grant; + +arb_2_1 arb_2_1(.clk(clk), .rst_n(rst_n), .valid0(apb_valid_cpu), .valid1(apb_valid_dma), .dma_grant(dma_grant)); + +assign apb_addr = dma_grant ? apb_addr_dma:apb_addr_cpu; +assign apb_rw = dma_grant ? apb_rw_dma:apb_rw_cpu; +assign apb_psel = dma_grant ? apb_psel_dma:apb_psel_cpu; +assign apb_enab = dma_grant ? apb_enab_dma:apb_enab_cpu; +assign apb_datai = dma_grant ? apb_wdata_dma[7:0]:apb_datai_cpu; +assign high_24b_wr = dma_grant ? apb_wdata_dma[31:8]:apb_high_24b_wr; +assign high_24b_rd = apb1_req ? apb1_datao[31:8] : 24'h0; + +assign apb_word_trans_cpu = dma_grant ? 1'h0: apb1_req; + +assign apb_high_24b_rd = dma_grant ? 24'h0: high_24b_rd; +assign apb_datao_cpu = dma_grant ? 8'h0: apb_datao; +assign apb_rdata_dma = dma_grant ? {high_24b_rd,apb_datao }:32'h0; +assign apb_ack_cpu = ~dma_grant & apb_ack; +assign apb_ready_dma = dma_grant & apb_ack; + +assign apb0_req = (apb_addr[ADDR_APB-1:14] ==`APB_DEV0); +//assign apb1_req = (apb_addr[ADDR_APB-1:14] ==`APB_DEV1); +assign apb1_req = !apb0_req; + +assign apb0_psel = apb_psel && apb0_req ; +assign apb1_psel = apb_psel && apb1_req; + +assign apb0_enab = apb_enab && apb0_req ; +assign apb1_enab = apb_enab && apb1_req; + +assign apb_ack = apb0_req ? apb0_ack : + apb1_req ? apb1_ack : + 1'b0; + +assign apb_datao = apb0_req ? apb0_datao : + apb1_req ? apb1_datao[7:0] : + 8'b0; + + + +assign apb0_addr = apb_addr; +assign apb0_datai = apb_datai; +assign apb0_rw = apb_rw; + +assign apb1_addr = apb_addr; +assign apb1_datai = {high_24b_wr,apb_datai}; +assign apb1_rw = apb_rw; + +endmodule + +module arb_2_1( clk, rst_n, valid0, valid1, dma_grant); +input clk; +input rst_n; +input valid0; +input valid1; +output dma_grant; +reg dma_grant; + +always @(posedge clk) + if(~rst_n) + dma_grant<= 1'b0; + else if(valid0&&~valid1) + dma_grant<= 1'b0; + else if(valid1&&~valid0) + dma_grant<= 1'b1; + else if(valid0&&valid1&&~dma_grant) + dma_grant<= 1'b0; + else if(valid0&&valid1&&dma_grant) + dma_grant<= 1'b1; + else dma_grant<= 1'b0; + +endmodule diff --git a/rtl/ip/APB_UART/axi2apb.v b/rtl/ip/APB_UART/axi2apb.v new file mode 100644 index 0000000..bfbdcc6 --- /dev/null +++ b/rtl/ip/APB_UART/axi2apb.v @@ -0,0 +1,674 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +`include "config.h" + +module axi2apb_bridge( +clk, +rst_n, +axi_s_awid, +axi_s_awaddr, +axi_s_awlen, +axi_s_awsize, +axi_s_awburst, +axi_s_awlock, +axi_s_awcache, +axi_s_awprot, +axi_s_awvalid, +axi_s_awready, +axi_s_wid, +axi_s_wdata, +axi_s_wstrb, +axi_s_wlast, +axi_s_wvalid, +axi_s_wready, +axi_s_bid, +axi_s_bresp, +axi_s_bvalid, +axi_s_bready, +axi_s_arid, +axi_s_araddr, +axi_s_arlen, +axi_s_arsize, +axi_s_arburst, +axi_s_arlock, +axi_s_arcache, +axi_s_arprot, +axi_s_arvalid, +axi_s_arready, +axi_s_rid, +axi_s_rdata, +axi_s_rresp, +axi_s_rlast, +axi_s_rvalid, +axi_s_rready, + +apb_valid_cpu, +cpu_grant, +apb_word_trans, +apb_high_24b_rd, +apb_high_24b_wr, +apb_clk, +apb_reset_n, +reg_psel, +reg_enable, +reg_rw, +reg_addr, +reg_datai, +reg_ready_1, +reg_datao +); +parameter L_ADDR_APB = 20; + +input clk; +input rst_n; + +input [`LID :0] axi_s_awid; +input [`Lawaddr -1 :0] axi_s_awaddr; +input [`Lawlen -1 :0] axi_s_awlen; +input [`Lawsize -1 :0] axi_s_awsize; +input [`Lawburst -1 :0] axi_s_awburst; +input [`Lawlock -1 :0] axi_s_awlock; +input [`Lawcache -1 :0] axi_s_awcache; +input [`Lawprot -1 :0] axi_s_awprot; +input axi_s_awvalid; +output axi_s_awready; +input [`LID :0] axi_s_wid; +input [`Lwdata -1 :0] axi_s_wdata; +input [`Lwstrb -1 :0] axi_s_wstrb; +input axi_s_wlast; +input axi_s_wvalid; +output axi_s_wready; +output [`LID :0] axi_s_bid; +output [`Lbresp -1 :0] axi_s_bresp; +output axi_s_bvalid; +input axi_s_bready; +input [`LID :0] axi_s_arid; +input [`Laraddr -1 :0] axi_s_araddr; +input [`Larlen -1 :0] axi_s_arlen; +input [`Larsize -1 :0] axi_s_arsize; +input [`Larburst -1 :0] axi_s_arburst; +input [`Larlock -1 :0] axi_s_arlock; +input [`Larcache -1 :0] axi_s_arcache; +input [`Larprot -1 :0] axi_s_arprot; +input axi_s_arvalid; +output axi_s_arready; +output [`LID :0] axi_s_rid; +output [`Lrdata -1 :0] axi_s_rdata; +output [`Lrresp -1 :0] axi_s_rresp; +output axi_s_rlast; +output axi_s_rvalid; +input axi_s_rready; +input apb_word_trans; +input cpu_grant; +output apb_valid_cpu; +input [23:0] apb_high_24b_rd; +output [23:0] apb_high_24b_wr; +output apb_clk; +output apb_reset_n; +output reg_psel; +output reg_enable; +output reg_rw; +output[L_ADDR_APB-1:0] reg_addr; +output[7:0] reg_datai; +input [7:0] reg_datao; +input reg_ready_1; + +wire csr_rw_send_axi_rsp_done; +wire reg_ready; + +parameter CSR_RW_SM_IDLE = 4'b0001, + CSR_RW_SM_GET_AXI_ADDR = 4'b0010, + CSR_RW_SM_SEND_AXI_RSP = 4'b1000; + +reg reg_psel; +reg reg_enable; +reg axi_s_sel_rd; +reg axi_s_sel_wr; +reg[3:0] csr_rw_sm; +reg[3:0] csr_rw_sm_nxt; +reg[L_ADDR_APB-1:0] axi_s_req_addr; +reg[`LID:0] axi_s_w_id; +reg[`LID:0] axi_s_r_id; +reg[23:0] apb_high_24b_wr; + +assign apb_clk = clk; +assign apb_reset_n = rst_n; +assign reg_rw = axi_s_sel_wr; +assign reg_addr = axi_s_req_addr; +assign reg_ready = reg_enable & reg_ready_1; +assign apb_valid_cpu = axi_s_sel_wr | axi_s_sel_rd | axi_s_awvalid | axi_s_arvalid; +reg axi_s_rlast; +reg axi_s_rvalid; +reg axi_s_wready; +reg axi_s_awready; +reg axi_s_arready; + +reg [3:0]axi_s_rstrb; +reg [3:0]apb_s_wstrb; +reg [31:0]reg_datai_32; +reg [31:0]reg_datao_32; +reg [2:0] rd_count; +reg [2:0] apb_rd_size; +reg [2:0] apb_wr_size; +reg [7:0] reg_datai; +reg axi_s_bvalid; + +always@(posedge clk) +begin + if(!rst_n) + begin + reg_datai_32 <= 32'h0; + reg_datao_32 <= 32'h0; + axi_s_req_addr <= 20'h0; + apb_s_wstrb <= 4'b0; + axi_s_rstrb <= 4'b0; + axi_s_wready <= 1'b0; + reg_enable <= 1'b0; + reg_psel <= 1'b0; + rd_count <= 3'b0; + apb_rd_size <= 3'b0; + apb_wr_size <= 3'b0; + axi_s_rlast <= 1'b0; + axi_s_rvalid <= 1'b0; + reg_datai <= 8'b0; + axi_s_awready <= 1'b0; + axi_s_arready <= 1'b0; + axi_s_bvalid <= 1'b0; + axi_s_sel_wr <= 1'b0; + axi_s_sel_rd <= 1'b0; + axi_s_w_id <= 'h0; + axi_s_r_id <= 'h0; + apb_high_24b_wr <= 24'h0; + end + else begin + if(axi_s_awvalid & ~axi_s_bvalid & ~axi_s_sel_rd & (csr_rw_sm == CSR_RW_SM_IDLE) &cpu_grant) begin + axi_s_req_addr <= axi_s_awaddr[L_ADDR_APB-1:0]; + axi_s_awready <= 1'b1; + axi_s_sel_wr <= 1'b1; + apb_wr_size <= axi_s_awsize; + end + else if(axi_s_sel_wr) begin + axi_s_awready <= 1'b0; + if(axi_s_wvalid && ~axi_s_wready) begin + `ifdef AXI128 + axi_s_req_addr <= (axi_s_wstrb[15:0]==16'h0002)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h1): + (axi_s_wstrb[15:0]==16'h0004)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h2): + (axi_s_wstrb[15:0]==16'h0008)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h3): + (axi_s_wstrb[15:0]==16'h0010)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'h4): + (axi_s_wstrb[15:0]==16'h0020)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h5): + (axi_s_wstrb[15:0]==16'h0040)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h6): + (axi_s_wstrb[15:0]==16'h0080)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h7): + (axi_s_wstrb[15:0]==16'h0100)&&(axi_s_req_addr[ 3]==1'h0)? (axi_s_req_addr + 4'h8): + (axi_s_wstrb[15:0]==16'h0200)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h9): + (axi_s_wstrb[15:0]==16'h0400)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'ha): + (axi_s_wstrb[15:0]==16'h0800)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hb): + (axi_s_wstrb[15:0]==16'h1000)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'hc): + (axi_s_wstrb[15:0]==16'h2000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hd): + (axi_s_wstrb[15:0]==16'h4000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'he): + (axi_s_wstrb[15:0]==16'h8000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hf): + (axi_s_wstrb[15:0]==16'h0006)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h1): + (axi_s_wstrb[15:0]==16'h000c)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h2): + (axi_s_wstrb[15:0]==16'h0018)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h3): + (axi_s_wstrb[15:0]==16'h0030)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'h4): + (axi_s_wstrb[15:0]==16'h0060)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h5): + (axi_s_wstrb[15:0]==16'h00c0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h6): + (axi_s_wstrb[15:0]==16'h0180)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h7): + (axi_s_wstrb[15:0]==16'h0300)&&(axi_s_req_addr[ 3]==1'h0)? (axi_s_req_addr + 4'h8): + (axi_s_wstrb[15:0]==16'h0600)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h9): + (axi_s_wstrb[15:0]==16'h0c00)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'ha): + (axi_s_wstrb[15:0]==16'h1800)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hb): + (axi_s_wstrb[15:0]==16'h3000)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'hc): + (axi_s_wstrb[15:0]==16'h6000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hd): + (axi_s_wstrb[15:0]==16'hc000)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'he): + (axi_s_wstrb[15:0]==16'h001e)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h1): + (axi_s_wstrb[15:0]==16'h003c)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h2): + (axi_s_wstrb[15:0]==16'h0078)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h3): + (axi_s_wstrb[15:0]==16'h00f0)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'h4): + (axi_s_wstrb[15:0]==16'h01e0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h5): + (axi_s_wstrb[15:0]==16'h03c0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h6): + (axi_s_wstrb[15:0]==16'h0780)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h7): + (axi_s_wstrb[15:0]==16'h0f00)&&(axi_s_req_addr[ 3]==1'h0)? (axi_s_req_addr + 4'h8): + (axi_s_wstrb[15:0]==16'h1e00)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h9): + (axi_s_wstrb[15:0]==16'h3c00)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'ha): + (axi_s_wstrb[15:0]==16'h7800)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'hb): + (axi_s_wstrb[15:0]==16'hf000)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'hc): + (axi_s_wstrb[15:0]==16'h01fe)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h1): + (axi_s_wstrb[15:0]==16'h03fc)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h2): + (axi_s_wstrb[15:0]==16'h07f8)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h3): + (axi_s_wstrb[15:0]==16'h0ff0)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 4'h4): + (axi_s_wstrb[15:0]==16'h1fe0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h5): + (axi_s_wstrb[15:0]==16'h3fc0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h6): + (axi_s_wstrb[15:0]==16'h7f80)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 4'h7): + (axi_s_wstrb[15:0]==16'hff00)&&(axi_s_req_addr[ 3]==1'h0)? (axi_s_req_addr + 4'h8): axi_s_req_addr ; + `elsif AXI64 + axi_s_req_addr <= (axi_s_wstrb[7:0]==8'h02)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1): + (axi_s_wstrb[7:0]==8'h04)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2): + (axi_s_wstrb[7:0]==8'h08)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3): + (axi_s_wstrb[7:0]==8'h10)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 2'h4): + (axi_s_wstrb[7:0]==8'h20)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h5): + (axi_s_wstrb[7:0]==8'h40)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h6): + (axi_s_wstrb[7:0]==8'h80)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h7): + (axi_s_wstrb[7:0]==8'h06)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1): + (axi_s_wstrb[7:0]==8'h0c)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2): + (axi_s_wstrb[7:0]==8'h18)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3): + (axi_s_wstrb[7:0]==8'h30)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 2'h4): + (axi_s_wstrb[7:0]==8'h60)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h5): + (axi_s_wstrb[7:0]==8'hc0)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h6): + (axi_s_wstrb[7:0]==8'h1e)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1): + (axi_s_wstrb[7:0]==8'h3c)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2): + (axi_s_wstrb[7:0]==8'h78)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3): + (axi_s_wstrb[7:0]==8'hf0)&&(axi_s_req_addr[ 2]==1'h0)? (axi_s_req_addr + 2'h4): axi_s_req_addr ; + `else + axi_s_req_addr <= (axi_s_wstrb[3:0]==4'h2)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1): + (axi_s_wstrb[3:0]==4'h4)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2): + (axi_s_wstrb[3:0]==4'h8)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3): + (axi_s_wstrb[3:0]==4'h6)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1): + (axi_s_wstrb[3:0]==4'hc)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2): axi_s_req_addr ; + `endif + + axi_s_wready <= 1'b1; + reg_psel <= 1'b0; + reg_enable <= 1'b0; + axi_s_w_id <= axi_s_wid; + `ifdef AXI128 + case({axi_s_req_addr[3:0]}) + 4'b0000: begin apb_s_wstrb <= axi_s_wstrb[ 3: 0]; reg_datai_32 <=axi_s_wdata[ 31: 0]; end + 4'b0001: begin apb_s_wstrb <= axi_s_wstrb[ 4: 1]; reg_datai_32 <=axi_s_wdata[ 39: 8]; end + 4'b0010: begin apb_s_wstrb <= axi_s_wstrb[ 5: 2]; reg_datai_32 <=axi_s_wdata[ 47: 16]; end + 4'b0011: begin apb_s_wstrb <= axi_s_wstrb[ 6: 3]; reg_datai_32 <=axi_s_wdata[ 55: 24]; end + 4'b0100: begin apb_s_wstrb <= axi_s_wstrb[ 7: 4]; reg_datai_32 <=axi_s_wdata[ 63: 32]; end + 4'b0101: begin apb_s_wstrb <= axi_s_wstrb[ 8: 5]; reg_datai_32 <=axi_s_wdata[ 71: 40]; end + 4'b0110: begin apb_s_wstrb <= axi_s_wstrb[ 9: 6]; reg_datai_32 <=axi_s_wdata[ 79: 48]; end + 4'b0111: begin apb_s_wstrb <= axi_s_wstrb[10: 7]; reg_datai_32 <=axi_s_wdata[ 87: 56]; end + 4'b1000: begin apb_s_wstrb <= axi_s_wstrb[11: 8]; reg_datai_32 <=axi_s_wdata[ 95: 64]; end + 4'b1001: begin apb_s_wstrb <= axi_s_wstrb[12: 9]; reg_datai_32 <=axi_s_wdata[103: 72]; end + 4'b1010: begin apb_s_wstrb <= axi_s_wstrb[13:10]; reg_datai_32 <=axi_s_wdata[111: 80]; end + 4'b1011: begin apb_s_wstrb <= axi_s_wstrb[14:11]; reg_datai_32 <=axi_s_wdata[119: 88]; end + 4'b1100: begin apb_s_wstrb <= axi_s_wstrb[15:12]; reg_datai_32 <=axi_s_wdata[127: 96]; end + 4'b1101: begin apb_s_wstrb <= {1'b0, axi_s_wstrb[15:13]}; reg_datai_32 <={ 8'b0, axi_s_wdata[127:104]}; end + 4'b1110: begin apb_s_wstrb <= {2'b0, axi_s_wstrb[15:14]}; reg_datai_32 <={16'b0, axi_s_wdata[127:112]}; end + 4'b1111: begin apb_s_wstrb <= {3'b0, axi_s_wstrb[ 15]}; reg_datai_32 <={24'b0, axi_s_wdata[127:120]}; end + default: begin apb_s_wstrb <= 4'b0; reg_datai_32 <=32'h0; end + endcase + `elsif AXI64 + case({axi_s_req_addr[2:0]}) + 3'b000: begin apb_s_wstrb <= axi_s_wstrb[3:0]; reg_datai_32 <=axi_s_wdata[31: 0]; end + 3'b001: begin apb_s_wstrb <= axi_s_wstrb[4:1]; reg_datai_32 <=axi_s_wdata[39: 8]; end + 3'b010: begin apb_s_wstrb <= axi_s_wstrb[5:2]; reg_datai_32 <=axi_s_wdata[47:16]; end + 3'b011: begin apb_s_wstrb <= axi_s_wstrb[6:3]; reg_datai_32 <=axi_s_wdata[55:24]; end + 3'b100: begin apb_s_wstrb <= axi_s_wstrb[7:4]; reg_datai_32 <=axi_s_wdata[63:32]; end + 3'b101: begin apb_s_wstrb <= {1'b0, axi_s_wstrb[7:5]}; reg_datai_32 <={8 'b0, axi_s_wdata[63:40]}; end + 3'b110: begin apb_s_wstrb <= {2'b0, axi_s_wstrb[7:6]}; reg_datai_32 <={16'b0, axi_s_wdata[63:48]}; end + 3'b111: begin apb_s_wstrb <= {3'b0, axi_s_wstrb[ 7]}; reg_datai_32 <={24'b0, axi_s_wdata[63:56]}; end + default: begin apb_s_wstrb <= 4'b0; reg_datai_32 <=32'h0; end + endcase + `else + case({axi_s_req_addr[1:0]}) + 2'b00: begin apb_s_wstrb <= axi_s_wstrb[3:0]; reg_datai_32 <=axi_s_wdata[31:0]; end + 2'b01: begin apb_s_wstrb <= {1'b0,axi_s_wstrb[3:1]}; reg_datai_32 <={8'h0,axi_s_wdata[31:8]}; end + 2'b10: begin apb_s_wstrb <= {2'b0,axi_s_wstrb[3:2]}; reg_datai_32 <={16'b0,axi_s_wdata[31:16]}; end + 2'b11: begin apb_s_wstrb <= {3'b0,axi_s_wstrb[3]}; reg_datai_32 <={24'b0,axi_s_wdata[31:24]}; end + default: begin apb_s_wstrb <= 4'b0; reg_datai_32 <=32'h0; end + endcase + `endif + end + else if((~reg_psel) && (apb_s_wstrb!=4'h0) ) begin + reg_psel <= 1'b1; + reg_enable <= 1'b0; + reg_datai <= (apb_s_wstrb == 4'h1) ? reg_datai_32[7:0]: + (apb_s_wstrb == 4'h2) ? reg_datai_32[15:8]: + (apb_s_wstrb == 4'h6) ? reg_datai_32[15:8]: + (apb_s_wstrb == 4'h4) ? reg_datai_32[23:16]: + (apb_s_wstrb == 4'h8) ? reg_datai_32[31:24]: reg_datai_32[7:0]; + apb_high_24b_wr <= reg_datai_32[31:8]; + if(axi_s_bready) axi_s_bvalid <= 1'b0; + end + else if(apb_word_trans & apb_s_wstrb==4'hf ) begin + if(~reg_ready)begin + reg_psel <= 1'b1; + reg_enable <= 1'b1; + end + else begin + reg_psel <= 1'b0; + reg_enable <= 1'b0; + axi_s_sel_wr <= 1'b0; + axi_s_bvalid <= 1'b1; + apb_s_wstrb <= 4'b0; + end + reg_datai <= reg_datai_32[7:0]; + apb_high_24b_wr <= reg_datai_32[31:8]; + axi_s_wready <= 1'b0; + end + else if(apb_s_wstrb[0]) begin + if(~reg_ready)begin + reg_psel <= 1'b1; + reg_enable <= 1'b1; + reg_datai <= reg_datai_32[7:0]; + end + else begin + if(apb_s_wstrb[3:1] ==3'b0) + begin + reg_psel <= 1'b0; + axi_s_sel_wr<= 1'b0; + axi_s_bvalid <= 1'b1; + end + else + reg_psel <= 1'b1; + reg_enable <= 1'b0; + apb_s_wstrb[0] <= 1'b0; + axi_s_req_addr <= axi_s_req_addr +1'b1; + reg_datai <= reg_datai_32[15:8]; + end + axi_s_wready <= 1'b0; + end + else if (apb_s_wstrb[1]) begin + if(~reg_ready)begin + reg_psel <= 1'b1; + reg_enable <= 1'b1; + end + else begin + if(apb_s_wstrb[3:2] ==2'b0) + begin + reg_psel <= 1'b0; + axi_s_sel_wr <= 1'b0; + axi_s_bvalid <= 1'b1; + end + else + reg_psel <= 1'b1; + reg_enable <= 1'b0; + apb_s_wstrb[1] <= 1'b0; + axi_s_req_addr <= axi_s_req_addr +1'b1; + reg_datai <= reg_datai_32[23:16]; + end + axi_s_wready <= 1'b0; + end + else if (apb_s_wstrb[2]) begin + if(~reg_ready)begin + reg_psel <= 1'b1; + reg_enable <= 1'b1; + end + else begin + if(apb_s_wstrb[3] ==1'b0) + begin + reg_psel <= 1'b0; + axi_s_sel_wr <= 1'b0; + axi_s_bvalid <= 1'b1; + end + else + reg_psel <= 1'b1; + reg_enable <= 1'b0; + apb_s_wstrb[2] <= 1'b0; + axi_s_req_addr <= axi_s_req_addr +1'b1; + reg_datai <= reg_datai_32[31:24]; + end + axi_s_wready <= 1'b0; + end + else if (apb_s_wstrb[3]) begin + if(~reg_ready)begin + reg_psel <= 1'b1; + reg_enable <= 1'b1; + end + else begin + reg_psel <= 1'b0; + reg_enable <= 1'b0; + axi_s_sel_wr <= 1'b0; + axi_s_bvalid <= 1'b1; + apb_s_wstrb[3] <= 1'b0; + end + axi_s_wready <= 1'b0; + end + else begin + reg_psel <= 1'b0; + reg_enable <= 1'b0; + reg_datai <= 8'h0; + apb_s_wstrb <= 4'h0; + axi_s_wready <= 1'b0; + if(csr_rw_sm == CSR_RW_SM_IDLE) axi_s_sel_wr <= 1'b0; + end + end + else if(axi_s_arvalid & ~axi_s_arready & ~axi_s_bvalid & (csr_rw_sm == CSR_RW_SM_IDLE)&cpu_grant) + begin + reg_enable <= 1'b0; + reg_psel <= 1'b1; + axi_s_arready <= 1'b1; + axi_s_sel_rd <= 1'b1; + axi_s_r_id <= axi_s_arid; + apb_rd_size <= axi_s_arsize; + axi_s_req_addr <= axi_s_araddr[L_ADDR_APB-1:0]; + axi_s_rstrb <= axi_s_araddr[3:0]; + if(axi_s_arsize==3'b010) + rd_count<= 3'h4; + else if(axi_s_arsize==3'b01) + rd_count<= 3'h2; + else if(axi_s_arsize==3'b0) + rd_count<= 3'h1; + end + else if(axi_s_sel_rd) + begin + axi_s_arready <= 1'b0; + if(apb_word_trans) + begin + if(reg_ready) + begin + reg_psel <= rd_count==3'b10; + reg_enable <= 1'b0; + rd_count <= rd_count-3'b1; + axi_s_rlast <= apb_rd_size==3'h2|rd_count==2'b1; + axi_s_rvalid <= apb_rd_size==3'h2|rd_count==2'b1; + axi_s_sel_rd <= rd_count==3'b10; + reg_datao_32 <= {apb_high_24b_rd,reg_datao}; + end + else begin + reg_psel <= 1'b1; + reg_enable <= 1'b1; + end + end + else if(rd_count==3'h4) + begin + if(reg_ready) + begin + reg_psel <= 1'b1; + reg_enable <= 1'b0; + rd_count <= rd_count-3'h1; + reg_datao_32[7:0] <= reg_datao; + axi_s_req_addr <= axi_s_req_addr +1'b1; + end + else begin + reg_psel <= 1'b1; + reg_enable <= 1'b1; + end + end + else if(rd_count==3'h3) + begin + if(reg_ready) + begin + reg_psel <= 1'b1; + reg_enable <= 1'b0; + rd_count <= rd_count-3'h1; + reg_datao_32[15:8] <= reg_datao; + axi_s_req_addr <= axi_s_req_addr +1'b1; + end + else begin + reg_psel <= 1'b1; + reg_enable <= 1'b1; + end + end + else if(rd_count==3'h2) + begin + if(reg_ready) + begin + reg_psel <= 1'b1; + reg_enable <= 1'b0; + rd_count <= rd_count-3'h1; + axi_s_req_addr <= axi_s_req_addr +1'b1; + if(apb_rd_size==3'h2 ) + reg_datao_32[23:16] <= reg_datao; + else if(apb_rd_size==3'h1) + reg_datao_32[7:0] <= reg_datao; + end + else begin + reg_psel <= 1'b1; + reg_enable <= 1'b1; + end + end + else if(rd_count==3'h1) + begin + if(reg_ready) + begin + reg_psel <= 1'b0; + reg_enable <= 1'b0; + axi_s_rlast <= 1'b1; + axi_s_rvalid <= 1'b1; + axi_s_sel_rd <= 1'b0; + if(apb_rd_size==3'h2 ) + reg_datao_32[31:24] <= reg_datao; + else if(apb_rd_size==3'h1) + reg_datao_32[15:8] <= reg_datao; + else if(apb_rd_size==3'h0) + reg_datao_32[7:0] <= reg_datao; + end + else begin + reg_psel <= 1'b1; + reg_enable <= 1'b1; + end + end// end if(rd_count) + else begin + axi_s_arready <= 1'b0; + axi_s_rlast <= 1'b1; + axi_s_rvalid <= 1'b1; + reg_psel <= 1'b0; + reg_enable <= 1'b0; + if(axi_s_rvalid && axi_s_rready) + begin + reg_datao_32 <= 32'h0; + axi_s_rlast <= 1'b0; + axi_s_rvalid <= 1'b0; + end + if(csr_rw_sm == CSR_RW_SM_IDLE) axi_s_sel_rd <= 1'b0; + if(axi_s_bready) axi_s_bvalid <= 1'b0; + end + end//end if(axi_s_sel_rd) + else begin + reg_psel <= 1'b0; + reg_enable <= 1'b0; + axi_s_sel_wr <= 1'b0; + axi_s_sel_rd <= 1'b0; + axi_s_wready <= 1'b0; + axi_s_arready <= 1'b0; + axi_s_req_addr <= 32'h0; + reg_datai_32 <= 32'h0; + if(axi_s_bready) axi_s_bvalid <= 1'b0; + if(axi_s_rvalid && axi_s_rready) + begin + reg_datao_32 <= 32'h0; + axi_s_rlast <= 1'b0; + axi_s_rvalid <= 1'b0; + end + end + end//end if(rst_n) +end//end always + +assign csr_rw_send_axi_rsp_done = csr_rw_sm == CSR_RW_SM_SEND_AXI_RSP && axi_s_rlast && axi_s_rready || axi_s_bvalid && axi_s_bready; + +assign axi_s_bid = axi_s_w_id; +assign axi_s_rid = axi_s_r_id; +assign axi_s_bresp = 2'b00; +assign axi_s_rresp = 2'b00; +`ifdef AXI128 +assign axi_s_rdata= ( axi_s_rstrb == 4'h0) ? {96'b0, reg_datao_32 } : + ( axi_s_rstrb == 4'h1) ? {88'b0, reg_datao_32, 8'b0 } : + ( axi_s_rstrb == 4'h2) ? {80'b0, reg_datao_32, 16'b0 } : + ( axi_s_rstrb == 4'h3) ? {72'b0, reg_datao_32, 24'b0 } : + ( axi_s_rstrb == 4'h4) ? {64'b0, reg_datao_32, 32'b0 } : + ( axi_s_rstrb == 4'h5) ? {56'b0, reg_datao_32, 40'b0 } : + ( axi_s_rstrb == 4'h6) ? {48'b0, reg_datao_32, 48'b0 } : + ( axi_s_rstrb == 4'h7) ? {40'b0, reg_datao_32, 56'b0 } : + ( axi_s_rstrb == 4'h8) ? {32'b0, reg_datao_32, 64'b0 } : + ( axi_s_rstrb == 4'h9) ? {24'b0, reg_datao_32, 72'b0 } : + ( axi_s_rstrb == 4'ha) ? {16'b0, reg_datao_32, 80'b0 } : + ( axi_s_rstrb == 4'hb) ? { 8'b0, reg_datao_32, 88'b0 } : + ( axi_s_rstrb == 4'hc) ? {reg_datao_32, 96'b0 } : + ( axi_s_rstrb == 4'hd) ? {reg_datao_32[23:0], 104'b0 } : + ( axi_s_rstrb == 4'he) ? {reg_datao_32[15:0], 112'b0 } : + ( axi_s_rstrb == 4'hf) ? {reg_datao_32[ 7:0], 120'b0 } : 128'h0; + +`elsif AXI64 +assign axi_s_rdata= ( axi_s_rstrb[2:0] == 3'h0) ? {32'b0, reg_datao_32 } : + ( axi_s_rstrb[2:0] == 3'h1) ? {24'b0, reg_datao_32, 8'b0 } : + ( axi_s_rstrb[2:0] == 3'h2) ? {16'b0, reg_datao_32, 16'b0 } : + ( axi_s_rstrb[2:0] == 3'h3) ? { 8'b0, reg_datao_32, 24'b0 } : + ( axi_s_rstrb[2:0] == 3'h4) ? {reg_datao_32, 32'b0 } : + ( axi_s_rstrb[2:0] == 3'h5) ? {reg_datao_32[23:0], 40'b0 } : + ( axi_s_rstrb[2:0] == 3'h6) ? {reg_datao_32[15:0], 48'b0 } : + ( axi_s_rstrb[2:0] == 3'h7) ? {reg_datao_32[ 7:0], 56'b0 } : 64'h0; +`else +assign axi_s_rdata= ( axi_s_rstrb[1:0] == 2'h0) ? { reg_datao_32 } : + ( axi_s_rstrb[1:0] == 2'h1) ? {reg_datao_32[23:0], 8'h0} : + ( axi_s_rstrb[1:0] == 2'h2) ? {reg_datao_32[15:0],16'h0} : + ( axi_s_rstrb[1:0] == 2'h3) ? {reg_datao_32[7:0], 24'h0} : 32'h0; +`endif +always@(csr_rw_sm or axi_s_awvalid or axi_s_arvalid or axi_s_sel_rd or axi_s_sel_wr or + axi_s_wready or csr_rw_send_axi_rsp_done or cpu_grant) begin + case(csr_rw_sm) + CSR_RW_SM_IDLE: + if((axi_s_awvalid || axi_s_arvalid)&&~(axi_s_sel_wr||axi_s_sel_rd)&cpu_grant) + csr_rw_sm_nxt = CSR_RW_SM_GET_AXI_ADDR; + else + csr_rw_sm_nxt = CSR_RW_SM_IDLE; + CSR_RW_SM_GET_AXI_ADDR: + if(axi_s_sel_wr) + csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP; + else if(axi_s_sel_rd) + csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP; + else + csr_rw_sm_nxt = CSR_RW_SM_GET_AXI_ADDR; + CSR_RW_SM_SEND_AXI_RSP: + if(csr_rw_send_axi_rsp_done) + csr_rw_sm_nxt = CSR_RW_SM_IDLE; + else + csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP; + default: + csr_rw_sm_nxt = CSR_RW_SM_IDLE; + endcase +end + +always@(posedge clk) begin + if(!rst_n) + csr_rw_sm <= CSR_RW_SM_IDLE; + else + csr_rw_sm <= csr_rw_sm_nxt; +end + +endmodule + diff --git a/rtl/ip/APB_UART/axi_uart_controller.v b/rtl/ip/APB_UART/axi_uart_controller.v new file mode 100644 index 0000000..e93ea75 --- /dev/null +++ b/rtl/ip/APB_UART/axi_uart_controller.v @@ -0,0 +1,356 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +`include "config.h" + +module axi_uart_controller +( +clk, +rst_n, + +axi_s_awid, +axi_s_awaddr, +axi_s_awlen, +axi_s_awsize, +axi_s_awburst, +axi_s_awlock, +axi_s_awcache, +axi_s_awprot, +axi_s_awvalid, +axi_s_awready, +axi_s_wid, +axi_s_wdata, +axi_s_wstrb, +axi_s_wlast, +axi_s_wvalid, +axi_s_wready, +axi_s_bid, +axi_s_bresp, +axi_s_bvalid, +axi_s_bready, +axi_s_arid, +axi_s_araddr, +axi_s_arlen, +axi_s_arsize, +axi_s_arburst, +axi_s_arlock, +axi_s_arcache, +axi_s_arprot, +axi_s_arvalid, +axi_s_arready, +axi_s_rid, +axi_s_rdata, +axi_s_rresp, +axi_s_rlast, +axi_s_rvalid, +axi_s_rready, + +apb_rw_dma, +apb_psel_dma, +apb_enab_dma, +apb_addr_dma, +apb_valid_dma, +apb_wdata_dma, +apb_rdata_dma, +apb_ready_dma, +dma_grant, + +dma_req_o, +dma_ack_i, + +uart0_txd_i, +uart0_txd_o, +uart0_txd_oe, +uart0_rxd_i, +uart0_rxd_o, +uart0_rxd_oe, +uart0_rts_o, +uart0_dtr_o, +uart0_cts_i, +uart0_dsr_i, +uart0_dcd_i, +uart0_ri_i, + +uart0_int +); + +parameter ADDR_APB = 20, + DATA_APB = 8; + +input clk; +input rst_n; + +input [`LID :0] axi_s_awid; +input [`Lawaddr -1 :0] axi_s_awaddr; +input [`Lawlen -1 :0] axi_s_awlen; +input [`Lawsize -1 :0] axi_s_awsize; +input [`Lawburst -1 :0] axi_s_awburst; +input [`Lawlock -1 :0] axi_s_awlock; +input [`Lawcache -1 :0] axi_s_awcache; +input [`Lawprot -1 :0] axi_s_awprot; +input axi_s_awvalid; +output axi_s_awready; +input [`LID :0] axi_s_wid; +input [`Lwdata -1 :0] axi_s_wdata; +input [`Lwstrb -1 :0] axi_s_wstrb; +input axi_s_wlast; +input axi_s_wvalid; +output axi_s_wready; +output [`LID :0] axi_s_bid; +output [`Lbresp -1 :0] axi_s_bresp; +output axi_s_bvalid; +input axi_s_bready; +input [`LID :0] axi_s_arid; +input [`Laraddr -1 :0] axi_s_araddr; +input [`Larlen -1 :0] axi_s_arlen; +input [`Larsize -1 :0] axi_s_arsize; +input [`Larburst -1 :0] axi_s_arburst; +input [`Larlock -1 :0] axi_s_arlock; +input [`Larcache -1 :0] axi_s_arcache; +input [`Larprot -1 :0] axi_s_arprot; +input axi_s_arvalid; +output axi_s_arready; +output [`LID :0] axi_s_rid; +output [`Lrdata -1 :0] axi_s_rdata; +output [`Lrresp -1 :0] axi_s_rresp; +output axi_s_rlast; +output axi_s_rvalid; +input axi_s_rready; + +output apb_ready_dma; +input apb_rw_dma; +input apb_psel_dma; +input apb_enab_dma; +input [ADDR_APB-1:0] apb_addr_dma; +input [31:0] apb_wdata_dma; +output[31:0] apb_rdata_dma; +input apb_valid_dma; +output dma_grant; + +output dma_req_o; +input dma_ack_i; + +input uart0_txd_i; +output uart0_txd_o; +output uart0_txd_oe; +input uart0_rxd_i; +output uart0_rxd_o; +output uart0_rxd_oe; +output uart0_rts_o; +output uart0_dtr_o; +input uart0_cts_i; +input uart0_dsr_i; +input uart0_dcd_i; +input uart0_ri_i; + +output uart0_int; + +assign dma_req_o = 1'b0; +assign nand_dma_ack_i = dma_ack_i; + +wire apb_ready_cpu; +wire apb_rw_cpu; +wire apb_psel_cpu; +wire apb_enab_cpu; +wire [ADDR_APB-1 :0] apb_addr_cpu; +wire [DATA_APB-1:0] apb_datai_cpu; +wire [DATA_APB-1:0] apb_datao_cpu; +wire apb_clk_cpu; +wire apb_reset_n_cpu; +wire apb_word_trans_cpu; +wire apb_valid_cpu; +wire dma_grant; +wire [23:0] apb_high_24b_rd; +wire [23:0] apb_high_24b_wr; + +wire apb_rw_dma; +wire apb_psel_dma; +wire apb_enab_dma; +wire [31:0] apb_wdata_dma; +wire [31:0] apb_rdata_dma; +wire apb_clk_dma; +wire apb_reset_n_dma; + +wire apb_uart0_req; +wire apb_uart0_ack; +wire apb_uart0_rw; +wire apb_uart0_enab; +wire apb_uart0_psel; +wire [ADDR_APB -1:0] apb_uart0_addr; +wire [DATA_APB -1:0] apb_uart0_datai; +wire [DATA_APB -1:0] apb_uart0_datao; + +wire apb_nand_req; +wire apb_nand_ack; +wire apb_nand_rw; +wire apb_nand_enab; +wire apb_nand_psel; +wire [ADDR_APB -1:0] apb_nand_addr; +wire [31:0] apb_nand_datai; +wire [31:0] apb_nand_datao; + +axi2apb_bridge AA_axi2apb_bridge_cpu +( +.clk (clk ), +.rst_n (rst_n ), +.axi_s_awid (axi_s_awid ), +.axi_s_awaddr (axi_s_awaddr ), +.axi_s_awlen (axi_s_awlen ), +.axi_s_awsize (axi_s_awsize ), +.axi_s_awburst (axi_s_awburst ), +.axi_s_awlock (axi_s_awlock ), +.axi_s_awcache (axi_s_awcache ), +.axi_s_awprot (axi_s_awprot ), +.axi_s_awvalid (axi_s_awvalid ), +.axi_s_awready (axi_s_awready ), +.axi_s_wid (axi_s_wid ), +.axi_s_wdata (axi_s_wdata ), +.axi_s_wstrb (axi_s_wstrb ), +.axi_s_wlast (axi_s_wlast ), +.axi_s_wvalid (axi_s_wvalid ), +.axi_s_wready (axi_s_wready ), +.axi_s_bid (axi_s_bid ), +.axi_s_bresp (axi_s_bresp ), +.axi_s_bvalid (axi_s_bvalid ), +.axi_s_bready (axi_s_bready ), +.axi_s_arid (axi_s_arid ), +.axi_s_araddr (axi_s_araddr ), +.axi_s_arlen (axi_s_arlen ), +.axi_s_arsize (axi_s_arsize ), +.axi_s_arburst (axi_s_arburst ), +.axi_s_arlock (axi_s_arlock ), +.axi_s_arcache (axi_s_arcache ), +.axi_s_arprot (axi_s_arprot ), +.axi_s_arvalid (axi_s_arvalid ), +.axi_s_arready (axi_s_arready ), +.axi_s_rid (axi_s_rid ), +.axi_s_rdata (axi_s_rdata ), +.axi_s_rresp (axi_s_rresp ), +.axi_s_rlast (axi_s_rlast ), +.axi_s_rvalid (axi_s_rvalid ), +.axi_s_rready (axi_s_rready ), + +.apb_word_trans (apb_word_trans_cpu ), +.apb_high_24b_rd (apb_high_24b_rd ), +.apb_high_24b_wr (apb_high_24b_wr ), +.apb_valid_cpu (apb_valid_cpu ), +.cpu_grant (~dma_grant ), + +.apb_clk (apb_clk_cpu ), +.apb_reset_n (apb_reset_n_cpu ), +.reg_psel (apb_psel_cpu ), +.reg_enable (apb_enab_cpu ), +.reg_rw (apb_rw_cpu ), +.reg_addr (apb_addr_cpu ), +.reg_datai (apb_datai_cpu ), +.reg_datao (apb_datao_cpu ), +.reg_ready_1 (apb_ready_cpu ) +); + +apb_mux2 u_apb_mux2 +( +.clk (clk ), +.rst_n (rst_n ), +.apb_ready_dma (apb_ready_dma ), +.apb_rw_dma (apb_rw_dma ), +.apb_addr_dma (apb_addr_dma ), +.apb_psel_dma (apb_psel_dma ), +.apb_enab_dma (apb_enab_dma ), +.apb_wdata_dma (apb_wdata_dma ), +.apb_rdata_dma (apb_rdata_dma ), +.apb_valid_dma (apb_valid_dma ), +.apb_valid_cpu (apb_valid_cpu ), +.dma_grant (dma_grant ), + +.apb_ack_cpu (apb_ready_cpu ), +.apb_rw_cpu (apb_rw_cpu ), +.apb_addr_cpu (apb_addr_cpu ), +.apb_psel_cpu (apb_psel_cpu ), +.apb_enab_cpu (apb_enab_cpu ), +.apb_datai_cpu (apb_datai_cpu ), +.apb_datao_cpu (apb_datao_cpu ), +.apb_high_24b_rd (apb_high_24b_rd), +.apb_high_24b_wr (apb_high_24b_wr), +.apb_word_trans_cpu (apb_word_trans_cpu ), + +.apb0_req (apb_uart0_req ), +.apb0_ack (apb_uart0_ack ), +.apb0_rw (apb_uart0_rw ), +.apb0_psel (apb_uart0_psel ), +.apb0_enab (apb_uart0_enab ), +.apb0_addr (apb_uart0_addr ), +.apb0_datai (apb_uart0_datai ), +.apb0_datao (apb_uart0_datao ), + +.apb1_req ( ), +.apb1_ack (1'b1 ), +.apb1_rw ( ), +.apb1_enab ( ), +.apb1_psel ( ), +.apb1_addr ( ), +.apb1_datai ( ), +.apb1_datao (32'b0 ) + +); + +//uart0 +assign apb_uart0_ack = apb_uart0_enab; +UART_TOP uart0 +( +.PCLK (clk ), +.clk_carrier (1'b0 ), +.PRST_ (rst_n ), +.PSEL (apb_uart0_psel ), +.PENABLE (apb_uart0_enab ), +.PADDR (apb_uart0_addr[7:0] ), +.PWRITE (apb_uart0_rw ), +.PWDATA (apb_uart0_datai ), +.URT_PRDATA (apb_uart0_datao ), +.INT (uart0_int ), +.TXD_o (uart0_txd_o ), +.TXD_i (uart0_txd_i ), +.TXD_oe (uart0_txd_oe ), +.RXD_o (uart0_rxd_o ), +.RXD_i (uart0_rxd_i ), +.RXD_oe (uart0_rxd_oe ), +.RTS (uart0_rts_o ), +.CTS (uart0_cts_i ), +.DSR (uart0_dsr_i ), +.DCD (uart0_dcd_i ), +.DTR (uart0_dtr_o ), +.RI (uart0_ri_i ) +); + +endmodule + + diff --git a/rtl/ip/Bus_interconnects/AxiCrossbar_2x8.v b/rtl/ip/Bus_interconnects/AxiCrossbar_2x8.v new file mode 100644 index 0000000..a1d84a1 --- /dev/null +++ b/rtl/ip/Bus_interconnects/AxiCrossbar_2x8.v @@ -0,0 +1,6331 @@ +// Generator : SpinalHDL v1.10.1 git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43 +// Component : AxiCrossbar_2x8 + + +module AxiCrossbar_2x8 ( + input wire axiIn_0_awvalid, + output wire axiIn_0_awready, + input wire [31:0] axiIn_0_awaddr, + input wire [3:0] axiIn_0_awid, + input wire [7:0] axiIn_0_awlen, + input wire [2:0] axiIn_0_awsize, + input wire [1:0] axiIn_0_awburst, + input wire [0:0] axiIn_0_awlock, + input wire [3:0] axiIn_0_awcache, + input wire [2:0] axiIn_0_awprot, + input wire axiIn_0_wvalid, + output wire axiIn_0_wready, + input wire [31:0] axiIn_0_wdata, + input wire [3:0] axiIn_0_wstrb, + input wire axiIn_0_wlast, + output wire axiIn_0_bvalid, + input wire axiIn_0_bready, + output wire [3:0] axiIn_0_bid, + output wire [1:0] axiIn_0_bresp, + input wire axiIn_0_arvalid, + output wire axiIn_0_arready, + input wire [31:0] axiIn_0_araddr, + input wire [3:0] axiIn_0_arid, + input wire [7:0] axiIn_0_arlen, + input wire [2:0] axiIn_0_arsize, + input wire [1:0] axiIn_0_arburst, + input wire [0:0] axiIn_0_arlock, + input wire [3:0] axiIn_0_arcache, + input wire [2:0] axiIn_0_arprot, + output wire axiIn_0_rvalid, + input wire axiIn_0_rready, + output wire [31:0] axiIn_0_rdata, + output wire [3:0] axiIn_0_rid, + output wire [1:0] axiIn_0_rresp, + output wire axiIn_0_rlast, + input wire axiIn_1_awvalid, + output wire axiIn_1_awready, + input wire [31:0] axiIn_1_awaddr, + input wire [3:0] axiIn_1_awid, + input wire [7:0] axiIn_1_awlen, + input wire [2:0] axiIn_1_awsize, + input wire [1:0] axiIn_1_awburst, + input wire [0:0] axiIn_1_awlock, + input wire [3:0] axiIn_1_awcache, + input wire [2:0] axiIn_1_awprot, + input wire axiIn_1_wvalid, + output wire axiIn_1_wready, + input wire [31:0] axiIn_1_wdata, + input wire [3:0] axiIn_1_wstrb, + input wire axiIn_1_wlast, + output wire axiIn_1_bvalid, + input wire axiIn_1_bready, + output wire [3:0] axiIn_1_bid, + output wire [1:0] axiIn_1_bresp, + input wire axiIn_1_arvalid, + output wire axiIn_1_arready, + input wire [31:0] axiIn_1_araddr, + input wire [3:0] axiIn_1_arid, + input wire [7:0] axiIn_1_arlen, + input wire [2:0] axiIn_1_arsize, + input wire [1:0] axiIn_1_arburst, + input wire [0:0] axiIn_1_arlock, + input wire [3:0] axiIn_1_arcache, + input wire [2:0] axiIn_1_arprot, + output wire axiIn_1_rvalid, + input wire axiIn_1_rready, + output wire [31:0] axiIn_1_rdata, + output wire [3:0] axiIn_1_rid, + output wire [1:0] axiIn_1_rresp, + output wire axiIn_1_rlast, + output wire axiOut_0_awvalid, + input wire axiOut_0_awready, + output wire [31:0] axiOut_0_awaddr, + output wire [4:0] axiOut_0_awid, + output wire [7:0] axiOut_0_awlen, + output wire [2:0] axiOut_0_awsize, + output wire [1:0] axiOut_0_awburst, + output wire [0:0] axiOut_0_awlock, + output wire [3:0] axiOut_0_awcache, + output wire [2:0] axiOut_0_awprot, + output wire axiOut_0_wvalid, + input wire axiOut_0_wready, + output wire [31:0] axiOut_0_wdata, + output wire [3:0] axiOut_0_wstrb, + output wire axiOut_0_wlast, + input wire axiOut_0_bvalid, + output wire axiOut_0_bready, + input wire [4:0] axiOut_0_bid, + input wire [1:0] axiOut_0_bresp, + output wire axiOut_0_arvalid, + input wire axiOut_0_arready, + output wire [31:0] axiOut_0_araddr, + output wire [4:0] axiOut_0_arid, + output wire [7:0] axiOut_0_arlen, + output wire [2:0] axiOut_0_arsize, + output wire [1:0] axiOut_0_arburst, + output wire [0:0] axiOut_0_arlock, + output wire [3:0] axiOut_0_arcache, + output wire [2:0] axiOut_0_arprot, + input wire axiOut_0_rvalid, + output wire axiOut_0_rready, + input wire [31:0] axiOut_0_rdata, + input wire [4:0] axiOut_0_rid, + input wire [1:0] axiOut_0_rresp, + input wire axiOut_0_rlast, + output wire axiOut_1_awvalid, + input wire axiOut_1_awready, + output wire [31:0] axiOut_1_awaddr, + output wire [4:0] axiOut_1_awid, + output wire [7:0] axiOut_1_awlen, + output wire [2:0] axiOut_1_awsize, + output wire [1:0] axiOut_1_awburst, + output wire [0:0] axiOut_1_awlock, + output wire [3:0] axiOut_1_awcache, + output wire [2:0] axiOut_1_awprot, + output wire axiOut_1_wvalid, + input wire axiOut_1_wready, + output wire [31:0] axiOut_1_wdata, + output wire [3:0] axiOut_1_wstrb, + output wire axiOut_1_wlast, + input wire axiOut_1_bvalid, + output wire axiOut_1_bready, + input wire [4:0] axiOut_1_bid, + input wire [1:0] axiOut_1_bresp, + output wire axiOut_1_arvalid, + input wire axiOut_1_arready, + output wire [31:0] axiOut_1_araddr, + output wire [4:0] axiOut_1_arid, + output wire [7:0] axiOut_1_arlen, + output wire [2:0] axiOut_1_arsize, + output wire [1:0] axiOut_1_arburst, + output wire [0:0] axiOut_1_arlock, + output wire [3:0] axiOut_1_arcache, + output wire [2:0] axiOut_1_arprot, + input wire axiOut_1_rvalid, + output wire axiOut_1_rready, + input wire [31:0] axiOut_1_rdata, + input wire [4:0] axiOut_1_rid, + input wire [1:0] axiOut_1_rresp, + input wire axiOut_1_rlast, + output wire axiOut_2_awvalid, + input wire axiOut_2_awready, + output wire [31:0] axiOut_2_awaddr, + output wire [4:0] axiOut_2_awid, + output wire [7:0] axiOut_2_awlen, + output wire [2:0] axiOut_2_awsize, + output wire [1:0] axiOut_2_awburst, + output wire [0:0] axiOut_2_awlock, + output wire [3:0] axiOut_2_awcache, + output wire [2:0] axiOut_2_awprot, + output wire axiOut_2_wvalid, + input wire axiOut_2_wready, + output wire [31:0] axiOut_2_wdata, + output wire [3:0] axiOut_2_wstrb, + output wire axiOut_2_wlast, + input wire axiOut_2_bvalid, + output wire axiOut_2_bready, + input wire [4:0] axiOut_2_bid, + input wire [1:0] axiOut_2_bresp, + output wire axiOut_2_arvalid, + input wire axiOut_2_arready, + output wire [31:0] axiOut_2_araddr, + output wire [4:0] axiOut_2_arid, + output wire [7:0] axiOut_2_arlen, + output wire [2:0] axiOut_2_arsize, + output wire [1:0] axiOut_2_arburst, + output wire [0:0] axiOut_2_arlock, + output wire [3:0] axiOut_2_arcache, + output wire [2:0] axiOut_2_arprot, + input wire axiOut_2_rvalid, + output wire axiOut_2_rready, + input wire [31:0] axiOut_2_rdata, + input wire [4:0] axiOut_2_rid, + input wire [1:0] axiOut_2_rresp, + input wire axiOut_2_rlast, + output wire axiOut_3_awvalid, + input wire axiOut_3_awready, + output wire [31:0] axiOut_3_awaddr, + output wire [4:0] axiOut_3_awid, + output wire [7:0] axiOut_3_awlen, + output wire [2:0] axiOut_3_awsize, + output wire [1:0] axiOut_3_awburst, + output wire [0:0] axiOut_3_awlock, + output wire [3:0] axiOut_3_awcache, + output wire [2:0] axiOut_3_awprot, + output wire axiOut_3_wvalid, + input wire axiOut_3_wready, + output wire [31:0] axiOut_3_wdata, + output wire [3:0] axiOut_3_wstrb, + output wire axiOut_3_wlast, + input wire axiOut_3_bvalid, + output wire axiOut_3_bready, + input wire [4:0] axiOut_3_bid, + input wire [1:0] axiOut_3_bresp, + output wire axiOut_3_arvalid, + input wire axiOut_3_arready, + output wire [31:0] axiOut_3_araddr, + output wire [4:0] axiOut_3_arid, + output wire [7:0] axiOut_3_arlen, + output wire [2:0] axiOut_3_arsize, + output wire [1:0] axiOut_3_arburst, + output wire [0:0] axiOut_3_arlock, + output wire [3:0] axiOut_3_arcache, + output wire [2:0] axiOut_3_arprot, + input wire axiOut_3_rvalid, + output wire axiOut_3_rready, + input wire [31:0] axiOut_3_rdata, + input wire [4:0] axiOut_3_rid, + input wire [1:0] axiOut_3_rresp, + input wire axiOut_3_rlast, + output wire axiOut_4_awvalid, + input wire axiOut_4_awready, + output wire [31:0] axiOut_4_awaddr, + output wire [4:0] axiOut_4_awid, + output wire [7:0] axiOut_4_awlen, + output wire [2:0] axiOut_4_awsize, + output wire [1:0] axiOut_4_awburst, + output wire [0:0] axiOut_4_awlock, + output wire [3:0] axiOut_4_awcache, + output wire [2:0] axiOut_4_awprot, + output wire axiOut_4_wvalid, + input wire axiOut_4_wready, + output wire [31:0] axiOut_4_wdata, + output wire [3:0] axiOut_4_wstrb, + output wire axiOut_4_wlast, + input wire axiOut_4_bvalid, + output wire axiOut_4_bready, + input wire [4:0] axiOut_4_bid, + input wire [1:0] axiOut_4_bresp, + output wire axiOut_4_arvalid, + input wire axiOut_4_arready, + output wire [31:0] axiOut_4_araddr, + output wire [4:0] axiOut_4_arid, + output wire [7:0] axiOut_4_arlen, + output wire [2:0] axiOut_4_arsize, + output wire [1:0] axiOut_4_arburst, + output wire [0:0] axiOut_4_arlock, + output wire [3:0] axiOut_4_arcache, + output wire [2:0] axiOut_4_arprot, + input wire axiOut_4_rvalid, + output wire axiOut_4_rready, + input wire [31:0] axiOut_4_rdata, + input wire [4:0] axiOut_4_rid, + input wire [1:0] axiOut_4_rresp, + input wire axiOut_4_rlast, + output wire axiOut_5_awvalid, + input wire axiOut_5_awready, + output wire [31:0] axiOut_5_awaddr, + output wire [4:0] axiOut_5_awid, + output wire [7:0] axiOut_5_awlen, + output wire [2:0] axiOut_5_awsize, + output wire [1:0] axiOut_5_awburst, + output wire [0:0] axiOut_5_awlock, + output wire [3:0] axiOut_5_awcache, + output wire [2:0] axiOut_5_awprot, + output wire axiOut_5_wvalid, + input wire axiOut_5_wready, + output wire [31:0] axiOut_5_wdata, + output wire [3:0] axiOut_5_wstrb, + output wire axiOut_5_wlast, + input wire axiOut_5_bvalid, + output wire axiOut_5_bready, + input wire [4:0] axiOut_5_bid, + input wire [1:0] axiOut_5_bresp, + output wire axiOut_5_arvalid, + input wire axiOut_5_arready, + output wire [31:0] axiOut_5_araddr, + output wire [4:0] axiOut_5_arid, + output wire [7:0] axiOut_5_arlen, + output wire [2:0] axiOut_5_arsize, + output wire [1:0] axiOut_5_arburst, + output wire [0:0] axiOut_5_arlock, + output wire [3:0] axiOut_5_arcache, + output wire [2:0] axiOut_5_arprot, + input wire axiOut_5_rvalid, + output wire axiOut_5_rready, + input wire [31:0] axiOut_5_rdata, + input wire [4:0] axiOut_5_rid, + input wire [1:0] axiOut_5_rresp, + input wire axiOut_5_rlast, + output wire axiOut_6_awvalid, + input wire axiOut_6_awready, + output wire [31:0] axiOut_6_awaddr, + output wire [4:0] axiOut_6_awid, + output wire [7:0] axiOut_6_awlen, + output wire [2:0] axiOut_6_awsize, + output wire [1:0] axiOut_6_awburst, + output wire [0:0] axiOut_6_awlock, + output wire [3:0] axiOut_6_awcache, + output wire [2:0] axiOut_6_awprot, + output wire axiOut_6_wvalid, + input wire axiOut_6_wready, + output wire [31:0] axiOut_6_wdata, + output wire [3:0] axiOut_6_wstrb, + output wire axiOut_6_wlast, + input wire axiOut_6_bvalid, + output wire axiOut_6_bready, + input wire [4:0] axiOut_6_bid, + input wire [1:0] axiOut_6_bresp, + output wire axiOut_6_arvalid, + input wire axiOut_6_arready, + output wire [31:0] axiOut_6_araddr, + output wire [4:0] axiOut_6_arid, + output wire [7:0] axiOut_6_arlen, + output wire [2:0] axiOut_6_arsize, + output wire [1:0] axiOut_6_arburst, + output wire [0:0] axiOut_6_arlock, + output wire [3:0] axiOut_6_arcache, + output wire [2:0] axiOut_6_arprot, + input wire axiOut_6_rvalid, + output wire axiOut_6_rready, + input wire [31:0] axiOut_6_rdata, + input wire [4:0] axiOut_6_rid, + input wire [1:0] axiOut_6_rresp, + input wire axiOut_6_rlast, + output wire axiOut_7_awvalid, + input wire axiOut_7_awready, + output wire [31:0] axiOut_7_awaddr, + output wire [4:0] axiOut_7_awid, + output wire [7:0] axiOut_7_awlen, + output wire [2:0] axiOut_7_awsize, + output wire [1:0] axiOut_7_awburst, + output wire [0:0] axiOut_7_awlock, + output wire [3:0] axiOut_7_awcache, + output wire [2:0] axiOut_7_awprot, + output wire axiOut_7_wvalid, + input wire axiOut_7_wready, + output wire [31:0] axiOut_7_wdata, + output wire [3:0] axiOut_7_wstrb, + output wire axiOut_7_wlast, + input wire axiOut_7_bvalid, + output wire axiOut_7_bready, + input wire [4:0] axiOut_7_bid, + input wire [1:0] axiOut_7_bresp, + output wire axiOut_7_arvalid, + input wire axiOut_7_arready, + output wire [31:0] axiOut_7_araddr, + output wire [4:0] axiOut_7_arid, + output wire [7:0] axiOut_7_arlen, + output wire [2:0] axiOut_7_arsize, + output wire [1:0] axiOut_7_arburst, + output wire [0:0] axiOut_7_arlock, + output wire [3:0] axiOut_7_arcache, + output wire [2:0] axiOut_7_arprot, + input wire axiOut_7_rvalid, + output wire axiOut_7_rready, + input wire [31:0] axiOut_7_rdata, + input wire [4:0] axiOut_7_rid, + input wire [1:0] axiOut_7_rresp, + input wire axiOut_7_rlast, + input wire clk, + input wire resetn +); + + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_2_r_payload_id; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_3_r_payload_id; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_4_r_payload_id; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_5_r_payload_id; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_2_b_payload_id; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_3_b_payload_id; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_4_b_payload_id; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_5_b_payload_id; + wire axiIn_0_readOnly_decoder_io_input_ar_ready; + wire axiIn_0_readOnly_decoder_io_input_r_valid; + wire [31:0] axiIn_0_readOnly_decoder_io_input_r_payload_data; + wire [3:0] axiIn_0_readOnly_decoder_io_input_r_payload_id; + wire [1:0] axiIn_0_readOnly_decoder_io_input_r_payload_resp; + wire axiIn_0_readOnly_decoder_io_input_r_payload_last; + wire axiIn_0_readOnly_decoder_io_outputs_0_ar_valid; + wire [31:0] axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_addr; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_id; + wire [7:0] axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_len; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_size; + wire [1:0] axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_burst; + wire [0:0] axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_lock; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_cache; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_prot; + wire axiIn_0_readOnly_decoder_io_outputs_0_r_ready; + wire axiIn_0_readOnly_decoder_io_outputs_1_ar_valid; + wire [31:0] axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_addr; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_id; + wire [7:0] axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_len; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_size; + wire [1:0] axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_burst; + wire [0:0] axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_lock; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_cache; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_prot; + wire axiIn_0_readOnly_decoder_io_outputs_1_r_ready; + wire axiIn_0_readOnly_decoder_io_outputs_2_ar_valid; + wire [31:0] axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_addr; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_id; + wire [7:0] axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_len; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_size; + wire [1:0] axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_burst; + wire [0:0] axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_lock; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_cache; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_prot; + wire axiIn_0_readOnly_decoder_io_outputs_2_r_ready; + wire axiIn_0_readOnly_decoder_io_outputs_3_ar_valid; + wire [31:0] axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_addr; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_id; + wire [7:0] axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_len; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_size; + wire [1:0] axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_burst; + wire [0:0] axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_lock; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_cache; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_prot; + wire axiIn_0_readOnly_decoder_io_outputs_3_r_ready; + wire axiIn_0_readOnly_decoder_io_outputs_4_ar_valid; + wire [31:0] axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_addr; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_id; + wire [7:0] axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_len; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_size; + wire [1:0] axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_burst; + wire [0:0] axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_lock; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_cache; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_prot; + wire axiIn_0_readOnly_decoder_io_outputs_4_r_ready; + wire axiIn_0_readOnly_decoder_io_outputs_5_ar_valid; + wire [31:0] axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_addr; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_id; + wire [7:0] axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_len; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_size; + wire [1:0] axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_burst; + wire [0:0] axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_lock; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_cache; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_prot; + wire axiIn_0_readOnly_decoder_io_outputs_5_r_ready; + wire axiIn_0_readOnly_decoder_io_outputs_6_ar_valid; + wire [31:0] axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_addr; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_id; + wire [7:0] axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_len; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_size; + wire [1:0] axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_burst; + wire [0:0] axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_lock; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_cache; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_prot; + wire axiIn_0_readOnly_decoder_io_outputs_6_r_ready; + wire axiIn_0_readOnly_decoder_io_outputs_7_ar_valid; + wire [31:0] axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_addr; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_id; + wire [7:0] axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_len; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_size; + wire [1:0] axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_burst; + wire [0:0] axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_lock; + wire [3:0] axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_cache; + wire [2:0] axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_prot; + wire axiIn_0_readOnly_decoder_io_outputs_7_r_ready; + wire axiIn_0_writeOnly_decoder_io_input_aw_ready; + wire axiIn_0_writeOnly_decoder_io_input_w_ready; + wire axiIn_0_writeOnly_decoder_io_input_b_valid; + wire [3:0] axiIn_0_writeOnly_decoder_io_input_b_payload_id; + wire [1:0] axiIn_0_writeOnly_decoder_io_input_b_payload_resp; + wire axiIn_0_writeOnly_decoder_io_outputs_0_aw_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_addr; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_id; + wire [7:0] axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_len; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_size; + wire [1:0] axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_burst; + wire [0:0] axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_lock; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_cache; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_prot; + wire axiIn_0_writeOnly_decoder_io_outputs_0_w_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_0_w_payload_data; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_0_w_payload_strb; + wire axiIn_0_writeOnly_decoder_io_outputs_0_w_payload_last; + wire axiIn_0_writeOnly_decoder_io_outputs_0_b_ready; + wire axiIn_0_writeOnly_decoder_io_outputs_1_aw_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_addr; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_id; + wire [7:0] axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_len; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_size; + wire [1:0] axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_burst; + wire [0:0] axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_lock; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_cache; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_prot; + wire axiIn_0_writeOnly_decoder_io_outputs_1_w_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_1_w_payload_data; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_1_w_payload_strb; + wire axiIn_0_writeOnly_decoder_io_outputs_1_w_payload_last; + wire axiIn_0_writeOnly_decoder_io_outputs_1_b_ready; + wire axiIn_0_writeOnly_decoder_io_outputs_2_aw_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_addr; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_id; + wire [7:0] axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_len; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_size; + wire [1:0] axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_burst; + wire [0:0] axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_lock; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_cache; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_prot; + wire axiIn_0_writeOnly_decoder_io_outputs_2_w_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_2_w_payload_data; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_2_w_payload_strb; + wire axiIn_0_writeOnly_decoder_io_outputs_2_w_payload_last; + wire axiIn_0_writeOnly_decoder_io_outputs_2_b_ready; + wire axiIn_0_writeOnly_decoder_io_outputs_3_aw_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_addr; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_id; + wire [7:0] axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_len; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_size; + wire [1:0] axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_burst; + wire [0:0] axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_lock; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_cache; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_prot; + wire axiIn_0_writeOnly_decoder_io_outputs_3_w_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_3_w_payload_data; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_3_w_payload_strb; + wire axiIn_0_writeOnly_decoder_io_outputs_3_w_payload_last; + wire axiIn_0_writeOnly_decoder_io_outputs_3_b_ready; + wire axiIn_0_writeOnly_decoder_io_outputs_4_aw_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_addr; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_id; + wire [7:0] axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_len; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_size; + wire [1:0] axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_burst; + wire [0:0] axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_lock; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_cache; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_prot; + wire axiIn_0_writeOnly_decoder_io_outputs_4_w_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_4_w_payload_data; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_4_w_payload_strb; + wire axiIn_0_writeOnly_decoder_io_outputs_4_w_payload_last; + wire axiIn_0_writeOnly_decoder_io_outputs_4_b_ready; + wire axiIn_0_writeOnly_decoder_io_outputs_5_aw_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_addr; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_id; + wire [7:0] axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_len; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_size; + wire [1:0] axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_burst; + wire [0:0] axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_lock; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_cache; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_prot; + wire axiIn_0_writeOnly_decoder_io_outputs_5_w_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_5_w_payload_data; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_5_w_payload_strb; + wire axiIn_0_writeOnly_decoder_io_outputs_5_w_payload_last; + wire axiIn_0_writeOnly_decoder_io_outputs_5_b_ready; + wire axiIn_0_writeOnly_decoder_io_outputs_6_aw_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_addr; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_id; + wire [7:0] axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_len; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_size; + wire [1:0] axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_burst; + wire [0:0] axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_lock; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_cache; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_prot; + wire axiIn_0_writeOnly_decoder_io_outputs_6_w_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_6_w_payload_data; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_6_w_payload_strb; + wire axiIn_0_writeOnly_decoder_io_outputs_6_w_payload_last; + wire axiIn_0_writeOnly_decoder_io_outputs_6_b_ready; + wire axiIn_0_writeOnly_decoder_io_outputs_7_aw_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_addr; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_id; + wire [7:0] axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_len; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_size; + wire [1:0] axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_burst; + wire [0:0] axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_lock; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_cache; + wire [2:0] axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_prot; + wire axiIn_0_writeOnly_decoder_io_outputs_7_w_valid; + wire [31:0] axiIn_0_writeOnly_decoder_io_outputs_7_w_payload_data; + wire [3:0] axiIn_0_writeOnly_decoder_io_outputs_7_w_payload_strb; + wire axiIn_0_writeOnly_decoder_io_outputs_7_w_payload_last; + wire axiIn_0_writeOnly_decoder_io_outputs_7_b_ready; + wire axiIn_1_readOnly_decoder_io_input_ar_ready; + wire axiIn_1_readOnly_decoder_io_input_r_valid; + wire [31:0] axiIn_1_readOnly_decoder_io_input_r_payload_data; + wire [3:0] axiIn_1_readOnly_decoder_io_input_r_payload_id; + wire [1:0] axiIn_1_readOnly_decoder_io_input_r_payload_resp; + wire axiIn_1_readOnly_decoder_io_input_r_payload_last; + wire axiIn_1_readOnly_decoder_io_outputs_0_ar_valid; + wire [31:0] axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_addr; + wire [3:0] axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_id; + wire [7:0] axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_len; + wire [2:0] axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_size; + wire [1:0] axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_burst; + wire [0:0] axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_lock; + wire [3:0] axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_cache; + wire [2:0] axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_prot; + wire axiIn_1_readOnly_decoder_io_outputs_0_r_ready; + wire axiIn_1_readOnly_decoder_io_outputs_1_ar_valid; + wire [31:0] axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_addr; + wire [3:0] axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_id; + wire [7:0] axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_len; + wire [2:0] axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_size; + wire [1:0] axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_burst; + wire [0:0] axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_lock; + wire [3:0] axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_cache; + wire [2:0] axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_prot; + wire axiIn_1_readOnly_decoder_io_outputs_1_r_ready; + wire axiIn_1_readOnly_decoder_io_outputs_2_ar_valid; + wire [31:0] axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_addr; + wire [3:0] axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_id; + wire [7:0] axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_len; + wire [2:0] axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_size; + wire [1:0] axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_burst; + wire [0:0] axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_lock; + wire [3:0] axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_cache; + wire [2:0] axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_prot; + wire axiIn_1_readOnly_decoder_io_outputs_2_r_ready; + wire axiIn_1_readOnly_decoder_io_outputs_3_ar_valid; + wire [31:0] axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_addr; + wire [3:0] axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_id; + wire [7:0] axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_len; + wire [2:0] axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_size; + wire [1:0] axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_burst; + wire [0:0] axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_lock; + wire [3:0] axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_cache; + wire [2:0] axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_prot; + wire axiIn_1_readOnly_decoder_io_outputs_3_r_ready; + wire axiIn_1_writeOnly_decoder_io_input_aw_ready; + wire axiIn_1_writeOnly_decoder_io_input_w_ready; + wire axiIn_1_writeOnly_decoder_io_input_b_valid; + wire [3:0] axiIn_1_writeOnly_decoder_io_input_b_payload_id; + wire [1:0] axiIn_1_writeOnly_decoder_io_input_b_payload_resp; + wire axiIn_1_writeOnly_decoder_io_outputs_0_aw_valid; + wire [31:0] axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_addr; + wire [3:0] axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_id; + wire [7:0] axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_len; + wire [2:0] axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_size; + wire [1:0] axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_burst; + wire [0:0] axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_lock; + wire [3:0] axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_cache; + wire [2:0] axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_prot; + wire axiIn_1_writeOnly_decoder_io_outputs_0_w_valid; + wire [31:0] axiIn_1_writeOnly_decoder_io_outputs_0_w_payload_data; + wire [3:0] axiIn_1_writeOnly_decoder_io_outputs_0_w_payload_strb; + wire axiIn_1_writeOnly_decoder_io_outputs_0_w_payload_last; + wire axiIn_1_writeOnly_decoder_io_outputs_0_b_ready; + wire axiIn_1_writeOnly_decoder_io_outputs_1_aw_valid; + wire [31:0] axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_addr; + wire [3:0] axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_id; + wire [7:0] axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_len; + wire [2:0] axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_size; + wire [1:0] axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_burst; + wire [0:0] axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_lock; + wire [3:0] axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_cache; + wire [2:0] axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_prot; + wire axiIn_1_writeOnly_decoder_io_outputs_1_w_valid; + wire [31:0] axiIn_1_writeOnly_decoder_io_outputs_1_w_payload_data; + wire [3:0] axiIn_1_writeOnly_decoder_io_outputs_1_w_payload_strb; + wire axiIn_1_writeOnly_decoder_io_outputs_1_w_payload_last; + wire axiIn_1_writeOnly_decoder_io_outputs_1_b_ready; + wire axiIn_1_writeOnly_decoder_io_outputs_2_aw_valid; + wire [31:0] axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_addr; + wire [3:0] axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_id; + wire [7:0] axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_len; + wire [2:0] axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_size; + wire [1:0] axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_burst; + wire [0:0] axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_lock; + wire [3:0] axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_cache; + wire [2:0] axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_prot; + wire axiIn_1_writeOnly_decoder_io_outputs_2_w_valid; + wire [31:0] axiIn_1_writeOnly_decoder_io_outputs_2_w_payload_data; + wire [3:0] axiIn_1_writeOnly_decoder_io_outputs_2_w_payload_strb; + wire axiIn_1_writeOnly_decoder_io_outputs_2_w_payload_last; + wire axiIn_1_writeOnly_decoder_io_outputs_2_b_ready; + wire axiIn_1_writeOnly_decoder_io_outputs_3_aw_valid; + wire [31:0] axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_addr; + wire [3:0] axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_id; + wire [7:0] axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_len; + wire [2:0] axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_size; + wire [1:0] axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_burst; + wire [0:0] axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_lock; + wire [3:0] axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_cache; + wire [2:0] axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_prot; + wire axiIn_1_writeOnly_decoder_io_outputs_3_w_valid; + wire [31:0] axiIn_1_writeOnly_decoder_io_outputs_3_w_payload_data; + wire [3:0] axiIn_1_writeOnly_decoder_io_outputs_3_w_payload_strb; + wire axiIn_1_writeOnly_decoder_io_outputs_3_w_payload_last; + wire axiIn_1_writeOnly_decoder_io_outputs_3_b_ready; + wire axi4ReadOnlyArbiter_4_io_inputs_0_ar_ready; + wire axi4ReadOnlyArbiter_4_io_inputs_0_r_valid; + wire [31:0] axi4ReadOnlyArbiter_4_io_inputs_0_r_payload_data; + wire [3:0] axi4ReadOnlyArbiter_4_io_inputs_0_r_payload_id; + wire [1:0] axi4ReadOnlyArbiter_4_io_inputs_0_r_payload_resp; + wire axi4ReadOnlyArbiter_4_io_inputs_0_r_payload_last; + wire axi4ReadOnlyArbiter_4_io_inputs_1_ar_ready; + wire axi4ReadOnlyArbiter_4_io_inputs_1_r_valid; + wire [31:0] axi4ReadOnlyArbiter_4_io_inputs_1_r_payload_data; + wire [3:0] axi4ReadOnlyArbiter_4_io_inputs_1_r_payload_id; + wire [1:0] axi4ReadOnlyArbiter_4_io_inputs_1_r_payload_resp; + wire axi4ReadOnlyArbiter_4_io_inputs_1_r_payload_last; + wire axi4ReadOnlyArbiter_4_io_output_ar_valid; + wire [31:0] axi4ReadOnlyArbiter_4_io_output_ar_payload_addr; + wire [4:0] axi4ReadOnlyArbiter_4_io_output_ar_payload_id; + wire [7:0] axi4ReadOnlyArbiter_4_io_output_ar_payload_len; + wire [2:0] axi4ReadOnlyArbiter_4_io_output_ar_payload_size; + wire [1:0] axi4ReadOnlyArbiter_4_io_output_ar_payload_burst; + wire [0:0] axi4ReadOnlyArbiter_4_io_output_ar_payload_lock; + wire [3:0] axi4ReadOnlyArbiter_4_io_output_ar_payload_cache; + wire [2:0] axi4ReadOnlyArbiter_4_io_output_ar_payload_prot; + wire axi4ReadOnlyArbiter_4_io_output_r_ready; + wire axi4WriteOnlyArbiter_4_io_inputs_0_aw_ready; + wire axi4WriteOnlyArbiter_4_io_inputs_0_w_ready; + wire axi4WriteOnlyArbiter_4_io_inputs_0_b_valid; + wire [3:0] axi4WriteOnlyArbiter_4_io_inputs_0_b_payload_id; + wire [1:0] axi4WriteOnlyArbiter_4_io_inputs_0_b_payload_resp; + wire axi4WriteOnlyArbiter_4_io_inputs_1_aw_ready; + wire axi4WriteOnlyArbiter_4_io_inputs_1_w_ready; + wire axi4WriteOnlyArbiter_4_io_inputs_1_b_valid; + wire [3:0] axi4WriteOnlyArbiter_4_io_inputs_1_b_payload_id; + wire [1:0] axi4WriteOnlyArbiter_4_io_inputs_1_b_payload_resp; + wire axi4WriteOnlyArbiter_4_io_output_aw_valid; + wire [31:0] axi4WriteOnlyArbiter_4_io_output_aw_payload_addr; + wire [4:0] axi4WriteOnlyArbiter_4_io_output_aw_payload_id; + wire [7:0] axi4WriteOnlyArbiter_4_io_output_aw_payload_len; + wire [2:0] axi4WriteOnlyArbiter_4_io_output_aw_payload_size; + wire [1:0] axi4WriteOnlyArbiter_4_io_output_aw_payload_burst; + wire [0:0] axi4WriteOnlyArbiter_4_io_output_aw_payload_lock; + wire [3:0] axi4WriteOnlyArbiter_4_io_output_aw_payload_cache; + wire [2:0] axi4WriteOnlyArbiter_4_io_output_aw_payload_prot; + wire axi4WriteOnlyArbiter_4_io_output_w_valid; + wire [31:0] axi4WriteOnlyArbiter_4_io_output_w_payload_data; + wire [3:0] axi4WriteOnlyArbiter_4_io_output_w_payload_strb; + wire axi4WriteOnlyArbiter_4_io_output_w_payload_last; + wire axi4WriteOnlyArbiter_4_io_output_b_ready; + wire axi4ReadOnlyArbiter_5_io_inputs_0_ar_ready; + wire axi4ReadOnlyArbiter_5_io_inputs_0_r_valid; + wire [31:0] axi4ReadOnlyArbiter_5_io_inputs_0_r_payload_data; + wire [3:0] axi4ReadOnlyArbiter_5_io_inputs_0_r_payload_id; + wire [1:0] axi4ReadOnlyArbiter_5_io_inputs_0_r_payload_resp; + wire axi4ReadOnlyArbiter_5_io_inputs_0_r_payload_last; + wire axi4ReadOnlyArbiter_5_io_inputs_1_ar_ready; + wire axi4ReadOnlyArbiter_5_io_inputs_1_r_valid; + wire [31:0] axi4ReadOnlyArbiter_5_io_inputs_1_r_payload_data; + wire [3:0] axi4ReadOnlyArbiter_5_io_inputs_1_r_payload_id; + wire [1:0] axi4ReadOnlyArbiter_5_io_inputs_1_r_payload_resp; + wire axi4ReadOnlyArbiter_5_io_inputs_1_r_payload_last; + wire axi4ReadOnlyArbiter_5_io_output_ar_valid; + wire [31:0] axi4ReadOnlyArbiter_5_io_output_ar_payload_addr; + wire [4:0] axi4ReadOnlyArbiter_5_io_output_ar_payload_id; + wire [7:0] axi4ReadOnlyArbiter_5_io_output_ar_payload_len; + wire [2:0] axi4ReadOnlyArbiter_5_io_output_ar_payload_size; + wire [1:0] axi4ReadOnlyArbiter_5_io_output_ar_payload_burst; + wire [0:0] axi4ReadOnlyArbiter_5_io_output_ar_payload_lock; + wire [3:0] axi4ReadOnlyArbiter_5_io_output_ar_payload_cache; + wire [2:0] axi4ReadOnlyArbiter_5_io_output_ar_payload_prot; + wire axi4ReadOnlyArbiter_5_io_output_r_ready; + wire axi4WriteOnlyArbiter_5_io_inputs_0_aw_ready; + wire axi4WriteOnlyArbiter_5_io_inputs_0_w_ready; + wire axi4WriteOnlyArbiter_5_io_inputs_0_b_valid; + wire [3:0] axi4WriteOnlyArbiter_5_io_inputs_0_b_payload_id; + wire [1:0] axi4WriteOnlyArbiter_5_io_inputs_0_b_payload_resp; + wire axi4WriteOnlyArbiter_5_io_inputs_1_aw_ready; + wire axi4WriteOnlyArbiter_5_io_inputs_1_w_ready; + wire axi4WriteOnlyArbiter_5_io_inputs_1_b_valid; + wire [3:0] axi4WriteOnlyArbiter_5_io_inputs_1_b_payload_id; + wire [1:0] axi4WriteOnlyArbiter_5_io_inputs_1_b_payload_resp; + wire axi4WriteOnlyArbiter_5_io_output_aw_valid; + wire [31:0] axi4WriteOnlyArbiter_5_io_output_aw_payload_addr; + wire [4:0] axi4WriteOnlyArbiter_5_io_output_aw_payload_id; + wire [7:0] axi4WriteOnlyArbiter_5_io_output_aw_payload_len; + wire [2:0] axi4WriteOnlyArbiter_5_io_output_aw_payload_size; + wire [1:0] axi4WriteOnlyArbiter_5_io_output_aw_payload_burst; + wire [0:0] axi4WriteOnlyArbiter_5_io_output_aw_payload_lock; + wire [3:0] axi4WriteOnlyArbiter_5_io_output_aw_payload_cache; + wire [2:0] axi4WriteOnlyArbiter_5_io_output_aw_payload_prot; + wire axi4WriteOnlyArbiter_5_io_output_w_valid; + wire [31:0] axi4WriteOnlyArbiter_5_io_output_w_payload_data; + wire [3:0] axi4WriteOnlyArbiter_5_io_output_w_payload_strb; + wire axi4WriteOnlyArbiter_5_io_output_w_payload_last; + wire axi4WriteOnlyArbiter_5_io_output_b_ready; + wire axi4ReadOnlyArbiter_6_io_inputs_0_ar_ready; + wire axi4ReadOnlyArbiter_6_io_inputs_0_r_valid; + wire [31:0] axi4ReadOnlyArbiter_6_io_inputs_0_r_payload_data; + wire [3:0] axi4ReadOnlyArbiter_6_io_inputs_0_r_payload_id; + wire [1:0] axi4ReadOnlyArbiter_6_io_inputs_0_r_payload_resp; + wire axi4ReadOnlyArbiter_6_io_inputs_0_r_payload_last; + wire axi4ReadOnlyArbiter_6_io_inputs_1_ar_ready; + wire axi4ReadOnlyArbiter_6_io_inputs_1_r_valid; + wire [31:0] axi4ReadOnlyArbiter_6_io_inputs_1_r_payload_data; + wire [3:0] axi4ReadOnlyArbiter_6_io_inputs_1_r_payload_id; + wire [1:0] axi4ReadOnlyArbiter_6_io_inputs_1_r_payload_resp; + wire axi4ReadOnlyArbiter_6_io_inputs_1_r_payload_last; + wire axi4ReadOnlyArbiter_6_io_output_ar_valid; + wire [31:0] axi4ReadOnlyArbiter_6_io_output_ar_payload_addr; + wire [4:0] axi4ReadOnlyArbiter_6_io_output_ar_payload_id; + wire [7:0] axi4ReadOnlyArbiter_6_io_output_ar_payload_len; + wire [2:0] axi4ReadOnlyArbiter_6_io_output_ar_payload_size; + wire [1:0] axi4ReadOnlyArbiter_6_io_output_ar_payload_burst; + wire [0:0] axi4ReadOnlyArbiter_6_io_output_ar_payload_lock; + wire [3:0] axi4ReadOnlyArbiter_6_io_output_ar_payload_cache; + wire [2:0] axi4ReadOnlyArbiter_6_io_output_ar_payload_prot; + wire axi4ReadOnlyArbiter_6_io_output_r_ready; + wire axi4WriteOnlyArbiter_6_io_inputs_0_aw_ready; + wire axi4WriteOnlyArbiter_6_io_inputs_0_w_ready; + wire axi4WriteOnlyArbiter_6_io_inputs_0_b_valid; + wire [3:0] axi4WriteOnlyArbiter_6_io_inputs_0_b_payload_id; + wire [1:0] axi4WriteOnlyArbiter_6_io_inputs_0_b_payload_resp; + wire axi4WriteOnlyArbiter_6_io_inputs_1_aw_ready; + wire axi4WriteOnlyArbiter_6_io_inputs_1_w_ready; + wire axi4WriteOnlyArbiter_6_io_inputs_1_b_valid; + wire [3:0] axi4WriteOnlyArbiter_6_io_inputs_1_b_payload_id; + wire [1:0] axi4WriteOnlyArbiter_6_io_inputs_1_b_payload_resp; + wire axi4WriteOnlyArbiter_6_io_output_aw_valid; + wire [31:0] axi4WriteOnlyArbiter_6_io_output_aw_payload_addr; + wire [4:0] axi4WriteOnlyArbiter_6_io_output_aw_payload_id; + wire [7:0] axi4WriteOnlyArbiter_6_io_output_aw_payload_len; + wire [2:0] axi4WriteOnlyArbiter_6_io_output_aw_payload_size; + wire [1:0] axi4WriteOnlyArbiter_6_io_output_aw_payload_burst; + wire [0:0] axi4WriteOnlyArbiter_6_io_output_aw_payload_lock; + wire [3:0] axi4WriteOnlyArbiter_6_io_output_aw_payload_cache; + wire [2:0] axi4WriteOnlyArbiter_6_io_output_aw_payload_prot; + wire axi4WriteOnlyArbiter_6_io_output_w_valid; + wire [31:0] axi4WriteOnlyArbiter_6_io_output_w_payload_data; + wire [3:0] axi4WriteOnlyArbiter_6_io_output_w_payload_strb; + wire axi4WriteOnlyArbiter_6_io_output_w_payload_last; + wire axi4WriteOnlyArbiter_6_io_output_b_ready; + wire axi4ReadOnlyArbiter_7_io_inputs_0_ar_ready; + wire axi4ReadOnlyArbiter_7_io_inputs_0_r_valid; + wire [31:0] axi4ReadOnlyArbiter_7_io_inputs_0_r_payload_data; + wire [3:0] axi4ReadOnlyArbiter_7_io_inputs_0_r_payload_id; + wire [1:0] axi4ReadOnlyArbiter_7_io_inputs_0_r_payload_resp; + wire axi4ReadOnlyArbiter_7_io_inputs_0_r_payload_last; + wire axi4ReadOnlyArbiter_7_io_inputs_1_ar_ready; + wire axi4ReadOnlyArbiter_7_io_inputs_1_r_valid; + wire [31:0] axi4ReadOnlyArbiter_7_io_inputs_1_r_payload_data; + wire [3:0] axi4ReadOnlyArbiter_7_io_inputs_1_r_payload_id; + wire [1:0] axi4ReadOnlyArbiter_7_io_inputs_1_r_payload_resp; + wire axi4ReadOnlyArbiter_7_io_inputs_1_r_payload_last; + wire axi4ReadOnlyArbiter_7_io_output_ar_valid; + wire [31:0] axi4ReadOnlyArbiter_7_io_output_ar_payload_addr; + wire [4:0] axi4ReadOnlyArbiter_7_io_output_ar_payload_id; + wire [7:0] axi4ReadOnlyArbiter_7_io_output_ar_payload_len; + wire [2:0] axi4ReadOnlyArbiter_7_io_output_ar_payload_size; + wire [1:0] axi4ReadOnlyArbiter_7_io_output_ar_payload_burst; + wire [0:0] axi4ReadOnlyArbiter_7_io_output_ar_payload_lock; + wire [3:0] axi4ReadOnlyArbiter_7_io_output_ar_payload_cache; + wire [2:0] axi4ReadOnlyArbiter_7_io_output_ar_payload_prot; + wire axi4ReadOnlyArbiter_7_io_output_r_ready; + wire axi4WriteOnlyArbiter_7_io_inputs_0_aw_ready; + wire axi4WriteOnlyArbiter_7_io_inputs_0_w_ready; + wire axi4WriteOnlyArbiter_7_io_inputs_0_b_valid; + wire [3:0] axi4WriteOnlyArbiter_7_io_inputs_0_b_payload_id; + wire [1:0] axi4WriteOnlyArbiter_7_io_inputs_0_b_payload_resp; + wire axi4WriteOnlyArbiter_7_io_inputs_1_aw_ready; + wire axi4WriteOnlyArbiter_7_io_inputs_1_w_ready; + wire axi4WriteOnlyArbiter_7_io_inputs_1_b_valid; + wire [3:0] axi4WriteOnlyArbiter_7_io_inputs_1_b_payload_id; + wire [1:0] axi4WriteOnlyArbiter_7_io_inputs_1_b_payload_resp; + wire axi4WriteOnlyArbiter_7_io_output_aw_valid; + wire [31:0] axi4WriteOnlyArbiter_7_io_output_aw_payload_addr; + wire [4:0] axi4WriteOnlyArbiter_7_io_output_aw_payload_id; + wire [7:0] axi4WriteOnlyArbiter_7_io_output_aw_payload_len; + wire [2:0] axi4WriteOnlyArbiter_7_io_output_aw_payload_size; + wire [1:0] axi4WriteOnlyArbiter_7_io_output_aw_payload_burst; + wire [0:0] axi4WriteOnlyArbiter_7_io_output_aw_payload_lock; + wire [3:0] axi4WriteOnlyArbiter_7_io_output_aw_payload_cache; + wire [2:0] axi4WriteOnlyArbiter_7_io_output_aw_payload_prot; + wire axi4WriteOnlyArbiter_7_io_output_w_valid; + wire [31:0] axi4WriteOnlyArbiter_7_io_output_w_payload_data; + wire [3:0] axi4WriteOnlyArbiter_7_io_output_w_payload_strb; + wire axi4WriteOnlyArbiter_7_io_output_w_payload_last; + wire axi4WriteOnlyArbiter_7_io_output_b_ready; + wire axiIn_0_readOnly_ar_valid; + wire axiIn_0_readOnly_ar_ready; + wire [31:0] axiIn_0_readOnly_ar_payload_addr; + wire [3:0] axiIn_0_readOnly_ar_payload_id; + wire [7:0] axiIn_0_readOnly_ar_payload_len; + wire [2:0] axiIn_0_readOnly_ar_payload_size; + wire [1:0] axiIn_0_readOnly_ar_payload_burst; + wire [0:0] axiIn_0_readOnly_ar_payload_lock; + wire [3:0] axiIn_0_readOnly_ar_payload_cache; + wire [2:0] axiIn_0_readOnly_ar_payload_prot; + wire axiIn_0_readOnly_r_valid; + wire axiIn_0_readOnly_r_ready; + wire [31:0] axiIn_0_readOnly_r_payload_data; + wire [3:0] axiIn_0_readOnly_r_payload_id; + wire [1:0] axiIn_0_readOnly_r_payload_resp; + wire axiIn_0_readOnly_r_payload_last; + wire axiIn_0_writeOnly_aw_valid; + wire axiIn_0_writeOnly_aw_ready; + wire [31:0] axiIn_0_writeOnly_aw_payload_addr; + wire [3:0] axiIn_0_writeOnly_aw_payload_id; + wire [7:0] axiIn_0_writeOnly_aw_payload_len; + wire [2:0] axiIn_0_writeOnly_aw_payload_size; + wire [1:0] axiIn_0_writeOnly_aw_payload_burst; + wire [0:0] axiIn_0_writeOnly_aw_payload_lock; + wire [3:0] axiIn_0_writeOnly_aw_payload_cache; + wire [2:0] axiIn_0_writeOnly_aw_payload_prot; + wire axiIn_0_writeOnly_w_valid; + wire axiIn_0_writeOnly_w_ready; + wire [31:0] axiIn_0_writeOnly_w_payload_data; + wire [3:0] axiIn_0_writeOnly_w_payload_strb; + wire axiIn_0_writeOnly_w_payload_last; + wire axiIn_0_writeOnly_b_valid; + wire axiIn_0_writeOnly_b_ready; + wire [3:0] axiIn_0_writeOnly_b_payload_id; + wire [1:0] axiIn_0_writeOnly_b_payload_resp; + wire axiIn_1_readOnly_ar_valid; + wire axiIn_1_readOnly_ar_ready; + wire [31:0] axiIn_1_readOnly_ar_payload_addr; + wire [3:0] axiIn_1_readOnly_ar_payload_id; + wire [7:0] axiIn_1_readOnly_ar_payload_len; + wire [2:0] axiIn_1_readOnly_ar_payload_size; + wire [1:0] axiIn_1_readOnly_ar_payload_burst; + wire [0:0] axiIn_1_readOnly_ar_payload_lock; + wire [3:0] axiIn_1_readOnly_ar_payload_cache; + wire [2:0] axiIn_1_readOnly_ar_payload_prot; + wire axiIn_1_readOnly_r_valid; + wire axiIn_1_readOnly_r_ready; + wire [31:0] axiIn_1_readOnly_r_payload_data; + wire [3:0] axiIn_1_readOnly_r_payload_id; + wire [1:0] axiIn_1_readOnly_r_payload_resp; + wire axiIn_1_readOnly_r_payload_last; + wire axiIn_1_writeOnly_aw_valid; + wire axiIn_1_writeOnly_aw_ready; + wire [31:0] axiIn_1_writeOnly_aw_payload_addr; + wire [3:0] axiIn_1_writeOnly_aw_payload_id; + wire [7:0] axiIn_1_writeOnly_aw_payload_len; + wire [2:0] axiIn_1_writeOnly_aw_payload_size; + wire [1:0] axiIn_1_writeOnly_aw_payload_burst; + wire [0:0] axiIn_1_writeOnly_aw_payload_lock; + wire [3:0] axiIn_1_writeOnly_aw_payload_cache; + wire [2:0] axiIn_1_writeOnly_aw_payload_prot; + wire axiIn_1_writeOnly_w_valid; + wire axiIn_1_writeOnly_w_ready; + wire [31:0] axiIn_1_writeOnly_w_payload_data; + wire [3:0] axiIn_1_writeOnly_w_payload_strb; + wire axiIn_1_writeOnly_w_payload_last; + wire axiIn_1_writeOnly_b_valid; + wire axiIn_1_writeOnly_b_ready; + wire [3:0] axiIn_1_writeOnly_b_payload_id; + wire [1:0] axiIn_1_writeOnly_b_payload_resp; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_valid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_ready; + wire [31:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_prot; + reg toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_rValid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_fire; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_valid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_ready; + wire [31:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_prot; + reg toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_rValid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_fire; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_valid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_ready; + wire [31:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_prot; + reg toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_rValid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_fire; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_valid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_ready; + wire [31:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_prot; + reg toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_rValid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_fire; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_valid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_ready; + wire [31:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_prot; + reg toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_rValid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_fire; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_valid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_ready; + wire [31:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_prot; + reg toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_rValid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_fire; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_valid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_ready; + wire [31:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_prot; + reg toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_rValid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_fire; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_valid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_ready; + wire [31:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_prot; + reg toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_rValid; + wire toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_fire; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_valid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_ready; + wire [31:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_prot; + reg toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_rValid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_fire; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_valid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_ready; + wire [31:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_prot; + reg toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_rValid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_fire; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_valid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_ready; + wire [31:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_prot; + reg toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_rValid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_fire; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_valid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_ready; + wire [31:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_prot; + reg toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_rValid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_fire; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_valid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_ready; + wire [31:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_prot; + reg toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_rValid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_fire; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_valid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_ready; + wire [31:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_prot; + reg toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_rValid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_fire; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_valid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_ready; + wire [31:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_prot; + reg toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_rValid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_fire; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_valid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_ready; + wire [31:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_id; + wire [7:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_len; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_size; + wire [1:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_prot; + reg toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_rValid; + wire toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_fire; + wire toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_valid; + wire toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_ready; + wire [31:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_id; + wire [7:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_len; + wire [2:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_size; + wire [1:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_prot; + reg toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_rValid; + wire toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_fire; + wire toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_valid; + wire toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_ready; + wire [31:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_id; + wire [7:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_len; + wire [2:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_size; + wire [1:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_prot; + reg toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_rValid; + wire toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_fire; + wire toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_valid; + wire toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_ready; + wire [31:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_id; + wire [7:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_len; + wire [2:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_size; + wire [1:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_prot; + reg toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_rValid; + wire toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_fire; + wire toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_valid; + wire toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_ready; + wire [31:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_id; + wire [7:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_len; + wire [2:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_size; + wire [1:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_prot; + reg toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_rValid; + wire toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_fire; + wire toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_valid; + wire toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_ready; + wire [31:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_id; + wire [7:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_len; + wire [2:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_size; + wire [1:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_prot; + reg toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_rValid; + wire toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_fire; + wire toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_valid; + wire toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_ready; + wire [31:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_id; + wire [7:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_len; + wire [2:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_size; + wire [1:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_prot; + reg toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_rValid; + wire toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_fire; + wire toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_valid; + wire toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_ready; + wire [31:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_id; + wire [7:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_len; + wire [2:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_size; + wire [1:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_prot; + reg toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_rValid; + wire toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_fire; + wire toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_valid; + wire toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_ready; + wire [31:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_addr; + wire [3:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_id; + wire [7:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_len; + wire [2:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_size; + wire [1:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_burst; + wire [0:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_lock; + wire [3:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_cache; + wire [2:0] toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_prot; + reg toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_rValid; + wire toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_fire; + + Axi4ReadOnlyDecoder axiIn_0_readOnly_decoder ( + .io_input_ar_valid (axiIn_0_readOnly_ar_valid ), //i + .io_input_ar_ready (axiIn_0_readOnly_decoder_io_input_ar_ready ), //o + .io_input_ar_payload_addr (axiIn_0_readOnly_ar_payload_addr[31:0] ), //i + .io_input_ar_payload_id (axiIn_0_readOnly_ar_payload_id[3:0] ), //i + .io_input_ar_payload_len (axiIn_0_readOnly_ar_payload_len[7:0] ), //i + .io_input_ar_payload_size (axiIn_0_readOnly_ar_payload_size[2:0] ), //i + .io_input_ar_payload_burst (axiIn_0_readOnly_ar_payload_burst[1:0] ), //i + .io_input_ar_payload_lock (axiIn_0_readOnly_ar_payload_lock ), //i + .io_input_ar_payload_cache (axiIn_0_readOnly_ar_payload_cache[3:0] ), //i + .io_input_ar_payload_prot (axiIn_0_readOnly_ar_payload_prot[2:0] ), //i + .io_input_r_valid (axiIn_0_readOnly_decoder_io_input_r_valid ), //o + .io_input_r_ready (axiIn_0_readOnly_r_ready ), //i + .io_input_r_payload_data (axiIn_0_readOnly_decoder_io_input_r_payload_data[31:0] ), //o + .io_input_r_payload_id (axiIn_0_readOnly_decoder_io_input_r_payload_id[3:0] ), //o + .io_input_r_payload_resp (axiIn_0_readOnly_decoder_io_input_r_payload_resp[1:0] ), //o + .io_input_r_payload_last (axiIn_0_readOnly_decoder_io_input_r_payload_last ), //o + .io_outputs_0_ar_valid (axiIn_0_readOnly_decoder_io_outputs_0_ar_valid ), //o + .io_outputs_0_ar_ready (toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_fire), //i + .io_outputs_0_ar_payload_addr (axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_addr[31:0] ), //o + .io_outputs_0_ar_payload_id (axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_id[3:0] ), //o + .io_outputs_0_ar_payload_len (axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_len[7:0] ), //o + .io_outputs_0_ar_payload_size (axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_size[2:0] ), //o + .io_outputs_0_ar_payload_burst (axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_burst[1:0] ), //o + .io_outputs_0_ar_payload_lock (axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_lock ), //o + .io_outputs_0_ar_payload_cache (axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_cache[3:0] ), //o + .io_outputs_0_ar_payload_prot (axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_prot[2:0] ), //o + .io_outputs_0_r_valid (axi4ReadOnlyArbiter_4_io_inputs_0_r_valid ), //i + .io_outputs_0_r_ready (axiIn_0_readOnly_decoder_io_outputs_0_r_ready ), //o + .io_outputs_0_r_payload_data (axi4ReadOnlyArbiter_4_io_inputs_0_r_payload_data[31:0] ), //i + .io_outputs_0_r_payload_id (axi4ReadOnlyArbiter_4_io_inputs_0_r_payload_id[3:0] ), //i + .io_outputs_0_r_payload_resp (axi4ReadOnlyArbiter_4_io_inputs_0_r_payload_resp[1:0] ), //i + .io_outputs_0_r_payload_last (axi4ReadOnlyArbiter_4_io_inputs_0_r_payload_last ), //i + .io_outputs_1_ar_valid (axiIn_0_readOnly_decoder_io_outputs_1_ar_valid ), //o + .io_outputs_1_ar_ready (toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_fire), //i + .io_outputs_1_ar_payload_addr (axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_addr[31:0] ), //o + .io_outputs_1_ar_payload_id (axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_id[3:0] ), //o + .io_outputs_1_ar_payload_len (axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_len[7:0] ), //o + .io_outputs_1_ar_payload_size (axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_size[2:0] ), //o + .io_outputs_1_ar_payload_burst (axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_burst[1:0] ), //o + .io_outputs_1_ar_payload_lock (axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_lock ), //o + .io_outputs_1_ar_payload_cache (axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_cache[3:0] ), //o + .io_outputs_1_ar_payload_prot (axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_prot[2:0] ), //o + .io_outputs_1_r_valid (axi4ReadOnlyArbiter_5_io_inputs_0_r_valid ), //i + .io_outputs_1_r_ready (axiIn_0_readOnly_decoder_io_outputs_1_r_ready ), //o + .io_outputs_1_r_payload_data (axi4ReadOnlyArbiter_5_io_inputs_0_r_payload_data[31:0] ), //i + .io_outputs_1_r_payload_id (axi4ReadOnlyArbiter_5_io_inputs_0_r_payload_id[3:0] ), //i + .io_outputs_1_r_payload_resp (axi4ReadOnlyArbiter_5_io_inputs_0_r_payload_resp[1:0] ), //i + .io_outputs_1_r_payload_last (axi4ReadOnlyArbiter_5_io_inputs_0_r_payload_last ), //i + .io_outputs_2_ar_valid (axiIn_0_readOnly_decoder_io_outputs_2_ar_valid ), //o + .io_outputs_2_ar_ready (toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_fire), //i + .io_outputs_2_ar_payload_addr (axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_addr[31:0] ), //o + .io_outputs_2_ar_payload_id (axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_id[3:0] ), //o + .io_outputs_2_ar_payload_len (axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_len[7:0] ), //o + .io_outputs_2_ar_payload_size (axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_size[2:0] ), //o + .io_outputs_2_ar_payload_burst (axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_burst[1:0] ), //o + .io_outputs_2_ar_payload_lock (axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_lock ), //o + .io_outputs_2_ar_payload_cache (axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_cache[3:0] ), //o + .io_outputs_2_ar_payload_prot (axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_prot[2:0] ), //o + .io_outputs_2_r_valid (axiOut_2_rvalid ), //i + .io_outputs_2_r_ready (axiIn_0_readOnly_decoder_io_outputs_2_r_ready ), //o + .io_outputs_2_r_payload_data (axiOut_2_rdata[31:0] ), //i + .io_outputs_2_r_payload_id (axiIn_0_readOnly_decoder_io_outputs_2_r_payload_id[3:0] ), //i + .io_outputs_2_r_payload_resp (axiOut_2_rresp[1:0] ), //i + .io_outputs_2_r_payload_last (axiOut_2_rlast ), //i + .io_outputs_3_ar_valid (axiIn_0_readOnly_decoder_io_outputs_3_ar_valid ), //o + .io_outputs_3_ar_ready (toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_fire), //i + .io_outputs_3_ar_payload_addr (axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_addr[31:0] ), //o + .io_outputs_3_ar_payload_id (axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_id[3:0] ), //o + .io_outputs_3_ar_payload_len (axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_len[7:0] ), //o + .io_outputs_3_ar_payload_size (axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_size[2:0] ), //o + .io_outputs_3_ar_payload_burst (axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_burst[1:0] ), //o + .io_outputs_3_ar_payload_lock (axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_lock ), //o + .io_outputs_3_ar_payload_cache (axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_cache[3:0] ), //o + .io_outputs_3_ar_payload_prot (axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_prot[2:0] ), //o + .io_outputs_3_r_valid (axiOut_3_rvalid ), //i + .io_outputs_3_r_ready (axiIn_0_readOnly_decoder_io_outputs_3_r_ready ), //o + .io_outputs_3_r_payload_data (axiOut_3_rdata[31:0] ), //i + .io_outputs_3_r_payload_id (axiIn_0_readOnly_decoder_io_outputs_3_r_payload_id[3:0] ), //i + .io_outputs_3_r_payload_resp (axiOut_3_rresp[1:0] ), //i + .io_outputs_3_r_payload_last (axiOut_3_rlast ), //i + .io_outputs_4_ar_valid (axiIn_0_readOnly_decoder_io_outputs_4_ar_valid ), //o + .io_outputs_4_ar_ready (toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_fire), //i + .io_outputs_4_ar_payload_addr (axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_addr[31:0] ), //o + .io_outputs_4_ar_payload_id (axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_id[3:0] ), //o + .io_outputs_4_ar_payload_len (axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_len[7:0] ), //o + .io_outputs_4_ar_payload_size (axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_size[2:0] ), //o + .io_outputs_4_ar_payload_burst (axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_burst[1:0] ), //o + .io_outputs_4_ar_payload_lock (axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_lock ), //o + .io_outputs_4_ar_payload_cache (axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_cache[3:0] ), //o + .io_outputs_4_ar_payload_prot (axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_prot[2:0] ), //o + .io_outputs_4_r_valid (axiOut_4_rvalid ), //i + .io_outputs_4_r_ready (axiIn_0_readOnly_decoder_io_outputs_4_r_ready ), //o + .io_outputs_4_r_payload_data (axiOut_4_rdata[31:0] ), //i + .io_outputs_4_r_payload_id (axiIn_0_readOnly_decoder_io_outputs_4_r_payload_id[3:0] ), //i + .io_outputs_4_r_payload_resp (axiOut_4_rresp[1:0] ), //i + .io_outputs_4_r_payload_last (axiOut_4_rlast ), //i + .io_outputs_5_ar_valid (axiIn_0_readOnly_decoder_io_outputs_5_ar_valid ), //o + .io_outputs_5_ar_ready (toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_fire), //i + .io_outputs_5_ar_payload_addr (axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_addr[31:0] ), //o + .io_outputs_5_ar_payload_id (axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_id[3:0] ), //o + .io_outputs_5_ar_payload_len (axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_len[7:0] ), //o + .io_outputs_5_ar_payload_size (axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_size[2:0] ), //o + .io_outputs_5_ar_payload_burst (axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_burst[1:0] ), //o + .io_outputs_5_ar_payload_lock (axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_lock ), //o + .io_outputs_5_ar_payload_cache (axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_cache[3:0] ), //o + .io_outputs_5_ar_payload_prot (axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_prot[2:0] ), //o + .io_outputs_5_r_valid (axiOut_5_rvalid ), //i + .io_outputs_5_r_ready (axiIn_0_readOnly_decoder_io_outputs_5_r_ready ), //o + .io_outputs_5_r_payload_data (axiOut_5_rdata[31:0] ), //i + .io_outputs_5_r_payload_id (axiIn_0_readOnly_decoder_io_outputs_5_r_payload_id[3:0] ), //i + .io_outputs_5_r_payload_resp (axiOut_5_rresp[1:0] ), //i + .io_outputs_5_r_payload_last (axiOut_5_rlast ), //i + .io_outputs_6_ar_valid (axiIn_0_readOnly_decoder_io_outputs_6_ar_valid ), //o + .io_outputs_6_ar_ready (toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_fire), //i + .io_outputs_6_ar_payload_addr (axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_addr[31:0] ), //o + .io_outputs_6_ar_payload_id (axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_id[3:0] ), //o + .io_outputs_6_ar_payload_len (axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_len[7:0] ), //o + .io_outputs_6_ar_payload_size (axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_size[2:0] ), //o + .io_outputs_6_ar_payload_burst (axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_burst[1:0] ), //o + .io_outputs_6_ar_payload_lock (axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_lock ), //o + .io_outputs_6_ar_payload_cache (axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_cache[3:0] ), //o + .io_outputs_6_ar_payload_prot (axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_prot[2:0] ), //o + .io_outputs_6_r_valid (axi4ReadOnlyArbiter_6_io_inputs_0_r_valid ), //i + .io_outputs_6_r_ready (axiIn_0_readOnly_decoder_io_outputs_6_r_ready ), //o + .io_outputs_6_r_payload_data (axi4ReadOnlyArbiter_6_io_inputs_0_r_payload_data[31:0] ), //i + .io_outputs_6_r_payload_id (axi4ReadOnlyArbiter_6_io_inputs_0_r_payload_id[3:0] ), //i + .io_outputs_6_r_payload_resp (axi4ReadOnlyArbiter_6_io_inputs_0_r_payload_resp[1:0] ), //i + .io_outputs_6_r_payload_last (axi4ReadOnlyArbiter_6_io_inputs_0_r_payload_last ), //i + .io_outputs_7_ar_valid (axiIn_0_readOnly_decoder_io_outputs_7_ar_valid ), //o + .io_outputs_7_ar_ready (toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_fire), //i + .io_outputs_7_ar_payload_addr (axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_addr[31:0] ), //o + .io_outputs_7_ar_payload_id (axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_id[3:0] ), //o + .io_outputs_7_ar_payload_len (axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_len[7:0] ), //o + .io_outputs_7_ar_payload_size (axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_size[2:0] ), //o + .io_outputs_7_ar_payload_burst (axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_burst[1:0] ), //o + .io_outputs_7_ar_payload_lock (axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_lock ), //o + .io_outputs_7_ar_payload_cache (axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_cache[3:0] ), //o + .io_outputs_7_ar_payload_prot (axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_prot[2:0] ), //o + .io_outputs_7_r_valid (axi4ReadOnlyArbiter_7_io_inputs_0_r_valid ), //i + .io_outputs_7_r_ready (axiIn_0_readOnly_decoder_io_outputs_7_r_ready ), //o + .io_outputs_7_r_payload_data (axi4ReadOnlyArbiter_7_io_inputs_0_r_payload_data[31:0] ), //i + .io_outputs_7_r_payload_id (axi4ReadOnlyArbiter_7_io_inputs_0_r_payload_id[3:0] ), //i + .io_outputs_7_r_payload_resp (axi4ReadOnlyArbiter_7_io_inputs_0_r_payload_resp[1:0] ), //i + .io_outputs_7_r_payload_last (axi4ReadOnlyArbiter_7_io_inputs_0_r_payload_last ), //i + .clk (clk ), //i + .resetn (resetn ) //i + ); + Axi4WriteOnlyDecoder axiIn_0_writeOnly_decoder ( + .io_input_aw_valid (axiIn_0_writeOnly_aw_valid ), //i + .io_input_aw_ready (axiIn_0_writeOnly_decoder_io_input_aw_ready ), //o + .io_input_aw_payload_addr (axiIn_0_writeOnly_aw_payload_addr[31:0] ), //i + .io_input_aw_payload_id (axiIn_0_writeOnly_aw_payload_id[3:0] ), //i + .io_input_aw_payload_len (axiIn_0_writeOnly_aw_payload_len[7:0] ), //i + .io_input_aw_payload_size (axiIn_0_writeOnly_aw_payload_size[2:0] ), //i + .io_input_aw_payload_burst (axiIn_0_writeOnly_aw_payload_burst[1:0] ), //i + .io_input_aw_payload_lock (axiIn_0_writeOnly_aw_payload_lock ), //i + .io_input_aw_payload_cache (axiIn_0_writeOnly_aw_payload_cache[3:0] ), //i + .io_input_aw_payload_prot (axiIn_0_writeOnly_aw_payload_prot[2:0] ), //i + .io_input_w_valid (axiIn_0_writeOnly_w_valid ), //i + .io_input_w_ready (axiIn_0_writeOnly_decoder_io_input_w_ready ), //o + .io_input_w_payload_data (axiIn_0_writeOnly_w_payload_data[31:0] ), //i + .io_input_w_payload_strb (axiIn_0_writeOnly_w_payload_strb[3:0] ), //i + .io_input_w_payload_last (axiIn_0_writeOnly_w_payload_last ), //i + .io_input_b_valid (axiIn_0_writeOnly_decoder_io_input_b_valid ), //o + .io_input_b_ready (axiIn_0_writeOnly_b_ready ), //i + .io_input_b_payload_id (axiIn_0_writeOnly_decoder_io_input_b_payload_id[3:0] ), //o + .io_input_b_payload_resp (axiIn_0_writeOnly_decoder_io_input_b_payload_resp[1:0] ), //o + .io_outputs_0_aw_valid (axiIn_0_writeOnly_decoder_io_outputs_0_aw_valid ), //o + .io_outputs_0_aw_ready (toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_fire), //i + .io_outputs_0_aw_payload_addr (axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_addr[31:0] ), //o + .io_outputs_0_aw_payload_id (axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_id[3:0] ), //o + .io_outputs_0_aw_payload_len (axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_len[7:0] ), //o + .io_outputs_0_aw_payload_size (axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_size[2:0] ), //o + .io_outputs_0_aw_payload_burst (axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_burst[1:0] ), //o + .io_outputs_0_aw_payload_lock (axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_lock ), //o + .io_outputs_0_aw_payload_cache (axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_cache[3:0] ), //o + .io_outputs_0_aw_payload_prot (axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_prot[2:0] ), //o + .io_outputs_0_w_valid (axiIn_0_writeOnly_decoder_io_outputs_0_w_valid ), //o + .io_outputs_0_w_ready (axi4WriteOnlyArbiter_4_io_inputs_0_w_ready ), //i + .io_outputs_0_w_payload_data (axiIn_0_writeOnly_decoder_io_outputs_0_w_payload_data[31:0] ), //o + .io_outputs_0_w_payload_strb (axiIn_0_writeOnly_decoder_io_outputs_0_w_payload_strb[3:0] ), //o + .io_outputs_0_w_payload_last (axiIn_0_writeOnly_decoder_io_outputs_0_w_payload_last ), //o + .io_outputs_0_b_valid (axi4WriteOnlyArbiter_4_io_inputs_0_b_valid ), //i + .io_outputs_0_b_ready (axiIn_0_writeOnly_decoder_io_outputs_0_b_ready ), //o + .io_outputs_0_b_payload_id (axi4WriteOnlyArbiter_4_io_inputs_0_b_payload_id[3:0] ), //i + .io_outputs_0_b_payload_resp (axi4WriteOnlyArbiter_4_io_inputs_0_b_payload_resp[1:0] ), //i + .io_outputs_1_aw_valid (axiIn_0_writeOnly_decoder_io_outputs_1_aw_valid ), //o + .io_outputs_1_aw_ready (toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_fire), //i + .io_outputs_1_aw_payload_addr (axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_addr[31:0] ), //o + .io_outputs_1_aw_payload_id (axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_id[3:0] ), //o + .io_outputs_1_aw_payload_len (axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_len[7:0] ), //o + .io_outputs_1_aw_payload_size (axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_size[2:0] ), //o + .io_outputs_1_aw_payload_burst (axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_burst[1:0] ), //o + .io_outputs_1_aw_payload_lock (axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_lock ), //o + .io_outputs_1_aw_payload_cache (axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_cache[3:0] ), //o + .io_outputs_1_aw_payload_prot (axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_prot[2:0] ), //o + .io_outputs_1_w_valid (axiIn_0_writeOnly_decoder_io_outputs_1_w_valid ), //o + .io_outputs_1_w_ready (axi4WriteOnlyArbiter_5_io_inputs_0_w_ready ), //i + .io_outputs_1_w_payload_data (axiIn_0_writeOnly_decoder_io_outputs_1_w_payload_data[31:0] ), //o + .io_outputs_1_w_payload_strb (axiIn_0_writeOnly_decoder_io_outputs_1_w_payload_strb[3:0] ), //o + .io_outputs_1_w_payload_last (axiIn_0_writeOnly_decoder_io_outputs_1_w_payload_last ), //o + .io_outputs_1_b_valid (axi4WriteOnlyArbiter_5_io_inputs_0_b_valid ), //i + .io_outputs_1_b_ready (axiIn_0_writeOnly_decoder_io_outputs_1_b_ready ), //o + .io_outputs_1_b_payload_id (axi4WriteOnlyArbiter_5_io_inputs_0_b_payload_id[3:0] ), //i + .io_outputs_1_b_payload_resp (axi4WriteOnlyArbiter_5_io_inputs_0_b_payload_resp[1:0] ), //i + .io_outputs_2_aw_valid (axiIn_0_writeOnly_decoder_io_outputs_2_aw_valid ), //o + .io_outputs_2_aw_ready (toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_fire), //i + .io_outputs_2_aw_payload_addr (axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_addr[31:0] ), //o + .io_outputs_2_aw_payload_id (axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_id[3:0] ), //o + .io_outputs_2_aw_payload_len (axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_len[7:0] ), //o + .io_outputs_2_aw_payload_size (axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_size[2:0] ), //o + .io_outputs_2_aw_payload_burst (axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_burst[1:0] ), //o + .io_outputs_2_aw_payload_lock (axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_lock ), //o + .io_outputs_2_aw_payload_cache (axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_cache[3:0] ), //o + .io_outputs_2_aw_payload_prot (axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_prot[2:0] ), //o + .io_outputs_2_w_valid (axiIn_0_writeOnly_decoder_io_outputs_2_w_valid ), //o + .io_outputs_2_w_ready (axiOut_2_wready ), //i + .io_outputs_2_w_payload_data (axiIn_0_writeOnly_decoder_io_outputs_2_w_payload_data[31:0] ), //o + .io_outputs_2_w_payload_strb (axiIn_0_writeOnly_decoder_io_outputs_2_w_payload_strb[3:0] ), //o + .io_outputs_2_w_payload_last (axiIn_0_writeOnly_decoder_io_outputs_2_w_payload_last ), //o + .io_outputs_2_b_valid (axiOut_2_bvalid ), //i + .io_outputs_2_b_ready (axiIn_0_writeOnly_decoder_io_outputs_2_b_ready ), //o + .io_outputs_2_b_payload_id (axiIn_0_writeOnly_decoder_io_outputs_2_b_payload_id[3:0] ), //i + .io_outputs_2_b_payload_resp (axiOut_2_bresp[1:0] ), //i + .io_outputs_3_aw_valid (axiIn_0_writeOnly_decoder_io_outputs_3_aw_valid ), //o + .io_outputs_3_aw_ready (toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_fire), //i + .io_outputs_3_aw_payload_addr (axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_addr[31:0] ), //o + .io_outputs_3_aw_payload_id (axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_id[3:0] ), //o + .io_outputs_3_aw_payload_len (axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_len[7:0] ), //o + .io_outputs_3_aw_payload_size (axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_size[2:0] ), //o + .io_outputs_3_aw_payload_burst (axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_burst[1:0] ), //o + .io_outputs_3_aw_payload_lock (axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_lock ), //o + .io_outputs_3_aw_payload_cache (axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_cache[3:0] ), //o + .io_outputs_3_aw_payload_prot (axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_prot[2:0] ), //o + .io_outputs_3_w_valid (axiIn_0_writeOnly_decoder_io_outputs_3_w_valid ), //o + .io_outputs_3_w_ready (axiOut_3_wready ), //i + .io_outputs_3_w_payload_data (axiIn_0_writeOnly_decoder_io_outputs_3_w_payload_data[31:0] ), //o + .io_outputs_3_w_payload_strb (axiIn_0_writeOnly_decoder_io_outputs_3_w_payload_strb[3:0] ), //o + .io_outputs_3_w_payload_last (axiIn_0_writeOnly_decoder_io_outputs_3_w_payload_last ), //o + .io_outputs_3_b_valid (axiOut_3_bvalid ), //i + .io_outputs_3_b_ready (axiIn_0_writeOnly_decoder_io_outputs_3_b_ready ), //o + .io_outputs_3_b_payload_id (axiIn_0_writeOnly_decoder_io_outputs_3_b_payload_id[3:0] ), //i + .io_outputs_3_b_payload_resp (axiOut_3_bresp[1:0] ), //i + .io_outputs_4_aw_valid (axiIn_0_writeOnly_decoder_io_outputs_4_aw_valid ), //o + .io_outputs_4_aw_ready (toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_fire), //i + .io_outputs_4_aw_payload_addr (axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_addr[31:0] ), //o + .io_outputs_4_aw_payload_id (axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_id[3:0] ), //o + .io_outputs_4_aw_payload_len (axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_len[7:0] ), //o + .io_outputs_4_aw_payload_size (axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_size[2:0] ), //o + .io_outputs_4_aw_payload_burst (axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_burst[1:0] ), //o + .io_outputs_4_aw_payload_lock (axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_lock ), //o + .io_outputs_4_aw_payload_cache (axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_cache[3:0] ), //o + .io_outputs_4_aw_payload_prot (axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_prot[2:0] ), //o + .io_outputs_4_w_valid (axiIn_0_writeOnly_decoder_io_outputs_4_w_valid ), //o + .io_outputs_4_w_ready (axiOut_4_wready ), //i + .io_outputs_4_w_payload_data (axiIn_0_writeOnly_decoder_io_outputs_4_w_payload_data[31:0] ), //o + .io_outputs_4_w_payload_strb (axiIn_0_writeOnly_decoder_io_outputs_4_w_payload_strb[3:0] ), //o + .io_outputs_4_w_payload_last (axiIn_0_writeOnly_decoder_io_outputs_4_w_payload_last ), //o + .io_outputs_4_b_valid (axiOut_4_bvalid ), //i + .io_outputs_4_b_ready (axiIn_0_writeOnly_decoder_io_outputs_4_b_ready ), //o + .io_outputs_4_b_payload_id (axiIn_0_writeOnly_decoder_io_outputs_4_b_payload_id[3:0] ), //i + .io_outputs_4_b_payload_resp (axiOut_4_bresp[1:0] ), //i + .io_outputs_5_aw_valid (axiIn_0_writeOnly_decoder_io_outputs_5_aw_valid ), //o + .io_outputs_5_aw_ready (toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_fire), //i + .io_outputs_5_aw_payload_addr (axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_addr[31:0] ), //o + .io_outputs_5_aw_payload_id (axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_id[3:0] ), //o + .io_outputs_5_aw_payload_len (axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_len[7:0] ), //o + .io_outputs_5_aw_payload_size (axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_size[2:0] ), //o + .io_outputs_5_aw_payload_burst (axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_burst[1:0] ), //o + .io_outputs_5_aw_payload_lock (axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_lock ), //o + .io_outputs_5_aw_payload_cache (axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_cache[3:0] ), //o + .io_outputs_5_aw_payload_prot (axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_prot[2:0] ), //o + .io_outputs_5_w_valid (axiIn_0_writeOnly_decoder_io_outputs_5_w_valid ), //o + .io_outputs_5_w_ready (axiOut_5_wready ), //i + .io_outputs_5_w_payload_data (axiIn_0_writeOnly_decoder_io_outputs_5_w_payload_data[31:0] ), //o + .io_outputs_5_w_payload_strb (axiIn_0_writeOnly_decoder_io_outputs_5_w_payload_strb[3:0] ), //o + .io_outputs_5_w_payload_last (axiIn_0_writeOnly_decoder_io_outputs_5_w_payload_last ), //o + .io_outputs_5_b_valid (axiOut_5_bvalid ), //i + .io_outputs_5_b_ready (axiIn_0_writeOnly_decoder_io_outputs_5_b_ready ), //o + .io_outputs_5_b_payload_id (axiIn_0_writeOnly_decoder_io_outputs_5_b_payload_id[3:0] ), //i + .io_outputs_5_b_payload_resp (axiOut_5_bresp[1:0] ), //i + .io_outputs_6_aw_valid (axiIn_0_writeOnly_decoder_io_outputs_6_aw_valid ), //o + .io_outputs_6_aw_ready (toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_fire), //i + .io_outputs_6_aw_payload_addr (axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_addr[31:0] ), //o + .io_outputs_6_aw_payload_id (axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_id[3:0] ), //o + .io_outputs_6_aw_payload_len (axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_len[7:0] ), //o + .io_outputs_6_aw_payload_size (axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_size[2:0] ), //o + .io_outputs_6_aw_payload_burst (axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_burst[1:0] ), //o + .io_outputs_6_aw_payload_lock (axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_lock ), //o + .io_outputs_6_aw_payload_cache (axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_cache[3:0] ), //o + .io_outputs_6_aw_payload_prot (axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_prot[2:0] ), //o + .io_outputs_6_w_valid (axiIn_0_writeOnly_decoder_io_outputs_6_w_valid ), //o + .io_outputs_6_w_ready (axi4WriteOnlyArbiter_6_io_inputs_0_w_ready ), //i + .io_outputs_6_w_payload_data (axiIn_0_writeOnly_decoder_io_outputs_6_w_payload_data[31:0] ), //o + .io_outputs_6_w_payload_strb (axiIn_0_writeOnly_decoder_io_outputs_6_w_payload_strb[3:0] ), //o + .io_outputs_6_w_payload_last (axiIn_0_writeOnly_decoder_io_outputs_6_w_payload_last ), //o + .io_outputs_6_b_valid (axi4WriteOnlyArbiter_6_io_inputs_0_b_valid ), //i + .io_outputs_6_b_ready (axiIn_0_writeOnly_decoder_io_outputs_6_b_ready ), //o + .io_outputs_6_b_payload_id (axi4WriteOnlyArbiter_6_io_inputs_0_b_payload_id[3:0] ), //i + .io_outputs_6_b_payload_resp (axi4WriteOnlyArbiter_6_io_inputs_0_b_payload_resp[1:0] ), //i + .io_outputs_7_aw_valid (axiIn_0_writeOnly_decoder_io_outputs_7_aw_valid ), //o + .io_outputs_7_aw_ready (toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_fire), //i + .io_outputs_7_aw_payload_addr (axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_addr[31:0] ), //o + .io_outputs_7_aw_payload_id (axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_id[3:0] ), //o + .io_outputs_7_aw_payload_len (axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_len[7:0] ), //o + .io_outputs_7_aw_payload_size (axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_size[2:0] ), //o + .io_outputs_7_aw_payload_burst (axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_burst[1:0] ), //o + .io_outputs_7_aw_payload_lock (axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_lock ), //o + .io_outputs_7_aw_payload_cache (axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_cache[3:0] ), //o + .io_outputs_7_aw_payload_prot (axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_prot[2:0] ), //o + .io_outputs_7_w_valid (axiIn_0_writeOnly_decoder_io_outputs_7_w_valid ), //o + .io_outputs_7_w_ready (axi4WriteOnlyArbiter_7_io_inputs_0_w_ready ), //i + .io_outputs_7_w_payload_data (axiIn_0_writeOnly_decoder_io_outputs_7_w_payload_data[31:0] ), //o + .io_outputs_7_w_payload_strb (axiIn_0_writeOnly_decoder_io_outputs_7_w_payload_strb[3:0] ), //o + .io_outputs_7_w_payload_last (axiIn_0_writeOnly_decoder_io_outputs_7_w_payload_last ), //o + .io_outputs_7_b_valid (axi4WriteOnlyArbiter_7_io_inputs_0_b_valid ), //i + .io_outputs_7_b_ready (axiIn_0_writeOnly_decoder_io_outputs_7_b_ready ), //o + .io_outputs_7_b_payload_id (axi4WriteOnlyArbiter_7_io_inputs_0_b_payload_id[3:0] ), //i + .io_outputs_7_b_payload_resp (axi4WriteOnlyArbiter_7_io_inputs_0_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .resetn (resetn ) //i + ); + Axi4ReadOnlyDecoder_1 axiIn_1_readOnly_decoder ( + .io_input_ar_valid (axiIn_1_readOnly_ar_valid ), //i + .io_input_ar_ready (axiIn_1_readOnly_decoder_io_input_ar_ready ), //o + .io_input_ar_payload_addr (axiIn_1_readOnly_ar_payload_addr[31:0] ), //i + .io_input_ar_payload_id (axiIn_1_readOnly_ar_payload_id[3:0] ), //i + .io_input_ar_payload_len (axiIn_1_readOnly_ar_payload_len[7:0] ), //i + .io_input_ar_payload_size (axiIn_1_readOnly_ar_payload_size[2:0] ), //i + .io_input_ar_payload_burst (axiIn_1_readOnly_ar_payload_burst[1:0] ), //i + .io_input_ar_payload_lock (axiIn_1_readOnly_ar_payload_lock ), //i + .io_input_ar_payload_cache (axiIn_1_readOnly_ar_payload_cache[3:0] ), //i + .io_input_ar_payload_prot (axiIn_1_readOnly_ar_payload_prot[2:0] ), //i + .io_input_r_valid (axiIn_1_readOnly_decoder_io_input_r_valid ), //o + .io_input_r_ready (axiIn_1_readOnly_r_ready ), //i + .io_input_r_payload_data (axiIn_1_readOnly_decoder_io_input_r_payload_data[31:0] ), //o + .io_input_r_payload_id (axiIn_1_readOnly_decoder_io_input_r_payload_id[3:0] ), //o + .io_input_r_payload_resp (axiIn_1_readOnly_decoder_io_input_r_payload_resp[1:0] ), //o + .io_input_r_payload_last (axiIn_1_readOnly_decoder_io_input_r_payload_last ), //o + .io_outputs_0_ar_valid (axiIn_1_readOnly_decoder_io_outputs_0_ar_valid ), //o + .io_outputs_0_ar_ready (toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_fire), //i + .io_outputs_0_ar_payload_addr (axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_addr[31:0] ), //o + .io_outputs_0_ar_payload_id (axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_id[3:0] ), //o + .io_outputs_0_ar_payload_len (axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_len[7:0] ), //o + .io_outputs_0_ar_payload_size (axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_size[2:0] ), //o + .io_outputs_0_ar_payload_burst (axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_burst[1:0] ), //o + .io_outputs_0_ar_payload_lock (axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_lock ), //o + .io_outputs_0_ar_payload_cache (axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_cache[3:0] ), //o + .io_outputs_0_ar_payload_prot (axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_prot[2:0] ), //o + .io_outputs_0_r_valid (axi4ReadOnlyArbiter_4_io_inputs_1_r_valid ), //i + .io_outputs_0_r_ready (axiIn_1_readOnly_decoder_io_outputs_0_r_ready ), //o + .io_outputs_0_r_payload_data (axi4ReadOnlyArbiter_4_io_inputs_1_r_payload_data[31:0] ), //i + .io_outputs_0_r_payload_id (axi4ReadOnlyArbiter_4_io_inputs_1_r_payload_id[3:0] ), //i + .io_outputs_0_r_payload_resp (axi4ReadOnlyArbiter_4_io_inputs_1_r_payload_resp[1:0] ), //i + .io_outputs_0_r_payload_last (axi4ReadOnlyArbiter_4_io_inputs_1_r_payload_last ), //i + .io_outputs_1_ar_valid (axiIn_1_readOnly_decoder_io_outputs_1_ar_valid ), //o + .io_outputs_1_ar_ready (toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_fire), //i + .io_outputs_1_ar_payload_addr (axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_addr[31:0] ), //o + .io_outputs_1_ar_payload_id (axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_id[3:0] ), //o + .io_outputs_1_ar_payload_len (axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_len[7:0] ), //o + .io_outputs_1_ar_payload_size (axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_size[2:0] ), //o + .io_outputs_1_ar_payload_burst (axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_burst[1:0] ), //o + .io_outputs_1_ar_payload_lock (axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_lock ), //o + .io_outputs_1_ar_payload_cache (axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_cache[3:0] ), //o + .io_outputs_1_ar_payload_prot (axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_prot[2:0] ), //o + .io_outputs_1_r_valid (axi4ReadOnlyArbiter_5_io_inputs_1_r_valid ), //i + .io_outputs_1_r_ready (axiIn_1_readOnly_decoder_io_outputs_1_r_ready ), //o + .io_outputs_1_r_payload_data (axi4ReadOnlyArbiter_5_io_inputs_1_r_payload_data[31:0] ), //i + .io_outputs_1_r_payload_id (axi4ReadOnlyArbiter_5_io_inputs_1_r_payload_id[3:0] ), //i + .io_outputs_1_r_payload_resp (axi4ReadOnlyArbiter_5_io_inputs_1_r_payload_resp[1:0] ), //i + .io_outputs_1_r_payload_last (axi4ReadOnlyArbiter_5_io_inputs_1_r_payload_last ), //i + .io_outputs_2_ar_valid (axiIn_1_readOnly_decoder_io_outputs_2_ar_valid ), //o + .io_outputs_2_ar_ready (toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_fire), //i + .io_outputs_2_ar_payload_addr (axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_addr[31:0] ), //o + .io_outputs_2_ar_payload_id (axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_id[3:0] ), //o + .io_outputs_2_ar_payload_len (axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_len[7:0] ), //o + .io_outputs_2_ar_payload_size (axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_size[2:0] ), //o + .io_outputs_2_ar_payload_burst (axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_burst[1:0] ), //o + .io_outputs_2_ar_payload_lock (axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_lock ), //o + .io_outputs_2_ar_payload_cache (axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_cache[3:0] ), //o + .io_outputs_2_ar_payload_prot (axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_prot[2:0] ), //o + .io_outputs_2_r_valid (axi4ReadOnlyArbiter_6_io_inputs_1_r_valid ), //i + .io_outputs_2_r_ready (axiIn_1_readOnly_decoder_io_outputs_2_r_ready ), //o + .io_outputs_2_r_payload_data (axi4ReadOnlyArbiter_6_io_inputs_1_r_payload_data[31:0] ), //i + .io_outputs_2_r_payload_id (axi4ReadOnlyArbiter_6_io_inputs_1_r_payload_id[3:0] ), //i + .io_outputs_2_r_payload_resp (axi4ReadOnlyArbiter_6_io_inputs_1_r_payload_resp[1:0] ), //i + .io_outputs_2_r_payload_last (axi4ReadOnlyArbiter_6_io_inputs_1_r_payload_last ), //i + .io_outputs_3_ar_valid (axiIn_1_readOnly_decoder_io_outputs_3_ar_valid ), //o + .io_outputs_3_ar_ready (toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_fire), //i + .io_outputs_3_ar_payload_addr (axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_addr[31:0] ), //o + .io_outputs_3_ar_payload_id (axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_id[3:0] ), //o + .io_outputs_3_ar_payload_len (axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_len[7:0] ), //o + .io_outputs_3_ar_payload_size (axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_size[2:0] ), //o + .io_outputs_3_ar_payload_burst (axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_burst[1:0] ), //o + .io_outputs_3_ar_payload_lock (axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_lock ), //o + .io_outputs_3_ar_payload_cache (axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_cache[3:0] ), //o + .io_outputs_3_ar_payload_prot (axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_prot[2:0] ), //o + .io_outputs_3_r_valid (axi4ReadOnlyArbiter_7_io_inputs_1_r_valid ), //i + .io_outputs_3_r_ready (axiIn_1_readOnly_decoder_io_outputs_3_r_ready ), //o + .io_outputs_3_r_payload_data (axi4ReadOnlyArbiter_7_io_inputs_1_r_payload_data[31:0] ), //i + .io_outputs_3_r_payload_id (axi4ReadOnlyArbiter_7_io_inputs_1_r_payload_id[3:0] ), //i + .io_outputs_3_r_payload_resp (axi4ReadOnlyArbiter_7_io_inputs_1_r_payload_resp[1:0] ), //i + .io_outputs_3_r_payload_last (axi4ReadOnlyArbiter_7_io_inputs_1_r_payload_last ), //i + .clk (clk ), //i + .resetn (resetn ) //i + ); + Axi4WriteOnlyDecoder_1 axiIn_1_writeOnly_decoder ( + .io_input_aw_valid (axiIn_1_writeOnly_aw_valid ), //i + .io_input_aw_ready (axiIn_1_writeOnly_decoder_io_input_aw_ready ), //o + .io_input_aw_payload_addr (axiIn_1_writeOnly_aw_payload_addr[31:0] ), //i + .io_input_aw_payload_id (axiIn_1_writeOnly_aw_payload_id[3:0] ), //i + .io_input_aw_payload_len (axiIn_1_writeOnly_aw_payload_len[7:0] ), //i + .io_input_aw_payload_size (axiIn_1_writeOnly_aw_payload_size[2:0] ), //i + .io_input_aw_payload_burst (axiIn_1_writeOnly_aw_payload_burst[1:0] ), //i + .io_input_aw_payload_lock (axiIn_1_writeOnly_aw_payload_lock ), //i + .io_input_aw_payload_cache (axiIn_1_writeOnly_aw_payload_cache[3:0] ), //i + .io_input_aw_payload_prot (axiIn_1_writeOnly_aw_payload_prot[2:0] ), //i + .io_input_w_valid (axiIn_1_writeOnly_w_valid ), //i + .io_input_w_ready (axiIn_1_writeOnly_decoder_io_input_w_ready ), //o + .io_input_w_payload_data (axiIn_1_writeOnly_w_payload_data[31:0] ), //i + .io_input_w_payload_strb (axiIn_1_writeOnly_w_payload_strb[3:0] ), //i + .io_input_w_payload_last (axiIn_1_writeOnly_w_payload_last ), //i + .io_input_b_valid (axiIn_1_writeOnly_decoder_io_input_b_valid ), //o + .io_input_b_ready (axiIn_1_writeOnly_b_ready ), //i + .io_input_b_payload_id (axiIn_1_writeOnly_decoder_io_input_b_payload_id[3:0] ), //o + .io_input_b_payload_resp (axiIn_1_writeOnly_decoder_io_input_b_payload_resp[1:0] ), //o + .io_outputs_0_aw_valid (axiIn_1_writeOnly_decoder_io_outputs_0_aw_valid ), //o + .io_outputs_0_aw_ready (toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_fire), //i + .io_outputs_0_aw_payload_addr (axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_addr[31:0] ), //o + .io_outputs_0_aw_payload_id (axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_id[3:0] ), //o + .io_outputs_0_aw_payload_len (axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_len[7:0] ), //o + .io_outputs_0_aw_payload_size (axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_size[2:0] ), //o + .io_outputs_0_aw_payload_burst (axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_burst[1:0] ), //o + .io_outputs_0_aw_payload_lock (axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_lock ), //o + .io_outputs_0_aw_payload_cache (axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_cache[3:0] ), //o + .io_outputs_0_aw_payload_prot (axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_prot[2:0] ), //o + .io_outputs_0_w_valid (axiIn_1_writeOnly_decoder_io_outputs_0_w_valid ), //o + .io_outputs_0_w_ready (axi4WriteOnlyArbiter_4_io_inputs_1_w_ready ), //i + .io_outputs_0_w_payload_data (axiIn_1_writeOnly_decoder_io_outputs_0_w_payload_data[31:0] ), //o + .io_outputs_0_w_payload_strb (axiIn_1_writeOnly_decoder_io_outputs_0_w_payload_strb[3:0] ), //o + .io_outputs_0_w_payload_last (axiIn_1_writeOnly_decoder_io_outputs_0_w_payload_last ), //o + .io_outputs_0_b_valid (axi4WriteOnlyArbiter_4_io_inputs_1_b_valid ), //i + .io_outputs_0_b_ready (axiIn_1_writeOnly_decoder_io_outputs_0_b_ready ), //o + .io_outputs_0_b_payload_id (axi4WriteOnlyArbiter_4_io_inputs_1_b_payload_id[3:0] ), //i + .io_outputs_0_b_payload_resp (axi4WriteOnlyArbiter_4_io_inputs_1_b_payload_resp[1:0] ), //i + .io_outputs_1_aw_valid (axiIn_1_writeOnly_decoder_io_outputs_1_aw_valid ), //o + .io_outputs_1_aw_ready (toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_fire), //i + .io_outputs_1_aw_payload_addr (axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_addr[31:0] ), //o + .io_outputs_1_aw_payload_id (axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_id[3:0] ), //o + .io_outputs_1_aw_payload_len (axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_len[7:0] ), //o + .io_outputs_1_aw_payload_size (axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_size[2:0] ), //o + .io_outputs_1_aw_payload_burst (axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_burst[1:0] ), //o + .io_outputs_1_aw_payload_lock (axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_lock ), //o + .io_outputs_1_aw_payload_cache (axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_cache[3:0] ), //o + .io_outputs_1_aw_payload_prot (axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_prot[2:0] ), //o + .io_outputs_1_w_valid (axiIn_1_writeOnly_decoder_io_outputs_1_w_valid ), //o + .io_outputs_1_w_ready (axi4WriteOnlyArbiter_5_io_inputs_1_w_ready ), //i + .io_outputs_1_w_payload_data (axiIn_1_writeOnly_decoder_io_outputs_1_w_payload_data[31:0] ), //o + .io_outputs_1_w_payload_strb (axiIn_1_writeOnly_decoder_io_outputs_1_w_payload_strb[3:0] ), //o + .io_outputs_1_w_payload_last (axiIn_1_writeOnly_decoder_io_outputs_1_w_payload_last ), //o + .io_outputs_1_b_valid (axi4WriteOnlyArbiter_5_io_inputs_1_b_valid ), //i + .io_outputs_1_b_ready (axiIn_1_writeOnly_decoder_io_outputs_1_b_ready ), //o + .io_outputs_1_b_payload_id (axi4WriteOnlyArbiter_5_io_inputs_1_b_payload_id[3:0] ), //i + .io_outputs_1_b_payload_resp (axi4WriteOnlyArbiter_5_io_inputs_1_b_payload_resp[1:0] ), //i + .io_outputs_2_aw_valid (axiIn_1_writeOnly_decoder_io_outputs_2_aw_valid ), //o + .io_outputs_2_aw_ready (toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_fire), //i + .io_outputs_2_aw_payload_addr (axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_addr[31:0] ), //o + .io_outputs_2_aw_payload_id (axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_id[3:0] ), //o + .io_outputs_2_aw_payload_len (axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_len[7:0] ), //o + .io_outputs_2_aw_payload_size (axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_size[2:0] ), //o + .io_outputs_2_aw_payload_burst (axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_burst[1:0] ), //o + .io_outputs_2_aw_payload_lock (axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_lock ), //o + .io_outputs_2_aw_payload_cache (axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_cache[3:0] ), //o + .io_outputs_2_aw_payload_prot (axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_prot[2:0] ), //o + .io_outputs_2_w_valid (axiIn_1_writeOnly_decoder_io_outputs_2_w_valid ), //o + .io_outputs_2_w_ready (axi4WriteOnlyArbiter_6_io_inputs_1_w_ready ), //i + .io_outputs_2_w_payload_data (axiIn_1_writeOnly_decoder_io_outputs_2_w_payload_data[31:0] ), //o + .io_outputs_2_w_payload_strb (axiIn_1_writeOnly_decoder_io_outputs_2_w_payload_strb[3:0] ), //o + .io_outputs_2_w_payload_last (axiIn_1_writeOnly_decoder_io_outputs_2_w_payload_last ), //o + .io_outputs_2_b_valid (axi4WriteOnlyArbiter_6_io_inputs_1_b_valid ), //i + .io_outputs_2_b_ready (axiIn_1_writeOnly_decoder_io_outputs_2_b_ready ), //o + .io_outputs_2_b_payload_id (axi4WriteOnlyArbiter_6_io_inputs_1_b_payload_id[3:0] ), //i + .io_outputs_2_b_payload_resp (axi4WriteOnlyArbiter_6_io_inputs_1_b_payload_resp[1:0] ), //i + .io_outputs_3_aw_valid (axiIn_1_writeOnly_decoder_io_outputs_3_aw_valid ), //o + .io_outputs_3_aw_ready (toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_fire), //i + .io_outputs_3_aw_payload_addr (axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_addr[31:0] ), //o + .io_outputs_3_aw_payload_id (axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_id[3:0] ), //o + .io_outputs_3_aw_payload_len (axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_len[7:0] ), //o + .io_outputs_3_aw_payload_size (axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_size[2:0] ), //o + .io_outputs_3_aw_payload_burst (axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_burst[1:0] ), //o + .io_outputs_3_aw_payload_lock (axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_lock ), //o + .io_outputs_3_aw_payload_cache (axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_cache[3:0] ), //o + .io_outputs_3_aw_payload_prot (axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_prot[2:0] ), //o + .io_outputs_3_w_valid (axiIn_1_writeOnly_decoder_io_outputs_3_w_valid ), //o + .io_outputs_3_w_ready (axi4WriteOnlyArbiter_7_io_inputs_1_w_ready ), //i + .io_outputs_3_w_payload_data (axiIn_1_writeOnly_decoder_io_outputs_3_w_payload_data[31:0] ), //o + .io_outputs_3_w_payload_strb (axiIn_1_writeOnly_decoder_io_outputs_3_w_payload_strb[3:0] ), //o + .io_outputs_3_w_payload_last (axiIn_1_writeOnly_decoder_io_outputs_3_w_payload_last ), //o + .io_outputs_3_b_valid (axi4WriteOnlyArbiter_7_io_inputs_1_b_valid ), //i + .io_outputs_3_b_ready (axiIn_1_writeOnly_decoder_io_outputs_3_b_ready ), //o + .io_outputs_3_b_payload_id (axi4WriteOnlyArbiter_7_io_inputs_1_b_payload_id[3:0] ), //i + .io_outputs_3_b_payload_resp (axi4WriteOnlyArbiter_7_io_inputs_1_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .resetn (resetn ) //i + ); + Axi4ReadOnlyArbiter axi4ReadOnlyArbiter_4 ( + .io_inputs_0_ar_valid (toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_valid ), //i + .io_inputs_0_ar_ready (axi4ReadOnlyArbiter_4_io_inputs_0_ar_ready ), //o + .io_inputs_0_ar_payload_addr (toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_addr[31:0]), //i + .io_inputs_0_ar_payload_id (toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_id[3:0] ), //i + .io_inputs_0_ar_payload_len (toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_len[7:0] ), //i + .io_inputs_0_ar_payload_size (toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_size[2:0] ), //i + .io_inputs_0_ar_payload_burst (toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_burst[1:0]), //i + .io_inputs_0_ar_payload_lock (toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_lock ), //i + .io_inputs_0_ar_payload_cache (toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_cache[3:0]), //i + .io_inputs_0_ar_payload_prot (toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_prot[2:0] ), //i + .io_inputs_0_r_valid (axi4ReadOnlyArbiter_4_io_inputs_0_r_valid ), //o + .io_inputs_0_r_ready (axiIn_0_readOnly_decoder_io_outputs_0_r_ready ), //i + .io_inputs_0_r_payload_data (axi4ReadOnlyArbiter_4_io_inputs_0_r_payload_data[31:0] ), //o + .io_inputs_0_r_payload_id (axi4ReadOnlyArbiter_4_io_inputs_0_r_payload_id[3:0] ), //o + .io_inputs_0_r_payload_resp (axi4ReadOnlyArbiter_4_io_inputs_0_r_payload_resp[1:0] ), //o + .io_inputs_0_r_payload_last (axi4ReadOnlyArbiter_4_io_inputs_0_r_payload_last ), //o + .io_inputs_1_ar_valid (toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_valid ), //i + .io_inputs_1_ar_ready (axi4ReadOnlyArbiter_4_io_inputs_1_ar_ready ), //o + .io_inputs_1_ar_payload_addr (toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_addr[31:0]), //i + .io_inputs_1_ar_payload_id (toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_id[3:0] ), //i + .io_inputs_1_ar_payload_len (toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_len[7:0] ), //i + .io_inputs_1_ar_payload_size (toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_size[2:0] ), //i + .io_inputs_1_ar_payload_burst (toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_burst[1:0]), //i + .io_inputs_1_ar_payload_lock (toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_lock ), //i + .io_inputs_1_ar_payload_cache (toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_cache[3:0]), //i + .io_inputs_1_ar_payload_prot (toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_prot[2:0] ), //i + .io_inputs_1_r_valid (axi4ReadOnlyArbiter_4_io_inputs_1_r_valid ), //o + .io_inputs_1_r_ready (axiIn_1_readOnly_decoder_io_outputs_0_r_ready ), //i + .io_inputs_1_r_payload_data (axi4ReadOnlyArbiter_4_io_inputs_1_r_payload_data[31:0] ), //o + .io_inputs_1_r_payload_id (axi4ReadOnlyArbiter_4_io_inputs_1_r_payload_id[3:0] ), //o + .io_inputs_1_r_payload_resp (axi4ReadOnlyArbiter_4_io_inputs_1_r_payload_resp[1:0] ), //o + .io_inputs_1_r_payload_last (axi4ReadOnlyArbiter_4_io_inputs_1_r_payload_last ), //o + .io_output_ar_valid (axi4ReadOnlyArbiter_4_io_output_ar_valid ), //o + .io_output_ar_ready (axiOut_0_arready ), //i + .io_output_ar_payload_addr (axi4ReadOnlyArbiter_4_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_id (axi4ReadOnlyArbiter_4_io_output_ar_payload_id[4:0] ), //o + .io_output_ar_payload_len (axi4ReadOnlyArbiter_4_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (axi4ReadOnlyArbiter_4_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_burst (axi4ReadOnlyArbiter_4_io_output_ar_payload_burst[1:0] ), //o + .io_output_ar_payload_lock (axi4ReadOnlyArbiter_4_io_output_ar_payload_lock ), //o + .io_output_ar_payload_cache (axi4ReadOnlyArbiter_4_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_prot (axi4ReadOnlyArbiter_4_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (axiOut_0_rvalid ), //i + .io_output_r_ready (axi4ReadOnlyArbiter_4_io_output_r_ready ), //o + .io_output_r_payload_data (axiOut_0_rdata[31:0] ), //i + .io_output_r_payload_id (axiOut_0_rid[4:0] ), //i + .io_output_r_payload_resp (axiOut_0_rresp[1:0] ), //i + .io_output_r_payload_last (axiOut_0_rlast ), //i + .clk (clk ), //i + .resetn (resetn ) //i + ); + Axi4WriteOnlyArbiter axi4WriteOnlyArbiter_4 ( + .io_inputs_0_aw_valid (toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_valid ), //i + .io_inputs_0_aw_ready (axi4WriteOnlyArbiter_4_io_inputs_0_aw_ready ), //o + .io_inputs_0_aw_payload_addr (toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_addr[31:0]), //i + .io_inputs_0_aw_payload_id (toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_id[3:0] ), //i + .io_inputs_0_aw_payload_len (toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_len[7:0] ), //i + .io_inputs_0_aw_payload_size (toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_size[2:0] ), //i + .io_inputs_0_aw_payload_burst (toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_burst[1:0]), //i + .io_inputs_0_aw_payload_lock (toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_lock ), //i + .io_inputs_0_aw_payload_cache (toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_cache[3:0]), //i + .io_inputs_0_aw_payload_prot (toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_prot[2:0] ), //i + .io_inputs_0_w_valid (axiIn_0_writeOnly_decoder_io_outputs_0_w_valid ), //i + .io_inputs_0_w_ready (axi4WriteOnlyArbiter_4_io_inputs_0_w_ready ), //o + .io_inputs_0_w_payload_data (axiIn_0_writeOnly_decoder_io_outputs_0_w_payload_data[31:0] ), //i + .io_inputs_0_w_payload_strb (axiIn_0_writeOnly_decoder_io_outputs_0_w_payload_strb[3:0] ), //i + .io_inputs_0_w_payload_last (axiIn_0_writeOnly_decoder_io_outputs_0_w_payload_last ), //i + .io_inputs_0_b_valid (axi4WriteOnlyArbiter_4_io_inputs_0_b_valid ), //o + .io_inputs_0_b_ready (axiIn_0_writeOnly_decoder_io_outputs_0_b_ready ), //i + .io_inputs_0_b_payload_id (axi4WriteOnlyArbiter_4_io_inputs_0_b_payload_id[3:0] ), //o + .io_inputs_0_b_payload_resp (axi4WriteOnlyArbiter_4_io_inputs_0_b_payload_resp[1:0] ), //o + .io_inputs_1_aw_valid (toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_valid ), //i + .io_inputs_1_aw_ready (axi4WriteOnlyArbiter_4_io_inputs_1_aw_ready ), //o + .io_inputs_1_aw_payload_addr (toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_addr[31:0]), //i + .io_inputs_1_aw_payload_id (toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_id[3:0] ), //i + .io_inputs_1_aw_payload_len (toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_len[7:0] ), //i + .io_inputs_1_aw_payload_size (toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_size[2:0] ), //i + .io_inputs_1_aw_payload_burst (toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_burst[1:0]), //i + .io_inputs_1_aw_payload_lock (toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_lock ), //i + .io_inputs_1_aw_payload_cache (toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_cache[3:0]), //i + .io_inputs_1_aw_payload_prot (toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_prot[2:0] ), //i + .io_inputs_1_w_valid (axiIn_1_writeOnly_decoder_io_outputs_0_w_valid ), //i + .io_inputs_1_w_ready (axi4WriteOnlyArbiter_4_io_inputs_1_w_ready ), //o + .io_inputs_1_w_payload_data (axiIn_1_writeOnly_decoder_io_outputs_0_w_payload_data[31:0] ), //i + .io_inputs_1_w_payload_strb (axiIn_1_writeOnly_decoder_io_outputs_0_w_payload_strb[3:0] ), //i + .io_inputs_1_w_payload_last (axiIn_1_writeOnly_decoder_io_outputs_0_w_payload_last ), //i + .io_inputs_1_b_valid (axi4WriteOnlyArbiter_4_io_inputs_1_b_valid ), //o + .io_inputs_1_b_ready (axiIn_1_writeOnly_decoder_io_outputs_0_b_ready ), //i + .io_inputs_1_b_payload_id (axi4WriteOnlyArbiter_4_io_inputs_1_b_payload_id[3:0] ), //o + .io_inputs_1_b_payload_resp (axi4WriteOnlyArbiter_4_io_inputs_1_b_payload_resp[1:0] ), //o + .io_output_aw_valid (axi4WriteOnlyArbiter_4_io_output_aw_valid ), //o + .io_output_aw_ready (axiOut_0_awready ), //i + .io_output_aw_payload_addr (axi4WriteOnlyArbiter_4_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_id (axi4WriteOnlyArbiter_4_io_output_aw_payload_id[4:0] ), //o + .io_output_aw_payload_len (axi4WriteOnlyArbiter_4_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (axi4WriteOnlyArbiter_4_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_burst (axi4WriteOnlyArbiter_4_io_output_aw_payload_burst[1:0] ), //o + .io_output_aw_payload_lock (axi4WriteOnlyArbiter_4_io_output_aw_payload_lock ), //o + .io_output_aw_payload_cache (axi4WriteOnlyArbiter_4_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_prot (axi4WriteOnlyArbiter_4_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (axi4WriteOnlyArbiter_4_io_output_w_valid ), //o + .io_output_w_ready (axiOut_0_wready ), //i + .io_output_w_payload_data (axi4WriteOnlyArbiter_4_io_output_w_payload_data[31:0] ), //o + .io_output_w_payload_strb (axi4WriteOnlyArbiter_4_io_output_w_payload_strb[3:0] ), //o + .io_output_w_payload_last (axi4WriteOnlyArbiter_4_io_output_w_payload_last ), //o + .io_output_b_valid (axiOut_0_bvalid ), //i + .io_output_b_ready (axi4WriteOnlyArbiter_4_io_output_b_ready ), //o + .io_output_b_payload_id (axiOut_0_bid[4:0] ), //i + .io_output_b_payload_resp (axiOut_0_bresp[1:0] ), //i + .clk (clk ), //i + .resetn (resetn ) //i + ); + Axi4ReadOnlyArbiter axi4ReadOnlyArbiter_5 ( + .io_inputs_0_ar_valid (toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_valid ), //i + .io_inputs_0_ar_ready (axi4ReadOnlyArbiter_5_io_inputs_0_ar_ready ), //o + .io_inputs_0_ar_payload_addr (toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_addr[31:0]), //i + .io_inputs_0_ar_payload_id (toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_id[3:0] ), //i + .io_inputs_0_ar_payload_len (toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_len[7:0] ), //i + .io_inputs_0_ar_payload_size (toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_size[2:0] ), //i + .io_inputs_0_ar_payload_burst (toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_burst[1:0]), //i + .io_inputs_0_ar_payload_lock (toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_lock ), //i + .io_inputs_0_ar_payload_cache (toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_cache[3:0]), //i + .io_inputs_0_ar_payload_prot (toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_prot[2:0] ), //i + .io_inputs_0_r_valid (axi4ReadOnlyArbiter_5_io_inputs_0_r_valid ), //o + .io_inputs_0_r_ready (axiIn_0_readOnly_decoder_io_outputs_1_r_ready ), //i + .io_inputs_0_r_payload_data (axi4ReadOnlyArbiter_5_io_inputs_0_r_payload_data[31:0] ), //o + .io_inputs_0_r_payload_id (axi4ReadOnlyArbiter_5_io_inputs_0_r_payload_id[3:0] ), //o + .io_inputs_0_r_payload_resp (axi4ReadOnlyArbiter_5_io_inputs_0_r_payload_resp[1:0] ), //o + .io_inputs_0_r_payload_last (axi4ReadOnlyArbiter_5_io_inputs_0_r_payload_last ), //o + .io_inputs_1_ar_valid (toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_valid ), //i + .io_inputs_1_ar_ready (axi4ReadOnlyArbiter_5_io_inputs_1_ar_ready ), //o + .io_inputs_1_ar_payload_addr (toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_addr[31:0]), //i + .io_inputs_1_ar_payload_id (toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_id[3:0] ), //i + .io_inputs_1_ar_payload_len (toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_len[7:0] ), //i + .io_inputs_1_ar_payload_size (toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_size[2:0] ), //i + .io_inputs_1_ar_payload_burst (toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_burst[1:0]), //i + .io_inputs_1_ar_payload_lock (toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_lock ), //i + .io_inputs_1_ar_payload_cache (toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_cache[3:0]), //i + .io_inputs_1_ar_payload_prot (toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_prot[2:0] ), //i + .io_inputs_1_r_valid (axi4ReadOnlyArbiter_5_io_inputs_1_r_valid ), //o + .io_inputs_1_r_ready (axiIn_1_readOnly_decoder_io_outputs_1_r_ready ), //i + .io_inputs_1_r_payload_data (axi4ReadOnlyArbiter_5_io_inputs_1_r_payload_data[31:0] ), //o + .io_inputs_1_r_payload_id (axi4ReadOnlyArbiter_5_io_inputs_1_r_payload_id[3:0] ), //o + .io_inputs_1_r_payload_resp (axi4ReadOnlyArbiter_5_io_inputs_1_r_payload_resp[1:0] ), //o + .io_inputs_1_r_payload_last (axi4ReadOnlyArbiter_5_io_inputs_1_r_payload_last ), //o + .io_output_ar_valid (axi4ReadOnlyArbiter_5_io_output_ar_valid ), //o + .io_output_ar_ready (axiOut_1_arready ), //i + .io_output_ar_payload_addr (axi4ReadOnlyArbiter_5_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_id (axi4ReadOnlyArbiter_5_io_output_ar_payload_id[4:0] ), //o + .io_output_ar_payload_len (axi4ReadOnlyArbiter_5_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (axi4ReadOnlyArbiter_5_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_burst (axi4ReadOnlyArbiter_5_io_output_ar_payload_burst[1:0] ), //o + .io_output_ar_payload_lock (axi4ReadOnlyArbiter_5_io_output_ar_payload_lock ), //o + .io_output_ar_payload_cache (axi4ReadOnlyArbiter_5_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_prot (axi4ReadOnlyArbiter_5_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (axiOut_1_rvalid ), //i + .io_output_r_ready (axi4ReadOnlyArbiter_5_io_output_r_ready ), //o + .io_output_r_payload_data (axiOut_1_rdata[31:0] ), //i + .io_output_r_payload_id (axiOut_1_rid[4:0] ), //i + .io_output_r_payload_resp (axiOut_1_rresp[1:0] ), //i + .io_output_r_payload_last (axiOut_1_rlast ), //i + .clk (clk ), //i + .resetn (resetn ) //i + ); + Axi4WriteOnlyArbiter_1 axi4WriteOnlyArbiter_5 ( + .io_inputs_0_aw_valid (toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_valid ), //i + .io_inputs_0_aw_ready (axi4WriteOnlyArbiter_5_io_inputs_0_aw_ready ), //o + .io_inputs_0_aw_payload_addr (toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_addr[31:0]), //i + .io_inputs_0_aw_payload_id (toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_id[3:0] ), //i + .io_inputs_0_aw_payload_len (toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_len[7:0] ), //i + .io_inputs_0_aw_payload_size (toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_size[2:0] ), //i + .io_inputs_0_aw_payload_burst (toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_burst[1:0]), //i + .io_inputs_0_aw_payload_lock (toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_lock ), //i + .io_inputs_0_aw_payload_cache (toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_cache[3:0]), //i + .io_inputs_0_aw_payload_prot (toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_prot[2:0] ), //i + .io_inputs_0_w_valid (axiIn_0_writeOnly_decoder_io_outputs_1_w_valid ), //i + .io_inputs_0_w_ready (axi4WriteOnlyArbiter_5_io_inputs_0_w_ready ), //o + .io_inputs_0_w_payload_data (axiIn_0_writeOnly_decoder_io_outputs_1_w_payload_data[31:0] ), //i + .io_inputs_0_w_payload_strb (axiIn_0_writeOnly_decoder_io_outputs_1_w_payload_strb[3:0] ), //i + .io_inputs_0_w_payload_last (axiIn_0_writeOnly_decoder_io_outputs_1_w_payload_last ), //i + .io_inputs_0_b_valid (axi4WriteOnlyArbiter_5_io_inputs_0_b_valid ), //o + .io_inputs_0_b_ready (axiIn_0_writeOnly_decoder_io_outputs_1_b_ready ), //i + .io_inputs_0_b_payload_id (axi4WriteOnlyArbiter_5_io_inputs_0_b_payload_id[3:0] ), //o + .io_inputs_0_b_payload_resp (axi4WriteOnlyArbiter_5_io_inputs_0_b_payload_resp[1:0] ), //o + .io_inputs_1_aw_valid (toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_valid ), //i + .io_inputs_1_aw_ready (axi4WriteOnlyArbiter_5_io_inputs_1_aw_ready ), //o + .io_inputs_1_aw_payload_addr (toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_addr[31:0]), //i + .io_inputs_1_aw_payload_id (toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_id[3:0] ), //i + .io_inputs_1_aw_payload_len (toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_len[7:0] ), //i + .io_inputs_1_aw_payload_size (toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_size[2:0] ), //i + .io_inputs_1_aw_payload_burst (toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_burst[1:0]), //i + .io_inputs_1_aw_payload_lock (toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_lock ), //i + .io_inputs_1_aw_payload_cache (toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_cache[3:0]), //i + .io_inputs_1_aw_payload_prot (toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_prot[2:0] ), //i + .io_inputs_1_w_valid (axiIn_1_writeOnly_decoder_io_outputs_1_w_valid ), //i + .io_inputs_1_w_ready (axi4WriteOnlyArbiter_5_io_inputs_1_w_ready ), //o + .io_inputs_1_w_payload_data (axiIn_1_writeOnly_decoder_io_outputs_1_w_payload_data[31:0] ), //i + .io_inputs_1_w_payload_strb (axiIn_1_writeOnly_decoder_io_outputs_1_w_payload_strb[3:0] ), //i + .io_inputs_1_w_payload_last (axiIn_1_writeOnly_decoder_io_outputs_1_w_payload_last ), //i + .io_inputs_1_b_valid (axi4WriteOnlyArbiter_5_io_inputs_1_b_valid ), //o + .io_inputs_1_b_ready (axiIn_1_writeOnly_decoder_io_outputs_1_b_ready ), //i + .io_inputs_1_b_payload_id (axi4WriteOnlyArbiter_5_io_inputs_1_b_payload_id[3:0] ), //o + .io_inputs_1_b_payload_resp (axi4WriteOnlyArbiter_5_io_inputs_1_b_payload_resp[1:0] ), //o + .io_output_aw_valid (axi4WriteOnlyArbiter_5_io_output_aw_valid ), //o + .io_output_aw_ready (axiOut_1_awready ), //i + .io_output_aw_payload_addr (axi4WriteOnlyArbiter_5_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_id (axi4WriteOnlyArbiter_5_io_output_aw_payload_id[4:0] ), //o + .io_output_aw_payload_len (axi4WriteOnlyArbiter_5_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (axi4WriteOnlyArbiter_5_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_burst (axi4WriteOnlyArbiter_5_io_output_aw_payload_burst[1:0] ), //o + .io_output_aw_payload_lock (axi4WriteOnlyArbiter_5_io_output_aw_payload_lock ), //o + .io_output_aw_payload_cache (axi4WriteOnlyArbiter_5_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_prot (axi4WriteOnlyArbiter_5_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (axi4WriteOnlyArbiter_5_io_output_w_valid ), //o + .io_output_w_ready (axiOut_1_wready ), //i + .io_output_w_payload_data (axi4WriteOnlyArbiter_5_io_output_w_payload_data[31:0] ), //o + .io_output_w_payload_strb (axi4WriteOnlyArbiter_5_io_output_w_payload_strb[3:0] ), //o + .io_output_w_payload_last (axi4WriteOnlyArbiter_5_io_output_w_payload_last ), //o + .io_output_b_valid (axiOut_1_bvalid ), //i + .io_output_b_ready (axi4WriteOnlyArbiter_5_io_output_b_ready ), //o + .io_output_b_payload_id (axiOut_1_bid[4:0] ), //i + .io_output_b_payload_resp (axiOut_1_bresp[1:0] ), //i + .clk (clk ), //i + .resetn (resetn ) //i + ); + Axi4ReadOnlyArbiter axi4ReadOnlyArbiter_6 ( + .io_inputs_0_ar_valid (toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_valid ), //i + .io_inputs_0_ar_ready (axi4ReadOnlyArbiter_6_io_inputs_0_ar_ready ), //o + .io_inputs_0_ar_payload_addr (toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_addr[31:0]), //i + .io_inputs_0_ar_payload_id (toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_id[3:0] ), //i + .io_inputs_0_ar_payload_len (toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_len[7:0] ), //i + .io_inputs_0_ar_payload_size (toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_size[2:0] ), //i + .io_inputs_0_ar_payload_burst (toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_burst[1:0]), //i + .io_inputs_0_ar_payload_lock (toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_lock ), //i + .io_inputs_0_ar_payload_cache (toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_cache[3:0]), //i + .io_inputs_0_ar_payload_prot (toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_prot[2:0] ), //i + .io_inputs_0_r_valid (axi4ReadOnlyArbiter_6_io_inputs_0_r_valid ), //o + .io_inputs_0_r_ready (axiIn_0_readOnly_decoder_io_outputs_6_r_ready ), //i + .io_inputs_0_r_payload_data (axi4ReadOnlyArbiter_6_io_inputs_0_r_payload_data[31:0] ), //o + .io_inputs_0_r_payload_id (axi4ReadOnlyArbiter_6_io_inputs_0_r_payload_id[3:0] ), //o + .io_inputs_0_r_payload_resp (axi4ReadOnlyArbiter_6_io_inputs_0_r_payload_resp[1:0] ), //o + .io_inputs_0_r_payload_last (axi4ReadOnlyArbiter_6_io_inputs_0_r_payload_last ), //o + .io_inputs_1_ar_valid (toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_valid ), //i + .io_inputs_1_ar_ready (axi4ReadOnlyArbiter_6_io_inputs_1_ar_ready ), //o + .io_inputs_1_ar_payload_addr (toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_addr[31:0]), //i + .io_inputs_1_ar_payload_id (toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_id[3:0] ), //i + .io_inputs_1_ar_payload_len (toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_len[7:0] ), //i + .io_inputs_1_ar_payload_size (toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_size[2:0] ), //i + .io_inputs_1_ar_payload_burst (toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_burst[1:0]), //i + .io_inputs_1_ar_payload_lock (toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_lock ), //i + .io_inputs_1_ar_payload_cache (toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_cache[3:0]), //i + .io_inputs_1_ar_payload_prot (toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_prot[2:0] ), //i + .io_inputs_1_r_valid (axi4ReadOnlyArbiter_6_io_inputs_1_r_valid ), //o + .io_inputs_1_r_ready (axiIn_1_readOnly_decoder_io_outputs_2_r_ready ), //i + .io_inputs_1_r_payload_data (axi4ReadOnlyArbiter_6_io_inputs_1_r_payload_data[31:0] ), //o + .io_inputs_1_r_payload_id (axi4ReadOnlyArbiter_6_io_inputs_1_r_payload_id[3:0] ), //o + .io_inputs_1_r_payload_resp (axi4ReadOnlyArbiter_6_io_inputs_1_r_payload_resp[1:0] ), //o + .io_inputs_1_r_payload_last (axi4ReadOnlyArbiter_6_io_inputs_1_r_payload_last ), //o + .io_output_ar_valid (axi4ReadOnlyArbiter_6_io_output_ar_valid ), //o + .io_output_ar_ready (axiOut_6_arready ), //i + .io_output_ar_payload_addr (axi4ReadOnlyArbiter_6_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_id (axi4ReadOnlyArbiter_6_io_output_ar_payload_id[4:0] ), //o + .io_output_ar_payload_len (axi4ReadOnlyArbiter_6_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (axi4ReadOnlyArbiter_6_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_burst (axi4ReadOnlyArbiter_6_io_output_ar_payload_burst[1:0] ), //o + .io_output_ar_payload_lock (axi4ReadOnlyArbiter_6_io_output_ar_payload_lock ), //o + .io_output_ar_payload_cache (axi4ReadOnlyArbiter_6_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_prot (axi4ReadOnlyArbiter_6_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (axiOut_6_rvalid ), //i + .io_output_r_ready (axi4ReadOnlyArbiter_6_io_output_r_ready ), //o + .io_output_r_payload_data (axiOut_6_rdata[31:0] ), //i + .io_output_r_payload_id (axiOut_6_rid[4:0] ), //i + .io_output_r_payload_resp (axiOut_6_rresp[1:0] ), //i + .io_output_r_payload_last (axiOut_6_rlast ), //i + .clk (clk ), //i + .resetn (resetn ) //i + ); + Axi4WriteOnlyArbiter_2 axi4WriteOnlyArbiter_6 ( + .io_inputs_0_aw_valid (toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_valid ), //i + .io_inputs_0_aw_ready (axi4WriteOnlyArbiter_6_io_inputs_0_aw_ready ), //o + .io_inputs_0_aw_payload_addr (toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_addr[31:0]), //i + .io_inputs_0_aw_payload_id (toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_id[3:0] ), //i + .io_inputs_0_aw_payload_len (toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_len[7:0] ), //i + .io_inputs_0_aw_payload_size (toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_size[2:0] ), //i + .io_inputs_0_aw_payload_burst (toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_burst[1:0]), //i + .io_inputs_0_aw_payload_lock (toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_lock ), //i + .io_inputs_0_aw_payload_cache (toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_cache[3:0]), //i + .io_inputs_0_aw_payload_prot (toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_prot[2:0] ), //i + .io_inputs_0_w_valid (axiIn_0_writeOnly_decoder_io_outputs_6_w_valid ), //i + .io_inputs_0_w_ready (axi4WriteOnlyArbiter_6_io_inputs_0_w_ready ), //o + .io_inputs_0_w_payload_data (axiIn_0_writeOnly_decoder_io_outputs_6_w_payload_data[31:0] ), //i + .io_inputs_0_w_payload_strb (axiIn_0_writeOnly_decoder_io_outputs_6_w_payload_strb[3:0] ), //i + .io_inputs_0_w_payload_last (axiIn_0_writeOnly_decoder_io_outputs_6_w_payload_last ), //i + .io_inputs_0_b_valid (axi4WriteOnlyArbiter_6_io_inputs_0_b_valid ), //o + .io_inputs_0_b_ready (axiIn_0_writeOnly_decoder_io_outputs_6_b_ready ), //i + .io_inputs_0_b_payload_id (axi4WriteOnlyArbiter_6_io_inputs_0_b_payload_id[3:0] ), //o + .io_inputs_0_b_payload_resp (axi4WriteOnlyArbiter_6_io_inputs_0_b_payload_resp[1:0] ), //o + .io_inputs_1_aw_valid (toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_valid ), //i + .io_inputs_1_aw_ready (axi4WriteOnlyArbiter_6_io_inputs_1_aw_ready ), //o + .io_inputs_1_aw_payload_addr (toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_addr[31:0]), //i + .io_inputs_1_aw_payload_id (toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_id[3:0] ), //i + .io_inputs_1_aw_payload_len (toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_len[7:0] ), //i + .io_inputs_1_aw_payload_size (toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_size[2:0] ), //i + .io_inputs_1_aw_payload_burst (toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_burst[1:0]), //i + .io_inputs_1_aw_payload_lock (toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_lock ), //i + .io_inputs_1_aw_payload_cache (toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_cache[3:0]), //i + .io_inputs_1_aw_payload_prot (toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_prot[2:0] ), //i + .io_inputs_1_w_valid (axiIn_1_writeOnly_decoder_io_outputs_2_w_valid ), //i + .io_inputs_1_w_ready (axi4WriteOnlyArbiter_6_io_inputs_1_w_ready ), //o + .io_inputs_1_w_payload_data (axiIn_1_writeOnly_decoder_io_outputs_2_w_payload_data[31:0] ), //i + .io_inputs_1_w_payload_strb (axiIn_1_writeOnly_decoder_io_outputs_2_w_payload_strb[3:0] ), //i + .io_inputs_1_w_payload_last (axiIn_1_writeOnly_decoder_io_outputs_2_w_payload_last ), //i + .io_inputs_1_b_valid (axi4WriteOnlyArbiter_6_io_inputs_1_b_valid ), //o + .io_inputs_1_b_ready (axiIn_1_writeOnly_decoder_io_outputs_2_b_ready ), //i + .io_inputs_1_b_payload_id (axi4WriteOnlyArbiter_6_io_inputs_1_b_payload_id[3:0] ), //o + .io_inputs_1_b_payload_resp (axi4WriteOnlyArbiter_6_io_inputs_1_b_payload_resp[1:0] ), //o + .io_output_aw_valid (axi4WriteOnlyArbiter_6_io_output_aw_valid ), //o + .io_output_aw_ready (axiOut_6_awready ), //i + .io_output_aw_payload_addr (axi4WriteOnlyArbiter_6_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_id (axi4WriteOnlyArbiter_6_io_output_aw_payload_id[4:0] ), //o + .io_output_aw_payload_len (axi4WriteOnlyArbiter_6_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (axi4WriteOnlyArbiter_6_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_burst (axi4WriteOnlyArbiter_6_io_output_aw_payload_burst[1:0] ), //o + .io_output_aw_payload_lock (axi4WriteOnlyArbiter_6_io_output_aw_payload_lock ), //o + .io_output_aw_payload_cache (axi4WriteOnlyArbiter_6_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_prot (axi4WriteOnlyArbiter_6_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (axi4WriteOnlyArbiter_6_io_output_w_valid ), //o + .io_output_w_ready (axiOut_6_wready ), //i + .io_output_w_payload_data (axi4WriteOnlyArbiter_6_io_output_w_payload_data[31:0] ), //o + .io_output_w_payload_strb (axi4WriteOnlyArbiter_6_io_output_w_payload_strb[3:0] ), //o + .io_output_w_payload_last (axi4WriteOnlyArbiter_6_io_output_w_payload_last ), //o + .io_output_b_valid (axiOut_6_bvalid ), //i + .io_output_b_ready (axi4WriteOnlyArbiter_6_io_output_b_ready ), //o + .io_output_b_payload_id (axiOut_6_bid[4:0] ), //i + .io_output_b_payload_resp (axiOut_6_bresp[1:0] ), //i + .clk (clk ), //i + .resetn (resetn ) //i + ); + Axi4ReadOnlyArbiter axi4ReadOnlyArbiter_7 ( + .io_inputs_0_ar_valid (toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_valid ), //i + .io_inputs_0_ar_ready (axi4ReadOnlyArbiter_7_io_inputs_0_ar_ready ), //o + .io_inputs_0_ar_payload_addr (toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_addr[31:0]), //i + .io_inputs_0_ar_payload_id (toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_id[3:0] ), //i + .io_inputs_0_ar_payload_len (toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_len[7:0] ), //i + .io_inputs_0_ar_payload_size (toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_size[2:0] ), //i + .io_inputs_0_ar_payload_burst (toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_burst[1:0]), //i + .io_inputs_0_ar_payload_lock (toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_lock ), //i + .io_inputs_0_ar_payload_cache (toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_cache[3:0]), //i + .io_inputs_0_ar_payload_prot (toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_prot[2:0] ), //i + .io_inputs_0_r_valid (axi4ReadOnlyArbiter_7_io_inputs_0_r_valid ), //o + .io_inputs_0_r_ready (axiIn_0_readOnly_decoder_io_outputs_7_r_ready ), //i + .io_inputs_0_r_payload_data (axi4ReadOnlyArbiter_7_io_inputs_0_r_payload_data[31:0] ), //o + .io_inputs_0_r_payload_id (axi4ReadOnlyArbiter_7_io_inputs_0_r_payload_id[3:0] ), //o + .io_inputs_0_r_payload_resp (axi4ReadOnlyArbiter_7_io_inputs_0_r_payload_resp[1:0] ), //o + .io_inputs_0_r_payload_last (axi4ReadOnlyArbiter_7_io_inputs_0_r_payload_last ), //o + .io_inputs_1_ar_valid (toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_valid ), //i + .io_inputs_1_ar_ready (axi4ReadOnlyArbiter_7_io_inputs_1_ar_ready ), //o + .io_inputs_1_ar_payload_addr (toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_addr[31:0]), //i + .io_inputs_1_ar_payload_id (toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_id[3:0] ), //i + .io_inputs_1_ar_payload_len (toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_len[7:0] ), //i + .io_inputs_1_ar_payload_size (toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_size[2:0] ), //i + .io_inputs_1_ar_payload_burst (toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_burst[1:0]), //i + .io_inputs_1_ar_payload_lock (toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_lock ), //i + .io_inputs_1_ar_payload_cache (toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_cache[3:0]), //i + .io_inputs_1_ar_payload_prot (toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_prot[2:0] ), //i + .io_inputs_1_r_valid (axi4ReadOnlyArbiter_7_io_inputs_1_r_valid ), //o + .io_inputs_1_r_ready (axiIn_1_readOnly_decoder_io_outputs_3_r_ready ), //i + .io_inputs_1_r_payload_data (axi4ReadOnlyArbiter_7_io_inputs_1_r_payload_data[31:0] ), //o + .io_inputs_1_r_payload_id (axi4ReadOnlyArbiter_7_io_inputs_1_r_payload_id[3:0] ), //o + .io_inputs_1_r_payload_resp (axi4ReadOnlyArbiter_7_io_inputs_1_r_payload_resp[1:0] ), //o + .io_inputs_1_r_payload_last (axi4ReadOnlyArbiter_7_io_inputs_1_r_payload_last ), //o + .io_output_ar_valid (axi4ReadOnlyArbiter_7_io_output_ar_valid ), //o + .io_output_ar_ready (axiOut_7_arready ), //i + .io_output_ar_payload_addr (axi4ReadOnlyArbiter_7_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_id (axi4ReadOnlyArbiter_7_io_output_ar_payload_id[4:0] ), //o + .io_output_ar_payload_len (axi4ReadOnlyArbiter_7_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (axi4ReadOnlyArbiter_7_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_burst (axi4ReadOnlyArbiter_7_io_output_ar_payload_burst[1:0] ), //o + .io_output_ar_payload_lock (axi4ReadOnlyArbiter_7_io_output_ar_payload_lock ), //o + .io_output_ar_payload_cache (axi4ReadOnlyArbiter_7_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_prot (axi4ReadOnlyArbiter_7_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (axiOut_7_rvalid ), //i + .io_output_r_ready (axi4ReadOnlyArbiter_7_io_output_r_ready ), //o + .io_output_r_payload_data (axiOut_7_rdata[31:0] ), //i + .io_output_r_payload_id (axiOut_7_rid[4:0] ), //i + .io_output_r_payload_resp (axiOut_7_rresp[1:0] ), //i + .io_output_r_payload_last (axiOut_7_rlast ), //i + .clk (clk ), //i + .resetn (resetn ) //i + ); + Axi4WriteOnlyArbiter_3 axi4WriteOnlyArbiter_7 ( + .io_inputs_0_aw_valid (toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_valid ), //i + .io_inputs_0_aw_ready (axi4WriteOnlyArbiter_7_io_inputs_0_aw_ready ), //o + .io_inputs_0_aw_payload_addr (toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_addr[31:0]), //i + .io_inputs_0_aw_payload_id (toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_id[3:0] ), //i + .io_inputs_0_aw_payload_len (toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_len[7:0] ), //i + .io_inputs_0_aw_payload_size (toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_size[2:0] ), //i + .io_inputs_0_aw_payload_burst (toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_burst[1:0]), //i + .io_inputs_0_aw_payload_lock (toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_lock ), //i + .io_inputs_0_aw_payload_cache (toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_cache[3:0]), //i + .io_inputs_0_aw_payload_prot (toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_prot[2:0] ), //i + .io_inputs_0_w_valid (axiIn_0_writeOnly_decoder_io_outputs_7_w_valid ), //i + .io_inputs_0_w_ready (axi4WriteOnlyArbiter_7_io_inputs_0_w_ready ), //o + .io_inputs_0_w_payload_data (axiIn_0_writeOnly_decoder_io_outputs_7_w_payload_data[31:0] ), //i + .io_inputs_0_w_payload_strb (axiIn_0_writeOnly_decoder_io_outputs_7_w_payload_strb[3:0] ), //i + .io_inputs_0_w_payload_last (axiIn_0_writeOnly_decoder_io_outputs_7_w_payload_last ), //i + .io_inputs_0_b_valid (axi4WriteOnlyArbiter_7_io_inputs_0_b_valid ), //o + .io_inputs_0_b_ready (axiIn_0_writeOnly_decoder_io_outputs_7_b_ready ), //i + .io_inputs_0_b_payload_id (axi4WriteOnlyArbiter_7_io_inputs_0_b_payload_id[3:0] ), //o + .io_inputs_0_b_payload_resp (axi4WriteOnlyArbiter_7_io_inputs_0_b_payload_resp[1:0] ), //o + .io_inputs_1_aw_valid (toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_valid ), //i + .io_inputs_1_aw_ready (axi4WriteOnlyArbiter_7_io_inputs_1_aw_ready ), //o + .io_inputs_1_aw_payload_addr (toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_addr[31:0]), //i + .io_inputs_1_aw_payload_id (toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_id[3:0] ), //i + .io_inputs_1_aw_payload_len (toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_len[7:0] ), //i + .io_inputs_1_aw_payload_size (toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_size[2:0] ), //i + .io_inputs_1_aw_payload_burst (toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_burst[1:0]), //i + .io_inputs_1_aw_payload_lock (toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_lock ), //i + .io_inputs_1_aw_payload_cache (toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_cache[3:0]), //i + .io_inputs_1_aw_payload_prot (toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_prot[2:0] ), //i + .io_inputs_1_w_valid (axiIn_1_writeOnly_decoder_io_outputs_3_w_valid ), //i + .io_inputs_1_w_ready (axi4WriteOnlyArbiter_7_io_inputs_1_w_ready ), //o + .io_inputs_1_w_payload_data (axiIn_1_writeOnly_decoder_io_outputs_3_w_payload_data[31:0] ), //i + .io_inputs_1_w_payload_strb (axiIn_1_writeOnly_decoder_io_outputs_3_w_payload_strb[3:0] ), //i + .io_inputs_1_w_payload_last (axiIn_1_writeOnly_decoder_io_outputs_3_w_payload_last ), //i + .io_inputs_1_b_valid (axi4WriteOnlyArbiter_7_io_inputs_1_b_valid ), //o + .io_inputs_1_b_ready (axiIn_1_writeOnly_decoder_io_outputs_3_b_ready ), //i + .io_inputs_1_b_payload_id (axi4WriteOnlyArbiter_7_io_inputs_1_b_payload_id[3:0] ), //o + .io_inputs_1_b_payload_resp (axi4WriteOnlyArbiter_7_io_inputs_1_b_payload_resp[1:0] ), //o + .io_output_aw_valid (axi4WriteOnlyArbiter_7_io_output_aw_valid ), //o + .io_output_aw_ready (axiOut_7_awready ), //i + .io_output_aw_payload_addr (axi4WriteOnlyArbiter_7_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_id (axi4WriteOnlyArbiter_7_io_output_aw_payload_id[4:0] ), //o + .io_output_aw_payload_len (axi4WriteOnlyArbiter_7_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (axi4WriteOnlyArbiter_7_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_burst (axi4WriteOnlyArbiter_7_io_output_aw_payload_burst[1:0] ), //o + .io_output_aw_payload_lock (axi4WriteOnlyArbiter_7_io_output_aw_payload_lock ), //o + .io_output_aw_payload_cache (axi4WriteOnlyArbiter_7_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_prot (axi4WriteOnlyArbiter_7_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (axi4WriteOnlyArbiter_7_io_output_w_valid ), //o + .io_output_w_ready (axiOut_7_wready ), //i + .io_output_w_payload_data (axi4WriteOnlyArbiter_7_io_output_w_payload_data[31:0] ), //o + .io_output_w_payload_strb (axi4WriteOnlyArbiter_7_io_output_w_payload_strb[3:0] ), //o + .io_output_w_payload_last (axi4WriteOnlyArbiter_7_io_output_w_payload_last ), //o + .io_output_b_valid (axiOut_7_bvalid ), //i + .io_output_b_ready (axi4WriteOnlyArbiter_7_io_output_b_ready ), //o + .io_output_b_payload_id (axiOut_7_bid[4:0] ), //i + .io_output_b_payload_resp (axiOut_7_bresp[1:0] ), //i + .clk (clk ), //i + .resetn (resetn ) //i + ); + assign axiOut_0_arvalid = axi4ReadOnlyArbiter_4_io_output_ar_valid; + assign axiOut_0_araddr = axi4ReadOnlyArbiter_4_io_output_ar_payload_addr; + assign axiOut_0_arid = axi4ReadOnlyArbiter_4_io_output_ar_payload_id; + assign axiOut_0_arlen = axi4ReadOnlyArbiter_4_io_output_ar_payload_len; + assign axiOut_0_arsize = axi4ReadOnlyArbiter_4_io_output_ar_payload_size; + assign axiOut_0_arburst = axi4ReadOnlyArbiter_4_io_output_ar_payload_burst; + assign axiOut_0_arlock = axi4ReadOnlyArbiter_4_io_output_ar_payload_lock; + assign axiOut_0_arcache = axi4ReadOnlyArbiter_4_io_output_ar_payload_cache; + assign axiOut_0_arprot = axi4ReadOnlyArbiter_4_io_output_ar_payload_prot; + assign axiOut_0_rready = axi4ReadOnlyArbiter_4_io_output_r_ready; + assign axiOut_0_awvalid = axi4WriteOnlyArbiter_4_io_output_aw_valid; + assign axiOut_0_awaddr = axi4WriteOnlyArbiter_4_io_output_aw_payload_addr; + assign axiOut_0_awid = axi4WriteOnlyArbiter_4_io_output_aw_payload_id; + assign axiOut_0_awlen = axi4WriteOnlyArbiter_4_io_output_aw_payload_len; + assign axiOut_0_awsize = axi4WriteOnlyArbiter_4_io_output_aw_payload_size; + assign axiOut_0_awburst = axi4WriteOnlyArbiter_4_io_output_aw_payload_burst; + assign axiOut_0_awlock = axi4WriteOnlyArbiter_4_io_output_aw_payload_lock; + assign axiOut_0_awcache = axi4WriteOnlyArbiter_4_io_output_aw_payload_cache; + assign axiOut_0_awprot = axi4WriteOnlyArbiter_4_io_output_aw_payload_prot; + assign axiOut_0_wvalid = axi4WriteOnlyArbiter_4_io_output_w_valid; + assign axiOut_0_wdata = axi4WriteOnlyArbiter_4_io_output_w_payload_data; + assign axiOut_0_wstrb = axi4WriteOnlyArbiter_4_io_output_w_payload_strb; + assign axiOut_0_wlast = axi4WriteOnlyArbiter_4_io_output_w_payload_last; + assign axiOut_0_bready = axi4WriteOnlyArbiter_4_io_output_b_ready; + assign axiOut_1_arvalid = axi4ReadOnlyArbiter_5_io_output_ar_valid; + assign axiOut_1_araddr = axi4ReadOnlyArbiter_5_io_output_ar_payload_addr; + assign axiOut_1_arid = axi4ReadOnlyArbiter_5_io_output_ar_payload_id; + assign axiOut_1_arlen = axi4ReadOnlyArbiter_5_io_output_ar_payload_len; + assign axiOut_1_arsize = axi4ReadOnlyArbiter_5_io_output_ar_payload_size; + assign axiOut_1_arburst = axi4ReadOnlyArbiter_5_io_output_ar_payload_burst; + assign axiOut_1_arlock = axi4ReadOnlyArbiter_5_io_output_ar_payload_lock; + assign axiOut_1_arcache = axi4ReadOnlyArbiter_5_io_output_ar_payload_cache; + assign axiOut_1_arprot = axi4ReadOnlyArbiter_5_io_output_ar_payload_prot; + assign axiOut_1_rready = axi4ReadOnlyArbiter_5_io_output_r_ready; + assign axiOut_1_awvalid = axi4WriteOnlyArbiter_5_io_output_aw_valid; + assign axiOut_1_awaddr = axi4WriteOnlyArbiter_5_io_output_aw_payload_addr; + assign axiOut_1_awid = axi4WriteOnlyArbiter_5_io_output_aw_payload_id; + assign axiOut_1_awlen = axi4WriteOnlyArbiter_5_io_output_aw_payload_len; + assign axiOut_1_awsize = axi4WriteOnlyArbiter_5_io_output_aw_payload_size; + assign axiOut_1_awburst = axi4WriteOnlyArbiter_5_io_output_aw_payload_burst; + assign axiOut_1_awlock = axi4WriteOnlyArbiter_5_io_output_aw_payload_lock; + assign axiOut_1_awcache = axi4WriteOnlyArbiter_5_io_output_aw_payload_cache; + assign axiOut_1_awprot = axi4WriteOnlyArbiter_5_io_output_aw_payload_prot; + assign axiOut_1_wvalid = axi4WriteOnlyArbiter_5_io_output_w_valid; + assign axiOut_1_wdata = axi4WriteOnlyArbiter_5_io_output_w_payload_data; + assign axiOut_1_wstrb = axi4WriteOnlyArbiter_5_io_output_w_payload_strb; + assign axiOut_1_wlast = axi4WriteOnlyArbiter_5_io_output_w_payload_last; + assign axiOut_1_bready = axi4WriteOnlyArbiter_5_io_output_b_ready; + assign axiOut_2_arvalid = toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_valid; + assign axiOut_2_araddr = toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_addr; + assign axiOut_2_arid = {1'd0, toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_id}; + assign axiOut_2_arlen = toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_len; + assign axiOut_2_arsize = toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_size; + assign axiOut_2_arburst = toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_burst; + assign axiOut_2_arlock = toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_lock; + assign axiOut_2_arcache = toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_cache; + assign axiOut_2_arprot = toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_prot; + assign axiOut_2_rready = axiIn_0_readOnly_decoder_io_outputs_2_r_ready; + assign axiOut_2_awvalid = toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_valid; + assign axiOut_2_awaddr = toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_addr; + assign axiOut_2_awid = {1'd0, toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_id}; + assign axiOut_2_awlen = toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_len; + assign axiOut_2_awsize = toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_size; + assign axiOut_2_awburst = toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_burst; + assign axiOut_2_awlock = toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_lock; + assign axiOut_2_awcache = toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_cache; + assign axiOut_2_awprot = toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_prot; + assign axiOut_2_wvalid = axiIn_0_writeOnly_decoder_io_outputs_2_w_valid; + assign axiOut_2_wdata = axiIn_0_writeOnly_decoder_io_outputs_2_w_payload_data; + assign axiOut_2_wstrb = axiIn_0_writeOnly_decoder_io_outputs_2_w_payload_strb; + assign axiOut_2_wlast = axiIn_0_writeOnly_decoder_io_outputs_2_w_payload_last; + assign axiOut_2_bready = axiIn_0_writeOnly_decoder_io_outputs_2_b_ready; + assign axiOut_3_arvalid = toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_valid; + assign axiOut_3_araddr = toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_addr; + assign axiOut_3_arid = {1'd0, toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_id}; + assign axiOut_3_arlen = toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_len; + assign axiOut_3_arsize = toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_size; + assign axiOut_3_arburst = toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_burst; + assign axiOut_3_arlock = toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_lock; + assign axiOut_3_arcache = toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_cache; + assign axiOut_3_arprot = toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_prot; + assign axiOut_3_rready = axiIn_0_readOnly_decoder_io_outputs_3_r_ready; + assign axiOut_3_awvalid = toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_valid; + assign axiOut_3_awaddr = toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_addr; + assign axiOut_3_awid = {1'd0, toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_id}; + assign axiOut_3_awlen = toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_len; + assign axiOut_3_awsize = toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_size; + assign axiOut_3_awburst = toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_burst; + assign axiOut_3_awlock = toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_lock; + assign axiOut_3_awcache = toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_cache; + assign axiOut_3_awprot = toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_prot; + assign axiOut_3_wvalid = axiIn_0_writeOnly_decoder_io_outputs_3_w_valid; + assign axiOut_3_wdata = axiIn_0_writeOnly_decoder_io_outputs_3_w_payload_data; + assign axiOut_3_wstrb = axiIn_0_writeOnly_decoder_io_outputs_3_w_payload_strb; + assign axiOut_3_wlast = axiIn_0_writeOnly_decoder_io_outputs_3_w_payload_last; + assign axiOut_3_bready = axiIn_0_writeOnly_decoder_io_outputs_3_b_ready; + assign axiOut_4_arvalid = toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_valid; + assign axiOut_4_araddr = toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_addr; + assign axiOut_4_arid = {1'd0, toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_id}; + assign axiOut_4_arlen = toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_len; + assign axiOut_4_arsize = toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_size; + assign axiOut_4_arburst = toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_burst; + assign axiOut_4_arlock = toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_lock; + assign axiOut_4_arcache = toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_cache; + assign axiOut_4_arprot = toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_prot; + assign axiOut_4_rready = axiIn_0_readOnly_decoder_io_outputs_4_r_ready; + assign axiOut_4_awvalid = toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_valid; + assign axiOut_4_awaddr = toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_addr; + assign axiOut_4_awid = {1'd0, toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_id}; + assign axiOut_4_awlen = toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_len; + assign axiOut_4_awsize = toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_size; + assign axiOut_4_awburst = toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_burst; + assign axiOut_4_awlock = toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_lock; + assign axiOut_4_awcache = toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_cache; + assign axiOut_4_awprot = toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_prot; + assign axiOut_4_wvalid = axiIn_0_writeOnly_decoder_io_outputs_4_w_valid; + assign axiOut_4_wdata = axiIn_0_writeOnly_decoder_io_outputs_4_w_payload_data; + assign axiOut_4_wstrb = axiIn_0_writeOnly_decoder_io_outputs_4_w_payload_strb; + assign axiOut_4_wlast = axiIn_0_writeOnly_decoder_io_outputs_4_w_payload_last; + assign axiOut_4_bready = axiIn_0_writeOnly_decoder_io_outputs_4_b_ready; + assign axiOut_5_arvalid = toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_valid; + assign axiOut_5_araddr = toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_addr; + assign axiOut_5_arid = {1'd0, toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_id}; + assign axiOut_5_arlen = toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_len; + assign axiOut_5_arsize = toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_size; + assign axiOut_5_arburst = toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_burst; + assign axiOut_5_arlock = toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_lock; + assign axiOut_5_arcache = toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_cache; + assign axiOut_5_arprot = toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_prot; + assign axiOut_5_rready = axiIn_0_readOnly_decoder_io_outputs_5_r_ready; + assign axiOut_5_awvalid = toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_valid; + assign axiOut_5_awaddr = toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_addr; + assign axiOut_5_awid = {1'd0, toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_id}; + assign axiOut_5_awlen = toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_len; + assign axiOut_5_awsize = toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_size; + assign axiOut_5_awburst = toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_burst; + assign axiOut_5_awlock = toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_lock; + assign axiOut_5_awcache = toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_cache; + assign axiOut_5_awprot = toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_prot; + assign axiOut_5_wvalid = axiIn_0_writeOnly_decoder_io_outputs_5_w_valid; + assign axiOut_5_wdata = axiIn_0_writeOnly_decoder_io_outputs_5_w_payload_data; + assign axiOut_5_wstrb = axiIn_0_writeOnly_decoder_io_outputs_5_w_payload_strb; + assign axiOut_5_wlast = axiIn_0_writeOnly_decoder_io_outputs_5_w_payload_last; + assign axiOut_5_bready = axiIn_0_writeOnly_decoder_io_outputs_5_b_ready; + assign axiOut_6_arvalid = axi4ReadOnlyArbiter_6_io_output_ar_valid; + assign axiOut_6_araddr = axi4ReadOnlyArbiter_6_io_output_ar_payload_addr; + assign axiOut_6_arid = axi4ReadOnlyArbiter_6_io_output_ar_payload_id; + assign axiOut_6_arlen = axi4ReadOnlyArbiter_6_io_output_ar_payload_len; + assign axiOut_6_arsize = axi4ReadOnlyArbiter_6_io_output_ar_payload_size; + assign axiOut_6_arburst = axi4ReadOnlyArbiter_6_io_output_ar_payload_burst; + assign axiOut_6_arlock = axi4ReadOnlyArbiter_6_io_output_ar_payload_lock; + assign axiOut_6_arcache = axi4ReadOnlyArbiter_6_io_output_ar_payload_cache; + assign axiOut_6_arprot = axi4ReadOnlyArbiter_6_io_output_ar_payload_prot; + assign axiOut_6_rready = axi4ReadOnlyArbiter_6_io_output_r_ready; + assign axiOut_6_awvalid = axi4WriteOnlyArbiter_6_io_output_aw_valid; + assign axiOut_6_awaddr = axi4WriteOnlyArbiter_6_io_output_aw_payload_addr; + assign axiOut_6_awid = axi4WriteOnlyArbiter_6_io_output_aw_payload_id; + assign axiOut_6_awlen = axi4WriteOnlyArbiter_6_io_output_aw_payload_len; + assign axiOut_6_awsize = axi4WriteOnlyArbiter_6_io_output_aw_payload_size; + assign axiOut_6_awburst = axi4WriteOnlyArbiter_6_io_output_aw_payload_burst; + assign axiOut_6_awlock = axi4WriteOnlyArbiter_6_io_output_aw_payload_lock; + assign axiOut_6_awcache = axi4WriteOnlyArbiter_6_io_output_aw_payload_cache; + assign axiOut_6_awprot = axi4WriteOnlyArbiter_6_io_output_aw_payload_prot; + assign axiOut_6_wvalid = axi4WriteOnlyArbiter_6_io_output_w_valid; + assign axiOut_6_wdata = axi4WriteOnlyArbiter_6_io_output_w_payload_data; + assign axiOut_6_wstrb = axi4WriteOnlyArbiter_6_io_output_w_payload_strb; + assign axiOut_6_wlast = axi4WriteOnlyArbiter_6_io_output_w_payload_last; + assign axiOut_6_bready = axi4WriteOnlyArbiter_6_io_output_b_ready; + assign axiOut_7_arvalid = axi4ReadOnlyArbiter_7_io_output_ar_valid; + assign axiOut_7_araddr = axi4ReadOnlyArbiter_7_io_output_ar_payload_addr; + assign axiOut_7_arid = axi4ReadOnlyArbiter_7_io_output_ar_payload_id; + assign axiOut_7_arlen = axi4ReadOnlyArbiter_7_io_output_ar_payload_len; + assign axiOut_7_arsize = axi4ReadOnlyArbiter_7_io_output_ar_payload_size; + assign axiOut_7_arburst = axi4ReadOnlyArbiter_7_io_output_ar_payload_burst; + assign axiOut_7_arlock = axi4ReadOnlyArbiter_7_io_output_ar_payload_lock; + assign axiOut_7_arcache = axi4ReadOnlyArbiter_7_io_output_ar_payload_cache; + assign axiOut_7_arprot = axi4ReadOnlyArbiter_7_io_output_ar_payload_prot; + assign axiOut_7_rready = axi4ReadOnlyArbiter_7_io_output_r_ready; + assign axiOut_7_awvalid = axi4WriteOnlyArbiter_7_io_output_aw_valid; + assign axiOut_7_awaddr = axi4WriteOnlyArbiter_7_io_output_aw_payload_addr; + assign axiOut_7_awid = axi4WriteOnlyArbiter_7_io_output_aw_payload_id; + assign axiOut_7_awlen = axi4WriteOnlyArbiter_7_io_output_aw_payload_len; + assign axiOut_7_awsize = axi4WriteOnlyArbiter_7_io_output_aw_payload_size; + assign axiOut_7_awburst = axi4WriteOnlyArbiter_7_io_output_aw_payload_burst; + assign axiOut_7_awlock = axi4WriteOnlyArbiter_7_io_output_aw_payload_lock; + assign axiOut_7_awcache = axi4WriteOnlyArbiter_7_io_output_aw_payload_cache; + assign axiOut_7_awprot = axi4WriteOnlyArbiter_7_io_output_aw_payload_prot; + assign axiOut_7_wvalid = axi4WriteOnlyArbiter_7_io_output_w_valid; + assign axiOut_7_wdata = axi4WriteOnlyArbiter_7_io_output_w_payload_data; + assign axiOut_7_wstrb = axi4WriteOnlyArbiter_7_io_output_w_payload_strb; + assign axiOut_7_wlast = axi4WriteOnlyArbiter_7_io_output_w_payload_last; + assign axiOut_7_bready = axi4WriteOnlyArbiter_7_io_output_b_ready; + assign axiIn_0_readOnly_ar_valid = axiIn_0_arvalid; + assign axiIn_0_arready = axiIn_0_readOnly_ar_ready; + assign axiIn_0_readOnly_ar_payload_addr = axiIn_0_araddr; + assign axiIn_0_readOnly_ar_payload_id = axiIn_0_arid; + assign axiIn_0_readOnly_ar_payload_len = axiIn_0_arlen; + assign axiIn_0_readOnly_ar_payload_size = axiIn_0_arsize; + assign axiIn_0_readOnly_ar_payload_burst = axiIn_0_arburst; + assign axiIn_0_readOnly_ar_payload_lock = axiIn_0_arlock; + assign axiIn_0_readOnly_ar_payload_cache = axiIn_0_arcache; + assign axiIn_0_readOnly_ar_payload_prot = axiIn_0_arprot; + assign axiIn_0_rvalid = axiIn_0_readOnly_r_valid; + assign axiIn_0_readOnly_r_ready = axiIn_0_rready; + assign axiIn_0_rdata = axiIn_0_readOnly_r_payload_data; + assign axiIn_0_rlast = axiIn_0_readOnly_r_payload_last; + assign axiIn_0_rid = axiIn_0_readOnly_r_payload_id; + assign axiIn_0_rresp = axiIn_0_readOnly_r_payload_resp; + assign axiIn_0_writeOnly_aw_valid = axiIn_0_awvalid; + assign axiIn_0_awready = axiIn_0_writeOnly_aw_ready; + assign axiIn_0_writeOnly_aw_payload_addr = axiIn_0_awaddr; + assign axiIn_0_writeOnly_aw_payload_id = axiIn_0_awid; + assign axiIn_0_writeOnly_aw_payload_len = axiIn_0_awlen; + assign axiIn_0_writeOnly_aw_payload_size = axiIn_0_awsize; + assign axiIn_0_writeOnly_aw_payload_burst = axiIn_0_awburst; + assign axiIn_0_writeOnly_aw_payload_lock = axiIn_0_awlock; + assign axiIn_0_writeOnly_aw_payload_cache = axiIn_0_awcache; + assign axiIn_0_writeOnly_aw_payload_prot = axiIn_0_awprot; + assign axiIn_0_writeOnly_w_valid = axiIn_0_wvalid; + assign axiIn_0_wready = axiIn_0_writeOnly_w_ready; + assign axiIn_0_writeOnly_w_payload_data = axiIn_0_wdata; + assign axiIn_0_writeOnly_w_payload_strb = axiIn_0_wstrb; + assign axiIn_0_writeOnly_w_payload_last = axiIn_0_wlast; + assign axiIn_0_bvalid = axiIn_0_writeOnly_b_valid; + assign axiIn_0_writeOnly_b_ready = axiIn_0_bready; + assign axiIn_0_bid = axiIn_0_writeOnly_b_payload_id; + assign axiIn_0_bresp = axiIn_0_writeOnly_b_payload_resp; + assign axiIn_1_readOnly_ar_valid = axiIn_1_arvalid; + assign axiIn_1_arready = axiIn_1_readOnly_ar_ready; + assign axiIn_1_readOnly_ar_payload_addr = axiIn_1_araddr; + assign axiIn_1_readOnly_ar_payload_id = axiIn_1_arid; + assign axiIn_1_readOnly_ar_payload_len = axiIn_1_arlen; + assign axiIn_1_readOnly_ar_payload_size = axiIn_1_arsize; + assign axiIn_1_readOnly_ar_payload_burst = axiIn_1_arburst; + assign axiIn_1_readOnly_ar_payload_lock = axiIn_1_arlock; + assign axiIn_1_readOnly_ar_payload_cache = axiIn_1_arcache; + assign axiIn_1_readOnly_ar_payload_prot = axiIn_1_arprot; + assign axiIn_1_rvalid = axiIn_1_readOnly_r_valid; + assign axiIn_1_readOnly_r_ready = axiIn_1_rready; + assign axiIn_1_rdata = axiIn_1_readOnly_r_payload_data; + assign axiIn_1_rlast = axiIn_1_readOnly_r_payload_last; + assign axiIn_1_rid = axiIn_1_readOnly_r_payload_id; + assign axiIn_1_rresp = axiIn_1_readOnly_r_payload_resp; + assign axiIn_1_writeOnly_aw_valid = axiIn_1_awvalid; + assign axiIn_1_awready = axiIn_1_writeOnly_aw_ready; + assign axiIn_1_writeOnly_aw_payload_addr = axiIn_1_awaddr; + assign axiIn_1_writeOnly_aw_payload_id = axiIn_1_awid; + assign axiIn_1_writeOnly_aw_payload_len = axiIn_1_awlen; + assign axiIn_1_writeOnly_aw_payload_size = axiIn_1_awsize; + assign axiIn_1_writeOnly_aw_payload_burst = axiIn_1_awburst; + assign axiIn_1_writeOnly_aw_payload_lock = axiIn_1_awlock; + assign axiIn_1_writeOnly_aw_payload_cache = axiIn_1_awcache; + assign axiIn_1_writeOnly_aw_payload_prot = axiIn_1_awprot; + assign axiIn_1_writeOnly_w_valid = axiIn_1_wvalid; + assign axiIn_1_wready = axiIn_1_writeOnly_w_ready; + assign axiIn_1_writeOnly_w_payload_data = axiIn_1_wdata; + assign axiIn_1_writeOnly_w_payload_strb = axiIn_1_wstrb; + assign axiIn_1_writeOnly_w_payload_last = axiIn_1_wlast; + assign axiIn_1_bvalid = axiIn_1_writeOnly_b_valid; + assign axiIn_1_writeOnly_b_ready = axiIn_1_bready; + assign axiIn_1_bid = axiIn_1_writeOnly_b_payload_id; + assign axiIn_1_bresp = axiIn_1_writeOnly_b_payload_resp; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_fire = (toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_valid && toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_ready); + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_valid = toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_rValid; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_addr = axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_addr; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_id = axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_id; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_len = axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_len; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_size = axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_size; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_burst = axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_burst; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_lock = axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_lock; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_cache = axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_cache; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_payload_prot = axiIn_0_readOnly_decoder_io_outputs_0_ar_payload_prot; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_ready = axi4ReadOnlyArbiter_4_io_inputs_0_ar_ready; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_fire = (toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_valid && toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_ready); + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_valid = toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_rValid; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_addr = axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_addr; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_id = axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_id; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_len = axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_len; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_size = axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_size; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_burst = axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_burst; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_lock = axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_lock; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_cache = axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_cache; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_payload_prot = axiIn_0_readOnly_decoder_io_outputs_1_ar_payload_prot; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_ready = axi4ReadOnlyArbiter_5_io_inputs_0_ar_ready; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_fire = (toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_valid && toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_ready); + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_valid = toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_rValid; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_addr = axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_addr; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_id = axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_id; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_len = axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_len; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_size = axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_size; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_burst = axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_burst; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_lock = axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_lock; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_cache = axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_cache; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_payload_prot = axiIn_0_readOnly_decoder_io_outputs_2_ar_payload_prot; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_ready = axiOut_2_arready; + assign axiIn_0_readOnly_decoder_io_outputs_2_r_payload_id = axiOut_2_rid[3:0]; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_fire = (toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_valid && toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_ready); + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_valid = toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_rValid; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_addr = axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_addr; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_id = axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_id; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_len = axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_len; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_size = axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_size; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_burst = axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_burst; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_lock = axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_lock; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_cache = axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_cache; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_payload_prot = axiIn_0_readOnly_decoder_io_outputs_3_ar_payload_prot; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_ready = axiOut_3_arready; + assign axiIn_0_readOnly_decoder_io_outputs_3_r_payload_id = axiOut_3_rid[3:0]; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_fire = (toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_valid && toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_ready); + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_valid = toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_rValid; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_addr = axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_addr; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_id = axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_id; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_len = axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_len; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_size = axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_size; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_burst = axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_burst; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_lock = axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_lock; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_cache = axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_cache; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_payload_prot = axiIn_0_readOnly_decoder_io_outputs_4_ar_payload_prot; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_ready = axiOut_4_arready; + assign axiIn_0_readOnly_decoder_io_outputs_4_r_payload_id = axiOut_4_rid[3:0]; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_fire = (toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_valid && toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_ready); + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_valid = toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_rValid; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_addr = axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_addr; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_id = axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_id; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_len = axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_len; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_size = axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_size; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_burst = axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_burst; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_lock = axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_lock; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_cache = axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_cache; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_payload_prot = axiIn_0_readOnly_decoder_io_outputs_5_ar_payload_prot; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_ready = axiOut_5_arready; + assign axiIn_0_readOnly_decoder_io_outputs_5_r_payload_id = axiOut_5_rid[3:0]; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_fire = (toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_valid && toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_ready); + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_valid = toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_rValid; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_addr = axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_addr; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_id = axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_id; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_len = axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_len; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_size = axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_size; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_burst = axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_burst; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_lock = axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_lock; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_cache = axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_cache; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_payload_prot = axiIn_0_readOnly_decoder_io_outputs_6_ar_payload_prot; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_ready = axi4ReadOnlyArbiter_6_io_inputs_0_ar_ready; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_fire = (toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_valid && toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_ready); + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_valid = toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_rValid; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_addr = axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_addr; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_id = axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_id; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_len = axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_len; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_size = axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_size; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_burst = axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_burst; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_lock = axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_lock; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_cache = axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_cache; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_payload_prot = axiIn_0_readOnly_decoder_io_outputs_7_ar_payload_prot; + assign toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_ready = axi4ReadOnlyArbiter_7_io_inputs_0_ar_ready; + assign axiIn_0_readOnly_ar_ready = axiIn_0_readOnly_decoder_io_input_ar_ready; + assign axiIn_0_readOnly_r_valid = axiIn_0_readOnly_decoder_io_input_r_valid; + assign axiIn_0_readOnly_r_payload_data = axiIn_0_readOnly_decoder_io_input_r_payload_data; + assign axiIn_0_readOnly_r_payload_last = axiIn_0_readOnly_decoder_io_input_r_payload_last; + assign axiIn_0_readOnly_r_payload_id = axiIn_0_readOnly_decoder_io_input_r_payload_id; + assign axiIn_0_readOnly_r_payload_resp = axiIn_0_readOnly_decoder_io_input_r_payload_resp; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_fire = (toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_valid && toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_ready); + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_valid = toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_rValid; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_addr = axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_addr; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_id = axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_id; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_len = axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_len; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_size = axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_size; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_burst = axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_burst; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_lock = axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_lock; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_cache = axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_cache; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_prot = axiIn_0_writeOnly_decoder_io_outputs_0_aw_payload_prot; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_ready = axi4WriteOnlyArbiter_4_io_inputs_0_aw_ready; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_fire = (toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_valid && toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_ready); + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_valid = toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_rValid; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_addr = axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_addr; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_id = axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_id; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_len = axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_len; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_size = axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_size; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_burst = axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_burst; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_lock = axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_lock; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_cache = axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_cache; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_prot = axiIn_0_writeOnly_decoder_io_outputs_1_aw_payload_prot; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_ready = axi4WriteOnlyArbiter_5_io_inputs_0_aw_ready; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_fire = (toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_valid && toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_ready); + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_valid = toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_rValid; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_addr = axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_addr; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_id = axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_id; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_len = axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_len; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_size = axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_size; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_burst = axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_burst; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_lock = axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_lock; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_cache = axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_cache; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_prot = axiIn_0_writeOnly_decoder_io_outputs_2_aw_payload_prot; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_ready = axiOut_2_awready; + assign axiIn_0_writeOnly_decoder_io_outputs_2_b_payload_id = axiOut_2_bid[3:0]; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_fire = (toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_valid && toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_ready); + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_valid = toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_rValid; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_addr = axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_addr; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_id = axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_id; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_len = axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_len; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_size = axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_size; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_burst = axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_burst; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_lock = axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_lock; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_cache = axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_cache; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_prot = axiIn_0_writeOnly_decoder_io_outputs_3_aw_payload_prot; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_ready = axiOut_3_awready; + assign axiIn_0_writeOnly_decoder_io_outputs_3_b_payload_id = axiOut_3_bid[3:0]; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_fire = (toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_valid && toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_ready); + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_valid = toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_rValid; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_addr = axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_addr; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_id = axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_id; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_len = axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_len; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_size = axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_size; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_burst = axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_burst; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_lock = axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_lock; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_cache = axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_cache; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_payload_prot = axiIn_0_writeOnly_decoder_io_outputs_4_aw_payload_prot; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_ready = axiOut_4_awready; + assign axiIn_0_writeOnly_decoder_io_outputs_4_b_payload_id = axiOut_4_bid[3:0]; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_fire = (toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_valid && toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_ready); + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_valid = toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_rValid; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_addr = axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_addr; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_id = axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_id; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_len = axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_len; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_size = axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_size; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_burst = axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_burst; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_lock = axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_lock; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_cache = axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_cache; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_payload_prot = axiIn_0_writeOnly_decoder_io_outputs_5_aw_payload_prot; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_ready = axiOut_5_awready; + assign axiIn_0_writeOnly_decoder_io_outputs_5_b_payload_id = axiOut_5_bid[3:0]; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_fire = (toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_valid && toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_ready); + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_valid = toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_rValid; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_addr = axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_addr; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_id = axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_id; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_len = axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_len; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_size = axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_size; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_burst = axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_burst; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_lock = axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_lock; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_cache = axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_cache; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_payload_prot = axiIn_0_writeOnly_decoder_io_outputs_6_aw_payload_prot; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_ready = axi4WriteOnlyArbiter_6_io_inputs_0_aw_ready; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_fire = (toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_valid && toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_ready); + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_valid = toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_rValid; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_addr = axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_addr; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_id = axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_id; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_len = axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_len; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_size = axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_size; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_burst = axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_burst; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_lock = axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_lock; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_cache = axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_cache; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_payload_prot = axiIn_0_writeOnly_decoder_io_outputs_7_aw_payload_prot; + assign toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_ready = axi4WriteOnlyArbiter_7_io_inputs_0_aw_ready; + assign axiIn_0_writeOnly_aw_ready = axiIn_0_writeOnly_decoder_io_input_aw_ready; + assign axiIn_0_writeOnly_w_ready = axiIn_0_writeOnly_decoder_io_input_w_ready; + assign axiIn_0_writeOnly_b_valid = axiIn_0_writeOnly_decoder_io_input_b_valid; + assign axiIn_0_writeOnly_b_payload_id = axiIn_0_writeOnly_decoder_io_input_b_payload_id; + assign axiIn_0_writeOnly_b_payload_resp = axiIn_0_writeOnly_decoder_io_input_b_payload_resp; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_fire = (toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_valid && toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_ready); + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_valid = toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_rValid; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_addr = axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_addr; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_id = axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_id; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_len = axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_len; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_size = axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_size; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_burst = axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_burst; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_lock = axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_lock; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_cache = axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_cache; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_payload_prot = axiIn_1_readOnly_decoder_io_outputs_0_ar_payload_prot; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_ready = axi4ReadOnlyArbiter_4_io_inputs_1_ar_ready; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_fire = (toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_valid && toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_ready); + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_valid = toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_rValid; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_addr = axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_addr; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_id = axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_id; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_len = axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_len; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_size = axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_size; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_burst = axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_burst; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_lock = axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_lock; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_cache = axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_cache; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_payload_prot = axiIn_1_readOnly_decoder_io_outputs_1_ar_payload_prot; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_ready = axi4ReadOnlyArbiter_5_io_inputs_1_ar_ready; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_fire = (toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_valid && toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_ready); + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_valid = toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_rValid; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_addr = axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_addr; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_id = axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_id; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_len = axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_len; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_size = axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_size; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_burst = axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_burst; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_lock = axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_lock; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_cache = axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_cache; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_payload_prot = axiIn_1_readOnly_decoder_io_outputs_2_ar_payload_prot; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_ready = axi4ReadOnlyArbiter_6_io_inputs_1_ar_ready; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_fire = (toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_valid && toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_ready); + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_valid = toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_rValid; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_addr = axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_addr; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_id = axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_id; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_len = axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_len; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_size = axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_size; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_burst = axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_burst; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_lock = axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_lock; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_cache = axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_cache; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_payload_prot = axiIn_1_readOnly_decoder_io_outputs_3_ar_payload_prot; + assign toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_ready = axi4ReadOnlyArbiter_7_io_inputs_1_ar_ready; + assign axiIn_1_readOnly_ar_ready = axiIn_1_readOnly_decoder_io_input_ar_ready; + assign axiIn_1_readOnly_r_valid = axiIn_1_readOnly_decoder_io_input_r_valid; + assign axiIn_1_readOnly_r_payload_data = axiIn_1_readOnly_decoder_io_input_r_payload_data; + assign axiIn_1_readOnly_r_payload_last = axiIn_1_readOnly_decoder_io_input_r_payload_last; + assign axiIn_1_readOnly_r_payload_id = axiIn_1_readOnly_decoder_io_input_r_payload_id; + assign axiIn_1_readOnly_r_payload_resp = axiIn_1_readOnly_decoder_io_input_r_payload_resp; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_fire = (toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_valid && toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_ready); + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_valid = toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_rValid; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_addr = axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_addr; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_id = axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_id; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_len = axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_len; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_size = axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_size; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_burst = axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_burst; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_lock = axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_lock; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_cache = axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_cache; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_payload_prot = axiIn_1_writeOnly_decoder_io_outputs_0_aw_payload_prot; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_ready = axi4WriteOnlyArbiter_4_io_inputs_1_aw_ready; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_fire = (toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_valid && toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_ready); + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_valid = toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_rValid; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_addr = axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_addr; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_id = axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_id; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_len = axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_len; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_size = axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_size; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_burst = axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_burst; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_lock = axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_lock; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_cache = axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_cache; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_payload_prot = axiIn_1_writeOnly_decoder_io_outputs_1_aw_payload_prot; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_ready = axi4WriteOnlyArbiter_5_io_inputs_1_aw_ready; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_fire = (toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_valid && toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_ready); + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_valid = toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_rValid; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_addr = axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_addr; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_id = axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_id; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_len = axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_len; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_size = axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_size; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_burst = axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_burst; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_lock = axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_lock; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_cache = axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_cache; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_payload_prot = axiIn_1_writeOnly_decoder_io_outputs_2_aw_payload_prot; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_ready = axi4WriteOnlyArbiter_6_io_inputs_1_aw_ready; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_fire = (toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_valid && toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_ready); + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_valid = toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_rValid; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_addr = axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_addr; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_id = axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_id; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_len = axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_len; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_size = axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_size; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_burst = axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_burst; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_lock = axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_lock; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_cache = axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_cache; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_payload_prot = axiIn_1_writeOnly_decoder_io_outputs_3_aw_payload_prot; + assign toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_ready = axi4WriteOnlyArbiter_7_io_inputs_1_aw_ready; + assign axiIn_1_writeOnly_aw_ready = axiIn_1_writeOnly_decoder_io_input_aw_ready; + assign axiIn_1_writeOnly_w_ready = axiIn_1_writeOnly_decoder_io_input_w_ready; + assign axiIn_1_writeOnly_b_valid = axiIn_1_writeOnly_decoder_io_input_b_valid; + assign axiIn_1_writeOnly_b_payload_id = axiIn_1_writeOnly_decoder_io_input_b_payload_id; + assign axiIn_1_writeOnly_b_payload_resp = axiIn_1_writeOnly_decoder_io_input_b_payload_resp; + always @(posedge clk or negedge resetn) begin + if(!resetn) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_rValid <= 1'b0; + toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_rValid <= 1'b0; + toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_rValid <= 1'b0; + toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_rValid <= 1'b0; + toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_rValid <= 1'b0; + toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_rValid <= 1'b0; + toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_rValid <= 1'b0; + toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_rValid <= 1'b0; + toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_rValid <= 1'b0; + toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_rValid <= 1'b0; + toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_rValid <= 1'b0; + toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_rValid <= 1'b0; + toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_rValid <= 1'b0; + toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_rValid <= 1'b0; + toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_rValid <= 1'b0; + toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_rValid <= 1'b0; + toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_rValid <= 1'b0; + toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_rValid <= 1'b0; + toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_rValid <= 1'b0; + toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_rValid <= 1'b0; + toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_rValid <= 1'b0; + toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_rValid <= 1'b0; + toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_rValid <= 1'b0; + toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_rValid <= 1'b0; + end else begin + if(axiIn_0_readOnly_decoder_io_outputs_0_ar_valid) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_rValid <= 1'b1; + end + if(toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_validPipe_fire) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_0_ar_rValid <= 1'b0; + end + if(axiIn_0_readOnly_decoder_io_outputs_1_ar_valid) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_rValid <= 1'b1; + end + if(toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_validPipe_fire) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_1_ar_rValid <= 1'b0; + end + if(axiIn_0_readOnly_decoder_io_outputs_2_ar_valid) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_rValid <= 1'b1; + end + if(toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_validPipe_fire) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_2_ar_rValid <= 1'b0; + end + if(axiIn_0_readOnly_decoder_io_outputs_3_ar_valid) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_rValid <= 1'b1; + end + if(toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_validPipe_fire) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_3_ar_rValid <= 1'b0; + end + if(axiIn_0_readOnly_decoder_io_outputs_4_ar_valid) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_rValid <= 1'b1; + end + if(toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_validPipe_fire) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_4_ar_rValid <= 1'b0; + end + if(axiIn_0_readOnly_decoder_io_outputs_5_ar_valid) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_rValid <= 1'b1; + end + if(toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_validPipe_fire) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_5_ar_rValid <= 1'b0; + end + if(axiIn_0_readOnly_decoder_io_outputs_6_ar_valid) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_rValid <= 1'b1; + end + if(toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_validPipe_fire) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_6_ar_rValid <= 1'b0; + end + if(axiIn_0_readOnly_decoder_io_outputs_7_ar_valid) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_rValid <= 1'b1; + end + if(toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_validPipe_fire) begin + toplevel_axiIn_0_readOnly_decoder_io_outputs_7_ar_rValid <= 1'b0; + end + if(axiIn_0_writeOnly_decoder_io_outputs_0_aw_valid) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_rValid <= 1'b1; + end + if(toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_validPipe_fire) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_rValid <= 1'b0; + end + if(axiIn_0_writeOnly_decoder_io_outputs_1_aw_valid) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_rValid <= 1'b1; + end + if(toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_validPipe_fire) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_1_aw_rValid <= 1'b0; + end + if(axiIn_0_writeOnly_decoder_io_outputs_2_aw_valid) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_rValid <= 1'b1; + end + if(toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_validPipe_fire) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_2_aw_rValid <= 1'b0; + end + if(axiIn_0_writeOnly_decoder_io_outputs_3_aw_valid) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_rValid <= 1'b1; + end + if(toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_validPipe_fire) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_3_aw_rValid <= 1'b0; + end + if(axiIn_0_writeOnly_decoder_io_outputs_4_aw_valid) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_rValid <= 1'b1; + end + if(toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_validPipe_fire) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_4_aw_rValid <= 1'b0; + end + if(axiIn_0_writeOnly_decoder_io_outputs_5_aw_valid) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_rValid <= 1'b1; + end + if(toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_validPipe_fire) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_5_aw_rValid <= 1'b0; + end + if(axiIn_0_writeOnly_decoder_io_outputs_6_aw_valid) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_rValid <= 1'b1; + end + if(toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_validPipe_fire) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_6_aw_rValid <= 1'b0; + end + if(axiIn_0_writeOnly_decoder_io_outputs_7_aw_valid) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_rValid <= 1'b1; + end + if(toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_validPipe_fire) begin + toplevel_axiIn_0_writeOnly_decoder_io_outputs_7_aw_rValid <= 1'b0; + end + if(axiIn_1_readOnly_decoder_io_outputs_0_ar_valid) begin + toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_rValid <= 1'b1; + end + if(toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_validPipe_fire) begin + toplevel_axiIn_1_readOnly_decoder_io_outputs_0_ar_rValid <= 1'b0; + end + if(axiIn_1_readOnly_decoder_io_outputs_1_ar_valid) begin + toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_rValid <= 1'b1; + end + if(toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_validPipe_fire) begin + toplevel_axiIn_1_readOnly_decoder_io_outputs_1_ar_rValid <= 1'b0; + end + if(axiIn_1_readOnly_decoder_io_outputs_2_ar_valid) begin + toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_rValid <= 1'b1; + end + if(toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_validPipe_fire) begin + toplevel_axiIn_1_readOnly_decoder_io_outputs_2_ar_rValid <= 1'b0; + end + if(axiIn_1_readOnly_decoder_io_outputs_3_ar_valid) begin + toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_rValid <= 1'b1; + end + if(toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_validPipe_fire) begin + toplevel_axiIn_1_readOnly_decoder_io_outputs_3_ar_rValid <= 1'b0; + end + if(axiIn_1_writeOnly_decoder_io_outputs_0_aw_valid) begin + toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_rValid <= 1'b1; + end + if(toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_validPipe_fire) begin + toplevel_axiIn_1_writeOnly_decoder_io_outputs_0_aw_rValid <= 1'b0; + end + if(axiIn_1_writeOnly_decoder_io_outputs_1_aw_valid) begin + toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_rValid <= 1'b1; + end + if(toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_validPipe_fire) begin + toplevel_axiIn_1_writeOnly_decoder_io_outputs_1_aw_rValid <= 1'b0; + end + if(axiIn_1_writeOnly_decoder_io_outputs_2_aw_valid) begin + toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_rValid <= 1'b1; + end + if(toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_validPipe_fire) begin + toplevel_axiIn_1_writeOnly_decoder_io_outputs_2_aw_rValid <= 1'b0; + end + if(axiIn_1_writeOnly_decoder_io_outputs_3_aw_valid) begin + toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_rValid <= 1'b1; + end + if(toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_validPipe_fire) begin + toplevel_axiIn_1_writeOnly_decoder_io_outputs_3_aw_rValid <= 1'b0; + end + end + end + + +endmodule + +module Axi4WriteOnlyArbiter_3 ( + input wire io_inputs_0_aw_valid, + output wire io_inputs_0_aw_ready, + input wire [31:0] io_inputs_0_aw_payload_addr, + input wire [3:0] io_inputs_0_aw_payload_id, + input wire [7:0] io_inputs_0_aw_payload_len, + input wire [2:0] io_inputs_0_aw_payload_size, + input wire [1:0] io_inputs_0_aw_payload_burst, + input wire [0:0] io_inputs_0_aw_payload_lock, + input wire [3:0] io_inputs_0_aw_payload_cache, + input wire [2:0] io_inputs_0_aw_payload_prot, + input wire io_inputs_0_w_valid, + output wire io_inputs_0_w_ready, + input wire [31:0] io_inputs_0_w_payload_data, + input wire [3:0] io_inputs_0_w_payload_strb, + input wire io_inputs_0_w_payload_last, + output wire io_inputs_0_b_valid, + input wire io_inputs_0_b_ready, + output wire [3:0] io_inputs_0_b_payload_id, + output wire [1:0] io_inputs_0_b_payload_resp, + input wire io_inputs_1_aw_valid, + output wire io_inputs_1_aw_ready, + input wire [31:0] io_inputs_1_aw_payload_addr, + input wire [3:0] io_inputs_1_aw_payload_id, + input wire [7:0] io_inputs_1_aw_payload_len, + input wire [2:0] io_inputs_1_aw_payload_size, + input wire [1:0] io_inputs_1_aw_payload_burst, + input wire [0:0] io_inputs_1_aw_payload_lock, + input wire [3:0] io_inputs_1_aw_payload_cache, + input wire [2:0] io_inputs_1_aw_payload_prot, + input wire io_inputs_1_w_valid, + output wire io_inputs_1_w_ready, + input wire [31:0] io_inputs_1_w_payload_data, + input wire [3:0] io_inputs_1_w_payload_strb, + input wire io_inputs_1_w_payload_last, + output wire io_inputs_1_b_valid, + input wire io_inputs_1_b_ready, + output wire [3:0] io_inputs_1_b_payload_id, + output wire [1:0] io_inputs_1_b_payload_resp, + output wire io_output_aw_valid, + input wire io_output_aw_ready, + output wire [31:0] io_output_aw_payload_addr, + output wire [4:0] io_output_aw_payload_id, + output wire [7:0] io_output_aw_payload_len, + output wire [2:0] io_output_aw_payload_size, + output wire [1:0] io_output_aw_payload_burst, + output wire [0:0] io_output_aw_payload_lock, + output wire [3:0] io_output_aw_payload_cache, + output wire [2:0] io_output_aw_payload_prot, + output wire io_output_w_valid, + input wire io_output_w_ready, + output wire [31:0] io_output_w_payload_data, + output wire [3:0] io_output_w_payload_strb, + output wire io_output_w_payload_last, + input wire io_output_b_valid, + output wire io_output_b_ready, + input wire [4:0] io_output_b_payload_id, + input wire [1:0] io_output_b_payload_resp, + input wire clk, + input wire resetn +); + + reg cmdArbiter_io_output_ready; + wire cmdRouteFork_translated_fifo_io_pop_ready; + wire cmdRouteFork_translated_fifo_io_flush; + wire cmdArbiter_io_inputs_0_ready; + wire cmdArbiter_io_inputs_1_ready; + wire cmdArbiter_io_output_valid; + wire [31:0] cmdArbiter_io_output_payload_addr; + wire [3:0] cmdArbiter_io_output_payload_id; + wire [7:0] cmdArbiter_io_output_payload_len; + wire [2:0] cmdArbiter_io_output_payload_size; + wire [1:0] cmdArbiter_io_output_payload_burst; + wire [0:0] cmdArbiter_io_output_payload_lock; + wire [3:0] cmdArbiter_io_output_payload_cache; + wire [2:0] cmdArbiter_io_output_payload_prot; + wire [0:0] cmdArbiter_io_chosen; + wire [1:0] cmdArbiter_io_chosenOH; + wire cmdRouteFork_translated_fifo_io_push_ready; + wire cmdRouteFork_translated_fifo_io_pop_valid; + wire [0:0] cmdRouteFork_translated_fifo_io_pop_payload; + wire [2:0] cmdRouteFork_translated_fifo_io_occupancy; + wire [2:0] cmdRouteFork_translated_fifo_io_availability; + reg _zz_io_output_w_valid; + reg [31:0] _zz_io_output_w_payload_data; + reg [3:0] _zz_io_output_w_payload_strb; + reg _zz_io_output_w_payload_last; + reg _zz_io_output_b_ready; + wire cmdOutputFork_valid; + wire cmdOutputFork_ready; + wire [31:0] cmdOutputFork_payload_addr; + wire [3:0] cmdOutputFork_payload_id; + wire [7:0] cmdOutputFork_payload_len; + wire [2:0] cmdOutputFork_payload_size; + wire [1:0] cmdOutputFork_payload_burst; + wire [0:0] cmdOutputFork_payload_lock; + wire [3:0] cmdOutputFork_payload_cache; + wire [2:0] cmdOutputFork_payload_prot; + wire cmdRouteFork_valid; + wire cmdRouteFork_ready; + wire [31:0] cmdRouteFork_payload_addr; + wire [3:0] cmdRouteFork_payload_id; + wire [7:0] cmdRouteFork_payload_len; + wire [2:0] cmdRouteFork_payload_size; + wire [1:0] cmdRouteFork_payload_burst; + wire [0:0] cmdRouteFork_payload_lock; + wire [3:0] cmdRouteFork_payload_cache; + wire [2:0] cmdRouteFork_payload_prot; + reg axi4WriteOnlyArbiter_7_cmdArbiter_io_output_fork2_logic_linkEnable_0; + reg axi4WriteOnlyArbiter_7_cmdArbiter_io_output_fork2_logic_linkEnable_1; + wire when_Stream_l1020; + wire when_Stream_l1020_1; + wire cmdOutputFork_fire; + wire cmdRouteFork_fire; + wire cmdRouteFork_translated_valid; + wire cmdRouteFork_translated_ready; + wire [0:0] cmdRouteFork_translated_payload; + wire io_output_w_fire; + wire [0:0] writeRspIndex; + wire writeRspSels_0; + wire writeRspSels_1; + + StreamArbiter_7 cmdArbiter ( + .io_inputs_0_valid (io_inputs_0_aw_valid ), //i + .io_inputs_0_ready (cmdArbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_addr (io_inputs_0_aw_payload_addr[31:0] ), //i + .io_inputs_0_payload_id (io_inputs_0_aw_payload_id[3:0] ), //i + .io_inputs_0_payload_len (io_inputs_0_aw_payload_len[7:0] ), //i + .io_inputs_0_payload_size (io_inputs_0_aw_payload_size[2:0] ), //i + .io_inputs_0_payload_burst (io_inputs_0_aw_payload_burst[1:0] ), //i + .io_inputs_0_payload_lock (io_inputs_0_aw_payload_lock ), //i + .io_inputs_0_payload_cache (io_inputs_0_aw_payload_cache[3:0] ), //i + .io_inputs_0_payload_prot (io_inputs_0_aw_payload_prot[2:0] ), //i + .io_inputs_1_valid (io_inputs_1_aw_valid ), //i + .io_inputs_1_ready (cmdArbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_addr (io_inputs_1_aw_payload_addr[31:0] ), //i + .io_inputs_1_payload_id (io_inputs_1_aw_payload_id[3:0] ), //i + .io_inputs_1_payload_len (io_inputs_1_aw_payload_len[7:0] ), //i + .io_inputs_1_payload_size (io_inputs_1_aw_payload_size[2:0] ), //i + .io_inputs_1_payload_burst (io_inputs_1_aw_payload_burst[1:0] ), //i + .io_inputs_1_payload_lock (io_inputs_1_aw_payload_lock ), //i + .io_inputs_1_payload_cache (io_inputs_1_aw_payload_cache[3:0] ), //i + .io_inputs_1_payload_prot (io_inputs_1_aw_payload_prot[2:0] ), //i + .io_output_valid (cmdArbiter_io_output_valid ), //o + .io_output_ready (cmdArbiter_io_output_ready ), //i + .io_output_payload_addr (cmdArbiter_io_output_payload_addr[31:0]), //o + .io_output_payload_id (cmdArbiter_io_output_payload_id[3:0] ), //o + .io_output_payload_len (cmdArbiter_io_output_payload_len[7:0] ), //o + .io_output_payload_size (cmdArbiter_io_output_payload_size[2:0] ), //o + .io_output_payload_burst (cmdArbiter_io_output_payload_burst[1:0]), //o + .io_output_payload_lock (cmdArbiter_io_output_payload_lock ), //o + .io_output_payload_cache (cmdArbiter_io_output_payload_cache[3:0]), //o + .io_output_payload_prot (cmdArbiter_io_output_payload_prot[2:0] ), //o + .io_chosen (cmdArbiter_io_chosen ), //o + .io_chosenOH (cmdArbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + StreamFifoLowLatency_3 cmdRouteFork_translated_fifo ( + .io_push_valid (cmdRouteFork_translated_valid ), //i + .io_push_ready (cmdRouteFork_translated_fifo_io_push_ready ), //o + .io_push_payload (cmdRouteFork_translated_payload ), //i + .io_pop_valid (cmdRouteFork_translated_fifo_io_pop_valid ), //o + .io_pop_ready (cmdRouteFork_translated_fifo_io_pop_ready ), //i + .io_pop_payload (cmdRouteFork_translated_fifo_io_pop_payload ), //o + .io_flush (cmdRouteFork_translated_fifo_io_flush ), //i + .io_occupancy (cmdRouteFork_translated_fifo_io_occupancy[2:0] ), //o + .io_availability (cmdRouteFork_translated_fifo_io_availability[2:0]), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + always @(*) begin + case(cmdRouteFork_translated_fifo_io_pop_payload) + 1'b0 : begin + _zz_io_output_w_valid = io_inputs_0_w_valid; + _zz_io_output_w_payload_data = io_inputs_0_w_payload_data; + _zz_io_output_w_payload_strb = io_inputs_0_w_payload_strb; + _zz_io_output_w_payload_last = io_inputs_0_w_payload_last; + end + default : begin + _zz_io_output_w_valid = io_inputs_1_w_valid; + _zz_io_output_w_payload_data = io_inputs_1_w_payload_data; + _zz_io_output_w_payload_strb = io_inputs_1_w_payload_strb; + _zz_io_output_w_payload_last = io_inputs_1_w_payload_last; + end + endcase + end + + always @(*) begin + case(writeRspIndex) + 1'b0 : _zz_io_output_b_ready = io_inputs_0_b_ready; + default : _zz_io_output_b_ready = io_inputs_1_b_ready; + endcase + end + + assign io_inputs_0_aw_ready = cmdArbiter_io_inputs_0_ready; + assign io_inputs_1_aw_ready = cmdArbiter_io_inputs_1_ready; + always @(*) begin + cmdArbiter_io_output_ready = 1'b1; + if(when_Stream_l1020) begin + cmdArbiter_io_output_ready = 1'b0; + end + if(when_Stream_l1020_1) begin + cmdArbiter_io_output_ready = 1'b0; + end + end + + assign when_Stream_l1020 = ((! cmdOutputFork_ready) && axi4WriteOnlyArbiter_7_cmdArbiter_io_output_fork2_logic_linkEnable_0); + assign when_Stream_l1020_1 = ((! cmdRouteFork_ready) && axi4WriteOnlyArbiter_7_cmdArbiter_io_output_fork2_logic_linkEnable_1); + assign cmdOutputFork_valid = (cmdArbiter_io_output_valid && axi4WriteOnlyArbiter_7_cmdArbiter_io_output_fork2_logic_linkEnable_0); + assign cmdOutputFork_payload_addr = cmdArbiter_io_output_payload_addr; + assign cmdOutputFork_payload_id = cmdArbiter_io_output_payload_id; + assign cmdOutputFork_payload_len = cmdArbiter_io_output_payload_len; + assign cmdOutputFork_payload_size = cmdArbiter_io_output_payload_size; + assign cmdOutputFork_payload_burst = cmdArbiter_io_output_payload_burst; + assign cmdOutputFork_payload_lock = cmdArbiter_io_output_payload_lock; + assign cmdOutputFork_payload_cache = cmdArbiter_io_output_payload_cache; + assign cmdOutputFork_payload_prot = cmdArbiter_io_output_payload_prot; + assign cmdOutputFork_fire = (cmdOutputFork_valid && cmdOutputFork_ready); + assign cmdRouteFork_valid = (cmdArbiter_io_output_valid && axi4WriteOnlyArbiter_7_cmdArbiter_io_output_fork2_logic_linkEnable_1); + assign cmdRouteFork_payload_addr = cmdArbiter_io_output_payload_addr; + assign cmdRouteFork_payload_id = cmdArbiter_io_output_payload_id; + assign cmdRouteFork_payload_len = cmdArbiter_io_output_payload_len; + assign cmdRouteFork_payload_size = cmdArbiter_io_output_payload_size; + assign cmdRouteFork_payload_burst = cmdArbiter_io_output_payload_burst; + assign cmdRouteFork_payload_lock = cmdArbiter_io_output_payload_lock; + assign cmdRouteFork_payload_cache = cmdArbiter_io_output_payload_cache; + assign cmdRouteFork_payload_prot = cmdArbiter_io_output_payload_prot; + assign cmdRouteFork_fire = (cmdRouteFork_valid && cmdRouteFork_ready); + assign io_output_aw_valid = cmdOutputFork_valid; + assign cmdOutputFork_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdOutputFork_payload_addr; + assign io_output_aw_payload_len = cmdOutputFork_payload_len; + assign io_output_aw_payload_size = cmdOutputFork_payload_size; + assign io_output_aw_payload_burst = cmdOutputFork_payload_burst; + assign io_output_aw_payload_lock = cmdOutputFork_payload_lock; + assign io_output_aw_payload_cache = cmdOutputFork_payload_cache; + assign io_output_aw_payload_prot = cmdOutputFork_payload_prot; + assign io_output_aw_payload_id = {cmdArbiter_io_chosen,cmdArbiter_io_output_payload_id}; + assign cmdRouteFork_translated_valid = cmdRouteFork_valid; + assign cmdRouteFork_ready = cmdRouteFork_translated_ready; + assign cmdRouteFork_translated_payload = cmdArbiter_io_chosen; + assign cmdRouteFork_translated_ready = cmdRouteFork_translated_fifo_io_push_ready; + assign io_output_w_valid = (cmdRouteFork_translated_fifo_io_pop_valid && _zz_io_output_w_valid); + assign io_output_w_payload_data = _zz_io_output_w_payload_data; + assign io_output_w_payload_strb = _zz_io_output_w_payload_strb; + assign io_output_w_payload_last = _zz_io_output_w_payload_last; + assign io_inputs_0_w_ready = ((cmdRouteFork_translated_fifo_io_pop_valid && io_output_w_ready) && (cmdRouteFork_translated_fifo_io_pop_payload == 1'b0)); + assign io_inputs_1_w_ready = ((cmdRouteFork_translated_fifo_io_pop_valid && io_output_w_ready) && (cmdRouteFork_translated_fifo_io_pop_payload == 1'b1)); + assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); + assign cmdRouteFork_translated_fifo_io_pop_ready = (io_output_w_fire && io_output_w_payload_last); + assign writeRspIndex = io_output_b_payload_id[4 : 4]; + assign writeRspSels_0 = (writeRspIndex == 1'b0); + assign writeRspSels_1 = (writeRspIndex == 1'b1); + assign io_inputs_0_b_valid = (io_output_b_valid && writeRspSels_0); + assign io_inputs_0_b_payload_resp = io_output_b_payload_resp; + assign io_inputs_0_b_payload_id = io_output_b_payload_id[3 : 0]; + assign io_inputs_1_b_valid = (io_output_b_valid && writeRspSels_1); + assign io_inputs_1_b_payload_resp = io_output_b_payload_resp; + assign io_inputs_1_b_payload_id = io_output_b_payload_id[3 : 0]; + assign io_output_b_ready = _zz_io_output_b_ready; + assign cmdRouteFork_translated_fifo_io_flush = 1'b0; + always @(posedge clk or negedge resetn) begin + if(!resetn) begin + axi4WriteOnlyArbiter_7_cmdArbiter_io_output_fork2_logic_linkEnable_0 <= 1'b1; + axi4WriteOnlyArbiter_7_cmdArbiter_io_output_fork2_logic_linkEnable_1 <= 1'b1; + end else begin + if(cmdOutputFork_fire) begin + axi4WriteOnlyArbiter_7_cmdArbiter_io_output_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdRouteFork_fire) begin + axi4WriteOnlyArbiter_7_cmdArbiter_io_output_fork2_logic_linkEnable_1 <= 1'b0; + end + if(cmdArbiter_io_output_ready) begin + axi4WriteOnlyArbiter_7_cmdArbiter_io_output_fork2_logic_linkEnable_0 <= 1'b1; + axi4WriteOnlyArbiter_7_cmdArbiter_io_output_fork2_logic_linkEnable_1 <= 1'b1; + end + end + end + + +endmodule + +//Axi4ReadOnlyArbiter_3 replaced by Axi4ReadOnlyArbiter + +module Axi4WriteOnlyArbiter_2 ( + input wire io_inputs_0_aw_valid, + output wire io_inputs_0_aw_ready, + input wire [31:0] io_inputs_0_aw_payload_addr, + input wire [3:0] io_inputs_0_aw_payload_id, + input wire [7:0] io_inputs_0_aw_payload_len, + input wire [2:0] io_inputs_0_aw_payload_size, + input wire [1:0] io_inputs_0_aw_payload_burst, + input wire [0:0] io_inputs_0_aw_payload_lock, + input wire [3:0] io_inputs_0_aw_payload_cache, + input wire [2:0] io_inputs_0_aw_payload_prot, + input wire io_inputs_0_w_valid, + output wire io_inputs_0_w_ready, + input wire [31:0] io_inputs_0_w_payload_data, + input wire [3:0] io_inputs_0_w_payload_strb, + input wire io_inputs_0_w_payload_last, + output wire io_inputs_0_b_valid, + input wire io_inputs_0_b_ready, + output wire [3:0] io_inputs_0_b_payload_id, + output wire [1:0] io_inputs_0_b_payload_resp, + input wire io_inputs_1_aw_valid, + output wire io_inputs_1_aw_ready, + input wire [31:0] io_inputs_1_aw_payload_addr, + input wire [3:0] io_inputs_1_aw_payload_id, + input wire [7:0] io_inputs_1_aw_payload_len, + input wire [2:0] io_inputs_1_aw_payload_size, + input wire [1:0] io_inputs_1_aw_payload_burst, + input wire [0:0] io_inputs_1_aw_payload_lock, + input wire [3:0] io_inputs_1_aw_payload_cache, + input wire [2:0] io_inputs_1_aw_payload_prot, + input wire io_inputs_1_w_valid, + output wire io_inputs_1_w_ready, + input wire [31:0] io_inputs_1_w_payload_data, + input wire [3:0] io_inputs_1_w_payload_strb, + input wire io_inputs_1_w_payload_last, + output wire io_inputs_1_b_valid, + input wire io_inputs_1_b_ready, + output wire [3:0] io_inputs_1_b_payload_id, + output wire [1:0] io_inputs_1_b_payload_resp, + output wire io_output_aw_valid, + input wire io_output_aw_ready, + output wire [31:0] io_output_aw_payload_addr, + output wire [4:0] io_output_aw_payload_id, + output wire [7:0] io_output_aw_payload_len, + output wire [2:0] io_output_aw_payload_size, + output wire [1:0] io_output_aw_payload_burst, + output wire [0:0] io_output_aw_payload_lock, + output wire [3:0] io_output_aw_payload_cache, + output wire [2:0] io_output_aw_payload_prot, + output wire io_output_w_valid, + input wire io_output_w_ready, + output wire [31:0] io_output_w_payload_data, + output wire [3:0] io_output_w_payload_strb, + output wire io_output_w_payload_last, + input wire io_output_b_valid, + output wire io_output_b_ready, + input wire [4:0] io_output_b_payload_id, + input wire [1:0] io_output_b_payload_resp, + input wire clk, + input wire resetn +); + + reg cmdArbiter_io_output_ready; + wire cmdRouteFork_translated_fifo_io_pop_ready; + wire cmdRouteFork_translated_fifo_io_flush; + wire cmdArbiter_io_inputs_0_ready; + wire cmdArbiter_io_inputs_1_ready; + wire cmdArbiter_io_output_valid; + wire [31:0] cmdArbiter_io_output_payload_addr; + wire [3:0] cmdArbiter_io_output_payload_id; + wire [7:0] cmdArbiter_io_output_payload_len; + wire [2:0] cmdArbiter_io_output_payload_size; + wire [1:0] cmdArbiter_io_output_payload_burst; + wire [0:0] cmdArbiter_io_output_payload_lock; + wire [3:0] cmdArbiter_io_output_payload_cache; + wire [2:0] cmdArbiter_io_output_payload_prot; + wire [0:0] cmdArbiter_io_chosen; + wire [1:0] cmdArbiter_io_chosenOH; + wire cmdRouteFork_translated_fifo_io_push_ready; + wire cmdRouteFork_translated_fifo_io_pop_valid; + wire [0:0] cmdRouteFork_translated_fifo_io_pop_payload; + wire [2:0] cmdRouteFork_translated_fifo_io_occupancy; + wire [2:0] cmdRouteFork_translated_fifo_io_availability; + reg _zz_io_output_w_valid; + reg [31:0] _zz_io_output_w_payload_data; + reg [3:0] _zz_io_output_w_payload_strb; + reg _zz_io_output_w_payload_last; + reg _zz_io_output_b_ready; + wire cmdOutputFork_valid; + wire cmdOutputFork_ready; + wire [31:0] cmdOutputFork_payload_addr; + wire [3:0] cmdOutputFork_payload_id; + wire [7:0] cmdOutputFork_payload_len; + wire [2:0] cmdOutputFork_payload_size; + wire [1:0] cmdOutputFork_payload_burst; + wire [0:0] cmdOutputFork_payload_lock; + wire [3:0] cmdOutputFork_payload_cache; + wire [2:0] cmdOutputFork_payload_prot; + wire cmdRouteFork_valid; + wire cmdRouteFork_ready; + wire [31:0] cmdRouteFork_payload_addr; + wire [3:0] cmdRouteFork_payload_id; + wire [7:0] cmdRouteFork_payload_len; + wire [2:0] cmdRouteFork_payload_size; + wire [1:0] cmdRouteFork_payload_burst; + wire [0:0] cmdRouteFork_payload_lock; + wire [3:0] cmdRouteFork_payload_cache; + wire [2:0] cmdRouteFork_payload_prot; + reg axi4WriteOnlyArbiter_6_cmdArbiter_io_output_fork2_logic_linkEnable_0; + reg axi4WriteOnlyArbiter_6_cmdArbiter_io_output_fork2_logic_linkEnable_1; + wire when_Stream_l1020; + wire when_Stream_l1020_1; + wire cmdOutputFork_fire; + wire cmdRouteFork_fire; + wire cmdRouteFork_translated_valid; + wire cmdRouteFork_translated_ready; + wire [0:0] cmdRouteFork_translated_payload; + wire io_output_w_fire; + wire [0:0] writeRspIndex; + wire writeRspSels_0; + wire writeRspSels_1; + + StreamArbiter_7 cmdArbiter ( + .io_inputs_0_valid (io_inputs_0_aw_valid ), //i + .io_inputs_0_ready (cmdArbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_addr (io_inputs_0_aw_payload_addr[31:0] ), //i + .io_inputs_0_payload_id (io_inputs_0_aw_payload_id[3:0] ), //i + .io_inputs_0_payload_len (io_inputs_0_aw_payload_len[7:0] ), //i + .io_inputs_0_payload_size (io_inputs_0_aw_payload_size[2:0] ), //i + .io_inputs_0_payload_burst (io_inputs_0_aw_payload_burst[1:0] ), //i + .io_inputs_0_payload_lock (io_inputs_0_aw_payload_lock ), //i + .io_inputs_0_payload_cache (io_inputs_0_aw_payload_cache[3:0] ), //i + .io_inputs_0_payload_prot (io_inputs_0_aw_payload_prot[2:0] ), //i + .io_inputs_1_valid (io_inputs_1_aw_valid ), //i + .io_inputs_1_ready (cmdArbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_addr (io_inputs_1_aw_payload_addr[31:0] ), //i + .io_inputs_1_payload_id (io_inputs_1_aw_payload_id[3:0] ), //i + .io_inputs_1_payload_len (io_inputs_1_aw_payload_len[7:0] ), //i + .io_inputs_1_payload_size (io_inputs_1_aw_payload_size[2:0] ), //i + .io_inputs_1_payload_burst (io_inputs_1_aw_payload_burst[1:0] ), //i + .io_inputs_1_payload_lock (io_inputs_1_aw_payload_lock ), //i + .io_inputs_1_payload_cache (io_inputs_1_aw_payload_cache[3:0] ), //i + .io_inputs_1_payload_prot (io_inputs_1_aw_payload_prot[2:0] ), //i + .io_output_valid (cmdArbiter_io_output_valid ), //o + .io_output_ready (cmdArbiter_io_output_ready ), //i + .io_output_payload_addr (cmdArbiter_io_output_payload_addr[31:0]), //o + .io_output_payload_id (cmdArbiter_io_output_payload_id[3:0] ), //o + .io_output_payload_len (cmdArbiter_io_output_payload_len[7:0] ), //o + .io_output_payload_size (cmdArbiter_io_output_payload_size[2:0] ), //o + .io_output_payload_burst (cmdArbiter_io_output_payload_burst[1:0]), //o + .io_output_payload_lock (cmdArbiter_io_output_payload_lock ), //o + .io_output_payload_cache (cmdArbiter_io_output_payload_cache[3:0]), //o + .io_output_payload_prot (cmdArbiter_io_output_payload_prot[2:0] ), //o + .io_chosen (cmdArbiter_io_chosen ), //o + .io_chosenOH (cmdArbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + StreamFifoLowLatency_3 cmdRouteFork_translated_fifo ( + .io_push_valid (cmdRouteFork_translated_valid ), //i + .io_push_ready (cmdRouteFork_translated_fifo_io_push_ready ), //o + .io_push_payload (cmdRouteFork_translated_payload ), //i + .io_pop_valid (cmdRouteFork_translated_fifo_io_pop_valid ), //o + .io_pop_ready (cmdRouteFork_translated_fifo_io_pop_ready ), //i + .io_pop_payload (cmdRouteFork_translated_fifo_io_pop_payload ), //o + .io_flush (cmdRouteFork_translated_fifo_io_flush ), //i + .io_occupancy (cmdRouteFork_translated_fifo_io_occupancy[2:0] ), //o + .io_availability (cmdRouteFork_translated_fifo_io_availability[2:0]), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + always @(*) begin + case(cmdRouteFork_translated_fifo_io_pop_payload) + 1'b0 : begin + _zz_io_output_w_valid = io_inputs_0_w_valid; + _zz_io_output_w_payload_data = io_inputs_0_w_payload_data; + _zz_io_output_w_payload_strb = io_inputs_0_w_payload_strb; + _zz_io_output_w_payload_last = io_inputs_0_w_payload_last; + end + default : begin + _zz_io_output_w_valid = io_inputs_1_w_valid; + _zz_io_output_w_payload_data = io_inputs_1_w_payload_data; + _zz_io_output_w_payload_strb = io_inputs_1_w_payload_strb; + _zz_io_output_w_payload_last = io_inputs_1_w_payload_last; + end + endcase + end + + always @(*) begin + case(writeRspIndex) + 1'b0 : _zz_io_output_b_ready = io_inputs_0_b_ready; + default : _zz_io_output_b_ready = io_inputs_1_b_ready; + endcase + end + + assign io_inputs_0_aw_ready = cmdArbiter_io_inputs_0_ready; + assign io_inputs_1_aw_ready = cmdArbiter_io_inputs_1_ready; + always @(*) begin + cmdArbiter_io_output_ready = 1'b1; + if(when_Stream_l1020) begin + cmdArbiter_io_output_ready = 1'b0; + end + if(when_Stream_l1020_1) begin + cmdArbiter_io_output_ready = 1'b0; + end + end + + assign when_Stream_l1020 = ((! cmdOutputFork_ready) && axi4WriteOnlyArbiter_6_cmdArbiter_io_output_fork2_logic_linkEnable_0); + assign when_Stream_l1020_1 = ((! cmdRouteFork_ready) && axi4WriteOnlyArbiter_6_cmdArbiter_io_output_fork2_logic_linkEnable_1); + assign cmdOutputFork_valid = (cmdArbiter_io_output_valid && axi4WriteOnlyArbiter_6_cmdArbiter_io_output_fork2_logic_linkEnable_0); + assign cmdOutputFork_payload_addr = cmdArbiter_io_output_payload_addr; + assign cmdOutputFork_payload_id = cmdArbiter_io_output_payload_id; + assign cmdOutputFork_payload_len = cmdArbiter_io_output_payload_len; + assign cmdOutputFork_payload_size = cmdArbiter_io_output_payload_size; + assign cmdOutputFork_payload_burst = cmdArbiter_io_output_payload_burst; + assign cmdOutputFork_payload_lock = cmdArbiter_io_output_payload_lock; + assign cmdOutputFork_payload_cache = cmdArbiter_io_output_payload_cache; + assign cmdOutputFork_payload_prot = cmdArbiter_io_output_payload_prot; + assign cmdOutputFork_fire = (cmdOutputFork_valid && cmdOutputFork_ready); + assign cmdRouteFork_valid = (cmdArbiter_io_output_valid && axi4WriteOnlyArbiter_6_cmdArbiter_io_output_fork2_logic_linkEnable_1); + assign cmdRouteFork_payload_addr = cmdArbiter_io_output_payload_addr; + assign cmdRouteFork_payload_id = cmdArbiter_io_output_payload_id; + assign cmdRouteFork_payload_len = cmdArbiter_io_output_payload_len; + assign cmdRouteFork_payload_size = cmdArbiter_io_output_payload_size; + assign cmdRouteFork_payload_burst = cmdArbiter_io_output_payload_burst; + assign cmdRouteFork_payload_lock = cmdArbiter_io_output_payload_lock; + assign cmdRouteFork_payload_cache = cmdArbiter_io_output_payload_cache; + assign cmdRouteFork_payload_prot = cmdArbiter_io_output_payload_prot; + assign cmdRouteFork_fire = (cmdRouteFork_valid && cmdRouteFork_ready); + assign io_output_aw_valid = cmdOutputFork_valid; + assign cmdOutputFork_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdOutputFork_payload_addr; + assign io_output_aw_payload_len = cmdOutputFork_payload_len; + assign io_output_aw_payload_size = cmdOutputFork_payload_size; + assign io_output_aw_payload_burst = cmdOutputFork_payload_burst; + assign io_output_aw_payload_lock = cmdOutputFork_payload_lock; + assign io_output_aw_payload_cache = cmdOutputFork_payload_cache; + assign io_output_aw_payload_prot = cmdOutputFork_payload_prot; + assign io_output_aw_payload_id = {cmdArbiter_io_chosen,cmdArbiter_io_output_payload_id}; + assign cmdRouteFork_translated_valid = cmdRouteFork_valid; + assign cmdRouteFork_ready = cmdRouteFork_translated_ready; + assign cmdRouteFork_translated_payload = cmdArbiter_io_chosen; + assign cmdRouteFork_translated_ready = cmdRouteFork_translated_fifo_io_push_ready; + assign io_output_w_valid = (cmdRouteFork_translated_fifo_io_pop_valid && _zz_io_output_w_valid); + assign io_output_w_payload_data = _zz_io_output_w_payload_data; + assign io_output_w_payload_strb = _zz_io_output_w_payload_strb; + assign io_output_w_payload_last = _zz_io_output_w_payload_last; + assign io_inputs_0_w_ready = ((cmdRouteFork_translated_fifo_io_pop_valid && io_output_w_ready) && (cmdRouteFork_translated_fifo_io_pop_payload == 1'b0)); + assign io_inputs_1_w_ready = ((cmdRouteFork_translated_fifo_io_pop_valid && io_output_w_ready) && (cmdRouteFork_translated_fifo_io_pop_payload == 1'b1)); + assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); + assign cmdRouteFork_translated_fifo_io_pop_ready = (io_output_w_fire && io_output_w_payload_last); + assign writeRspIndex = io_output_b_payload_id[4 : 4]; + assign writeRspSels_0 = (writeRspIndex == 1'b0); + assign writeRspSels_1 = (writeRspIndex == 1'b1); + assign io_inputs_0_b_valid = (io_output_b_valid && writeRspSels_0); + assign io_inputs_0_b_payload_resp = io_output_b_payload_resp; + assign io_inputs_0_b_payload_id = io_output_b_payload_id[3 : 0]; + assign io_inputs_1_b_valid = (io_output_b_valid && writeRspSels_1); + assign io_inputs_1_b_payload_resp = io_output_b_payload_resp; + assign io_inputs_1_b_payload_id = io_output_b_payload_id[3 : 0]; + assign io_output_b_ready = _zz_io_output_b_ready; + assign cmdRouteFork_translated_fifo_io_flush = 1'b0; + always @(posedge clk or negedge resetn) begin + if(!resetn) begin + axi4WriteOnlyArbiter_6_cmdArbiter_io_output_fork2_logic_linkEnable_0 <= 1'b1; + axi4WriteOnlyArbiter_6_cmdArbiter_io_output_fork2_logic_linkEnable_1 <= 1'b1; + end else begin + if(cmdOutputFork_fire) begin + axi4WriteOnlyArbiter_6_cmdArbiter_io_output_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdRouteFork_fire) begin + axi4WriteOnlyArbiter_6_cmdArbiter_io_output_fork2_logic_linkEnable_1 <= 1'b0; + end + if(cmdArbiter_io_output_ready) begin + axi4WriteOnlyArbiter_6_cmdArbiter_io_output_fork2_logic_linkEnable_0 <= 1'b1; + axi4WriteOnlyArbiter_6_cmdArbiter_io_output_fork2_logic_linkEnable_1 <= 1'b1; + end + end + end + + +endmodule + +//Axi4ReadOnlyArbiter_2 replaced by Axi4ReadOnlyArbiter + +module Axi4WriteOnlyArbiter_1 ( + input wire io_inputs_0_aw_valid, + output wire io_inputs_0_aw_ready, + input wire [31:0] io_inputs_0_aw_payload_addr, + input wire [3:0] io_inputs_0_aw_payload_id, + input wire [7:0] io_inputs_0_aw_payload_len, + input wire [2:0] io_inputs_0_aw_payload_size, + input wire [1:0] io_inputs_0_aw_payload_burst, + input wire [0:0] io_inputs_0_aw_payload_lock, + input wire [3:0] io_inputs_0_aw_payload_cache, + input wire [2:0] io_inputs_0_aw_payload_prot, + input wire io_inputs_0_w_valid, + output wire io_inputs_0_w_ready, + input wire [31:0] io_inputs_0_w_payload_data, + input wire [3:0] io_inputs_0_w_payload_strb, + input wire io_inputs_0_w_payload_last, + output wire io_inputs_0_b_valid, + input wire io_inputs_0_b_ready, + output wire [3:0] io_inputs_0_b_payload_id, + output wire [1:0] io_inputs_0_b_payload_resp, + input wire io_inputs_1_aw_valid, + output wire io_inputs_1_aw_ready, + input wire [31:0] io_inputs_1_aw_payload_addr, + input wire [3:0] io_inputs_1_aw_payload_id, + input wire [7:0] io_inputs_1_aw_payload_len, + input wire [2:0] io_inputs_1_aw_payload_size, + input wire [1:0] io_inputs_1_aw_payload_burst, + input wire [0:0] io_inputs_1_aw_payload_lock, + input wire [3:0] io_inputs_1_aw_payload_cache, + input wire [2:0] io_inputs_1_aw_payload_prot, + input wire io_inputs_1_w_valid, + output wire io_inputs_1_w_ready, + input wire [31:0] io_inputs_1_w_payload_data, + input wire [3:0] io_inputs_1_w_payload_strb, + input wire io_inputs_1_w_payload_last, + output wire io_inputs_1_b_valid, + input wire io_inputs_1_b_ready, + output wire [3:0] io_inputs_1_b_payload_id, + output wire [1:0] io_inputs_1_b_payload_resp, + output wire io_output_aw_valid, + input wire io_output_aw_ready, + output wire [31:0] io_output_aw_payload_addr, + output wire [4:0] io_output_aw_payload_id, + output wire [7:0] io_output_aw_payload_len, + output wire [2:0] io_output_aw_payload_size, + output wire [1:0] io_output_aw_payload_burst, + output wire [0:0] io_output_aw_payload_lock, + output wire [3:0] io_output_aw_payload_cache, + output wire [2:0] io_output_aw_payload_prot, + output wire io_output_w_valid, + input wire io_output_w_ready, + output wire [31:0] io_output_w_payload_data, + output wire [3:0] io_output_w_payload_strb, + output wire io_output_w_payload_last, + input wire io_output_b_valid, + output wire io_output_b_ready, + input wire [4:0] io_output_b_payload_id, + input wire [1:0] io_output_b_payload_resp, + input wire clk, + input wire resetn +); + + reg cmdArbiter_io_output_ready; + wire cmdRouteFork_translated_fifo_io_pop_ready; + wire cmdRouteFork_translated_fifo_io_flush; + wire cmdArbiter_io_inputs_0_ready; + wire cmdArbiter_io_inputs_1_ready; + wire cmdArbiter_io_output_valid; + wire [31:0] cmdArbiter_io_output_payload_addr; + wire [3:0] cmdArbiter_io_output_payload_id; + wire [7:0] cmdArbiter_io_output_payload_len; + wire [2:0] cmdArbiter_io_output_payload_size; + wire [1:0] cmdArbiter_io_output_payload_burst; + wire [0:0] cmdArbiter_io_output_payload_lock; + wire [3:0] cmdArbiter_io_output_payload_cache; + wire [2:0] cmdArbiter_io_output_payload_prot; + wire [0:0] cmdArbiter_io_chosen; + wire [1:0] cmdArbiter_io_chosenOH; + wire cmdRouteFork_translated_fifo_io_push_ready; + wire cmdRouteFork_translated_fifo_io_pop_valid; + wire [0:0] cmdRouteFork_translated_fifo_io_pop_payload; + wire [2:0] cmdRouteFork_translated_fifo_io_occupancy; + wire [2:0] cmdRouteFork_translated_fifo_io_availability; + reg _zz_io_output_w_valid; + reg [31:0] _zz_io_output_w_payload_data; + reg [3:0] _zz_io_output_w_payload_strb; + reg _zz_io_output_w_payload_last; + reg _zz_io_output_b_ready; + wire cmdOutputFork_valid; + wire cmdOutputFork_ready; + wire [31:0] cmdOutputFork_payload_addr; + wire [3:0] cmdOutputFork_payload_id; + wire [7:0] cmdOutputFork_payload_len; + wire [2:0] cmdOutputFork_payload_size; + wire [1:0] cmdOutputFork_payload_burst; + wire [0:0] cmdOutputFork_payload_lock; + wire [3:0] cmdOutputFork_payload_cache; + wire [2:0] cmdOutputFork_payload_prot; + wire cmdRouteFork_valid; + wire cmdRouteFork_ready; + wire [31:0] cmdRouteFork_payload_addr; + wire [3:0] cmdRouteFork_payload_id; + wire [7:0] cmdRouteFork_payload_len; + wire [2:0] cmdRouteFork_payload_size; + wire [1:0] cmdRouteFork_payload_burst; + wire [0:0] cmdRouteFork_payload_lock; + wire [3:0] cmdRouteFork_payload_cache; + wire [2:0] cmdRouteFork_payload_prot; + reg axi4WriteOnlyArbiter_5_cmdArbiter_io_output_fork2_logic_linkEnable_0; + reg axi4WriteOnlyArbiter_5_cmdArbiter_io_output_fork2_logic_linkEnable_1; + wire when_Stream_l1020; + wire when_Stream_l1020_1; + wire cmdOutputFork_fire; + wire cmdRouteFork_fire; + wire cmdRouteFork_translated_valid; + wire cmdRouteFork_translated_ready; + wire [0:0] cmdRouteFork_translated_payload; + wire io_output_w_fire; + wire [0:0] writeRspIndex; + wire writeRspSels_0; + wire writeRspSels_1; + + StreamArbiter_7 cmdArbiter ( + .io_inputs_0_valid (io_inputs_0_aw_valid ), //i + .io_inputs_0_ready (cmdArbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_addr (io_inputs_0_aw_payload_addr[31:0] ), //i + .io_inputs_0_payload_id (io_inputs_0_aw_payload_id[3:0] ), //i + .io_inputs_0_payload_len (io_inputs_0_aw_payload_len[7:0] ), //i + .io_inputs_0_payload_size (io_inputs_0_aw_payload_size[2:0] ), //i + .io_inputs_0_payload_burst (io_inputs_0_aw_payload_burst[1:0] ), //i + .io_inputs_0_payload_lock (io_inputs_0_aw_payload_lock ), //i + .io_inputs_0_payload_cache (io_inputs_0_aw_payload_cache[3:0] ), //i + .io_inputs_0_payload_prot (io_inputs_0_aw_payload_prot[2:0] ), //i + .io_inputs_1_valid (io_inputs_1_aw_valid ), //i + .io_inputs_1_ready (cmdArbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_addr (io_inputs_1_aw_payload_addr[31:0] ), //i + .io_inputs_1_payload_id (io_inputs_1_aw_payload_id[3:0] ), //i + .io_inputs_1_payload_len (io_inputs_1_aw_payload_len[7:0] ), //i + .io_inputs_1_payload_size (io_inputs_1_aw_payload_size[2:0] ), //i + .io_inputs_1_payload_burst (io_inputs_1_aw_payload_burst[1:0] ), //i + .io_inputs_1_payload_lock (io_inputs_1_aw_payload_lock ), //i + .io_inputs_1_payload_cache (io_inputs_1_aw_payload_cache[3:0] ), //i + .io_inputs_1_payload_prot (io_inputs_1_aw_payload_prot[2:0] ), //i + .io_output_valid (cmdArbiter_io_output_valid ), //o + .io_output_ready (cmdArbiter_io_output_ready ), //i + .io_output_payload_addr (cmdArbiter_io_output_payload_addr[31:0]), //o + .io_output_payload_id (cmdArbiter_io_output_payload_id[3:0] ), //o + .io_output_payload_len (cmdArbiter_io_output_payload_len[7:0] ), //o + .io_output_payload_size (cmdArbiter_io_output_payload_size[2:0] ), //o + .io_output_payload_burst (cmdArbiter_io_output_payload_burst[1:0]), //o + .io_output_payload_lock (cmdArbiter_io_output_payload_lock ), //o + .io_output_payload_cache (cmdArbiter_io_output_payload_cache[3:0]), //o + .io_output_payload_prot (cmdArbiter_io_output_payload_prot[2:0] ), //o + .io_chosen (cmdArbiter_io_chosen ), //o + .io_chosenOH (cmdArbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + StreamFifoLowLatency_3 cmdRouteFork_translated_fifo ( + .io_push_valid (cmdRouteFork_translated_valid ), //i + .io_push_ready (cmdRouteFork_translated_fifo_io_push_ready ), //o + .io_push_payload (cmdRouteFork_translated_payload ), //i + .io_pop_valid (cmdRouteFork_translated_fifo_io_pop_valid ), //o + .io_pop_ready (cmdRouteFork_translated_fifo_io_pop_ready ), //i + .io_pop_payload (cmdRouteFork_translated_fifo_io_pop_payload ), //o + .io_flush (cmdRouteFork_translated_fifo_io_flush ), //i + .io_occupancy (cmdRouteFork_translated_fifo_io_occupancy[2:0] ), //o + .io_availability (cmdRouteFork_translated_fifo_io_availability[2:0]), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + always @(*) begin + case(cmdRouteFork_translated_fifo_io_pop_payload) + 1'b0 : begin + _zz_io_output_w_valid = io_inputs_0_w_valid; + _zz_io_output_w_payload_data = io_inputs_0_w_payload_data; + _zz_io_output_w_payload_strb = io_inputs_0_w_payload_strb; + _zz_io_output_w_payload_last = io_inputs_0_w_payload_last; + end + default : begin + _zz_io_output_w_valid = io_inputs_1_w_valid; + _zz_io_output_w_payload_data = io_inputs_1_w_payload_data; + _zz_io_output_w_payload_strb = io_inputs_1_w_payload_strb; + _zz_io_output_w_payload_last = io_inputs_1_w_payload_last; + end + endcase + end + + always @(*) begin + case(writeRspIndex) + 1'b0 : _zz_io_output_b_ready = io_inputs_0_b_ready; + default : _zz_io_output_b_ready = io_inputs_1_b_ready; + endcase + end + + assign io_inputs_0_aw_ready = cmdArbiter_io_inputs_0_ready; + assign io_inputs_1_aw_ready = cmdArbiter_io_inputs_1_ready; + always @(*) begin + cmdArbiter_io_output_ready = 1'b1; + if(when_Stream_l1020) begin + cmdArbiter_io_output_ready = 1'b0; + end + if(when_Stream_l1020_1) begin + cmdArbiter_io_output_ready = 1'b0; + end + end + + assign when_Stream_l1020 = ((! cmdOutputFork_ready) && axi4WriteOnlyArbiter_5_cmdArbiter_io_output_fork2_logic_linkEnable_0); + assign when_Stream_l1020_1 = ((! cmdRouteFork_ready) && axi4WriteOnlyArbiter_5_cmdArbiter_io_output_fork2_logic_linkEnable_1); + assign cmdOutputFork_valid = (cmdArbiter_io_output_valid && axi4WriteOnlyArbiter_5_cmdArbiter_io_output_fork2_logic_linkEnable_0); + assign cmdOutputFork_payload_addr = cmdArbiter_io_output_payload_addr; + assign cmdOutputFork_payload_id = cmdArbiter_io_output_payload_id; + assign cmdOutputFork_payload_len = cmdArbiter_io_output_payload_len; + assign cmdOutputFork_payload_size = cmdArbiter_io_output_payload_size; + assign cmdOutputFork_payload_burst = cmdArbiter_io_output_payload_burst; + assign cmdOutputFork_payload_lock = cmdArbiter_io_output_payload_lock; + assign cmdOutputFork_payload_cache = cmdArbiter_io_output_payload_cache; + assign cmdOutputFork_payload_prot = cmdArbiter_io_output_payload_prot; + assign cmdOutputFork_fire = (cmdOutputFork_valid && cmdOutputFork_ready); + assign cmdRouteFork_valid = (cmdArbiter_io_output_valid && axi4WriteOnlyArbiter_5_cmdArbiter_io_output_fork2_logic_linkEnable_1); + assign cmdRouteFork_payload_addr = cmdArbiter_io_output_payload_addr; + assign cmdRouteFork_payload_id = cmdArbiter_io_output_payload_id; + assign cmdRouteFork_payload_len = cmdArbiter_io_output_payload_len; + assign cmdRouteFork_payload_size = cmdArbiter_io_output_payload_size; + assign cmdRouteFork_payload_burst = cmdArbiter_io_output_payload_burst; + assign cmdRouteFork_payload_lock = cmdArbiter_io_output_payload_lock; + assign cmdRouteFork_payload_cache = cmdArbiter_io_output_payload_cache; + assign cmdRouteFork_payload_prot = cmdArbiter_io_output_payload_prot; + assign cmdRouteFork_fire = (cmdRouteFork_valid && cmdRouteFork_ready); + assign io_output_aw_valid = cmdOutputFork_valid; + assign cmdOutputFork_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdOutputFork_payload_addr; + assign io_output_aw_payload_len = cmdOutputFork_payload_len; + assign io_output_aw_payload_size = cmdOutputFork_payload_size; + assign io_output_aw_payload_burst = cmdOutputFork_payload_burst; + assign io_output_aw_payload_lock = cmdOutputFork_payload_lock; + assign io_output_aw_payload_cache = cmdOutputFork_payload_cache; + assign io_output_aw_payload_prot = cmdOutputFork_payload_prot; + assign io_output_aw_payload_id = {cmdArbiter_io_chosen,cmdArbiter_io_output_payload_id}; + assign cmdRouteFork_translated_valid = cmdRouteFork_valid; + assign cmdRouteFork_ready = cmdRouteFork_translated_ready; + assign cmdRouteFork_translated_payload = cmdArbiter_io_chosen; + assign cmdRouteFork_translated_ready = cmdRouteFork_translated_fifo_io_push_ready; + assign io_output_w_valid = (cmdRouteFork_translated_fifo_io_pop_valid && _zz_io_output_w_valid); + assign io_output_w_payload_data = _zz_io_output_w_payload_data; + assign io_output_w_payload_strb = _zz_io_output_w_payload_strb; + assign io_output_w_payload_last = _zz_io_output_w_payload_last; + assign io_inputs_0_w_ready = ((cmdRouteFork_translated_fifo_io_pop_valid && io_output_w_ready) && (cmdRouteFork_translated_fifo_io_pop_payload == 1'b0)); + assign io_inputs_1_w_ready = ((cmdRouteFork_translated_fifo_io_pop_valid && io_output_w_ready) && (cmdRouteFork_translated_fifo_io_pop_payload == 1'b1)); + assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); + assign cmdRouteFork_translated_fifo_io_pop_ready = (io_output_w_fire && io_output_w_payload_last); + assign writeRspIndex = io_output_b_payload_id[4 : 4]; + assign writeRspSels_0 = (writeRspIndex == 1'b0); + assign writeRspSels_1 = (writeRspIndex == 1'b1); + assign io_inputs_0_b_valid = (io_output_b_valid && writeRspSels_0); + assign io_inputs_0_b_payload_resp = io_output_b_payload_resp; + assign io_inputs_0_b_payload_id = io_output_b_payload_id[3 : 0]; + assign io_inputs_1_b_valid = (io_output_b_valid && writeRspSels_1); + assign io_inputs_1_b_payload_resp = io_output_b_payload_resp; + assign io_inputs_1_b_payload_id = io_output_b_payload_id[3 : 0]; + assign io_output_b_ready = _zz_io_output_b_ready; + assign cmdRouteFork_translated_fifo_io_flush = 1'b0; + always @(posedge clk or negedge resetn) begin + if(!resetn) begin + axi4WriteOnlyArbiter_5_cmdArbiter_io_output_fork2_logic_linkEnable_0 <= 1'b1; + axi4WriteOnlyArbiter_5_cmdArbiter_io_output_fork2_logic_linkEnable_1 <= 1'b1; + end else begin + if(cmdOutputFork_fire) begin + axi4WriteOnlyArbiter_5_cmdArbiter_io_output_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdRouteFork_fire) begin + axi4WriteOnlyArbiter_5_cmdArbiter_io_output_fork2_logic_linkEnable_1 <= 1'b0; + end + if(cmdArbiter_io_output_ready) begin + axi4WriteOnlyArbiter_5_cmdArbiter_io_output_fork2_logic_linkEnable_0 <= 1'b1; + axi4WriteOnlyArbiter_5_cmdArbiter_io_output_fork2_logic_linkEnable_1 <= 1'b1; + end + end + end + + +endmodule + +//Axi4ReadOnlyArbiter_1 replaced by Axi4ReadOnlyArbiter + +module Axi4WriteOnlyArbiter ( + input wire io_inputs_0_aw_valid, + output wire io_inputs_0_aw_ready, + input wire [31:0] io_inputs_0_aw_payload_addr, + input wire [3:0] io_inputs_0_aw_payload_id, + input wire [7:0] io_inputs_0_aw_payload_len, + input wire [2:0] io_inputs_0_aw_payload_size, + input wire [1:0] io_inputs_0_aw_payload_burst, + input wire [0:0] io_inputs_0_aw_payload_lock, + input wire [3:0] io_inputs_0_aw_payload_cache, + input wire [2:0] io_inputs_0_aw_payload_prot, + input wire io_inputs_0_w_valid, + output wire io_inputs_0_w_ready, + input wire [31:0] io_inputs_0_w_payload_data, + input wire [3:0] io_inputs_0_w_payload_strb, + input wire io_inputs_0_w_payload_last, + output wire io_inputs_0_b_valid, + input wire io_inputs_0_b_ready, + output wire [3:0] io_inputs_0_b_payload_id, + output wire [1:0] io_inputs_0_b_payload_resp, + input wire io_inputs_1_aw_valid, + output wire io_inputs_1_aw_ready, + input wire [31:0] io_inputs_1_aw_payload_addr, + input wire [3:0] io_inputs_1_aw_payload_id, + input wire [7:0] io_inputs_1_aw_payload_len, + input wire [2:0] io_inputs_1_aw_payload_size, + input wire [1:0] io_inputs_1_aw_payload_burst, + input wire [0:0] io_inputs_1_aw_payload_lock, + input wire [3:0] io_inputs_1_aw_payload_cache, + input wire [2:0] io_inputs_1_aw_payload_prot, + input wire io_inputs_1_w_valid, + output wire io_inputs_1_w_ready, + input wire [31:0] io_inputs_1_w_payload_data, + input wire [3:0] io_inputs_1_w_payload_strb, + input wire io_inputs_1_w_payload_last, + output wire io_inputs_1_b_valid, + input wire io_inputs_1_b_ready, + output wire [3:0] io_inputs_1_b_payload_id, + output wire [1:0] io_inputs_1_b_payload_resp, + output wire io_output_aw_valid, + input wire io_output_aw_ready, + output wire [31:0] io_output_aw_payload_addr, + output wire [4:0] io_output_aw_payload_id, + output wire [7:0] io_output_aw_payload_len, + output wire [2:0] io_output_aw_payload_size, + output wire [1:0] io_output_aw_payload_burst, + output wire [0:0] io_output_aw_payload_lock, + output wire [3:0] io_output_aw_payload_cache, + output wire [2:0] io_output_aw_payload_prot, + output wire io_output_w_valid, + input wire io_output_w_ready, + output wire [31:0] io_output_w_payload_data, + output wire [3:0] io_output_w_payload_strb, + output wire io_output_w_payload_last, + input wire io_output_b_valid, + output wire io_output_b_ready, + input wire [4:0] io_output_b_payload_id, + input wire [1:0] io_output_b_payload_resp, + input wire clk, + input wire resetn +); + + reg cmdArbiter_io_output_ready; + wire cmdRouteFork_translated_fifo_io_pop_ready; + wire cmdRouteFork_translated_fifo_io_flush; + wire cmdArbiter_io_inputs_0_ready; + wire cmdArbiter_io_inputs_1_ready; + wire cmdArbiter_io_output_valid; + wire [31:0] cmdArbiter_io_output_payload_addr; + wire [3:0] cmdArbiter_io_output_payload_id; + wire [7:0] cmdArbiter_io_output_payload_len; + wire [2:0] cmdArbiter_io_output_payload_size; + wire [1:0] cmdArbiter_io_output_payload_burst; + wire [0:0] cmdArbiter_io_output_payload_lock; + wire [3:0] cmdArbiter_io_output_payload_cache; + wire [2:0] cmdArbiter_io_output_payload_prot; + wire [0:0] cmdArbiter_io_chosen; + wire [1:0] cmdArbiter_io_chosenOH; + wire cmdRouteFork_translated_fifo_io_push_ready; + wire cmdRouteFork_translated_fifo_io_pop_valid; + wire [0:0] cmdRouteFork_translated_fifo_io_pop_payload; + wire [2:0] cmdRouteFork_translated_fifo_io_occupancy; + wire [2:0] cmdRouteFork_translated_fifo_io_availability; + reg _zz_io_output_w_valid; + reg [31:0] _zz_io_output_w_payload_data; + reg [3:0] _zz_io_output_w_payload_strb; + reg _zz_io_output_w_payload_last; + reg _zz_io_output_b_ready; + wire cmdOutputFork_valid; + wire cmdOutputFork_ready; + wire [31:0] cmdOutputFork_payload_addr; + wire [3:0] cmdOutputFork_payload_id; + wire [7:0] cmdOutputFork_payload_len; + wire [2:0] cmdOutputFork_payload_size; + wire [1:0] cmdOutputFork_payload_burst; + wire [0:0] cmdOutputFork_payload_lock; + wire [3:0] cmdOutputFork_payload_cache; + wire [2:0] cmdOutputFork_payload_prot; + wire cmdRouteFork_valid; + wire cmdRouteFork_ready; + wire [31:0] cmdRouteFork_payload_addr; + wire [3:0] cmdRouteFork_payload_id; + wire [7:0] cmdRouteFork_payload_len; + wire [2:0] cmdRouteFork_payload_size; + wire [1:0] cmdRouteFork_payload_burst; + wire [0:0] cmdRouteFork_payload_lock; + wire [3:0] cmdRouteFork_payload_cache; + wire [2:0] cmdRouteFork_payload_prot; + reg axi4WriteOnlyArbiter_4_cmdArbiter_io_output_fork2_logic_linkEnable_0; + reg axi4WriteOnlyArbiter_4_cmdArbiter_io_output_fork2_logic_linkEnable_1; + wire when_Stream_l1020; + wire when_Stream_l1020_1; + wire cmdOutputFork_fire; + wire cmdRouteFork_fire; + wire cmdRouteFork_translated_valid; + wire cmdRouteFork_translated_ready; + wire [0:0] cmdRouteFork_translated_payload; + wire io_output_w_fire; + wire [0:0] writeRspIndex; + wire writeRspSels_0; + wire writeRspSels_1; + + StreamArbiter_7 cmdArbiter ( + .io_inputs_0_valid (io_inputs_0_aw_valid ), //i + .io_inputs_0_ready (cmdArbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_addr (io_inputs_0_aw_payload_addr[31:0] ), //i + .io_inputs_0_payload_id (io_inputs_0_aw_payload_id[3:0] ), //i + .io_inputs_0_payload_len (io_inputs_0_aw_payload_len[7:0] ), //i + .io_inputs_0_payload_size (io_inputs_0_aw_payload_size[2:0] ), //i + .io_inputs_0_payload_burst (io_inputs_0_aw_payload_burst[1:0] ), //i + .io_inputs_0_payload_lock (io_inputs_0_aw_payload_lock ), //i + .io_inputs_0_payload_cache (io_inputs_0_aw_payload_cache[3:0] ), //i + .io_inputs_0_payload_prot (io_inputs_0_aw_payload_prot[2:0] ), //i + .io_inputs_1_valid (io_inputs_1_aw_valid ), //i + .io_inputs_1_ready (cmdArbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_addr (io_inputs_1_aw_payload_addr[31:0] ), //i + .io_inputs_1_payload_id (io_inputs_1_aw_payload_id[3:0] ), //i + .io_inputs_1_payload_len (io_inputs_1_aw_payload_len[7:0] ), //i + .io_inputs_1_payload_size (io_inputs_1_aw_payload_size[2:0] ), //i + .io_inputs_1_payload_burst (io_inputs_1_aw_payload_burst[1:0] ), //i + .io_inputs_1_payload_lock (io_inputs_1_aw_payload_lock ), //i + .io_inputs_1_payload_cache (io_inputs_1_aw_payload_cache[3:0] ), //i + .io_inputs_1_payload_prot (io_inputs_1_aw_payload_prot[2:0] ), //i + .io_output_valid (cmdArbiter_io_output_valid ), //o + .io_output_ready (cmdArbiter_io_output_ready ), //i + .io_output_payload_addr (cmdArbiter_io_output_payload_addr[31:0]), //o + .io_output_payload_id (cmdArbiter_io_output_payload_id[3:0] ), //o + .io_output_payload_len (cmdArbiter_io_output_payload_len[7:0] ), //o + .io_output_payload_size (cmdArbiter_io_output_payload_size[2:0] ), //o + .io_output_payload_burst (cmdArbiter_io_output_payload_burst[1:0]), //o + .io_output_payload_lock (cmdArbiter_io_output_payload_lock ), //o + .io_output_payload_cache (cmdArbiter_io_output_payload_cache[3:0]), //o + .io_output_payload_prot (cmdArbiter_io_output_payload_prot[2:0] ), //o + .io_chosen (cmdArbiter_io_chosen ), //o + .io_chosenOH (cmdArbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + StreamFifoLowLatency_3 cmdRouteFork_translated_fifo ( + .io_push_valid (cmdRouteFork_translated_valid ), //i + .io_push_ready (cmdRouteFork_translated_fifo_io_push_ready ), //o + .io_push_payload (cmdRouteFork_translated_payload ), //i + .io_pop_valid (cmdRouteFork_translated_fifo_io_pop_valid ), //o + .io_pop_ready (cmdRouteFork_translated_fifo_io_pop_ready ), //i + .io_pop_payload (cmdRouteFork_translated_fifo_io_pop_payload ), //o + .io_flush (cmdRouteFork_translated_fifo_io_flush ), //i + .io_occupancy (cmdRouteFork_translated_fifo_io_occupancy[2:0] ), //o + .io_availability (cmdRouteFork_translated_fifo_io_availability[2:0]), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + always @(*) begin + case(cmdRouteFork_translated_fifo_io_pop_payload) + 1'b0 : begin + _zz_io_output_w_valid = io_inputs_0_w_valid; + _zz_io_output_w_payload_data = io_inputs_0_w_payload_data; + _zz_io_output_w_payload_strb = io_inputs_0_w_payload_strb; + _zz_io_output_w_payload_last = io_inputs_0_w_payload_last; + end + default : begin + _zz_io_output_w_valid = io_inputs_1_w_valid; + _zz_io_output_w_payload_data = io_inputs_1_w_payload_data; + _zz_io_output_w_payload_strb = io_inputs_1_w_payload_strb; + _zz_io_output_w_payload_last = io_inputs_1_w_payload_last; + end + endcase + end + + always @(*) begin + case(writeRspIndex) + 1'b0 : _zz_io_output_b_ready = io_inputs_0_b_ready; + default : _zz_io_output_b_ready = io_inputs_1_b_ready; + endcase + end + + assign io_inputs_0_aw_ready = cmdArbiter_io_inputs_0_ready; + assign io_inputs_1_aw_ready = cmdArbiter_io_inputs_1_ready; + always @(*) begin + cmdArbiter_io_output_ready = 1'b1; + if(when_Stream_l1020) begin + cmdArbiter_io_output_ready = 1'b0; + end + if(when_Stream_l1020_1) begin + cmdArbiter_io_output_ready = 1'b0; + end + end + + assign when_Stream_l1020 = ((! cmdOutputFork_ready) && axi4WriteOnlyArbiter_4_cmdArbiter_io_output_fork2_logic_linkEnable_0); + assign when_Stream_l1020_1 = ((! cmdRouteFork_ready) && axi4WriteOnlyArbiter_4_cmdArbiter_io_output_fork2_logic_linkEnable_1); + assign cmdOutputFork_valid = (cmdArbiter_io_output_valid && axi4WriteOnlyArbiter_4_cmdArbiter_io_output_fork2_logic_linkEnable_0); + assign cmdOutputFork_payload_addr = cmdArbiter_io_output_payload_addr; + assign cmdOutputFork_payload_id = cmdArbiter_io_output_payload_id; + assign cmdOutputFork_payload_len = cmdArbiter_io_output_payload_len; + assign cmdOutputFork_payload_size = cmdArbiter_io_output_payload_size; + assign cmdOutputFork_payload_burst = cmdArbiter_io_output_payload_burst; + assign cmdOutputFork_payload_lock = cmdArbiter_io_output_payload_lock; + assign cmdOutputFork_payload_cache = cmdArbiter_io_output_payload_cache; + assign cmdOutputFork_payload_prot = cmdArbiter_io_output_payload_prot; + assign cmdOutputFork_fire = (cmdOutputFork_valid && cmdOutputFork_ready); + assign cmdRouteFork_valid = (cmdArbiter_io_output_valid && axi4WriteOnlyArbiter_4_cmdArbiter_io_output_fork2_logic_linkEnable_1); + assign cmdRouteFork_payload_addr = cmdArbiter_io_output_payload_addr; + assign cmdRouteFork_payload_id = cmdArbiter_io_output_payload_id; + assign cmdRouteFork_payload_len = cmdArbiter_io_output_payload_len; + assign cmdRouteFork_payload_size = cmdArbiter_io_output_payload_size; + assign cmdRouteFork_payload_burst = cmdArbiter_io_output_payload_burst; + assign cmdRouteFork_payload_lock = cmdArbiter_io_output_payload_lock; + assign cmdRouteFork_payload_cache = cmdArbiter_io_output_payload_cache; + assign cmdRouteFork_payload_prot = cmdArbiter_io_output_payload_prot; + assign cmdRouteFork_fire = (cmdRouteFork_valid && cmdRouteFork_ready); + assign io_output_aw_valid = cmdOutputFork_valid; + assign cmdOutputFork_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdOutputFork_payload_addr; + assign io_output_aw_payload_len = cmdOutputFork_payload_len; + assign io_output_aw_payload_size = cmdOutputFork_payload_size; + assign io_output_aw_payload_burst = cmdOutputFork_payload_burst; + assign io_output_aw_payload_lock = cmdOutputFork_payload_lock; + assign io_output_aw_payload_cache = cmdOutputFork_payload_cache; + assign io_output_aw_payload_prot = cmdOutputFork_payload_prot; + assign io_output_aw_payload_id = {cmdArbiter_io_chosen,cmdArbiter_io_output_payload_id}; + assign cmdRouteFork_translated_valid = cmdRouteFork_valid; + assign cmdRouteFork_ready = cmdRouteFork_translated_ready; + assign cmdRouteFork_translated_payload = cmdArbiter_io_chosen; + assign cmdRouteFork_translated_ready = cmdRouteFork_translated_fifo_io_push_ready; + assign io_output_w_valid = (cmdRouteFork_translated_fifo_io_pop_valid && _zz_io_output_w_valid); + assign io_output_w_payload_data = _zz_io_output_w_payload_data; + assign io_output_w_payload_strb = _zz_io_output_w_payload_strb; + assign io_output_w_payload_last = _zz_io_output_w_payload_last; + assign io_inputs_0_w_ready = ((cmdRouteFork_translated_fifo_io_pop_valid && io_output_w_ready) && (cmdRouteFork_translated_fifo_io_pop_payload == 1'b0)); + assign io_inputs_1_w_ready = ((cmdRouteFork_translated_fifo_io_pop_valid && io_output_w_ready) && (cmdRouteFork_translated_fifo_io_pop_payload == 1'b1)); + assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); + assign cmdRouteFork_translated_fifo_io_pop_ready = (io_output_w_fire && io_output_w_payload_last); + assign writeRspIndex = io_output_b_payload_id[4 : 4]; + assign writeRspSels_0 = (writeRspIndex == 1'b0); + assign writeRspSels_1 = (writeRspIndex == 1'b1); + assign io_inputs_0_b_valid = (io_output_b_valid && writeRspSels_0); + assign io_inputs_0_b_payload_resp = io_output_b_payload_resp; + assign io_inputs_0_b_payload_id = io_output_b_payload_id[3 : 0]; + assign io_inputs_1_b_valid = (io_output_b_valid && writeRspSels_1); + assign io_inputs_1_b_payload_resp = io_output_b_payload_resp; + assign io_inputs_1_b_payload_id = io_output_b_payload_id[3 : 0]; + assign io_output_b_ready = _zz_io_output_b_ready; + assign cmdRouteFork_translated_fifo_io_flush = 1'b0; + always @(posedge clk or negedge resetn) begin + if(!resetn) begin + axi4WriteOnlyArbiter_4_cmdArbiter_io_output_fork2_logic_linkEnable_0 <= 1'b1; + axi4WriteOnlyArbiter_4_cmdArbiter_io_output_fork2_logic_linkEnable_1 <= 1'b1; + end else begin + if(cmdOutputFork_fire) begin + axi4WriteOnlyArbiter_4_cmdArbiter_io_output_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdRouteFork_fire) begin + axi4WriteOnlyArbiter_4_cmdArbiter_io_output_fork2_logic_linkEnable_1 <= 1'b0; + end + if(cmdArbiter_io_output_ready) begin + axi4WriteOnlyArbiter_4_cmdArbiter_io_output_fork2_logic_linkEnable_0 <= 1'b1; + axi4WriteOnlyArbiter_4_cmdArbiter_io_output_fork2_logic_linkEnable_1 <= 1'b1; + end + end + end + + +endmodule + +module Axi4ReadOnlyArbiter ( + input wire io_inputs_0_ar_valid, + output wire io_inputs_0_ar_ready, + input wire [31:0] io_inputs_0_ar_payload_addr, + input wire [3:0] io_inputs_0_ar_payload_id, + input wire [7:0] io_inputs_0_ar_payload_len, + input wire [2:0] io_inputs_0_ar_payload_size, + input wire [1:0] io_inputs_0_ar_payload_burst, + input wire [0:0] io_inputs_0_ar_payload_lock, + input wire [3:0] io_inputs_0_ar_payload_cache, + input wire [2:0] io_inputs_0_ar_payload_prot, + output wire io_inputs_0_r_valid, + input wire io_inputs_0_r_ready, + output wire [31:0] io_inputs_0_r_payload_data, + output wire [3:0] io_inputs_0_r_payload_id, + output wire [1:0] io_inputs_0_r_payload_resp, + output wire io_inputs_0_r_payload_last, + input wire io_inputs_1_ar_valid, + output wire io_inputs_1_ar_ready, + input wire [31:0] io_inputs_1_ar_payload_addr, + input wire [3:0] io_inputs_1_ar_payload_id, + input wire [7:0] io_inputs_1_ar_payload_len, + input wire [2:0] io_inputs_1_ar_payload_size, + input wire [1:0] io_inputs_1_ar_payload_burst, + input wire [0:0] io_inputs_1_ar_payload_lock, + input wire [3:0] io_inputs_1_ar_payload_cache, + input wire [2:0] io_inputs_1_ar_payload_prot, + output wire io_inputs_1_r_valid, + input wire io_inputs_1_r_ready, + output wire [31:0] io_inputs_1_r_payload_data, + output wire [3:0] io_inputs_1_r_payload_id, + output wire [1:0] io_inputs_1_r_payload_resp, + output wire io_inputs_1_r_payload_last, + output wire io_output_ar_valid, + input wire io_output_ar_ready, + output wire [31:0] io_output_ar_payload_addr, + output wire [4:0] io_output_ar_payload_id, + output wire [7:0] io_output_ar_payload_len, + output wire [2:0] io_output_ar_payload_size, + output wire [1:0] io_output_ar_payload_burst, + output wire [0:0] io_output_ar_payload_lock, + output wire [3:0] io_output_ar_payload_cache, + output wire [2:0] io_output_ar_payload_prot, + input wire io_output_r_valid, + output wire io_output_r_ready, + input wire [31:0] io_output_r_payload_data, + input wire [4:0] io_output_r_payload_id, + input wire [1:0] io_output_r_payload_resp, + input wire io_output_r_payload_last, + input wire clk, + input wire resetn +); + + wire cmdArbiter_io_inputs_0_ready; + wire cmdArbiter_io_inputs_1_ready; + wire cmdArbiter_io_output_valid; + wire [31:0] cmdArbiter_io_output_payload_addr; + wire [3:0] cmdArbiter_io_output_payload_id; + wire [7:0] cmdArbiter_io_output_payload_len; + wire [2:0] cmdArbiter_io_output_payload_size; + wire [1:0] cmdArbiter_io_output_payload_burst; + wire [0:0] cmdArbiter_io_output_payload_lock; + wire [3:0] cmdArbiter_io_output_payload_cache; + wire [2:0] cmdArbiter_io_output_payload_prot; + wire [0:0] cmdArbiter_io_chosen; + wire [1:0] cmdArbiter_io_chosenOH; + reg _zz_io_output_r_ready; + wire [0:0] readRspIndex; + wire readRspSels_0; + wire readRspSels_1; + + StreamArbiter_7 cmdArbiter ( + .io_inputs_0_valid (io_inputs_0_ar_valid ), //i + .io_inputs_0_ready (cmdArbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_addr (io_inputs_0_ar_payload_addr[31:0] ), //i + .io_inputs_0_payload_id (io_inputs_0_ar_payload_id[3:0] ), //i + .io_inputs_0_payload_len (io_inputs_0_ar_payload_len[7:0] ), //i + .io_inputs_0_payload_size (io_inputs_0_ar_payload_size[2:0] ), //i + .io_inputs_0_payload_burst (io_inputs_0_ar_payload_burst[1:0] ), //i + .io_inputs_0_payload_lock (io_inputs_0_ar_payload_lock ), //i + .io_inputs_0_payload_cache (io_inputs_0_ar_payload_cache[3:0] ), //i + .io_inputs_0_payload_prot (io_inputs_0_ar_payload_prot[2:0] ), //i + .io_inputs_1_valid (io_inputs_1_ar_valid ), //i + .io_inputs_1_ready (cmdArbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_addr (io_inputs_1_ar_payload_addr[31:0] ), //i + .io_inputs_1_payload_id (io_inputs_1_ar_payload_id[3:0] ), //i + .io_inputs_1_payload_len (io_inputs_1_ar_payload_len[7:0] ), //i + .io_inputs_1_payload_size (io_inputs_1_ar_payload_size[2:0] ), //i + .io_inputs_1_payload_burst (io_inputs_1_ar_payload_burst[1:0] ), //i + .io_inputs_1_payload_lock (io_inputs_1_ar_payload_lock ), //i + .io_inputs_1_payload_cache (io_inputs_1_ar_payload_cache[3:0] ), //i + .io_inputs_1_payload_prot (io_inputs_1_ar_payload_prot[2:0] ), //i + .io_output_valid (cmdArbiter_io_output_valid ), //o + .io_output_ready (io_output_ar_ready ), //i + .io_output_payload_addr (cmdArbiter_io_output_payload_addr[31:0]), //o + .io_output_payload_id (cmdArbiter_io_output_payload_id[3:0] ), //o + .io_output_payload_len (cmdArbiter_io_output_payload_len[7:0] ), //o + .io_output_payload_size (cmdArbiter_io_output_payload_size[2:0] ), //o + .io_output_payload_burst (cmdArbiter_io_output_payload_burst[1:0]), //o + .io_output_payload_lock (cmdArbiter_io_output_payload_lock ), //o + .io_output_payload_cache (cmdArbiter_io_output_payload_cache[3:0]), //o + .io_output_payload_prot (cmdArbiter_io_output_payload_prot[2:0] ), //o + .io_chosen (cmdArbiter_io_chosen ), //o + .io_chosenOH (cmdArbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + always @(*) begin + case(readRspIndex) + 1'b0 : _zz_io_output_r_ready = io_inputs_0_r_ready; + default : _zz_io_output_r_ready = io_inputs_1_r_ready; + endcase + end + + assign io_inputs_0_ar_ready = cmdArbiter_io_inputs_0_ready; + assign io_inputs_1_ar_ready = cmdArbiter_io_inputs_1_ready; + assign io_output_ar_valid = cmdArbiter_io_output_valid; + assign io_output_ar_payload_addr = cmdArbiter_io_output_payload_addr; + assign io_output_ar_payload_len = cmdArbiter_io_output_payload_len; + assign io_output_ar_payload_size = cmdArbiter_io_output_payload_size; + assign io_output_ar_payload_burst = cmdArbiter_io_output_payload_burst; + assign io_output_ar_payload_lock = cmdArbiter_io_output_payload_lock; + assign io_output_ar_payload_cache = cmdArbiter_io_output_payload_cache; + assign io_output_ar_payload_prot = cmdArbiter_io_output_payload_prot; + assign io_output_ar_payload_id = {cmdArbiter_io_chosen,cmdArbiter_io_output_payload_id}; + assign readRspIndex = io_output_r_payload_id[4 : 4]; + assign readRspSels_0 = (readRspIndex == 1'b0); + assign readRspSels_1 = (readRspIndex == 1'b1); + assign io_inputs_0_r_valid = (io_output_r_valid && readRspSels_0); + assign io_inputs_0_r_payload_data = io_output_r_payload_data; + assign io_inputs_0_r_payload_resp = io_output_r_payload_resp; + assign io_inputs_0_r_payload_last = io_output_r_payload_last; + assign io_inputs_0_r_payload_id = io_output_r_payload_id[3 : 0]; + assign io_inputs_1_r_valid = (io_output_r_valid && readRspSels_1); + assign io_inputs_1_r_payload_data = io_output_r_payload_data; + assign io_inputs_1_r_payload_resp = io_output_r_payload_resp; + assign io_inputs_1_r_payload_last = io_output_r_payload_last; + assign io_inputs_1_r_payload_id = io_output_r_payload_id[3 : 0]; + assign io_output_r_ready = _zz_io_output_r_ready; + +endmodule + +module Axi4WriteOnlyDecoder_1 ( + input wire io_input_aw_valid, + output wire io_input_aw_ready, + input wire [31:0] io_input_aw_payload_addr, + input wire [3:0] io_input_aw_payload_id, + input wire [7:0] io_input_aw_payload_len, + input wire [2:0] io_input_aw_payload_size, + input wire [1:0] io_input_aw_payload_burst, + input wire [0:0] io_input_aw_payload_lock, + input wire [3:0] io_input_aw_payload_cache, + input wire [2:0] io_input_aw_payload_prot, + input wire io_input_w_valid, + output wire io_input_w_ready, + input wire [31:0] io_input_w_payload_data, + input wire [3:0] io_input_w_payload_strb, + input wire io_input_w_payload_last, + output wire io_input_b_valid, + input wire io_input_b_ready, + output reg [3:0] io_input_b_payload_id, + output reg [1:0] io_input_b_payload_resp, + output wire io_outputs_0_aw_valid, + input wire io_outputs_0_aw_ready, + output wire [31:0] io_outputs_0_aw_payload_addr, + output wire [3:0] io_outputs_0_aw_payload_id, + output wire [7:0] io_outputs_0_aw_payload_len, + output wire [2:0] io_outputs_0_aw_payload_size, + output wire [1:0] io_outputs_0_aw_payload_burst, + output wire [0:0] io_outputs_0_aw_payload_lock, + output wire [3:0] io_outputs_0_aw_payload_cache, + output wire [2:0] io_outputs_0_aw_payload_prot, + output wire io_outputs_0_w_valid, + input wire io_outputs_0_w_ready, + output wire [31:0] io_outputs_0_w_payload_data, + output wire [3:0] io_outputs_0_w_payload_strb, + output wire io_outputs_0_w_payload_last, + input wire io_outputs_0_b_valid, + output wire io_outputs_0_b_ready, + input wire [3:0] io_outputs_0_b_payload_id, + input wire [1:0] io_outputs_0_b_payload_resp, + output wire io_outputs_1_aw_valid, + input wire io_outputs_1_aw_ready, + output wire [31:0] io_outputs_1_aw_payload_addr, + output wire [3:0] io_outputs_1_aw_payload_id, + output wire [7:0] io_outputs_1_aw_payload_len, + output wire [2:0] io_outputs_1_aw_payload_size, + output wire [1:0] io_outputs_1_aw_payload_burst, + output wire [0:0] io_outputs_1_aw_payload_lock, + output wire [3:0] io_outputs_1_aw_payload_cache, + output wire [2:0] io_outputs_1_aw_payload_prot, + output wire io_outputs_1_w_valid, + input wire io_outputs_1_w_ready, + output wire [31:0] io_outputs_1_w_payload_data, + output wire [3:0] io_outputs_1_w_payload_strb, + output wire io_outputs_1_w_payload_last, + input wire io_outputs_1_b_valid, + output wire io_outputs_1_b_ready, + input wire [3:0] io_outputs_1_b_payload_id, + input wire [1:0] io_outputs_1_b_payload_resp, + output wire io_outputs_2_aw_valid, + input wire io_outputs_2_aw_ready, + output wire [31:0] io_outputs_2_aw_payload_addr, + output wire [3:0] io_outputs_2_aw_payload_id, + output wire [7:0] io_outputs_2_aw_payload_len, + output wire [2:0] io_outputs_2_aw_payload_size, + output wire [1:0] io_outputs_2_aw_payload_burst, + output wire [0:0] io_outputs_2_aw_payload_lock, + output wire [3:0] io_outputs_2_aw_payload_cache, + output wire [2:0] io_outputs_2_aw_payload_prot, + output wire io_outputs_2_w_valid, + input wire io_outputs_2_w_ready, + output wire [31:0] io_outputs_2_w_payload_data, + output wire [3:0] io_outputs_2_w_payload_strb, + output wire io_outputs_2_w_payload_last, + input wire io_outputs_2_b_valid, + output wire io_outputs_2_b_ready, + input wire [3:0] io_outputs_2_b_payload_id, + input wire [1:0] io_outputs_2_b_payload_resp, + output wire io_outputs_3_aw_valid, + input wire io_outputs_3_aw_ready, + output wire [31:0] io_outputs_3_aw_payload_addr, + output wire [3:0] io_outputs_3_aw_payload_id, + output wire [7:0] io_outputs_3_aw_payload_len, + output wire [2:0] io_outputs_3_aw_payload_size, + output wire [1:0] io_outputs_3_aw_payload_burst, + output wire [0:0] io_outputs_3_aw_payload_lock, + output wire [3:0] io_outputs_3_aw_payload_cache, + output wire [2:0] io_outputs_3_aw_payload_prot, + output wire io_outputs_3_w_valid, + input wire io_outputs_3_w_ready, + output wire [31:0] io_outputs_3_w_payload_data, + output wire [3:0] io_outputs_3_w_payload_strb, + output wire io_outputs_3_w_payload_last, + input wire io_outputs_3_b_valid, + output wire io_outputs_3_b_ready, + input wire [3:0] io_outputs_3_b_payload_id, + input wire [1:0] io_outputs_3_b_payload_resp, + input wire clk, + input wire resetn +); + + wire errorSlave_io_axi_aw_valid; + wire errorSlave_io_axi_w_valid; + wire errorSlave_io_axi_aw_ready; + wire errorSlave_io_axi_w_ready; + wire errorSlave_io_axi_b_valid; + wire [3:0] errorSlave_io_axi_b_payload_id; + wire [1:0] errorSlave_io_axi_b_payload_resp; + wire [31:0] _zz_decodedCmdSels; + wire [31:0] _zz_decodedCmdSels_1; + wire [31:0] _zz_decodedCmdSels_2; + wire [31:0] _zz_decodedCmdSels_3; + wire [31:0] _zz_decodedCmdSels_4; + wire [31:0] _zz_decodedCmdSels_5; + reg [3:0] _zz_io_input_b_payload_id; + reg [1:0] _zz_io_input_b_payload_resp; + wire cmdAllowedStart; + wire io_input_aw_fire; + wire io_input_b_fire; + reg pendingCmdCounter_incrementIt; + reg pendingCmdCounter_decrementIt; + wire [2:0] pendingCmdCounter_valueNext; + reg [2:0] pendingCmdCounter_value; + wire pendingCmdCounter_mayOverflow; + wire pendingCmdCounter_willOverflowIfInc; + wire pendingCmdCounter_willOverflow; + reg [2:0] pendingCmdCounter_finalIncrement; + wire when_Utils_l723; + wire when_Utils_l725; + wire io_input_w_fire; + wire when_Utils_l697; + reg pendingDataCounter_incrementIt; + reg pendingDataCounter_decrementIt; + wire [2:0] pendingDataCounter_valueNext; + reg [2:0] pendingDataCounter_value; + wire pendingDataCounter_mayOverflow; + wire pendingDataCounter_willOverflowIfInc; + wire pendingDataCounter_willOverflow; + reg [2:0] pendingDataCounter_finalIncrement; + wire when_Utils_l723_1; + wire when_Utils_l725_1; + wire [3:0] decodedCmdSels; + wire decodedCmdError; + reg [3:0] pendingSels; + reg pendingError; + wire allowCmd; + wire allowData; + reg _zz_cmdAllowedStart; + wire _zz_io_outputs_1_w_valid; + wire _zz_io_outputs_2_w_valid; + wire _zz_io_outputs_3_w_valid; + wire _zz_writeRspIndex; + wire _zz_writeRspIndex_1; + wire [1:0] writeRspIndex; + + assign _zz_decodedCmdSels = 32'h000fffff; + assign _zz_decodedCmdSels_1 = (~ 32'h000fffff); + assign _zz_decodedCmdSels_2 = (io_input_aw_payload_addr & (~ 32'h007fffff)); + assign _zz_decodedCmdSels_3 = 32'h00000000; + assign _zz_decodedCmdSels_4 = (io_input_aw_payload_addr & (~ 32'h007fffff)); + assign _zz_decodedCmdSels_5 = 32'h1c000000; + Axi4WriteOnlyErrorSlave_1 errorSlave ( + .io_axi_aw_valid (errorSlave_io_axi_aw_valid ), //i + .io_axi_aw_ready (errorSlave_io_axi_aw_ready ), //o + .io_axi_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i + .io_axi_aw_payload_id (io_input_aw_payload_id[3:0] ), //i + .io_axi_aw_payload_len (io_input_aw_payload_len[7:0] ), //i + .io_axi_aw_payload_size (io_input_aw_payload_size[2:0] ), //i + .io_axi_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i + .io_axi_aw_payload_lock (io_input_aw_payload_lock ), //i + .io_axi_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i + .io_axi_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i + .io_axi_w_valid (errorSlave_io_axi_w_valid ), //i + .io_axi_w_ready (errorSlave_io_axi_w_ready ), //o + .io_axi_w_payload_data (io_input_w_payload_data[31:0] ), //i + .io_axi_w_payload_strb (io_input_w_payload_strb[3:0] ), //i + .io_axi_w_payload_last (io_input_w_payload_last ), //i + .io_axi_b_valid (errorSlave_io_axi_b_valid ), //o + .io_axi_b_ready (io_input_b_ready ), //i + .io_axi_b_payload_id (errorSlave_io_axi_b_payload_id[3:0] ), //o + .io_axi_b_payload_resp (errorSlave_io_axi_b_payload_resp[1:0]), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + always @(*) begin + case(writeRspIndex) + 2'b00 : begin + _zz_io_input_b_payload_id = io_outputs_0_b_payload_id; + _zz_io_input_b_payload_resp = io_outputs_0_b_payload_resp; + end + 2'b01 : begin + _zz_io_input_b_payload_id = io_outputs_1_b_payload_id; + _zz_io_input_b_payload_resp = io_outputs_1_b_payload_resp; + end + 2'b10 : begin + _zz_io_input_b_payload_id = io_outputs_2_b_payload_id; + _zz_io_input_b_payload_resp = io_outputs_2_b_payload_resp; + end + default : begin + _zz_io_input_b_payload_id = io_outputs_3_b_payload_id; + _zz_io_input_b_payload_resp = io_outputs_3_b_payload_resp; + end + endcase + end + + assign io_input_aw_fire = (io_input_aw_valid && io_input_aw_ready); + assign io_input_b_fire = (io_input_b_valid && io_input_b_ready); + always @(*) begin + pendingCmdCounter_incrementIt = 1'b0; + if(io_input_aw_fire) begin + pendingCmdCounter_incrementIt = 1'b1; + end + end + + always @(*) begin + pendingCmdCounter_decrementIt = 1'b0; + if(io_input_b_fire) begin + pendingCmdCounter_decrementIt = 1'b1; + end + end + + assign pendingCmdCounter_mayOverflow = (pendingCmdCounter_value == 3'b111); + assign pendingCmdCounter_willOverflowIfInc = (pendingCmdCounter_mayOverflow && (! pendingCmdCounter_decrementIt)); + assign pendingCmdCounter_willOverflow = (pendingCmdCounter_willOverflowIfInc && pendingCmdCounter_incrementIt); + assign when_Utils_l723 = (pendingCmdCounter_incrementIt && (! pendingCmdCounter_decrementIt)); + always @(*) begin + if(when_Utils_l723) begin + pendingCmdCounter_finalIncrement = 3'b001; + end else begin + if(when_Utils_l725) begin + pendingCmdCounter_finalIncrement = 3'b111; + end else begin + pendingCmdCounter_finalIncrement = 3'b000; + end + end + end + + assign when_Utils_l725 = ((! pendingCmdCounter_incrementIt) && pendingCmdCounter_decrementIt); + assign pendingCmdCounter_valueNext = (pendingCmdCounter_value + pendingCmdCounter_finalIncrement); + assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); + assign when_Utils_l697 = (io_input_w_fire && io_input_w_payload_last); + always @(*) begin + pendingDataCounter_incrementIt = 1'b0; + if(cmdAllowedStart) begin + pendingDataCounter_incrementIt = 1'b1; + end + end + + always @(*) begin + pendingDataCounter_decrementIt = 1'b0; + if(when_Utils_l697) begin + pendingDataCounter_decrementIt = 1'b1; + end + end + + assign pendingDataCounter_mayOverflow = (pendingDataCounter_value == 3'b111); + assign pendingDataCounter_willOverflowIfInc = (pendingDataCounter_mayOverflow && (! pendingDataCounter_decrementIt)); + assign pendingDataCounter_willOverflow = (pendingDataCounter_willOverflowIfInc && pendingDataCounter_incrementIt); + assign when_Utils_l723_1 = (pendingDataCounter_incrementIt && (! pendingDataCounter_decrementIt)); + always @(*) begin + if(when_Utils_l723_1) begin + pendingDataCounter_finalIncrement = 3'b001; + end else begin + if(when_Utils_l725_1) begin + pendingDataCounter_finalIncrement = 3'b111; + end else begin + pendingDataCounter_finalIncrement = 3'b000; + end + end + end + + assign when_Utils_l725_1 = ((! pendingDataCounter_incrementIt) && pendingDataCounter_decrementIt); + assign pendingDataCounter_valueNext = (pendingDataCounter_value + pendingDataCounter_finalIncrement); + assign decodedCmdSels = {(((io_input_aw_payload_addr & (~ _zz_decodedCmdSels)) == 32'h1f500000) && io_input_aw_valid),{(((io_input_aw_payload_addr & _zz_decodedCmdSels_1) == 32'h1f400000) && io_input_aw_valid),{((_zz_decodedCmdSels_2 == _zz_decodedCmdSels_3) && io_input_aw_valid),((_zz_decodedCmdSels_4 == _zz_decodedCmdSels_5) && io_input_aw_valid)}}}; + assign decodedCmdError = (decodedCmdSels == 4'b0000); + assign allowCmd = ((pendingCmdCounter_value == 3'b000) || ((pendingCmdCounter_value != 3'b111) && (pendingSels == decodedCmdSels))); + assign allowData = (pendingDataCounter_value != 3'b000); + assign cmdAllowedStart = ((io_input_aw_valid && allowCmd) && _zz_cmdAllowedStart); + assign io_input_aw_ready = (((|(decodedCmdSels & {io_outputs_3_aw_ready,{io_outputs_2_aw_ready,{io_outputs_1_aw_ready,io_outputs_0_aw_ready}}})) || (decodedCmdError && errorSlave_io_axi_aw_ready)) && allowCmd); + assign errorSlave_io_axi_aw_valid = ((io_input_aw_valid && decodedCmdError) && allowCmd); + assign io_outputs_0_aw_valid = ((io_input_aw_valid && decodedCmdSels[0]) && allowCmd); + assign io_outputs_0_aw_payload_addr = io_input_aw_payload_addr; + assign io_outputs_0_aw_payload_id = io_input_aw_payload_id; + assign io_outputs_0_aw_payload_len = io_input_aw_payload_len; + assign io_outputs_0_aw_payload_size = io_input_aw_payload_size; + assign io_outputs_0_aw_payload_burst = io_input_aw_payload_burst; + assign io_outputs_0_aw_payload_lock = io_input_aw_payload_lock; + assign io_outputs_0_aw_payload_cache = io_input_aw_payload_cache; + assign io_outputs_0_aw_payload_prot = io_input_aw_payload_prot; + assign io_outputs_1_aw_valid = ((io_input_aw_valid && decodedCmdSels[1]) && allowCmd); + assign io_outputs_1_aw_payload_addr = io_input_aw_payload_addr; + assign io_outputs_1_aw_payload_id = io_input_aw_payload_id; + assign io_outputs_1_aw_payload_len = io_input_aw_payload_len; + assign io_outputs_1_aw_payload_size = io_input_aw_payload_size; + assign io_outputs_1_aw_payload_burst = io_input_aw_payload_burst; + assign io_outputs_1_aw_payload_lock = io_input_aw_payload_lock; + assign io_outputs_1_aw_payload_cache = io_input_aw_payload_cache; + assign io_outputs_1_aw_payload_prot = io_input_aw_payload_prot; + assign io_outputs_2_aw_valid = ((io_input_aw_valid && decodedCmdSels[2]) && allowCmd); + assign io_outputs_2_aw_payload_addr = io_input_aw_payload_addr; + assign io_outputs_2_aw_payload_id = io_input_aw_payload_id; + assign io_outputs_2_aw_payload_len = io_input_aw_payload_len; + assign io_outputs_2_aw_payload_size = io_input_aw_payload_size; + assign io_outputs_2_aw_payload_burst = io_input_aw_payload_burst; + assign io_outputs_2_aw_payload_lock = io_input_aw_payload_lock; + assign io_outputs_2_aw_payload_cache = io_input_aw_payload_cache; + assign io_outputs_2_aw_payload_prot = io_input_aw_payload_prot; + assign io_outputs_3_aw_valid = ((io_input_aw_valid && decodedCmdSels[3]) && allowCmd); + assign io_outputs_3_aw_payload_addr = io_input_aw_payload_addr; + assign io_outputs_3_aw_payload_id = io_input_aw_payload_id; + assign io_outputs_3_aw_payload_len = io_input_aw_payload_len; + assign io_outputs_3_aw_payload_size = io_input_aw_payload_size; + assign io_outputs_3_aw_payload_burst = io_input_aw_payload_burst; + assign io_outputs_3_aw_payload_lock = io_input_aw_payload_lock; + assign io_outputs_3_aw_payload_cache = io_input_aw_payload_cache; + assign io_outputs_3_aw_payload_prot = io_input_aw_payload_prot; + assign io_input_w_ready = (((|(pendingSels & {io_outputs_3_w_ready,{io_outputs_2_w_ready,{io_outputs_1_w_ready,io_outputs_0_w_ready}}})) || (pendingError && errorSlave_io_axi_w_ready)) && allowData); + assign errorSlave_io_axi_w_valid = ((io_input_w_valid && pendingError) && allowData); + assign _zz_io_outputs_1_w_valid = pendingSels[1]; + assign _zz_io_outputs_2_w_valid = pendingSels[2]; + assign _zz_io_outputs_3_w_valid = pendingSels[3]; + assign io_outputs_0_w_valid = ((io_input_w_valid && pendingSels[0]) && allowData); + assign io_outputs_0_w_payload_data = io_input_w_payload_data; + assign io_outputs_0_w_payload_strb = io_input_w_payload_strb; + assign io_outputs_0_w_payload_last = io_input_w_payload_last; + assign io_outputs_1_w_valid = ((io_input_w_valid && _zz_io_outputs_1_w_valid) && allowData); + assign io_outputs_1_w_payload_data = io_input_w_payload_data; + assign io_outputs_1_w_payload_strb = io_input_w_payload_strb; + assign io_outputs_1_w_payload_last = io_input_w_payload_last; + assign io_outputs_2_w_valid = ((io_input_w_valid && _zz_io_outputs_2_w_valid) && allowData); + assign io_outputs_2_w_payload_data = io_input_w_payload_data; + assign io_outputs_2_w_payload_strb = io_input_w_payload_strb; + assign io_outputs_2_w_payload_last = io_input_w_payload_last; + assign io_outputs_3_w_valid = ((io_input_w_valid && _zz_io_outputs_3_w_valid) && allowData); + assign io_outputs_3_w_payload_data = io_input_w_payload_data; + assign io_outputs_3_w_payload_strb = io_input_w_payload_strb; + assign io_outputs_3_w_payload_last = io_input_w_payload_last; + assign _zz_writeRspIndex = (_zz_io_outputs_1_w_valid || _zz_io_outputs_3_w_valid); + assign _zz_writeRspIndex_1 = (_zz_io_outputs_2_w_valid || _zz_io_outputs_3_w_valid); + assign writeRspIndex = {_zz_writeRspIndex_1,_zz_writeRspIndex}; + assign io_input_b_valid = ((|{io_outputs_3_b_valid,{io_outputs_2_b_valid,{io_outputs_1_b_valid,io_outputs_0_b_valid}}}) || errorSlave_io_axi_b_valid); + always @(*) begin + io_input_b_payload_id = _zz_io_input_b_payload_id; + if(pendingError) begin + io_input_b_payload_id = errorSlave_io_axi_b_payload_id; + end + end + + always @(*) begin + io_input_b_payload_resp = _zz_io_input_b_payload_resp; + if(pendingError) begin + io_input_b_payload_resp = errorSlave_io_axi_b_payload_resp; + end + end + + assign io_outputs_0_b_ready = io_input_b_ready; + assign io_outputs_1_b_ready = io_input_b_ready; + assign io_outputs_2_b_ready = io_input_b_ready; + assign io_outputs_3_b_ready = io_input_b_ready; + always @(posedge clk or negedge resetn) begin + if(!resetn) begin + pendingCmdCounter_value <= 3'b000; + pendingDataCounter_value <= 3'b000; + pendingSels <= 4'b0000; + pendingError <= 1'b0; + _zz_cmdAllowedStart <= 1'b1; + end else begin + pendingCmdCounter_value <= pendingCmdCounter_valueNext; + pendingDataCounter_value <= pendingDataCounter_valueNext; + if(cmdAllowedStart) begin + pendingSels <= decodedCmdSels; + end + if(cmdAllowedStart) begin + pendingError <= decodedCmdError; + end + if(cmdAllowedStart) begin + _zz_cmdAllowedStart <= 1'b0; + end + if(io_input_aw_ready) begin + _zz_cmdAllowedStart <= 1'b1; + end + end + end + + +endmodule + +module Axi4ReadOnlyDecoder_1 ( + input wire io_input_ar_valid, + output wire io_input_ar_ready, + input wire [31:0] io_input_ar_payload_addr, + input wire [3:0] io_input_ar_payload_id, + input wire [7:0] io_input_ar_payload_len, + input wire [2:0] io_input_ar_payload_size, + input wire [1:0] io_input_ar_payload_burst, + input wire [0:0] io_input_ar_payload_lock, + input wire [3:0] io_input_ar_payload_cache, + input wire [2:0] io_input_ar_payload_prot, + output reg io_input_r_valid, + input wire io_input_r_ready, + output wire [31:0] io_input_r_payload_data, + output reg [3:0] io_input_r_payload_id, + output reg [1:0] io_input_r_payload_resp, + output reg io_input_r_payload_last, + output wire io_outputs_0_ar_valid, + input wire io_outputs_0_ar_ready, + output wire [31:0] io_outputs_0_ar_payload_addr, + output wire [3:0] io_outputs_0_ar_payload_id, + output wire [7:0] io_outputs_0_ar_payload_len, + output wire [2:0] io_outputs_0_ar_payload_size, + output wire [1:0] io_outputs_0_ar_payload_burst, + output wire [0:0] io_outputs_0_ar_payload_lock, + output wire [3:0] io_outputs_0_ar_payload_cache, + output wire [2:0] io_outputs_0_ar_payload_prot, + input wire io_outputs_0_r_valid, + output wire io_outputs_0_r_ready, + input wire [31:0] io_outputs_0_r_payload_data, + input wire [3:0] io_outputs_0_r_payload_id, + input wire [1:0] io_outputs_0_r_payload_resp, + input wire io_outputs_0_r_payload_last, + output wire io_outputs_1_ar_valid, + input wire io_outputs_1_ar_ready, + output wire [31:0] io_outputs_1_ar_payload_addr, + output wire [3:0] io_outputs_1_ar_payload_id, + output wire [7:0] io_outputs_1_ar_payload_len, + output wire [2:0] io_outputs_1_ar_payload_size, + output wire [1:0] io_outputs_1_ar_payload_burst, + output wire [0:0] io_outputs_1_ar_payload_lock, + output wire [3:0] io_outputs_1_ar_payload_cache, + output wire [2:0] io_outputs_1_ar_payload_prot, + input wire io_outputs_1_r_valid, + output wire io_outputs_1_r_ready, + input wire [31:0] io_outputs_1_r_payload_data, + input wire [3:0] io_outputs_1_r_payload_id, + input wire [1:0] io_outputs_1_r_payload_resp, + input wire io_outputs_1_r_payload_last, + output wire io_outputs_2_ar_valid, + input wire io_outputs_2_ar_ready, + output wire [31:0] io_outputs_2_ar_payload_addr, + output wire [3:0] io_outputs_2_ar_payload_id, + output wire [7:0] io_outputs_2_ar_payload_len, + output wire [2:0] io_outputs_2_ar_payload_size, + output wire [1:0] io_outputs_2_ar_payload_burst, + output wire [0:0] io_outputs_2_ar_payload_lock, + output wire [3:0] io_outputs_2_ar_payload_cache, + output wire [2:0] io_outputs_2_ar_payload_prot, + input wire io_outputs_2_r_valid, + output wire io_outputs_2_r_ready, + input wire [31:0] io_outputs_2_r_payload_data, + input wire [3:0] io_outputs_2_r_payload_id, + input wire [1:0] io_outputs_2_r_payload_resp, + input wire io_outputs_2_r_payload_last, + output wire io_outputs_3_ar_valid, + input wire io_outputs_3_ar_ready, + output wire [31:0] io_outputs_3_ar_payload_addr, + output wire [3:0] io_outputs_3_ar_payload_id, + output wire [7:0] io_outputs_3_ar_payload_len, + output wire [2:0] io_outputs_3_ar_payload_size, + output wire [1:0] io_outputs_3_ar_payload_burst, + output wire [0:0] io_outputs_3_ar_payload_lock, + output wire [3:0] io_outputs_3_ar_payload_cache, + output wire [2:0] io_outputs_3_ar_payload_prot, + input wire io_outputs_3_r_valid, + output wire io_outputs_3_r_ready, + input wire [31:0] io_outputs_3_r_payload_data, + input wire [3:0] io_outputs_3_r_payload_id, + input wire [1:0] io_outputs_3_r_payload_resp, + input wire io_outputs_3_r_payload_last, + input wire clk, + input wire resetn +); + + wire errorSlave_io_axi_ar_valid; + wire errorSlave_io_axi_ar_ready; + wire errorSlave_io_axi_r_valid; + wire [31:0] errorSlave_io_axi_r_payload_data; + wire [3:0] errorSlave_io_axi_r_payload_id; + wire [1:0] errorSlave_io_axi_r_payload_resp; + wire errorSlave_io_axi_r_payload_last; + wire [31:0] _zz_decodedCmdSels; + wire [31:0] _zz_decodedCmdSels_1; + wire [31:0] _zz_decodedCmdSels_2; + wire [31:0] _zz_decodedCmdSels_3; + wire [31:0] _zz_decodedCmdSels_4; + wire [31:0] _zz_decodedCmdSels_5; + reg [31:0] _zz_io_input_r_payload_data; + reg [3:0] _zz_io_input_r_payload_id; + reg [1:0] _zz_io_input_r_payload_resp; + reg _zz_io_input_r_payload_last; + wire io_input_ar_fire; + wire io_input_r_fire; + wire when_Utils_l697; + reg pendingCmdCounter_incrementIt; + reg pendingCmdCounter_decrementIt; + wire [2:0] pendingCmdCounter_valueNext; + reg [2:0] pendingCmdCounter_value; + wire pendingCmdCounter_mayOverflow; + wire pendingCmdCounter_willOverflowIfInc; + wire pendingCmdCounter_willOverflow; + reg [2:0] pendingCmdCounter_finalIncrement; + wire when_Utils_l723; + wire when_Utils_l725; + wire [3:0] decodedCmdSels; + wire decodedCmdError; + reg [3:0] pendingSels; + reg pendingError; + wire allowCmd; + wire _zz_readRspIndex; + wire _zz_readRspIndex_1; + wire _zz_readRspIndex_2; + wire [1:0] readRspIndex; + + assign _zz_decodedCmdSels = 32'h000fffff; + assign _zz_decodedCmdSels_1 = (~ 32'h000fffff); + assign _zz_decodedCmdSels_2 = (io_input_ar_payload_addr & (~ 32'h007fffff)); + assign _zz_decodedCmdSels_3 = 32'h00000000; + assign _zz_decodedCmdSels_4 = (io_input_ar_payload_addr & (~ 32'h007fffff)); + assign _zz_decodedCmdSels_5 = 32'h1c000000; + Axi4ReadOnlyErrorSlave_1 errorSlave ( + .io_axi_ar_valid (errorSlave_io_axi_ar_valid ), //i + .io_axi_ar_ready (errorSlave_io_axi_ar_ready ), //o + .io_axi_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i + .io_axi_ar_payload_id (io_input_ar_payload_id[3:0] ), //i + .io_axi_ar_payload_len (io_input_ar_payload_len[7:0] ), //i + .io_axi_ar_payload_size (io_input_ar_payload_size[2:0] ), //i + .io_axi_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i + .io_axi_ar_payload_lock (io_input_ar_payload_lock ), //i + .io_axi_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i + .io_axi_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i + .io_axi_r_valid (errorSlave_io_axi_r_valid ), //o + .io_axi_r_ready (io_input_r_ready ), //i + .io_axi_r_payload_data (errorSlave_io_axi_r_payload_data[31:0]), //o + .io_axi_r_payload_id (errorSlave_io_axi_r_payload_id[3:0] ), //o + .io_axi_r_payload_resp (errorSlave_io_axi_r_payload_resp[1:0] ), //o + .io_axi_r_payload_last (errorSlave_io_axi_r_payload_last ), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + always @(*) begin + case(readRspIndex) + 2'b00 : begin + _zz_io_input_r_payload_data = io_outputs_0_r_payload_data; + _zz_io_input_r_payload_id = io_outputs_0_r_payload_id; + _zz_io_input_r_payload_resp = io_outputs_0_r_payload_resp; + _zz_io_input_r_payload_last = io_outputs_0_r_payload_last; + end + 2'b01 : begin + _zz_io_input_r_payload_data = io_outputs_1_r_payload_data; + _zz_io_input_r_payload_id = io_outputs_1_r_payload_id; + _zz_io_input_r_payload_resp = io_outputs_1_r_payload_resp; + _zz_io_input_r_payload_last = io_outputs_1_r_payload_last; + end + 2'b10 : begin + _zz_io_input_r_payload_data = io_outputs_2_r_payload_data; + _zz_io_input_r_payload_id = io_outputs_2_r_payload_id; + _zz_io_input_r_payload_resp = io_outputs_2_r_payload_resp; + _zz_io_input_r_payload_last = io_outputs_2_r_payload_last; + end + default : begin + _zz_io_input_r_payload_data = io_outputs_3_r_payload_data; + _zz_io_input_r_payload_id = io_outputs_3_r_payload_id; + _zz_io_input_r_payload_resp = io_outputs_3_r_payload_resp; + _zz_io_input_r_payload_last = io_outputs_3_r_payload_last; + end + endcase + end + + assign io_input_ar_fire = (io_input_ar_valid && io_input_ar_ready); + assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); + assign when_Utils_l697 = (io_input_r_fire && io_input_r_payload_last); + always @(*) begin + pendingCmdCounter_incrementIt = 1'b0; + if(io_input_ar_fire) begin + pendingCmdCounter_incrementIt = 1'b1; + end + end + + always @(*) begin + pendingCmdCounter_decrementIt = 1'b0; + if(when_Utils_l697) begin + pendingCmdCounter_decrementIt = 1'b1; + end + end + + assign pendingCmdCounter_mayOverflow = (pendingCmdCounter_value == 3'b111); + assign pendingCmdCounter_willOverflowIfInc = (pendingCmdCounter_mayOverflow && (! pendingCmdCounter_decrementIt)); + assign pendingCmdCounter_willOverflow = (pendingCmdCounter_willOverflowIfInc && pendingCmdCounter_incrementIt); + assign when_Utils_l723 = (pendingCmdCounter_incrementIt && (! pendingCmdCounter_decrementIt)); + always @(*) begin + if(when_Utils_l723) begin + pendingCmdCounter_finalIncrement = 3'b001; + end else begin + if(when_Utils_l725) begin + pendingCmdCounter_finalIncrement = 3'b111; + end else begin + pendingCmdCounter_finalIncrement = 3'b000; + end + end + end + + assign when_Utils_l725 = ((! pendingCmdCounter_incrementIt) && pendingCmdCounter_decrementIt); + assign pendingCmdCounter_valueNext = (pendingCmdCounter_value + pendingCmdCounter_finalIncrement); + assign decodedCmdSels = {(((io_input_ar_payload_addr & (~ _zz_decodedCmdSels)) == 32'h1f500000) && io_input_ar_valid),{(((io_input_ar_payload_addr & _zz_decodedCmdSels_1) == 32'h1f400000) && io_input_ar_valid),{((_zz_decodedCmdSels_2 == _zz_decodedCmdSels_3) && io_input_ar_valid),((_zz_decodedCmdSels_4 == _zz_decodedCmdSels_5) && io_input_ar_valid)}}}; + assign decodedCmdError = (decodedCmdSels == 4'b0000); + assign allowCmd = ((pendingCmdCounter_value == 3'b000) || ((pendingCmdCounter_value != 3'b111) && (pendingSels == decodedCmdSels))); + assign io_input_ar_ready = (((|(decodedCmdSels & {io_outputs_3_ar_ready,{io_outputs_2_ar_ready,{io_outputs_1_ar_ready,io_outputs_0_ar_ready}}})) || (decodedCmdError && errorSlave_io_axi_ar_ready)) && allowCmd); + assign errorSlave_io_axi_ar_valid = ((io_input_ar_valid && decodedCmdError) && allowCmd); + assign io_outputs_0_ar_valid = ((io_input_ar_valid && decodedCmdSels[0]) && allowCmd); + assign io_outputs_0_ar_payload_addr = io_input_ar_payload_addr; + assign io_outputs_0_ar_payload_id = io_input_ar_payload_id; + assign io_outputs_0_ar_payload_len = io_input_ar_payload_len; + assign io_outputs_0_ar_payload_size = io_input_ar_payload_size; + assign io_outputs_0_ar_payload_burst = io_input_ar_payload_burst; + assign io_outputs_0_ar_payload_lock = io_input_ar_payload_lock; + assign io_outputs_0_ar_payload_cache = io_input_ar_payload_cache; + assign io_outputs_0_ar_payload_prot = io_input_ar_payload_prot; + assign io_outputs_1_ar_valid = ((io_input_ar_valid && decodedCmdSels[1]) && allowCmd); + assign io_outputs_1_ar_payload_addr = io_input_ar_payload_addr; + assign io_outputs_1_ar_payload_id = io_input_ar_payload_id; + assign io_outputs_1_ar_payload_len = io_input_ar_payload_len; + assign io_outputs_1_ar_payload_size = io_input_ar_payload_size; + assign io_outputs_1_ar_payload_burst = io_input_ar_payload_burst; + assign io_outputs_1_ar_payload_lock = io_input_ar_payload_lock; + assign io_outputs_1_ar_payload_cache = io_input_ar_payload_cache; + assign io_outputs_1_ar_payload_prot = io_input_ar_payload_prot; + assign io_outputs_2_ar_valid = ((io_input_ar_valid && decodedCmdSels[2]) && allowCmd); + assign io_outputs_2_ar_payload_addr = io_input_ar_payload_addr; + assign io_outputs_2_ar_payload_id = io_input_ar_payload_id; + assign io_outputs_2_ar_payload_len = io_input_ar_payload_len; + assign io_outputs_2_ar_payload_size = io_input_ar_payload_size; + assign io_outputs_2_ar_payload_burst = io_input_ar_payload_burst; + assign io_outputs_2_ar_payload_lock = io_input_ar_payload_lock; + assign io_outputs_2_ar_payload_cache = io_input_ar_payload_cache; + assign io_outputs_2_ar_payload_prot = io_input_ar_payload_prot; + assign io_outputs_3_ar_valid = ((io_input_ar_valid && decodedCmdSels[3]) && allowCmd); + assign io_outputs_3_ar_payload_addr = io_input_ar_payload_addr; + assign io_outputs_3_ar_payload_id = io_input_ar_payload_id; + assign io_outputs_3_ar_payload_len = io_input_ar_payload_len; + assign io_outputs_3_ar_payload_size = io_input_ar_payload_size; + assign io_outputs_3_ar_payload_burst = io_input_ar_payload_burst; + assign io_outputs_3_ar_payload_lock = io_input_ar_payload_lock; + assign io_outputs_3_ar_payload_cache = io_input_ar_payload_cache; + assign io_outputs_3_ar_payload_prot = io_input_ar_payload_prot; + assign _zz_readRspIndex = pendingSels[3]; + assign _zz_readRspIndex_1 = (pendingSels[1] || _zz_readRspIndex); + assign _zz_readRspIndex_2 = (pendingSels[2] || _zz_readRspIndex); + assign readRspIndex = {_zz_readRspIndex_2,_zz_readRspIndex_1}; + always @(*) begin + io_input_r_valid = (|{io_outputs_3_r_valid,{io_outputs_2_r_valid,{io_outputs_1_r_valid,io_outputs_0_r_valid}}}); + if(errorSlave_io_axi_r_valid) begin + io_input_r_valid = 1'b1; + end + end + + assign io_input_r_payload_data = _zz_io_input_r_payload_data; + always @(*) begin + io_input_r_payload_id = _zz_io_input_r_payload_id; + if(pendingError) begin + io_input_r_payload_id = errorSlave_io_axi_r_payload_id; + end + end + + always @(*) begin + io_input_r_payload_resp = _zz_io_input_r_payload_resp; + if(pendingError) begin + io_input_r_payload_resp = errorSlave_io_axi_r_payload_resp; + end + end + + always @(*) begin + io_input_r_payload_last = _zz_io_input_r_payload_last; + if(pendingError) begin + io_input_r_payload_last = errorSlave_io_axi_r_payload_last; + end + end + + assign io_outputs_0_r_ready = io_input_r_ready; + assign io_outputs_1_r_ready = io_input_r_ready; + assign io_outputs_2_r_ready = io_input_r_ready; + assign io_outputs_3_r_ready = io_input_r_ready; + always @(posedge clk or negedge resetn) begin + if(!resetn) begin + pendingCmdCounter_value <= 3'b000; + pendingSels <= 4'b0000; + pendingError <= 1'b0; + end else begin + pendingCmdCounter_value <= pendingCmdCounter_valueNext; + if(io_input_ar_ready) begin + pendingSels <= decodedCmdSels; + end + if(io_input_ar_ready) begin + pendingError <= decodedCmdError; + end + end + end + + +endmodule + +module Axi4WriteOnlyDecoder ( + input wire io_input_aw_valid, + output wire io_input_aw_ready, + input wire [31:0] io_input_aw_payload_addr, + input wire [3:0] io_input_aw_payload_id, + input wire [7:0] io_input_aw_payload_len, + input wire [2:0] io_input_aw_payload_size, + input wire [1:0] io_input_aw_payload_burst, + input wire [0:0] io_input_aw_payload_lock, + input wire [3:0] io_input_aw_payload_cache, + input wire [2:0] io_input_aw_payload_prot, + input wire io_input_w_valid, + output wire io_input_w_ready, + input wire [31:0] io_input_w_payload_data, + input wire [3:0] io_input_w_payload_strb, + input wire io_input_w_payload_last, + output wire io_input_b_valid, + input wire io_input_b_ready, + output reg [3:0] io_input_b_payload_id, + output reg [1:0] io_input_b_payload_resp, + output wire io_outputs_0_aw_valid, + input wire io_outputs_0_aw_ready, + output wire [31:0] io_outputs_0_aw_payload_addr, + output wire [3:0] io_outputs_0_aw_payload_id, + output wire [7:0] io_outputs_0_aw_payload_len, + output wire [2:0] io_outputs_0_aw_payload_size, + output wire [1:0] io_outputs_0_aw_payload_burst, + output wire [0:0] io_outputs_0_aw_payload_lock, + output wire [3:0] io_outputs_0_aw_payload_cache, + output wire [2:0] io_outputs_0_aw_payload_prot, + output wire io_outputs_0_w_valid, + input wire io_outputs_0_w_ready, + output wire [31:0] io_outputs_0_w_payload_data, + output wire [3:0] io_outputs_0_w_payload_strb, + output wire io_outputs_0_w_payload_last, + input wire io_outputs_0_b_valid, + output wire io_outputs_0_b_ready, + input wire [3:0] io_outputs_0_b_payload_id, + input wire [1:0] io_outputs_0_b_payload_resp, + output wire io_outputs_1_aw_valid, + input wire io_outputs_1_aw_ready, + output wire [31:0] io_outputs_1_aw_payload_addr, + output wire [3:0] io_outputs_1_aw_payload_id, + output wire [7:0] io_outputs_1_aw_payload_len, + output wire [2:0] io_outputs_1_aw_payload_size, + output wire [1:0] io_outputs_1_aw_payload_burst, + output wire [0:0] io_outputs_1_aw_payload_lock, + output wire [3:0] io_outputs_1_aw_payload_cache, + output wire [2:0] io_outputs_1_aw_payload_prot, + output wire io_outputs_1_w_valid, + input wire io_outputs_1_w_ready, + output wire [31:0] io_outputs_1_w_payload_data, + output wire [3:0] io_outputs_1_w_payload_strb, + output wire io_outputs_1_w_payload_last, + input wire io_outputs_1_b_valid, + output wire io_outputs_1_b_ready, + input wire [3:0] io_outputs_1_b_payload_id, + input wire [1:0] io_outputs_1_b_payload_resp, + output wire io_outputs_2_aw_valid, + input wire io_outputs_2_aw_ready, + output wire [31:0] io_outputs_2_aw_payload_addr, + output wire [3:0] io_outputs_2_aw_payload_id, + output wire [7:0] io_outputs_2_aw_payload_len, + output wire [2:0] io_outputs_2_aw_payload_size, + output wire [1:0] io_outputs_2_aw_payload_burst, + output wire [0:0] io_outputs_2_aw_payload_lock, + output wire [3:0] io_outputs_2_aw_payload_cache, + output wire [2:0] io_outputs_2_aw_payload_prot, + output wire io_outputs_2_w_valid, + input wire io_outputs_2_w_ready, + output wire [31:0] io_outputs_2_w_payload_data, + output wire [3:0] io_outputs_2_w_payload_strb, + output wire io_outputs_2_w_payload_last, + input wire io_outputs_2_b_valid, + output wire io_outputs_2_b_ready, + input wire [3:0] io_outputs_2_b_payload_id, + input wire [1:0] io_outputs_2_b_payload_resp, + output wire io_outputs_3_aw_valid, + input wire io_outputs_3_aw_ready, + output wire [31:0] io_outputs_3_aw_payload_addr, + output wire [3:0] io_outputs_3_aw_payload_id, + output wire [7:0] io_outputs_3_aw_payload_len, + output wire [2:0] io_outputs_3_aw_payload_size, + output wire [1:0] io_outputs_3_aw_payload_burst, + output wire [0:0] io_outputs_3_aw_payload_lock, + output wire [3:0] io_outputs_3_aw_payload_cache, + output wire [2:0] io_outputs_3_aw_payload_prot, + output wire io_outputs_3_w_valid, + input wire io_outputs_3_w_ready, + output wire [31:0] io_outputs_3_w_payload_data, + output wire [3:0] io_outputs_3_w_payload_strb, + output wire io_outputs_3_w_payload_last, + input wire io_outputs_3_b_valid, + output wire io_outputs_3_b_ready, + input wire [3:0] io_outputs_3_b_payload_id, + input wire [1:0] io_outputs_3_b_payload_resp, + output wire io_outputs_4_aw_valid, + input wire io_outputs_4_aw_ready, + output wire [31:0] io_outputs_4_aw_payload_addr, + output wire [3:0] io_outputs_4_aw_payload_id, + output wire [7:0] io_outputs_4_aw_payload_len, + output wire [2:0] io_outputs_4_aw_payload_size, + output wire [1:0] io_outputs_4_aw_payload_burst, + output wire [0:0] io_outputs_4_aw_payload_lock, + output wire [3:0] io_outputs_4_aw_payload_cache, + output wire [2:0] io_outputs_4_aw_payload_prot, + output wire io_outputs_4_w_valid, + input wire io_outputs_4_w_ready, + output wire [31:0] io_outputs_4_w_payload_data, + output wire [3:0] io_outputs_4_w_payload_strb, + output wire io_outputs_4_w_payload_last, + input wire io_outputs_4_b_valid, + output wire io_outputs_4_b_ready, + input wire [3:0] io_outputs_4_b_payload_id, + input wire [1:0] io_outputs_4_b_payload_resp, + output wire io_outputs_5_aw_valid, + input wire io_outputs_5_aw_ready, + output wire [31:0] io_outputs_5_aw_payload_addr, + output wire [3:0] io_outputs_5_aw_payload_id, + output wire [7:0] io_outputs_5_aw_payload_len, + output wire [2:0] io_outputs_5_aw_payload_size, + output wire [1:0] io_outputs_5_aw_payload_burst, + output wire [0:0] io_outputs_5_aw_payload_lock, + output wire [3:0] io_outputs_5_aw_payload_cache, + output wire [2:0] io_outputs_5_aw_payload_prot, + output wire io_outputs_5_w_valid, + input wire io_outputs_5_w_ready, + output wire [31:0] io_outputs_5_w_payload_data, + output wire [3:0] io_outputs_5_w_payload_strb, + output wire io_outputs_5_w_payload_last, + input wire io_outputs_5_b_valid, + output wire io_outputs_5_b_ready, + input wire [3:0] io_outputs_5_b_payload_id, + input wire [1:0] io_outputs_5_b_payload_resp, + output wire io_outputs_6_aw_valid, + input wire io_outputs_6_aw_ready, + output wire [31:0] io_outputs_6_aw_payload_addr, + output wire [3:0] io_outputs_6_aw_payload_id, + output wire [7:0] io_outputs_6_aw_payload_len, + output wire [2:0] io_outputs_6_aw_payload_size, + output wire [1:0] io_outputs_6_aw_payload_burst, + output wire [0:0] io_outputs_6_aw_payload_lock, + output wire [3:0] io_outputs_6_aw_payload_cache, + output wire [2:0] io_outputs_6_aw_payload_prot, + output wire io_outputs_6_w_valid, + input wire io_outputs_6_w_ready, + output wire [31:0] io_outputs_6_w_payload_data, + output wire [3:0] io_outputs_6_w_payload_strb, + output wire io_outputs_6_w_payload_last, + input wire io_outputs_6_b_valid, + output wire io_outputs_6_b_ready, + input wire [3:0] io_outputs_6_b_payload_id, + input wire [1:0] io_outputs_6_b_payload_resp, + output wire io_outputs_7_aw_valid, + input wire io_outputs_7_aw_ready, + output wire [31:0] io_outputs_7_aw_payload_addr, + output wire [3:0] io_outputs_7_aw_payload_id, + output wire [7:0] io_outputs_7_aw_payload_len, + output wire [2:0] io_outputs_7_aw_payload_size, + output wire [1:0] io_outputs_7_aw_payload_burst, + output wire [0:0] io_outputs_7_aw_payload_lock, + output wire [3:0] io_outputs_7_aw_payload_cache, + output wire [2:0] io_outputs_7_aw_payload_prot, + output wire io_outputs_7_w_valid, + input wire io_outputs_7_w_ready, + output wire [31:0] io_outputs_7_w_payload_data, + output wire [3:0] io_outputs_7_w_payload_strb, + output wire io_outputs_7_w_payload_last, + input wire io_outputs_7_b_valid, + output wire io_outputs_7_b_ready, + input wire [3:0] io_outputs_7_b_payload_id, + input wire [1:0] io_outputs_7_b_payload_resp, + input wire clk, + input wire resetn +); + + wire errorSlave_io_axi_aw_valid; + wire errorSlave_io_axi_w_valid; + wire errorSlave_io_axi_aw_ready; + wire errorSlave_io_axi_w_ready; + wire errorSlave_io_axi_b_valid; + wire [3:0] errorSlave_io_axi_b_payload_id; + wire [1:0] errorSlave_io_axi_b_payload_resp; + wire [31:0] _zz_decodedCmdSels; + wire [31:0] _zz_decodedCmdSels_1; + wire [31:0] _zz_decodedCmdSels_2; + wire [31:0] _zz_decodedCmdSels_3; + wire _zz_decodedCmdSels_4; + wire _zz_decodedCmdSels_5; + wire [0:0] _zz_decodedCmdSels_6; + wire [1:0] _zz_decodedCmdSels_7; + wire [31:0] _zz_decodedCmdSels_8; + wire [31:0] _zz_decodedCmdSels_9; + reg [3:0] _zz_io_input_b_payload_id; + reg [1:0] _zz_io_input_b_payload_resp; + wire cmdAllowedStart; + wire io_input_aw_fire; + wire io_input_b_fire; + reg pendingCmdCounter_incrementIt; + reg pendingCmdCounter_decrementIt; + wire [2:0] pendingCmdCounter_valueNext; + reg [2:0] pendingCmdCounter_value; + wire pendingCmdCounter_mayOverflow; + wire pendingCmdCounter_willOverflowIfInc; + wire pendingCmdCounter_willOverflow; + reg [2:0] pendingCmdCounter_finalIncrement; + wire when_Utils_l723; + wire when_Utils_l725; + wire io_input_w_fire; + wire when_Utils_l697; + reg pendingDataCounter_incrementIt; + reg pendingDataCounter_decrementIt; + wire [2:0] pendingDataCounter_valueNext; + reg [2:0] pendingDataCounter_value; + wire pendingDataCounter_mayOverflow; + wire pendingDataCounter_willOverflowIfInc; + wire pendingDataCounter_willOverflow; + reg [2:0] pendingDataCounter_finalIncrement; + wire when_Utils_l723_1; + wire when_Utils_l725_1; + wire [7:0] decodedCmdSels; + wire decodedCmdError; + reg [7:0] pendingSels; + reg pendingError; + wire allowCmd; + wire allowData; + reg _zz_cmdAllowedStart; + wire _zz_io_outputs_1_w_valid; + wire _zz_io_outputs_2_w_valid; + wire _zz_io_outputs_3_w_valid; + wire _zz_io_outputs_4_w_valid; + wire _zz_io_outputs_5_w_valid; + wire _zz_io_outputs_6_w_valid; + wire _zz_io_outputs_7_w_valid; + wire _zz_writeRspIndex; + wire _zz_writeRspIndex_1; + wire _zz_writeRspIndex_2; + wire [2:0] writeRspIndex; + + assign _zz_decodedCmdSels = 32'h000fffff; + assign _zz_decodedCmdSels_1 = (~ 32'h000fffff); + assign _zz_decodedCmdSels_2 = (io_input_aw_payload_addr & (~ 32'h000fffff)); + assign _zz_decodedCmdSels_3 = 32'h1f300000; + assign _zz_decodedCmdSels_4 = ((io_input_aw_payload_addr & (~ 32'h000fffff)) == 32'h1f200000); + assign _zz_decodedCmdSels_5 = (((io_input_aw_payload_addr & (~ 32'h000fffff)) == 32'h1f100000) && io_input_aw_valid); + assign _zz_decodedCmdSels_6 = (((io_input_aw_payload_addr & (~ 32'h000fffff)) == 32'h1f000000) && io_input_aw_valid); + assign _zz_decodedCmdSels_7 = {(((io_input_aw_payload_addr & (~ _zz_decodedCmdSels_8)) == 32'h00000000) && io_input_aw_valid),(((io_input_aw_payload_addr & (~ _zz_decodedCmdSels_9)) == 32'h1c000000) && io_input_aw_valid)}; + assign _zz_decodedCmdSels_8 = 32'h007fffff; + assign _zz_decodedCmdSels_9 = 32'h007fffff; + Axi4WriteOnlyErrorSlave_1 errorSlave ( + .io_axi_aw_valid (errorSlave_io_axi_aw_valid ), //i + .io_axi_aw_ready (errorSlave_io_axi_aw_ready ), //o + .io_axi_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i + .io_axi_aw_payload_id (io_input_aw_payload_id[3:0] ), //i + .io_axi_aw_payload_len (io_input_aw_payload_len[7:0] ), //i + .io_axi_aw_payload_size (io_input_aw_payload_size[2:0] ), //i + .io_axi_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i + .io_axi_aw_payload_lock (io_input_aw_payload_lock ), //i + .io_axi_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i + .io_axi_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i + .io_axi_w_valid (errorSlave_io_axi_w_valid ), //i + .io_axi_w_ready (errorSlave_io_axi_w_ready ), //o + .io_axi_w_payload_data (io_input_w_payload_data[31:0] ), //i + .io_axi_w_payload_strb (io_input_w_payload_strb[3:0] ), //i + .io_axi_w_payload_last (io_input_w_payload_last ), //i + .io_axi_b_valid (errorSlave_io_axi_b_valid ), //o + .io_axi_b_ready (io_input_b_ready ), //i + .io_axi_b_payload_id (errorSlave_io_axi_b_payload_id[3:0] ), //o + .io_axi_b_payload_resp (errorSlave_io_axi_b_payload_resp[1:0]), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + always @(*) begin + case(writeRspIndex) + 3'b000 : begin + _zz_io_input_b_payload_id = io_outputs_0_b_payload_id; + _zz_io_input_b_payload_resp = io_outputs_0_b_payload_resp; + end + 3'b001 : begin + _zz_io_input_b_payload_id = io_outputs_1_b_payload_id; + _zz_io_input_b_payload_resp = io_outputs_1_b_payload_resp; + end + 3'b010 : begin + _zz_io_input_b_payload_id = io_outputs_2_b_payload_id; + _zz_io_input_b_payload_resp = io_outputs_2_b_payload_resp; + end + 3'b011 : begin + _zz_io_input_b_payload_id = io_outputs_3_b_payload_id; + _zz_io_input_b_payload_resp = io_outputs_3_b_payload_resp; + end + 3'b100 : begin + _zz_io_input_b_payload_id = io_outputs_4_b_payload_id; + _zz_io_input_b_payload_resp = io_outputs_4_b_payload_resp; + end + 3'b101 : begin + _zz_io_input_b_payload_id = io_outputs_5_b_payload_id; + _zz_io_input_b_payload_resp = io_outputs_5_b_payload_resp; + end + 3'b110 : begin + _zz_io_input_b_payload_id = io_outputs_6_b_payload_id; + _zz_io_input_b_payload_resp = io_outputs_6_b_payload_resp; + end + default : begin + _zz_io_input_b_payload_id = io_outputs_7_b_payload_id; + _zz_io_input_b_payload_resp = io_outputs_7_b_payload_resp; + end + endcase + end + + assign io_input_aw_fire = (io_input_aw_valid && io_input_aw_ready); + assign io_input_b_fire = (io_input_b_valid && io_input_b_ready); + always @(*) begin + pendingCmdCounter_incrementIt = 1'b0; + if(io_input_aw_fire) begin + pendingCmdCounter_incrementIt = 1'b1; + end + end + + always @(*) begin + pendingCmdCounter_decrementIt = 1'b0; + if(io_input_b_fire) begin + pendingCmdCounter_decrementIt = 1'b1; + end + end + + assign pendingCmdCounter_mayOverflow = (pendingCmdCounter_value == 3'b111); + assign pendingCmdCounter_willOverflowIfInc = (pendingCmdCounter_mayOverflow && (! pendingCmdCounter_decrementIt)); + assign pendingCmdCounter_willOverflow = (pendingCmdCounter_willOverflowIfInc && pendingCmdCounter_incrementIt); + assign when_Utils_l723 = (pendingCmdCounter_incrementIt && (! pendingCmdCounter_decrementIt)); + always @(*) begin + if(when_Utils_l723) begin + pendingCmdCounter_finalIncrement = 3'b001; + end else begin + if(when_Utils_l725) begin + pendingCmdCounter_finalIncrement = 3'b111; + end else begin + pendingCmdCounter_finalIncrement = 3'b000; + end + end + end + + assign when_Utils_l725 = ((! pendingCmdCounter_incrementIt) && pendingCmdCounter_decrementIt); + assign pendingCmdCounter_valueNext = (pendingCmdCounter_value + pendingCmdCounter_finalIncrement); + assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); + assign when_Utils_l697 = (io_input_w_fire && io_input_w_payload_last); + always @(*) begin + pendingDataCounter_incrementIt = 1'b0; + if(cmdAllowedStart) begin + pendingDataCounter_incrementIt = 1'b1; + end + end + + always @(*) begin + pendingDataCounter_decrementIt = 1'b0; + if(when_Utils_l697) begin + pendingDataCounter_decrementIt = 1'b1; + end + end + + assign pendingDataCounter_mayOverflow = (pendingDataCounter_value == 3'b111); + assign pendingDataCounter_willOverflowIfInc = (pendingDataCounter_mayOverflow && (! pendingDataCounter_decrementIt)); + assign pendingDataCounter_willOverflow = (pendingDataCounter_willOverflowIfInc && pendingDataCounter_incrementIt); + assign when_Utils_l723_1 = (pendingDataCounter_incrementIt && (! pendingDataCounter_decrementIt)); + always @(*) begin + if(when_Utils_l723_1) begin + pendingDataCounter_finalIncrement = 3'b001; + end else begin + if(when_Utils_l725_1) begin + pendingDataCounter_finalIncrement = 3'b111; + end else begin + pendingDataCounter_finalIncrement = 3'b000; + end + end + end + + assign when_Utils_l725_1 = ((! pendingDataCounter_incrementIt) && pendingDataCounter_decrementIt); + assign pendingDataCounter_valueNext = (pendingDataCounter_value + pendingDataCounter_finalIncrement); + assign decodedCmdSels = {(((io_input_aw_payload_addr & (~ _zz_decodedCmdSels)) == 32'h1f500000) && io_input_aw_valid),{(((io_input_aw_payload_addr & _zz_decodedCmdSels_1) == 32'h1f400000) && io_input_aw_valid),{((_zz_decodedCmdSels_2 == _zz_decodedCmdSels_3) && io_input_aw_valid),{(_zz_decodedCmdSels_4 && io_input_aw_valid),{_zz_decodedCmdSels_5,{_zz_decodedCmdSels_6,_zz_decodedCmdSels_7}}}}}}; + assign decodedCmdError = (decodedCmdSels == 8'h00); + assign allowCmd = ((pendingCmdCounter_value == 3'b000) || ((pendingCmdCounter_value != 3'b111) && (pendingSels == decodedCmdSels))); + assign allowData = (pendingDataCounter_value != 3'b000); + assign cmdAllowedStart = ((io_input_aw_valid && allowCmd) && _zz_cmdAllowedStart); + assign io_input_aw_ready = (((|(decodedCmdSels & {io_outputs_7_aw_ready,{io_outputs_6_aw_ready,{io_outputs_5_aw_ready,{io_outputs_4_aw_ready,{io_outputs_3_aw_ready,{io_outputs_2_aw_ready,{io_outputs_1_aw_ready,io_outputs_0_aw_ready}}}}}}})) || (decodedCmdError && errorSlave_io_axi_aw_ready)) && allowCmd); + assign errorSlave_io_axi_aw_valid = ((io_input_aw_valid && decodedCmdError) && allowCmd); + assign io_outputs_0_aw_valid = ((io_input_aw_valid && decodedCmdSels[0]) && allowCmd); + assign io_outputs_0_aw_payload_addr = io_input_aw_payload_addr; + assign io_outputs_0_aw_payload_id = io_input_aw_payload_id; + assign io_outputs_0_aw_payload_len = io_input_aw_payload_len; + assign io_outputs_0_aw_payload_size = io_input_aw_payload_size; + assign io_outputs_0_aw_payload_burst = io_input_aw_payload_burst; + assign io_outputs_0_aw_payload_lock = io_input_aw_payload_lock; + assign io_outputs_0_aw_payload_cache = io_input_aw_payload_cache; + assign io_outputs_0_aw_payload_prot = io_input_aw_payload_prot; + assign io_outputs_1_aw_valid = ((io_input_aw_valid && decodedCmdSels[1]) && allowCmd); + assign io_outputs_1_aw_payload_addr = io_input_aw_payload_addr; + assign io_outputs_1_aw_payload_id = io_input_aw_payload_id; + assign io_outputs_1_aw_payload_len = io_input_aw_payload_len; + assign io_outputs_1_aw_payload_size = io_input_aw_payload_size; + assign io_outputs_1_aw_payload_burst = io_input_aw_payload_burst; + assign io_outputs_1_aw_payload_lock = io_input_aw_payload_lock; + assign io_outputs_1_aw_payload_cache = io_input_aw_payload_cache; + assign io_outputs_1_aw_payload_prot = io_input_aw_payload_prot; + assign io_outputs_2_aw_valid = ((io_input_aw_valid && decodedCmdSels[2]) && allowCmd); + assign io_outputs_2_aw_payload_addr = io_input_aw_payload_addr; + assign io_outputs_2_aw_payload_id = io_input_aw_payload_id; + assign io_outputs_2_aw_payload_len = io_input_aw_payload_len; + assign io_outputs_2_aw_payload_size = io_input_aw_payload_size; + assign io_outputs_2_aw_payload_burst = io_input_aw_payload_burst; + assign io_outputs_2_aw_payload_lock = io_input_aw_payload_lock; + assign io_outputs_2_aw_payload_cache = io_input_aw_payload_cache; + assign io_outputs_2_aw_payload_prot = io_input_aw_payload_prot; + assign io_outputs_3_aw_valid = ((io_input_aw_valid && decodedCmdSels[3]) && allowCmd); + assign io_outputs_3_aw_payload_addr = io_input_aw_payload_addr; + assign io_outputs_3_aw_payload_id = io_input_aw_payload_id; + assign io_outputs_3_aw_payload_len = io_input_aw_payload_len; + assign io_outputs_3_aw_payload_size = io_input_aw_payload_size; + assign io_outputs_3_aw_payload_burst = io_input_aw_payload_burst; + assign io_outputs_3_aw_payload_lock = io_input_aw_payload_lock; + assign io_outputs_3_aw_payload_cache = io_input_aw_payload_cache; + assign io_outputs_3_aw_payload_prot = io_input_aw_payload_prot; + assign io_outputs_4_aw_valid = ((io_input_aw_valid && decodedCmdSels[4]) && allowCmd); + assign io_outputs_4_aw_payload_addr = io_input_aw_payload_addr; + assign io_outputs_4_aw_payload_id = io_input_aw_payload_id; + assign io_outputs_4_aw_payload_len = io_input_aw_payload_len; + assign io_outputs_4_aw_payload_size = io_input_aw_payload_size; + assign io_outputs_4_aw_payload_burst = io_input_aw_payload_burst; + assign io_outputs_4_aw_payload_lock = io_input_aw_payload_lock; + assign io_outputs_4_aw_payload_cache = io_input_aw_payload_cache; + assign io_outputs_4_aw_payload_prot = io_input_aw_payload_prot; + assign io_outputs_5_aw_valid = ((io_input_aw_valid && decodedCmdSels[5]) && allowCmd); + assign io_outputs_5_aw_payload_addr = io_input_aw_payload_addr; + assign io_outputs_5_aw_payload_id = io_input_aw_payload_id; + assign io_outputs_5_aw_payload_len = io_input_aw_payload_len; + assign io_outputs_5_aw_payload_size = io_input_aw_payload_size; + assign io_outputs_5_aw_payload_burst = io_input_aw_payload_burst; + assign io_outputs_5_aw_payload_lock = io_input_aw_payload_lock; + assign io_outputs_5_aw_payload_cache = io_input_aw_payload_cache; + assign io_outputs_5_aw_payload_prot = io_input_aw_payload_prot; + assign io_outputs_6_aw_valid = ((io_input_aw_valid && decodedCmdSels[6]) && allowCmd); + assign io_outputs_6_aw_payload_addr = io_input_aw_payload_addr; + assign io_outputs_6_aw_payload_id = io_input_aw_payload_id; + assign io_outputs_6_aw_payload_len = io_input_aw_payload_len; + assign io_outputs_6_aw_payload_size = io_input_aw_payload_size; + assign io_outputs_6_aw_payload_burst = io_input_aw_payload_burst; + assign io_outputs_6_aw_payload_lock = io_input_aw_payload_lock; + assign io_outputs_6_aw_payload_cache = io_input_aw_payload_cache; + assign io_outputs_6_aw_payload_prot = io_input_aw_payload_prot; + assign io_outputs_7_aw_valid = ((io_input_aw_valid && decodedCmdSels[7]) && allowCmd); + assign io_outputs_7_aw_payload_addr = io_input_aw_payload_addr; + assign io_outputs_7_aw_payload_id = io_input_aw_payload_id; + assign io_outputs_7_aw_payload_len = io_input_aw_payload_len; + assign io_outputs_7_aw_payload_size = io_input_aw_payload_size; + assign io_outputs_7_aw_payload_burst = io_input_aw_payload_burst; + assign io_outputs_7_aw_payload_lock = io_input_aw_payload_lock; + assign io_outputs_7_aw_payload_cache = io_input_aw_payload_cache; + assign io_outputs_7_aw_payload_prot = io_input_aw_payload_prot; + assign io_input_w_ready = (((|(pendingSels & {io_outputs_7_w_ready,{io_outputs_6_w_ready,{io_outputs_5_w_ready,{io_outputs_4_w_ready,{io_outputs_3_w_ready,{io_outputs_2_w_ready,{io_outputs_1_w_ready,io_outputs_0_w_ready}}}}}}})) || (pendingError && errorSlave_io_axi_w_ready)) && allowData); + assign errorSlave_io_axi_w_valid = ((io_input_w_valid && pendingError) && allowData); + assign _zz_io_outputs_1_w_valid = pendingSels[1]; + assign _zz_io_outputs_2_w_valid = pendingSels[2]; + assign _zz_io_outputs_3_w_valid = pendingSels[3]; + assign _zz_io_outputs_4_w_valid = pendingSels[4]; + assign _zz_io_outputs_5_w_valid = pendingSels[5]; + assign _zz_io_outputs_6_w_valid = pendingSels[6]; + assign _zz_io_outputs_7_w_valid = pendingSels[7]; + assign io_outputs_0_w_valid = ((io_input_w_valid && pendingSels[0]) && allowData); + assign io_outputs_0_w_payload_data = io_input_w_payload_data; + assign io_outputs_0_w_payload_strb = io_input_w_payload_strb; + assign io_outputs_0_w_payload_last = io_input_w_payload_last; + assign io_outputs_1_w_valid = ((io_input_w_valid && _zz_io_outputs_1_w_valid) && allowData); + assign io_outputs_1_w_payload_data = io_input_w_payload_data; + assign io_outputs_1_w_payload_strb = io_input_w_payload_strb; + assign io_outputs_1_w_payload_last = io_input_w_payload_last; + assign io_outputs_2_w_valid = ((io_input_w_valid && _zz_io_outputs_2_w_valid) && allowData); + assign io_outputs_2_w_payload_data = io_input_w_payload_data; + assign io_outputs_2_w_payload_strb = io_input_w_payload_strb; + assign io_outputs_2_w_payload_last = io_input_w_payload_last; + assign io_outputs_3_w_valid = ((io_input_w_valid && _zz_io_outputs_3_w_valid) && allowData); + assign io_outputs_3_w_payload_data = io_input_w_payload_data; + assign io_outputs_3_w_payload_strb = io_input_w_payload_strb; + assign io_outputs_3_w_payload_last = io_input_w_payload_last; + assign io_outputs_4_w_valid = ((io_input_w_valid && _zz_io_outputs_4_w_valid) && allowData); + assign io_outputs_4_w_payload_data = io_input_w_payload_data; + assign io_outputs_4_w_payload_strb = io_input_w_payload_strb; + assign io_outputs_4_w_payload_last = io_input_w_payload_last; + assign io_outputs_5_w_valid = ((io_input_w_valid && _zz_io_outputs_5_w_valid) && allowData); + assign io_outputs_5_w_payload_data = io_input_w_payload_data; + assign io_outputs_5_w_payload_strb = io_input_w_payload_strb; + assign io_outputs_5_w_payload_last = io_input_w_payload_last; + assign io_outputs_6_w_valid = ((io_input_w_valid && _zz_io_outputs_6_w_valid) && allowData); + assign io_outputs_6_w_payload_data = io_input_w_payload_data; + assign io_outputs_6_w_payload_strb = io_input_w_payload_strb; + assign io_outputs_6_w_payload_last = io_input_w_payload_last; + assign io_outputs_7_w_valid = ((io_input_w_valid && _zz_io_outputs_7_w_valid) && allowData); + assign io_outputs_7_w_payload_data = io_input_w_payload_data; + assign io_outputs_7_w_payload_strb = io_input_w_payload_strb; + assign io_outputs_7_w_payload_last = io_input_w_payload_last; + assign _zz_writeRspIndex = (((_zz_io_outputs_1_w_valid || _zz_io_outputs_3_w_valid) || _zz_io_outputs_5_w_valid) || _zz_io_outputs_7_w_valid); + assign _zz_writeRspIndex_1 = (((_zz_io_outputs_2_w_valid || _zz_io_outputs_3_w_valid) || _zz_io_outputs_6_w_valid) || _zz_io_outputs_7_w_valid); + assign _zz_writeRspIndex_2 = (((_zz_io_outputs_4_w_valid || _zz_io_outputs_5_w_valid) || _zz_io_outputs_6_w_valid) || _zz_io_outputs_7_w_valid); + assign writeRspIndex = {_zz_writeRspIndex_2,{_zz_writeRspIndex_1,_zz_writeRspIndex}}; + assign io_input_b_valid = ((|{io_outputs_7_b_valid,{io_outputs_6_b_valid,{io_outputs_5_b_valid,{io_outputs_4_b_valid,{io_outputs_3_b_valid,{io_outputs_2_b_valid,{io_outputs_1_b_valid,io_outputs_0_b_valid}}}}}}}) || errorSlave_io_axi_b_valid); + always @(*) begin + io_input_b_payload_id = _zz_io_input_b_payload_id; + if(pendingError) begin + io_input_b_payload_id = errorSlave_io_axi_b_payload_id; + end + end + + always @(*) begin + io_input_b_payload_resp = _zz_io_input_b_payload_resp; + if(pendingError) begin + io_input_b_payload_resp = errorSlave_io_axi_b_payload_resp; + end + end + + assign io_outputs_0_b_ready = io_input_b_ready; + assign io_outputs_1_b_ready = io_input_b_ready; + assign io_outputs_2_b_ready = io_input_b_ready; + assign io_outputs_3_b_ready = io_input_b_ready; + assign io_outputs_4_b_ready = io_input_b_ready; + assign io_outputs_5_b_ready = io_input_b_ready; + assign io_outputs_6_b_ready = io_input_b_ready; + assign io_outputs_7_b_ready = io_input_b_ready; + always @(posedge clk or negedge resetn) begin + if(!resetn) begin + pendingCmdCounter_value <= 3'b000; + pendingDataCounter_value <= 3'b000; + pendingSels <= 8'h00; + pendingError <= 1'b0; + _zz_cmdAllowedStart <= 1'b1; + end else begin + pendingCmdCounter_value <= pendingCmdCounter_valueNext; + pendingDataCounter_value <= pendingDataCounter_valueNext; + if(cmdAllowedStart) begin + pendingSels <= decodedCmdSels; + end + if(cmdAllowedStart) begin + pendingError <= decodedCmdError; + end + if(cmdAllowedStart) begin + _zz_cmdAllowedStart <= 1'b0; + end + if(io_input_aw_ready) begin + _zz_cmdAllowedStart <= 1'b1; + end + end + end + + +endmodule + +module Axi4ReadOnlyDecoder ( + input wire io_input_ar_valid, + output wire io_input_ar_ready, + input wire [31:0] io_input_ar_payload_addr, + input wire [3:0] io_input_ar_payload_id, + input wire [7:0] io_input_ar_payload_len, + input wire [2:0] io_input_ar_payload_size, + input wire [1:0] io_input_ar_payload_burst, + input wire [0:0] io_input_ar_payload_lock, + input wire [3:0] io_input_ar_payload_cache, + input wire [2:0] io_input_ar_payload_prot, + output reg io_input_r_valid, + input wire io_input_r_ready, + output wire [31:0] io_input_r_payload_data, + output reg [3:0] io_input_r_payload_id, + output reg [1:0] io_input_r_payload_resp, + output reg io_input_r_payload_last, + output wire io_outputs_0_ar_valid, + input wire io_outputs_0_ar_ready, + output wire [31:0] io_outputs_0_ar_payload_addr, + output wire [3:0] io_outputs_0_ar_payload_id, + output wire [7:0] io_outputs_0_ar_payload_len, + output wire [2:0] io_outputs_0_ar_payload_size, + output wire [1:0] io_outputs_0_ar_payload_burst, + output wire [0:0] io_outputs_0_ar_payload_lock, + output wire [3:0] io_outputs_0_ar_payload_cache, + output wire [2:0] io_outputs_0_ar_payload_prot, + input wire io_outputs_0_r_valid, + output wire io_outputs_0_r_ready, + input wire [31:0] io_outputs_0_r_payload_data, + input wire [3:0] io_outputs_0_r_payload_id, + input wire [1:0] io_outputs_0_r_payload_resp, + input wire io_outputs_0_r_payload_last, + output wire io_outputs_1_ar_valid, + input wire io_outputs_1_ar_ready, + output wire [31:0] io_outputs_1_ar_payload_addr, + output wire [3:0] io_outputs_1_ar_payload_id, + output wire [7:0] io_outputs_1_ar_payload_len, + output wire [2:0] io_outputs_1_ar_payload_size, + output wire [1:0] io_outputs_1_ar_payload_burst, + output wire [0:0] io_outputs_1_ar_payload_lock, + output wire [3:0] io_outputs_1_ar_payload_cache, + output wire [2:0] io_outputs_1_ar_payload_prot, + input wire io_outputs_1_r_valid, + output wire io_outputs_1_r_ready, + input wire [31:0] io_outputs_1_r_payload_data, + input wire [3:0] io_outputs_1_r_payload_id, + input wire [1:0] io_outputs_1_r_payload_resp, + input wire io_outputs_1_r_payload_last, + output wire io_outputs_2_ar_valid, + input wire io_outputs_2_ar_ready, + output wire [31:0] io_outputs_2_ar_payload_addr, + output wire [3:0] io_outputs_2_ar_payload_id, + output wire [7:0] io_outputs_2_ar_payload_len, + output wire [2:0] io_outputs_2_ar_payload_size, + output wire [1:0] io_outputs_2_ar_payload_burst, + output wire [0:0] io_outputs_2_ar_payload_lock, + output wire [3:0] io_outputs_2_ar_payload_cache, + output wire [2:0] io_outputs_2_ar_payload_prot, + input wire io_outputs_2_r_valid, + output wire io_outputs_2_r_ready, + input wire [31:0] io_outputs_2_r_payload_data, + input wire [3:0] io_outputs_2_r_payload_id, + input wire [1:0] io_outputs_2_r_payload_resp, + input wire io_outputs_2_r_payload_last, + output wire io_outputs_3_ar_valid, + input wire io_outputs_3_ar_ready, + output wire [31:0] io_outputs_3_ar_payload_addr, + output wire [3:0] io_outputs_3_ar_payload_id, + output wire [7:0] io_outputs_3_ar_payload_len, + output wire [2:0] io_outputs_3_ar_payload_size, + output wire [1:0] io_outputs_3_ar_payload_burst, + output wire [0:0] io_outputs_3_ar_payload_lock, + output wire [3:0] io_outputs_3_ar_payload_cache, + output wire [2:0] io_outputs_3_ar_payload_prot, + input wire io_outputs_3_r_valid, + output wire io_outputs_3_r_ready, + input wire [31:0] io_outputs_3_r_payload_data, + input wire [3:0] io_outputs_3_r_payload_id, + input wire [1:0] io_outputs_3_r_payload_resp, + input wire io_outputs_3_r_payload_last, + output wire io_outputs_4_ar_valid, + input wire io_outputs_4_ar_ready, + output wire [31:0] io_outputs_4_ar_payload_addr, + output wire [3:0] io_outputs_4_ar_payload_id, + output wire [7:0] io_outputs_4_ar_payload_len, + output wire [2:0] io_outputs_4_ar_payload_size, + output wire [1:0] io_outputs_4_ar_payload_burst, + output wire [0:0] io_outputs_4_ar_payload_lock, + output wire [3:0] io_outputs_4_ar_payload_cache, + output wire [2:0] io_outputs_4_ar_payload_prot, + input wire io_outputs_4_r_valid, + output wire io_outputs_4_r_ready, + input wire [31:0] io_outputs_4_r_payload_data, + input wire [3:0] io_outputs_4_r_payload_id, + input wire [1:0] io_outputs_4_r_payload_resp, + input wire io_outputs_4_r_payload_last, + output wire io_outputs_5_ar_valid, + input wire io_outputs_5_ar_ready, + output wire [31:0] io_outputs_5_ar_payload_addr, + output wire [3:0] io_outputs_5_ar_payload_id, + output wire [7:0] io_outputs_5_ar_payload_len, + output wire [2:0] io_outputs_5_ar_payload_size, + output wire [1:0] io_outputs_5_ar_payload_burst, + output wire [0:0] io_outputs_5_ar_payload_lock, + output wire [3:0] io_outputs_5_ar_payload_cache, + output wire [2:0] io_outputs_5_ar_payload_prot, + input wire io_outputs_5_r_valid, + output wire io_outputs_5_r_ready, + input wire [31:0] io_outputs_5_r_payload_data, + input wire [3:0] io_outputs_5_r_payload_id, + input wire [1:0] io_outputs_5_r_payload_resp, + input wire io_outputs_5_r_payload_last, + output wire io_outputs_6_ar_valid, + input wire io_outputs_6_ar_ready, + output wire [31:0] io_outputs_6_ar_payload_addr, + output wire [3:0] io_outputs_6_ar_payload_id, + output wire [7:0] io_outputs_6_ar_payload_len, + output wire [2:0] io_outputs_6_ar_payload_size, + output wire [1:0] io_outputs_6_ar_payload_burst, + output wire [0:0] io_outputs_6_ar_payload_lock, + output wire [3:0] io_outputs_6_ar_payload_cache, + output wire [2:0] io_outputs_6_ar_payload_prot, + input wire io_outputs_6_r_valid, + output wire io_outputs_6_r_ready, + input wire [31:0] io_outputs_6_r_payload_data, + input wire [3:0] io_outputs_6_r_payload_id, + input wire [1:0] io_outputs_6_r_payload_resp, + input wire io_outputs_6_r_payload_last, + output wire io_outputs_7_ar_valid, + input wire io_outputs_7_ar_ready, + output wire [31:0] io_outputs_7_ar_payload_addr, + output wire [3:0] io_outputs_7_ar_payload_id, + output wire [7:0] io_outputs_7_ar_payload_len, + output wire [2:0] io_outputs_7_ar_payload_size, + output wire [1:0] io_outputs_7_ar_payload_burst, + output wire [0:0] io_outputs_7_ar_payload_lock, + output wire [3:0] io_outputs_7_ar_payload_cache, + output wire [2:0] io_outputs_7_ar_payload_prot, + input wire io_outputs_7_r_valid, + output wire io_outputs_7_r_ready, + input wire [31:0] io_outputs_7_r_payload_data, + input wire [3:0] io_outputs_7_r_payload_id, + input wire [1:0] io_outputs_7_r_payload_resp, + input wire io_outputs_7_r_payload_last, + input wire clk, + input wire resetn +); + + wire errorSlave_io_axi_ar_valid; + wire errorSlave_io_axi_ar_ready; + wire errorSlave_io_axi_r_valid; + wire [31:0] errorSlave_io_axi_r_payload_data; + wire [3:0] errorSlave_io_axi_r_payload_id; + wire [1:0] errorSlave_io_axi_r_payload_resp; + wire errorSlave_io_axi_r_payload_last; + wire [31:0] _zz_decodedCmdSels; + wire [31:0] _zz_decodedCmdSels_1; + wire [31:0] _zz_decodedCmdSels_2; + wire [31:0] _zz_decodedCmdSels_3; + wire _zz_decodedCmdSels_4; + wire _zz_decodedCmdSels_5; + wire [0:0] _zz_decodedCmdSels_6; + wire [1:0] _zz_decodedCmdSels_7; + wire [31:0] _zz_decodedCmdSels_8; + wire [31:0] _zz_decodedCmdSels_9; + reg [31:0] _zz_io_input_r_payload_data; + reg [3:0] _zz_io_input_r_payload_id; + reg [1:0] _zz_io_input_r_payload_resp; + reg _zz_io_input_r_payload_last; + wire io_input_ar_fire; + wire io_input_r_fire; + wire when_Utils_l697; + reg pendingCmdCounter_incrementIt; + reg pendingCmdCounter_decrementIt; + wire [2:0] pendingCmdCounter_valueNext; + reg [2:0] pendingCmdCounter_value; + wire pendingCmdCounter_mayOverflow; + wire pendingCmdCounter_willOverflowIfInc; + wire pendingCmdCounter_willOverflow; + reg [2:0] pendingCmdCounter_finalIncrement; + wire when_Utils_l723; + wire when_Utils_l725; + wire [7:0] decodedCmdSels; + wire decodedCmdError; + reg [7:0] pendingSels; + reg pendingError; + wire allowCmd; + wire _zz_readRspIndex; + wire _zz_readRspIndex_1; + wire _zz_readRspIndex_2; + wire _zz_readRspIndex_3; + wire _zz_readRspIndex_4; + wire _zz_readRspIndex_5; + wire _zz_readRspIndex_6; + wire [2:0] readRspIndex; + + assign _zz_decodedCmdSels = 32'h000fffff; + assign _zz_decodedCmdSels_1 = (~ 32'h000fffff); + assign _zz_decodedCmdSels_2 = (io_input_ar_payload_addr & (~ 32'h000fffff)); + assign _zz_decodedCmdSels_3 = 32'h1f300000; + assign _zz_decodedCmdSels_4 = ((io_input_ar_payload_addr & (~ 32'h000fffff)) == 32'h1f200000); + assign _zz_decodedCmdSels_5 = (((io_input_ar_payload_addr & (~ 32'h000fffff)) == 32'h1f100000) && io_input_ar_valid); + assign _zz_decodedCmdSels_6 = (((io_input_ar_payload_addr & (~ 32'h000fffff)) == 32'h1f000000) && io_input_ar_valid); + assign _zz_decodedCmdSels_7 = {(((io_input_ar_payload_addr & (~ _zz_decodedCmdSels_8)) == 32'h00000000) && io_input_ar_valid),(((io_input_ar_payload_addr & (~ _zz_decodedCmdSels_9)) == 32'h1c000000) && io_input_ar_valid)}; + assign _zz_decodedCmdSels_8 = 32'h007fffff; + assign _zz_decodedCmdSels_9 = 32'h007fffff; + Axi4ReadOnlyErrorSlave_1 errorSlave ( + .io_axi_ar_valid (errorSlave_io_axi_ar_valid ), //i + .io_axi_ar_ready (errorSlave_io_axi_ar_ready ), //o + .io_axi_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i + .io_axi_ar_payload_id (io_input_ar_payload_id[3:0] ), //i + .io_axi_ar_payload_len (io_input_ar_payload_len[7:0] ), //i + .io_axi_ar_payload_size (io_input_ar_payload_size[2:0] ), //i + .io_axi_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i + .io_axi_ar_payload_lock (io_input_ar_payload_lock ), //i + .io_axi_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i + .io_axi_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i + .io_axi_r_valid (errorSlave_io_axi_r_valid ), //o + .io_axi_r_ready (io_input_r_ready ), //i + .io_axi_r_payload_data (errorSlave_io_axi_r_payload_data[31:0]), //o + .io_axi_r_payload_id (errorSlave_io_axi_r_payload_id[3:0] ), //o + .io_axi_r_payload_resp (errorSlave_io_axi_r_payload_resp[1:0] ), //o + .io_axi_r_payload_last (errorSlave_io_axi_r_payload_last ), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + always @(*) begin + case(readRspIndex) + 3'b000 : begin + _zz_io_input_r_payload_data = io_outputs_0_r_payload_data; + _zz_io_input_r_payload_id = io_outputs_0_r_payload_id; + _zz_io_input_r_payload_resp = io_outputs_0_r_payload_resp; + _zz_io_input_r_payload_last = io_outputs_0_r_payload_last; + end + 3'b001 : begin + _zz_io_input_r_payload_data = io_outputs_1_r_payload_data; + _zz_io_input_r_payload_id = io_outputs_1_r_payload_id; + _zz_io_input_r_payload_resp = io_outputs_1_r_payload_resp; + _zz_io_input_r_payload_last = io_outputs_1_r_payload_last; + end + 3'b010 : begin + _zz_io_input_r_payload_data = io_outputs_2_r_payload_data; + _zz_io_input_r_payload_id = io_outputs_2_r_payload_id; + _zz_io_input_r_payload_resp = io_outputs_2_r_payload_resp; + _zz_io_input_r_payload_last = io_outputs_2_r_payload_last; + end + 3'b011 : begin + _zz_io_input_r_payload_data = io_outputs_3_r_payload_data; + _zz_io_input_r_payload_id = io_outputs_3_r_payload_id; + _zz_io_input_r_payload_resp = io_outputs_3_r_payload_resp; + _zz_io_input_r_payload_last = io_outputs_3_r_payload_last; + end + 3'b100 : begin + _zz_io_input_r_payload_data = io_outputs_4_r_payload_data; + _zz_io_input_r_payload_id = io_outputs_4_r_payload_id; + _zz_io_input_r_payload_resp = io_outputs_4_r_payload_resp; + _zz_io_input_r_payload_last = io_outputs_4_r_payload_last; + end + 3'b101 : begin + _zz_io_input_r_payload_data = io_outputs_5_r_payload_data; + _zz_io_input_r_payload_id = io_outputs_5_r_payload_id; + _zz_io_input_r_payload_resp = io_outputs_5_r_payload_resp; + _zz_io_input_r_payload_last = io_outputs_5_r_payload_last; + end + 3'b110 : begin + _zz_io_input_r_payload_data = io_outputs_6_r_payload_data; + _zz_io_input_r_payload_id = io_outputs_6_r_payload_id; + _zz_io_input_r_payload_resp = io_outputs_6_r_payload_resp; + _zz_io_input_r_payload_last = io_outputs_6_r_payload_last; + end + default : begin + _zz_io_input_r_payload_data = io_outputs_7_r_payload_data; + _zz_io_input_r_payload_id = io_outputs_7_r_payload_id; + _zz_io_input_r_payload_resp = io_outputs_7_r_payload_resp; + _zz_io_input_r_payload_last = io_outputs_7_r_payload_last; + end + endcase + end + + assign io_input_ar_fire = (io_input_ar_valid && io_input_ar_ready); + assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); + assign when_Utils_l697 = (io_input_r_fire && io_input_r_payload_last); + always @(*) begin + pendingCmdCounter_incrementIt = 1'b0; + if(io_input_ar_fire) begin + pendingCmdCounter_incrementIt = 1'b1; + end + end + + always @(*) begin + pendingCmdCounter_decrementIt = 1'b0; + if(when_Utils_l697) begin + pendingCmdCounter_decrementIt = 1'b1; + end + end + + assign pendingCmdCounter_mayOverflow = (pendingCmdCounter_value == 3'b111); + assign pendingCmdCounter_willOverflowIfInc = (pendingCmdCounter_mayOverflow && (! pendingCmdCounter_decrementIt)); + assign pendingCmdCounter_willOverflow = (pendingCmdCounter_willOverflowIfInc && pendingCmdCounter_incrementIt); + assign when_Utils_l723 = (pendingCmdCounter_incrementIt && (! pendingCmdCounter_decrementIt)); + always @(*) begin + if(when_Utils_l723) begin + pendingCmdCounter_finalIncrement = 3'b001; + end else begin + if(when_Utils_l725) begin + pendingCmdCounter_finalIncrement = 3'b111; + end else begin + pendingCmdCounter_finalIncrement = 3'b000; + end + end + end + + assign when_Utils_l725 = ((! pendingCmdCounter_incrementIt) && pendingCmdCounter_decrementIt); + assign pendingCmdCounter_valueNext = (pendingCmdCounter_value + pendingCmdCounter_finalIncrement); + assign decodedCmdSels = {(((io_input_ar_payload_addr & (~ _zz_decodedCmdSels)) == 32'h1f500000) && io_input_ar_valid),{(((io_input_ar_payload_addr & _zz_decodedCmdSels_1) == 32'h1f400000) && io_input_ar_valid),{((_zz_decodedCmdSels_2 == _zz_decodedCmdSels_3) && io_input_ar_valid),{(_zz_decodedCmdSels_4 && io_input_ar_valid),{_zz_decodedCmdSels_5,{_zz_decodedCmdSels_6,_zz_decodedCmdSels_7}}}}}}; + assign decodedCmdError = (decodedCmdSels == 8'h00); + assign allowCmd = ((pendingCmdCounter_value == 3'b000) || ((pendingCmdCounter_value != 3'b111) && (pendingSels == decodedCmdSels))); + assign io_input_ar_ready = (((|(decodedCmdSels & {io_outputs_7_ar_ready,{io_outputs_6_ar_ready,{io_outputs_5_ar_ready,{io_outputs_4_ar_ready,{io_outputs_3_ar_ready,{io_outputs_2_ar_ready,{io_outputs_1_ar_ready,io_outputs_0_ar_ready}}}}}}})) || (decodedCmdError && errorSlave_io_axi_ar_ready)) && allowCmd); + assign errorSlave_io_axi_ar_valid = ((io_input_ar_valid && decodedCmdError) && allowCmd); + assign io_outputs_0_ar_valid = ((io_input_ar_valid && decodedCmdSels[0]) && allowCmd); + assign io_outputs_0_ar_payload_addr = io_input_ar_payload_addr; + assign io_outputs_0_ar_payload_id = io_input_ar_payload_id; + assign io_outputs_0_ar_payload_len = io_input_ar_payload_len; + assign io_outputs_0_ar_payload_size = io_input_ar_payload_size; + assign io_outputs_0_ar_payload_burst = io_input_ar_payload_burst; + assign io_outputs_0_ar_payload_lock = io_input_ar_payload_lock; + assign io_outputs_0_ar_payload_cache = io_input_ar_payload_cache; + assign io_outputs_0_ar_payload_prot = io_input_ar_payload_prot; + assign io_outputs_1_ar_valid = ((io_input_ar_valid && decodedCmdSels[1]) && allowCmd); + assign io_outputs_1_ar_payload_addr = io_input_ar_payload_addr; + assign io_outputs_1_ar_payload_id = io_input_ar_payload_id; + assign io_outputs_1_ar_payload_len = io_input_ar_payload_len; + assign io_outputs_1_ar_payload_size = io_input_ar_payload_size; + assign io_outputs_1_ar_payload_burst = io_input_ar_payload_burst; + assign io_outputs_1_ar_payload_lock = io_input_ar_payload_lock; + assign io_outputs_1_ar_payload_cache = io_input_ar_payload_cache; + assign io_outputs_1_ar_payload_prot = io_input_ar_payload_prot; + assign io_outputs_2_ar_valid = ((io_input_ar_valid && decodedCmdSels[2]) && allowCmd); + assign io_outputs_2_ar_payload_addr = io_input_ar_payload_addr; + assign io_outputs_2_ar_payload_id = io_input_ar_payload_id; + assign io_outputs_2_ar_payload_len = io_input_ar_payload_len; + assign io_outputs_2_ar_payload_size = io_input_ar_payload_size; + assign io_outputs_2_ar_payload_burst = io_input_ar_payload_burst; + assign io_outputs_2_ar_payload_lock = io_input_ar_payload_lock; + assign io_outputs_2_ar_payload_cache = io_input_ar_payload_cache; + assign io_outputs_2_ar_payload_prot = io_input_ar_payload_prot; + assign io_outputs_3_ar_valid = ((io_input_ar_valid && decodedCmdSels[3]) && allowCmd); + assign io_outputs_3_ar_payload_addr = io_input_ar_payload_addr; + assign io_outputs_3_ar_payload_id = io_input_ar_payload_id; + assign io_outputs_3_ar_payload_len = io_input_ar_payload_len; + assign io_outputs_3_ar_payload_size = io_input_ar_payload_size; + assign io_outputs_3_ar_payload_burst = io_input_ar_payload_burst; + assign io_outputs_3_ar_payload_lock = io_input_ar_payload_lock; + assign io_outputs_3_ar_payload_cache = io_input_ar_payload_cache; + assign io_outputs_3_ar_payload_prot = io_input_ar_payload_prot; + assign io_outputs_4_ar_valid = ((io_input_ar_valid && decodedCmdSels[4]) && allowCmd); + assign io_outputs_4_ar_payload_addr = io_input_ar_payload_addr; + assign io_outputs_4_ar_payload_id = io_input_ar_payload_id; + assign io_outputs_4_ar_payload_len = io_input_ar_payload_len; + assign io_outputs_4_ar_payload_size = io_input_ar_payload_size; + assign io_outputs_4_ar_payload_burst = io_input_ar_payload_burst; + assign io_outputs_4_ar_payload_lock = io_input_ar_payload_lock; + assign io_outputs_4_ar_payload_cache = io_input_ar_payload_cache; + assign io_outputs_4_ar_payload_prot = io_input_ar_payload_prot; + assign io_outputs_5_ar_valid = ((io_input_ar_valid && decodedCmdSels[5]) && allowCmd); + assign io_outputs_5_ar_payload_addr = io_input_ar_payload_addr; + assign io_outputs_5_ar_payload_id = io_input_ar_payload_id; + assign io_outputs_5_ar_payload_len = io_input_ar_payload_len; + assign io_outputs_5_ar_payload_size = io_input_ar_payload_size; + assign io_outputs_5_ar_payload_burst = io_input_ar_payload_burst; + assign io_outputs_5_ar_payload_lock = io_input_ar_payload_lock; + assign io_outputs_5_ar_payload_cache = io_input_ar_payload_cache; + assign io_outputs_5_ar_payload_prot = io_input_ar_payload_prot; + assign io_outputs_6_ar_valid = ((io_input_ar_valid && decodedCmdSels[6]) && allowCmd); + assign io_outputs_6_ar_payload_addr = io_input_ar_payload_addr; + assign io_outputs_6_ar_payload_id = io_input_ar_payload_id; + assign io_outputs_6_ar_payload_len = io_input_ar_payload_len; + assign io_outputs_6_ar_payload_size = io_input_ar_payload_size; + assign io_outputs_6_ar_payload_burst = io_input_ar_payload_burst; + assign io_outputs_6_ar_payload_lock = io_input_ar_payload_lock; + assign io_outputs_6_ar_payload_cache = io_input_ar_payload_cache; + assign io_outputs_6_ar_payload_prot = io_input_ar_payload_prot; + assign io_outputs_7_ar_valid = ((io_input_ar_valid && decodedCmdSels[7]) && allowCmd); + assign io_outputs_7_ar_payload_addr = io_input_ar_payload_addr; + assign io_outputs_7_ar_payload_id = io_input_ar_payload_id; + assign io_outputs_7_ar_payload_len = io_input_ar_payload_len; + assign io_outputs_7_ar_payload_size = io_input_ar_payload_size; + assign io_outputs_7_ar_payload_burst = io_input_ar_payload_burst; + assign io_outputs_7_ar_payload_lock = io_input_ar_payload_lock; + assign io_outputs_7_ar_payload_cache = io_input_ar_payload_cache; + assign io_outputs_7_ar_payload_prot = io_input_ar_payload_prot; + assign _zz_readRspIndex = pendingSels[3]; + assign _zz_readRspIndex_1 = pendingSels[5]; + assign _zz_readRspIndex_2 = pendingSels[6]; + assign _zz_readRspIndex_3 = pendingSels[7]; + assign _zz_readRspIndex_4 = (((pendingSels[1] || _zz_readRspIndex) || _zz_readRspIndex_1) || _zz_readRspIndex_3); + assign _zz_readRspIndex_5 = (((pendingSels[2] || _zz_readRspIndex) || _zz_readRspIndex_2) || _zz_readRspIndex_3); + assign _zz_readRspIndex_6 = (((pendingSels[4] || _zz_readRspIndex_1) || _zz_readRspIndex_2) || _zz_readRspIndex_3); + assign readRspIndex = {_zz_readRspIndex_6,{_zz_readRspIndex_5,_zz_readRspIndex_4}}; + always @(*) begin + io_input_r_valid = (|{io_outputs_7_r_valid,{io_outputs_6_r_valid,{io_outputs_5_r_valid,{io_outputs_4_r_valid,{io_outputs_3_r_valid,{io_outputs_2_r_valid,{io_outputs_1_r_valid,io_outputs_0_r_valid}}}}}}}); + if(errorSlave_io_axi_r_valid) begin + io_input_r_valid = 1'b1; + end + end + + assign io_input_r_payload_data = _zz_io_input_r_payload_data; + always @(*) begin + io_input_r_payload_id = _zz_io_input_r_payload_id; + if(pendingError) begin + io_input_r_payload_id = errorSlave_io_axi_r_payload_id; + end + end + + always @(*) begin + io_input_r_payload_resp = _zz_io_input_r_payload_resp; + if(pendingError) begin + io_input_r_payload_resp = errorSlave_io_axi_r_payload_resp; + end + end + + always @(*) begin + io_input_r_payload_last = _zz_io_input_r_payload_last; + if(pendingError) begin + io_input_r_payload_last = errorSlave_io_axi_r_payload_last; + end + end + + assign io_outputs_0_r_ready = io_input_r_ready; + assign io_outputs_1_r_ready = io_input_r_ready; + assign io_outputs_2_r_ready = io_input_r_ready; + assign io_outputs_3_r_ready = io_input_r_ready; + assign io_outputs_4_r_ready = io_input_r_ready; + assign io_outputs_5_r_ready = io_input_r_ready; + assign io_outputs_6_r_ready = io_input_r_ready; + assign io_outputs_7_r_ready = io_input_r_ready; + always @(posedge clk or negedge resetn) begin + if(!resetn) begin + pendingCmdCounter_value <= 3'b000; + pendingSels <= 8'h00; + pendingError <= 1'b0; + end else begin + pendingCmdCounter_value <= pendingCmdCounter_valueNext; + if(io_input_ar_ready) begin + pendingSels <= decodedCmdSels; + end + if(io_input_ar_ready) begin + pendingError <= decodedCmdError; + end + end + end + + +endmodule + +//StreamFifoLowLatency replaced by StreamFifoLowLatency_3 + +//StreamArbiter replaced by StreamArbiter_7 + +//StreamArbiter_1 replaced by StreamArbiter_7 + +//StreamFifoLowLatency_1 replaced by StreamFifoLowLatency_3 + +//StreamArbiter_2 replaced by StreamArbiter_7 + +//StreamArbiter_3 replaced by StreamArbiter_7 + +//StreamFifoLowLatency_2 replaced by StreamFifoLowLatency_3 + +//StreamArbiter_4 replaced by StreamArbiter_7 + +//StreamArbiter_5 replaced by StreamArbiter_7 + +module StreamFifoLowLatency_3 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [0:0] io_push_payload, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [0:0] io_pop_payload, + input wire io_flush, + output wire [2:0] io_occupancy, + output wire [2:0] io_availability, + input wire clk, + input wire resetn +); + + wire fifo_io_push_ready; + wire fifo_io_pop_valid; + wire [0:0] fifo_io_pop_payload; + wire [2:0] fifo_io_occupancy; + wire [2:0] fifo_io_availability; + + StreamFifo_3 fifo ( + .io_push_valid (io_push_valid ), //i + .io_push_ready (fifo_io_push_ready ), //o + .io_push_payload (io_push_payload ), //i + .io_pop_valid (fifo_io_pop_valid ), //o + .io_pop_ready (io_pop_ready ), //i + .io_pop_payload (fifo_io_pop_payload ), //o + .io_flush (io_flush ), //i + .io_occupancy (fifo_io_occupancy[2:0] ), //o + .io_availability (fifo_io_availability[2:0]), //o + .clk (clk ), //i + .resetn (resetn ) //i + ); + assign io_push_ready = fifo_io_push_ready; + assign io_pop_valid = fifo_io_pop_valid; + assign io_pop_payload = fifo_io_pop_payload; + assign io_occupancy = fifo_io_occupancy; + assign io_availability = fifo_io_availability; + +endmodule + +//StreamArbiter_6 replaced by StreamArbiter_7 + +module StreamArbiter_7 ( + input wire io_inputs_0_valid, + output wire io_inputs_0_ready, + input wire [31:0] io_inputs_0_payload_addr, + input wire [3:0] io_inputs_0_payload_id, + input wire [7:0] io_inputs_0_payload_len, + input wire [2:0] io_inputs_0_payload_size, + input wire [1:0] io_inputs_0_payload_burst, + input wire [0:0] io_inputs_0_payload_lock, + input wire [3:0] io_inputs_0_payload_cache, + input wire [2:0] io_inputs_0_payload_prot, + input wire io_inputs_1_valid, + output wire io_inputs_1_ready, + input wire [31:0] io_inputs_1_payload_addr, + input wire [3:0] io_inputs_1_payload_id, + input wire [7:0] io_inputs_1_payload_len, + input wire [2:0] io_inputs_1_payload_size, + input wire [1:0] io_inputs_1_payload_burst, + input wire [0:0] io_inputs_1_payload_lock, + input wire [3:0] io_inputs_1_payload_cache, + input wire [2:0] io_inputs_1_payload_prot, + output wire io_output_valid, + input wire io_output_ready, + output wire [31:0] io_output_payload_addr, + output wire [3:0] io_output_payload_id, + output wire [7:0] io_output_payload_len, + output wire [2:0] io_output_payload_size, + output wire [1:0] io_output_payload_burst, + output wire [0:0] io_output_payload_lock, + output wire [3:0] io_output_payload_cache, + output wire [2:0] io_output_payload_prot, + output wire [0:0] io_chosen, + output wire [1:0] io_chosenOH, + input wire clk, + input wire resetn +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_addr = (maskRouted_0 ? io_inputs_0_payload_addr : io_inputs_1_payload_addr); + assign io_output_payload_id = (maskRouted_0 ? io_inputs_0_payload_id : io_inputs_1_payload_id); + assign io_output_payload_len = (maskRouted_0 ? io_inputs_0_payload_len : io_inputs_1_payload_len); + assign io_output_payload_size = (maskRouted_0 ? io_inputs_0_payload_size : io_inputs_1_payload_size); + assign io_output_payload_burst = (maskRouted_0 ? io_inputs_0_payload_burst : io_inputs_1_payload_burst); + assign io_output_payload_lock = (maskRouted_0 ? io_inputs_0_payload_lock : io_inputs_1_payload_lock); + assign io_output_payload_cache = (maskRouted_0 ? io_inputs_0_payload_cache : io_inputs_1_payload_cache); + assign io_output_payload_prot = (maskRouted_0 ? io_inputs_0_payload_prot : io_inputs_1_payload_prot); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge clk or negedge resetn) begin + if(!resetn) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(io_output_fire) begin + locked <= 1'b0; + end + end + end + + +endmodule + +//Axi4WriteOnlyErrorSlave replaced by Axi4WriteOnlyErrorSlave_1 + +//Axi4ReadOnlyErrorSlave replaced by Axi4ReadOnlyErrorSlave_1 + +module Axi4WriteOnlyErrorSlave_1 ( + input wire io_axi_aw_valid, + output wire io_axi_aw_ready, + input wire [31:0] io_axi_aw_payload_addr, + input wire [3:0] io_axi_aw_payload_id, + input wire [7:0] io_axi_aw_payload_len, + input wire [2:0] io_axi_aw_payload_size, + input wire [1:0] io_axi_aw_payload_burst, + input wire [0:0] io_axi_aw_payload_lock, + input wire [3:0] io_axi_aw_payload_cache, + input wire [2:0] io_axi_aw_payload_prot, + input wire io_axi_w_valid, + output wire io_axi_w_ready, + input wire [31:0] io_axi_w_payload_data, + input wire [3:0] io_axi_w_payload_strb, + input wire io_axi_w_payload_last, + output wire io_axi_b_valid, + input wire io_axi_b_ready, + output wire [3:0] io_axi_b_payload_id, + output wire [1:0] io_axi_b_payload_resp, + input wire clk, + input wire resetn +); + + reg consumeData; + reg sendRsp; + reg [3:0] id; + wire io_axi_aw_fire; + wire io_axi_w_fire; + wire when_Axi4ErrorSlave_l24; + wire io_axi_b_fire; + + assign io_axi_aw_ready = (! (consumeData || sendRsp)); + assign io_axi_aw_fire = (io_axi_aw_valid && io_axi_aw_ready); + assign io_axi_w_ready = consumeData; + assign io_axi_w_fire = (io_axi_w_valid && io_axi_w_ready); + assign when_Axi4ErrorSlave_l24 = (io_axi_w_fire && io_axi_w_payload_last); + assign io_axi_b_valid = sendRsp; + assign io_axi_b_payload_resp = 2'b11; + assign io_axi_b_payload_id = id; + assign io_axi_b_fire = (io_axi_b_valid && io_axi_b_ready); + always @(posedge clk or negedge resetn) begin + if(!resetn) begin + consumeData <= 1'b0; + sendRsp <= 1'b0; + end else begin + if(io_axi_aw_fire) begin + consumeData <= 1'b1; + end + if(when_Axi4ErrorSlave_l24) begin + consumeData <= 1'b0; + sendRsp <= 1'b1; + end + if(io_axi_b_fire) begin + sendRsp <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(io_axi_aw_fire) begin + id <= io_axi_aw_payload_id; + end + end + + +endmodule + +module Axi4ReadOnlyErrorSlave_1 ( + input wire io_axi_ar_valid, + output wire io_axi_ar_ready, + input wire [31:0] io_axi_ar_payload_addr, + input wire [3:0] io_axi_ar_payload_id, + input wire [7:0] io_axi_ar_payload_len, + input wire [2:0] io_axi_ar_payload_size, + input wire [1:0] io_axi_ar_payload_burst, + input wire [0:0] io_axi_ar_payload_lock, + input wire [3:0] io_axi_ar_payload_cache, + input wire [2:0] io_axi_ar_payload_prot, + output wire io_axi_r_valid, + input wire io_axi_r_ready, + output wire [31:0] io_axi_r_payload_data, + output wire [3:0] io_axi_r_payload_id, + output wire [1:0] io_axi_r_payload_resp, + output wire io_axi_r_payload_last, + input wire clk, + input wire resetn +); + + reg sendRsp; + reg [3:0] id; + reg [7:0] remaining; + wire remainingZero; + wire io_axi_ar_fire; + + assign remainingZero = (remaining == 8'h00); + assign io_axi_ar_ready = (! sendRsp); + assign io_axi_ar_fire = (io_axi_ar_valid && io_axi_ar_ready); + assign io_axi_r_valid = sendRsp; + assign io_axi_r_payload_id = id; + assign io_axi_r_payload_resp = 2'b11; + assign io_axi_r_payload_last = remainingZero; + always @(posedge clk or negedge resetn) begin + if(!resetn) begin + sendRsp <= 1'b0; + end else begin + if(io_axi_ar_fire) begin + sendRsp <= 1'b1; + end + if(sendRsp) begin + if(io_axi_r_ready) begin + if(remainingZero) begin + sendRsp <= 1'b0; + end + end + end + end + end + + always @(posedge clk) begin + if(io_axi_ar_fire) begin + remaining <= io_axi_ar_payload_len; + id <= io_axi_ar_payload_id; + end + if(sendRsp) begin + if(io_axi_r_ready) begin + remaining <= (remaining - 8'h01); + end + end + end + + +endmodule + +//StreamFifo replaced by StreamFifo_3 + +//StreamFifo_1 replaced by StreamFifo_3 + +//StreamFifo_2 replaced by StreamFifo_3 + +module StreamFifo_3 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [0:0] io_push_payload, + output reg io_pop_valid, + input wire io_pop_ready, + output reg [0:0] io_pop_payload, + input wire io_flush, + output wire [2:0] io_occupancy, + output wire [2:0] io_availability, + input wire clk, + input wire resetn +); + + wire [0:0] _zz_logic_ram_port1; + wire [0:0] _zz_logic_ram_port; + reg _zz_1; + reg logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [2:0] logic_ptr_push; + reg [2:0] logic_ptr_pop; + wire [2:0] logic_ptr_occupancy; + wire [2:0] logic_ptr_popOnIo; + wire when_Stream_l1205; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [1:0] logic_push_onRam_write_payload_address; + wire [0:0] logic_push_onRam_write_payload_data; + wire logic_pop_addressGen_valid; + wire logic_pop_addressGen_ready; + wire [1:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire [0:0] logic_pop_async_readed; + wire logic_pop_addressGen_translated_valid; + wire logic_pop_addressGen_translated_ready; + wire [0:0] logic_pop_addressGen_translated_payload; + (* ram_style = "distributed" *) reg [0:0] logic_ram [0:3]; + + assign _zz_logic_ram_port = logic_push_onRam_write_payload_data; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= _zz_logic_ram_port; + end + end + + assign _zz_logic_ram_port1 = logic_ram[logic_pop_addressGen_payload]; + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1205 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 3'b100) == 3'b000); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + always @(*) begin + logic_ptr_doPush = io_push_fire; + if(logic_ptr_empty) begin + if(io_pop_ready) begin + logic_ptr_doPush = 1'b0; + end + end + end + + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[1:0]; + assign logic_push_onRam_write_payload_data = io_push_payload; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[1:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + assign logic_pop_async_readed = _zz_logic_ram_port1; + assign logic_pop_addressGen_translated_valid = logic_pop_addressGen_valid; + assign logic_pop_addressGen_ready = logic_pop_addressGen_translated_ready; + assign logic_pop_addressGen_translated_payload = logic_pop_async_readed; + always @(*) begin + io_pop_valid = logic_pop_addressGen_translated_valid; + if(logic_ptr_empty) begin + io_pop_valid = io_push_valid; + end + end + + assign logic_pop_addressGen_translated_ready = io_pop_ready; + always @(*) begin + io_pop_payload = logic_pop_addressGen_translated_payload; + if(logic_ptr_empty) begin + io_pop_payload = io_push_payload; + end + end + + assign logic_ptr_popOnIo = logic_ptr_pop; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (3'b100 - logic_ptr_occupancy); + always @(posedge clk or negedge resetn) begin + if(!resetn) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + logic_ptr_wentUp <= 1'b0; + end else begin + if(when_Stream_l1205) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 3'b001); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 3'b001); + end + if(io_flush) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + end + end + end + + +endmodule diff --git a/rtl/ip/Bus_interconnects/Axi_CDC.v b/rtl/ip/Bus_interconnects/Axi_CDC.v new file mode 100644 index 0000000..572d826 --- /dev/null +++ b/rtl/ip/Bus_interconnects/Axi_CDC.v @@ -0,0 +1,1608 @@ +// Generator : SpinalHDL v1.10.1 git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43 +// Component : Axi_CDC + +`timescale 1ns/1ps + +module Axi_CDC ( + input wire axiInClk, + input wire axiInRstn, + input wire axiOutClk, + input wire axiOutRstn, + input wire axiIn_awvalid, + output wire axiIn_awready, + input wire [31:0] axiIn_awaddr, + input wire [4:0] axiIn_awid, + input wire [7:0] axiIn_awlen, + input wire [2:0] axiIn_awsize, + input wire [1:0] axiIn_awburst, + input wire [0:0] axiIn_awlock, + input wire [3:0] axiIn_awcache, + input wire [2:0] axiIn_awprot, + input wire axiIn_wvalid, + output wire axiIn_wready, + input wire [31:0] axiIn_wdata, + input wire [3:0] axiIn_wstrb, + input wire axiIn_wlast, + output wire axiIn_bvalid, + input wire axiIn_bready, + output wire [4:0] axiIn_bid, + output wire [1:0] axiIn_bresp, + input wire axiIn_arvalid, + output wire axiIn_arready, + input wire [31:0] axiIn_araddr, + input wire [4:0] axiIn_arid, + input wire [7:0] axiIn_arlen, + input wire [2:0] axiIn_arsize, + input wire [1:0] axiIn_arburst, + input wire [0:0] axiIn_arlock, + input wire [3:0] axiIn_arcache, + input wire [2:0] axiIn_arprot, + output wire axiIn_rvalid, + input wire axiIn_rready, + output wire [31:0] axiIn_rdata, + output wire [4:0] axiIn_rid, + output wire [1:0] axiIn_rresp, + output wire axiIn_rlast, + output wire axiOut_awvalid, + input wire axiOut_awready, + output wire [31:0] axiOut_awaddr, + output wire [4:0] axiOut_awid, + output wire [7:0] axiOut_awlen, + output wire [2:0] axiOut_awsize, + output wire [1:0] axiOut_awburst, + output wire [0:0] axiOut_awlock, + output wire [3:0] axiOut_awcache, + output wire [2:0] axiOut_awprot, + output wire axiOut_wvalid, + input wire axiOut_wready, + output wire [31:0] axiOut_wdata, + output wire [3:0] axiOut_wstrb, + output wire axiOut_wlast, + input wire axiOut_bvalid, + output wire axiOut_bready, + input wire [4:0] axiOut_bid, + input wire [1:0] axiOut_bresp, + output wire axiOut_arvalid, + input wire axiOut_arready, + output wire [31:0] axiOut_araddr, + output wire [4:0] axiOut_arid, + output wire [7:0] axiOut_arlen, + output wire [2:0] axiOut_arsize, + output wire [1:0] axiOut_arburst, + output wire [0:0] axiOut_arlock, + output wire [3:0] axiOut_arcache, + output wire [2:0] axiOut_arprot, + input wire axiOut_rvalid, + output wire axiOut_rready, + input wire [31:0] axiOut_rdata, + input wire [4:0] axiOut_rid, + input wire [1:0] axiOut_rresp, + input wire axiOut_rlast +); + + wire awFifo_io_push_ready; + wire awFifo_io_pop_valid; + wire [31:0] awFifo_io_pop_payload_addr; + wire [4:0] awFifo_io_pop_payload_id; + wire [7:0] awFifo_io_pop_payload_len; + wire [2:0] awFifo_io_pop_payload_size; + wire [1:0] awFifo_io_pop_payload_burst; + wire [0:0] awFifo_io_pop_payload_lock; + wire [3:0] awFifo_io_pop_payload_cache; + wire [2:0] awFifo_io_pop_payload_prot; + wire [2:0] awFifo_io_pushOccupancy; + wire [2:0] awFifo_io_popOccupancy; + wire awFifo_awFifo_toplevel_axiInRstn_syncronized_1; + wire wFifo_io_push_ready; + wire wFifo_io_pop_valid; + wire [31:0] wFifo_io_pop_payload_data; + wire [3:0] wFifo_io_pop_payload_strb; + wire wFifo_io_pop_payload_last; + wire [3:0] wFifo_io_pushOccupancy; + wire [3:0] wFifo_io_popOccupancy; + wire bFifo_io_push_ready; + wire bFifo_io_pop_valid; + wire [4:0] bFifo_io_pop_payload_id; + wire [1:0] bFifo_io_pop_payload_resp; + wire [2:0] bFifo_io_pushOccupancy; + wire [2:0] bFifo_io_popOccupancy; + wire bFifo_bFifo_toplevel_axiOutRstn_syncronized_1; + wire arFifo_io_push_ready; + wire arFifo_io_pop_valid; + wire [31:0] arFifo_io_pop_payload_addr; + wire [4:0] arFifo_io_pop_payload_id; + wire [7:0] arFifo_io_pop_payload_len; + wire [2:0] arFifo_io_pop_payload_size; + wire [1:0] arFifo_io_pop_payload_burst; + wire [0:0] arFifo_io_pop_payload_lock; + wire [3:0] arFifo_io_pop_payload_cache; + wire [2:0] arFifo_io_pop_payload_prot; + wire [2:0] arFifo_io_pushOccupancy; + wire [2:0] arFifo_io_popOccupancy; + wire rFifo_io_push_ready; + wire rFifo_io_pop_valid; + wire [31:0] rFifo_io_pop_payload_data; + wire [4:0] rFifo_io_pop_payload_id; + wire [1:0] rFifo_io_pop_payload_resp; + wire rFifo_io_pop_payload_last; + wire [3:0] rFifo_io_pushOccupancy; + wire [3:0] rFifo_io_popOccupancy; + + StreamFifoCC awFifo ( + .io_push_valid (axiIn_awvalid ), //i + .io_push_ready (awFifo_io_push_ready ), //o + .io_push_payload_addr (axiIn_awaddr[31:0] ), //i + .io_push_payload_id (axiIn_awid[4:0] ), //i + .io_push_payload_len (axiIn_awlen[7:0] ), //i + .io_push_payload_size (axiIn_awsize[2:0] ), //i + .io_push_payload_burst (axiIn_awburst[1:0] ), //i + .io_push_payload_lock (axiIn_awlock ), //i + .io_push_payload_cache (axiIn_awcache[3:0] ), //i + .io_push_payload_prot (axiIn_awprot[2:0] ), //i + .io_pop_valid (awFifo_io_pop_valid ), //o + .io_pop_ready (axiOut_awready ), //i + .io_pop_payload_addr (awFifo_io_pop_payload_addr[31:0] ), //o + .io_pop_payload_id (awFifo_io_pop_payload_id[4:0] ), //o + .io_pop_payload_len (awFifo_io_pop_payload_len[7:0] ), //o + .io_pop_payload_size (awFifo_io_pop_payload_size[2:0] ), //o + .io_pop_payload_burst (awFifo_io_pop_payload_burst[1:0] ), //o + .io_pop_payload_lock (awFifo_io_pop_payload_lock ), //o + .io_pop_payload_cache (awFifo_io_pop_payload_cache[3:0] ), //o + .io_pop_payload_prot (awFifo_io_pop_payload_prot[2:0] ), //o + .io_pushOccupancy (awFifo_io_pushOccupancy[2:0] ), //o + .io_popOccupancy (awFifo_io_popOccupancy[2:0] ), //o + .axiInClk (axiInClk ), //i + .axiInRstn (axiInRstn ), //i + .axiOutClk (axiOutClk ), //i + .awFifo_toplevel_axiInRstn_syncronized_1 (awFifo_awFifo_toplevel_axiInRstn_syncronized_1) //o + ); + StreamFifoCC_1 wFifo ( + .io_push_valid (axiIn_wvalid ), //i + .io_push_ready (wFifo_io_push_ready ), //o + .io_push_payload_data (axiIn_wdata[31:0] ), //i + .io_push_payload_strb (axiIn_wstrb[3:0] ), //i + .io_push_payload_last (axiIn_wlast ), //i + .io_pop_valid (wFifo_io_pop_valid ), //o + .io_pop_ready (axiOut_wready ), //i + .io_pop_payload_data (wFifo_io_pop_payload_data[31:0] ), //o + .io_pop_payload_strb (wFifo_io_pop_payload_strb[3:0] ), //o + .io_pop_payload_last (wFifo_io_pop_payload_last ), //o + .io_pushOccupancy (wFifo_io_pushOccupancy[3:0] ), //o + .io_popOccupancy (wFifo_io_popOccupancy[3:0] ), //o + .axiInClk (axiInClk ), //i + .axiInRstn (axiInRstn ), //i + .axiOutClk (axiOutClk ), //i + .awFifo_toplevel_axiInRstn_syncronized (awFifo_awFifo_toplevel_axiInRstn_syncronized_1) //i + ); + StreamFifoCC_2 bFifo ( + .io_push_valid (axiOut_bvalid ), //i + .io_push_ready (bFifo_io_push_ready ), //o + .io_push_payload_id (axiOut_bid[4:0] ), //i + .io_push_payload_resp (axiOut_bresp[1:0] ), //i + .io_pop_valid (bFifo_io_pop_valid ), //o + .io_pop_ready (axiIn_bready ), //i + .io_pop_payload_id (bFifo_io_pop_payload_id[4:0] ), //o + .io_pop_payload_resp (bFifo_io_pop_payload_resp[1:0] ), //o + .io_pushOccupancy (bFifo_io_pushOccupancy[2:0] ), //o + .io_popOccupancy (bFifo_io_popOccupancy[2:0] ), //o + .axiOutClk (axiOutClk ), //i + .axiOutRstn (axiOutRstn ), //i + .axiInClk (axiInClk ), //i + .bFifo_toplevel_axiOutRstn_syncronized_1 (bFifo_bFifo_toplevel_axiOutRstn_syncronized_1) //o + ); + StreamFifoCC_3 arFifo ( + .io_push_valid (axiIn_arvalid ), //i + .io_push_ready (arFifo_io_push_ready ), //o + .io_push_payload_addr (axiIn_araddr[31:0] ), //i + .io_push_payload_id (axiIn_arid[4:0] ), //i + .io_push_payload_len (axiIn_arlen[7:0] ), //i + .io_push_payload_size (axiIn_arsize[2:0] ), //i + .io_push_payload_burst (axiIn_arburst[1:0] ), //i + .io_push_payload_lock (axiIn_arlock ), //i + .io_push_payload_cache (axiIn_arcache[3:0] ), //i + .io_push_payload_prot (axiIn_arprot[2:0] ), //i + .io_pop_valid (arFifo_io_pop_valid ), //o + .io_pop_ready (axiOut_arready ), //i + .io_pop_payload_addr (arFifo_io_pop_payload_addr[31:0] ), //o + .io_pop_payload_id (arFifo_io_pop_payload_id[4:0] ), //o + .io_pop_payload_len (arFifo_io_pop_payload_len[7:0] ), //o + .io_pop_payload_size (arFifo_io_pop_payload_size[2:0] ), //o + .io_pop_payload_burst (arFifo_io_pop_payload_burst[1:0] ), //o + .io_pop_payload_lock (arFifo_io_pop_payload_lock ), //o + .io_pop_payload_cache (arFifo_io_pop_payload_cache[3:0] ), //o + .io_pop_payload_prot (arFifo_io_pop_payload_prot[2:0] ), //o + .io_pushOccupancy (arFifo_io_pushOccupancy[2:0] ), //o + .io_popOccupancy (arFifo_io_popOccupancy[2:0] ), //o + .axiInClk (axiInClk ), //i + .axiInRstn (axiInRstn ), //i + .axiOutClk (axiOutClk ), //i + .awFifo_toplevel_axiInRstn_syncronized (awFifo_awFifo_toplevel_axiInRstn_syncronized_1) //i + ); + StreamFifoCC_4 rFifo ( + .io_push_valid (axiOut_rvalid ), //i + .io_push_ready (rFifo_io_push_ready ), //o + .io_push_payload_data (axiOut_rdata[31:0] ), //i + .io_push_payload_id (axiOut_rid[4:0] ), //i + .io_push_payload_resp (axiOut_rresp[1:0] ), //i + .io_push_payload_last (axiOut_rlast ), //i + .io_pop_valid (rFifo_io_pop_valid ), //o + .io_pop_ready (axiIn_rready ), //i + .io_pop_payload_data (rFifo_io_pop_payload_data[31:0] ), //o + .io_pop_payload_id (rFifo_io_pop_payload_id[4:0] ), //o + .io_pop_payload_resp (rFifo_io_pop_payload_resp[1:0] ), //o + .io_pop_payload_last (rFifo_io_pop_payload_last ), //o + .io_pushOccupancy (rFifo_io_pushOccupancy[3:0] ), //o + .io_popOccupancy (rFifo_io_popOccupancy[3:0] ), //o + .axiOutClk (axiOutClk ), //i + .axiOutRstn (axiOutRstn ), //i + .axiInClk (axiInClk ), //i + .bFifo_toplevel_axiOutRstn_syncronized (bFifo_bFifo_toplevel_axiOutRstn_syncronized_1) //i + ); + assign axiIn_awready = awFifo_io_push_ready; + assign axiOut_awvalid = awFifo_io_pop_valid; + assign axiOut_awaddr = awFifo_io_pop_payload_addr; + assign axiOut_awid = awFifo_io_pop_payload_id; + assign axiOut_awlen = awFifo_io_pop_payload_len; + assign axiOut_awsize = awFifo_io_pop_payload_size; + assign axiOut_awburst = awFifo_io_pop_payload_burst; + assign axiOut_awlock = awFifo_io_pop_payload_lock; + assign axiOut_awcache = awFifo_io_pop_payload_cache; + assign axiOut_awprot = awFifo_io_pop_payload_prot; + assign axiIn_wready = wFifo_io_push_ready; + assign axiOut_wvalid = wFifo_io_pop_valid; + assign axiOut_wdata = wFifo_io_pop_payload_data; + assign axiOut_wstrb = wFifo_io_pop_payload_strb; + assign axiOut_wlast = wFifo_io_pop_payload_last; + assign axiOut_bready = bFifo_io_push_ready; + assign axiIn_bvalid = bFifo_io_pop_valid; + assign axiIn_bid = bFifo_io_pop_payload_id; + assign axiIn_bresp = bFifo_io_pop_payload_resp; + assign axiIn_arready = arFifo_io_push_ready; + assign axiOut_arvalid = arFifo_io_pop_valid; + assign axiOut_araddr = arFifo_io_pop_payload_addr; + assign axiOut_arid = arFifo_io_pop_payload_id; + assign axiOut_arlen = arFifo_io_pop_payload_len; + assign axiOut_arsize = arFifo_io_pop_payload_size; + assign axiOut_arburst = arFifo_io_pop_payload_burst; + assign axiOut_arlock = arFifo_io_pop_payload_lock; + assign axiOut_arcache = arFifo_io_pop_payload_cache; + assign axiOut_arprot = arFifo_io_pop_payload_prot; + assign axiOut_rready = rFifo_io_push_ready; + assign axiIn_rvalid = rFifo_io_pop_valid; + assign axiIn_rdata = rFifo_io_pop_payload_data; + assign axiIn_rid = rFifo_io_pop_payload_id; + assign axiIn_rresp = rFifo_io_pop_payload_resp; + assign axiIn_rlast = rFifo_io_pop_payload_last; + +endmodule + +module StreamFifoCC_4 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [31:0] io_push_payload_data, + input wire [4:0] io_push_payload_id, + input wire [1:0] io_push_payload_resp, + input wire io_push_payload_last, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [31:0] io_pop_payload_data, + output wire [4:0] io_pop_payload_id, + output wire [1:0] io_pop_payload_resp, + output wire io_pop_payload_last, + output wire [3:0] io_pushOccupancy, + output wire [3:0] io_popOccupancy, + input wire axiOutClk, + input wire axiOutRstn, + input wire axiInClk, + input wire bFifo_toplevel_axiOutRstn_syncronized +); + + reg [39:0] _zz_ram_port1; + wire [3:0] popToPushGray_buffercc_io_dataOut; + wire [3:0] pushToPopGray_buffercc_io_dataOut; + wire [3:0] _zz_pushCC_pushPtrGray; + wire [2:0] _zz_ram_port; + wire [39:0] _zz_ram_port_1; + wire [3:0] _zz_popCC_popPtrGray; + reg _zz_1; + wire [3:0] popToPushGray; + wire [3:0] pushToPopGray; + reg [3:0] pushCC_pushPtr; + wire [3:0] pushCC_pushPtrPlus; + wire io_push_fire; + reg [3:0] pushCC_pushPtrGray; + wire [3:0] pushCC_popPtrGray; + wire pushCC_full; + wire _zz_io_pushOccupancy; + wire _zz_io_pushOccupancy_1; + wire _zz_io_pushOccupancy_2; + reg [3:0] popCC_popPtr; + (* keep , syn_keep *) wire [3:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; + wire [3:0] popCC_popPtrGray; + wire [3:0] popCC_pushPtrGray; + wire popCC_addressGen_valid; + reg popCC_addressGen_ready; + wire [2:0] popCC_addressGen_payload; + wire popCC_empty; + wire popCC_addressGen_fire; + wire popCC_readArbitation_valid; + wire popCC_readArbitation_ready; + wire [2:0] popCC_readArbitation_payload; + reg popCC_addressGen_rValid; + reg [2:0] popCC_addressGen_rData; + wire when_Stream_l369; + wire popCC_readPort_cmd_valid; + wire [2:0] popCC_readPort_cmd_payload; + wire [31:0] popCC_readPort_rsp_data; + wire [4:0] popCC_readPort_rsp_id; + wire [1:0] popCC_readPort_rsp_resp; + wire popCC_readPort_rsp_last; + wire [39:0] _zz_popCC_readPort_rsp_data; + wire popCC_readArbitation_translated_valid; + wire popCC_readArbitation_translated_ready; + wire [31:0] popCC_readArbitation_translated_payload_data; + wire [4:0] popCC_readArbitation_translated_payload_id; + wire [1:0] popCC_readArbitation_translated_payload_resp; + wire popCC_readArbitation_translated_payload_last; + wire popCC_readArbitation_fire; + reg [3:0] popCC_ptrToPush; + reg [3:0] popCC_ptrToOccupancy; + wire _zz_io_popOccupancy; + wire _zz_io_popOccupancy_1; + wire _zz_io_popOccupancy_2; + reg [39:0] ram [0:7]; + + assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); + assign _zz_ram_port = pushCC_pushPtr[2:0]; + assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); + assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_resp,{io_push_payload_id,io_push_payload_data}}}; + always @(posedge axiOutClk) begin + if(_zz_1) begin + ram[_zz_ram_port] <= _zz_ram_port_1; + end + end + + always @(posedge axiInClk) begin + if(popCC_readPort_cmd_valid) begin + _zz_ram_port1 <= ram[popCC_readPort_cmd_payload]; + end + end + + BufferCC popToPushGray_buffercc ( + .io_dataIn (popToPushGray[3:0] ), //i + .io_dataOut (popToPushGray_buffercc_io_dataOut[3:0]), //o + .axiOutClk (axiOutClk ), //i + .axiOutRstn (axiOutRstn ) //i + ); + BufferCC_1 pushToPopGray_buffercc ( + .io_dataIn (pushToPopGray[3:0] ), //i + .io_dataOut (pushToPopGray_buffercc_io_dataOut[3:0]), //o + .axiInClk (axiInClk ), //i + .bFifo_toplevel_axiOutRstn_syncronized (bFifo_toplevel_axiOutRstn_syncronized ) //i + ); + always @(*) begin + _zz_1 = 1'b0; + if(io_push_fire) begin + _zz_1 = 1'b1; + end + end + + assign pushCC_pushPtrPlus = (pushCC_pushPtr + 4'b0001); + assign io_push_fire = (io_push_valid && io_push_ready); + assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; + assign pushCC_full = ((pushCC_pushPtrGray[3 : 2] == (~ pushCC_popPtrGray[3 : 2])) && (pushCC_pushPtrGray[1 : 0] == pushCC_popPtrGray[1 : 0])); + assign io_push_ready = (! pushCC_full); + assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); + assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); + assign _zz_io_pushOccupancy_2 = pushCC_popPtrGray[3]; + assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}); + assign popCC_popPtrPlus = (popCC_popPtr + 4'b0001); + assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); + assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; + assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); + assign popCC_addressGen_valid = (! popCC_empty); + assign popCC_addressGen_payload = popCC_popPtr[2:0]; + assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); + always @(*) begin + popCC_addressGen_ready = popCC_readArbitation_ready; + if(when_Stream_l369) begin + popCC_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l369 = (! popCC_readArbitation_valid); + assign popCC_readArbitation_valid = popCC_addressGen_rValid; + assign popCC_readArbitation_payload = popCC_addressGen_rData; + assign _zz_popCC_readPort_rsp_data = _zz_ram_port1; + assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[31 : 0]; + assign popCC_readPort_rsp_id = _zz_popCC_readPort_rsp_data[36 : 32]; + assign popCC_readPort_rsp_resp = _zz_popCC_readPort_rsp_data[38 : 37]; + assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[39]; + assign popCC_readPort_cmd_valid = popCC_addressGen_fire; + assign popCC_readPort_cmd_payload = popCC_addressGen_payload; + assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; + assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; + assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; + assign popCC_readArbitation_translated_payload_id = popCC_readPort_rsp_id; + assign popCC_readArbitation_translated_payload_resp = popCC_readPort_rsp_resp; + assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; + assign io_pop_valid = popCC_readArbitation_translated_valid; + assign popCC_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; + assign io_pop_payload_id = popCC_readArbitation_translated_payload_id; + assign io_pop_payload_resp = popCC_readArbitation_translated_payload_resp; + assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; + assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); + assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); + assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); + assign _zz_io_popOccupancy_2 = popCC_pushPtrGray[3]; + assign io_popOccupancy = ({_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}} - popCC_ptrToOccupancy); + assign pushToPopGray = pushCC_pushPtrGray; + assign popToPushGray = popCC_ptrToPush; + always @(posedge axiOutClk or negedge axiOutRstn) begin + if(!axiOutRstn) begin + pushCC_pushPtr <= 4'b0000; + pushCC_pushPtrGray <= 4'b0000; + end else begin + if(io_push_fire) begin + pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); + end + if(io_push_fire) begin + pushCC_pushPtr <= pushCC_pushPtrPlus; + end + end + end + + always @(posedge axiInClk or negedge bFifo_toplevel_axiOutRstn_syncronized) begin + if(!bFifo_toplevel_axiOutRstn_syncronized) begin + popCC_popPtr <= 4'b0000; + popCC_addressGen_rValid <= 1'b0; + popCC_ptrToPush <= 4'b0000; + popCC_ptrToOccupancy <= 4'b0000; + end else begin + if(popCC_addressGen_fire) begin + popCC_popPtr <= popCC_popPtrPlus; + end + if(popCC_addressGen_ready) begin + popCC_addressGen_rValid <= popCC_addressGen_valid; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToPush <= popCC_popPtrGray; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToOccupancy <= popCC_popPtr; + end + end + end + + always @(posedge axiInClk) begin + if(popCC_addressGen_ready) begin + popCC_addressGen_rData <= popCC_addressGen_payload; + end + end + + +endmodule + +module StreamFifoCC_3 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [31:0] io_push_payload_addr, + input wire [4:0] io_push_payload_id, + input wire [7:0] io_push_payload_len, + input wire [2:0] io_push_payload_size, + input wire [1:0] io_push_payload_burst, + input wire [0:0] io_push_payload_lock, + input wire [3:0] io_push_payload_cache, + input wire [2:0] io_push_payload_prot, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [31:0] io_pop_payload_addr, + output wire [4:0] io_pop_payload_id, + output wire [7:0] io_pop_payload_len, + output wire [2:0] io_pop_payload_size, + output wire [1:0] io_pop_payload_burst, + output wire [0:0] io_pop_payload_lock, + output wire [3:0] io_pop_payload_cache, + output wire [2:0] io_pop_payload_prot, + output wire [2:0] io_pushOccupancy, + output wire [2:0] io_popOccupancy, + input wire axiInClk, + input wire axiInRstn, + input wire axiOutClk, + input wire awFifo_toplevel_axiInRstn_syncronized +); + + reg [57:0] _zz_ram_port1; + wire [2:0] popToPushGray_buffercc_io_dataOut; + wire [2:0] pushToPopGray_buffercc_io_dataOut; + wire [2:0] _zz_pushCC_pushPtrGray; + wire [1:0] _zz_ram_port; + wire [57:0] _zz_ram_port_1; + wire [2:0] _zz_popCC_popPtrGray; + reg _zz_1; + wire [2:0] popToPushGray; + wire [2:0] pushToPopGray; + reg [2:0] pushCC_pushPtr; + wire [2:0] pushCC_pushPtrPlus; + wire io_push_fire; + reg [2:0] pushCC_pushPtrGray; + wire [2:0] pushCC_popPtrGray; + wire pushCC_full; + wire _zz_io_pushOccupancy; + wire _zz_io_pushOccupancy_1; + reg [2:0] popCC_popPtr; + (* keep , syn_keep *) wire [2:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; + wire [2:0] popCC_popPtrGray; + wire [2:0] popCC_pushPtrGray; + wire popCC_addressGen_valid; + reg popCC_addressGen_ready; + wire [1:0] popCC_addressGen_payload; + wire popCC_empty; + wire popCC_addressGen_fire; + wire popCC_readArbitation_valid; + wire popCC_readArbitation_ready; + wire [1:0] popCC_readArbitation_payload; + reg popCC_addressGen_rValid; + reg [1:0] popCC_addressGen_rData; + wire when_Stream_l369; + wire popCC_readPort_cmd_valid; + wire [1:0] popCC_readPort_cmd_payload; + wire [31:0] popCC_readPort_rsp_addr; + wire [4:0] popCC_readPort_rsp_id; + wire [7:0] popCC_readPort_rsp_len; + wire [2:0] popCC_readPort_rsp_size; + wire [1:0] popCC_readPort_rsp_burst; + wire [0:0] popCC_readPort_rsp_lock; + wire [3:0] popCC_readPort_rsp_cache; + wire [2:0] popCC_readPort_rsp_prot; + wire [57:0] _zz_popCC_readPort_rsp_addr; + wire popCC_readArbitation_translated_valid; + wire popCC_readArbitation_translated_ready; + wire [31:0] popCC_readArbitation_translated_payload_addr; + wire [4:0] popCC_readArbitation_translated_payload_id; + wire [7:0] popCC_readArbitation_translated_payload_len; + wire [2:0] popCC_readArbitation_translated_payload_size; + wire [1:0] popCC_readArbitation_translated_payload_burst; + wire [0:0] popCC_readArbitation_translated_payload_lock; + wire [3:0] popCC_readArbitation_translated_payload_cache; + wire [2:0] popCC_readArbitation_translated_payload_prot; + wire popCC_readArbitation_fire; + reg [2:0] popCC_ptrToPush; + reg [2:0] popCC_ptrToOccupancy; + wire _zz_io_popOccupancy; + wire _zz_io_popOccupancy_1; + reg [57:0] ram [0:3]; + + assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); + assign _zz_ram_port = pushCC_pushPtr[1:0]; + assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); + assign _zz_ram_port_1 = {io_push_payload_prot,{io_push_payload_cache,{io_push_payload_lock,{io_push_payload_burst,{io_push_payload_size,{io_push_payload_len,{io_push_payload_id,io_push_payload_addr}}}}}}}; + always @(posedge axiInClk) begin + if(_zz_1) begin + ram[_zz_ram_port] <= _zz_ram_port_1; + end + end + + always @(posedge axiOutClk) begin + if(popCC_readPort_cmd_valid) begin + _zz_ram_port1 <= ram[popCC_readPort_cmd_payload]; + end + end + + BufferCC_9 popToPushGray_buffercc ( + .io_dataIn (popToPushGray[2:0] ), //i + .io_dataOut (popToPushGray_buffercc_io_dataOut[2:0]), //o + .axiInClk (axiInClk ), //i + .axiInRstn (axiInRstn ) //i + ); + BufferCC_11 pushToPopGray_buffercc ( + .io_dataIn (pushToPopGray[2:0] ), //i + .io_dataOut (pushToPopGray_buffercc_io_dataOut[2:0]), //o + .axiOutClk (axiOutClk ), //i + .awFifo_toplevel_axiInRstn_syncronized (awFifo_toplevel_axiInRstn_syncronized ) //i + ); + always @(*) begin + _zz_1 = 1'b0; + if(io_push_fire) begin + _zz_1 = 1'b1; + end + end + + assign pushCC_pushPtrPlus = (pushCC_pushPtr + 3'b001); + assign io_push_fire = (io_push_valid && io_push_ready); + assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; + assign pushCC_full = ((pushCC_pushPtrGray[2 : 1] == (~ pushCC_popPtrGray[2 : 1])) && (pushCC_pushPtrGray[0 : 0] == pushCC_popPtrGray[0 : 0])); + assign io_push_ready = (! pushCC_full); + assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); + assign _zz_io_pushOccupancy_1 = pushCC_popPtrGray[2]; + assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}); + assign popCC_popPtrPlus = (popCC_popPtr + 3'b001); + assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); + assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; + assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); + assign popCC_addressGen_valid = (! popCC_empty); + assign popCC_addressGen_payload = popCC_popPtr[1:0]; + assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); + always @(*) begin + popCC_addressGen_ready = popCC_readArbitation_ready; + if(when_Stream_l369) begin + popCC_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l369 = (! popCC_readArbitation_valid); + assign popCC_readArbitation_valid = popCC_addressGen_rValid; + assign popCC_readArbitation_payload = popCC_addressGen_rData; + assign _zz_popCC_readPort_rsp_addr = _zz_ram_port1; + assign popCC_readPort_rsp_addr = _zz_popCC_readPort_rsp_addr[31 : 0]; + assign popCC_readPort_rsp_id = _zz_popCC_readPort_rsp_addr[36 : 32]; + assign popCC_readPort_rsp_len = _zz_popCC_readPort_rsp_addr[44 : 37]; + assign popCC_readPort_rsp_size = _zz_popCC_readPort_rsp_addr[47 : 45]; + assign popCC_readPort_rsp_burst = _zz_popCC_readPort_rsp_addr[49 : 48]; + assign popCC_readPort_rsp_lock = _zz_popCC_readPort_rsp_addr[50 : 50]; + assign popCC_readPort_rsp_cache = _zz_popCC_readPort_rsp_addr[54 : 51]; + assign popCC_readPort_rsp_prot = _zz_popCC_readPort_rsp_addr[57 : 55]; + assign popCC_readPort_cmd_valid = popCC_addressGen_fire; + assign popCC_readPort_cmd_payload = popCC_addressGen_payload; + assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; + assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; + assign popCC_readArbitation_translated_payload_addr = popCC_readPort_rsp_addr; + assign popCC_readArbitation_translated_payload_id = popCC_readPort_rsp_id; + assign popCC_readArbitation_translated_payload_len = popCC_readPort_rsp_len; + assign popCC_readArbitation_translated_payload_size = popCC_readPort_rsp_size; + assign popCC_readArbitation_translated_payload_burst = popCC_readPort_rsp_burst; + assign popCC_readArbitation_translated_payload_lock = popCC_readPort_rsp_lock; + assign popCC_readArbitation_translated_payload_cache = popCC_readPort_rsp_cache; + assign popCC_readArbitation_translated_payload_prot = popCC_readPort_rsp_prot; + assign io_pop_valid = popCC_readArbitation_translated_valid; + assign popCC_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_addr = popCC_readArbitation_translated_payload_addr; + assign io_pop_payload_id = popCC_readArbitation_translated_payload_id; + assign io_pop_payload_len = popCC_readArbitation_translated_payload_len; + assign io_pop_payload_size = popCC_readArbitation_translated_payload_size; + assign io_pop_payload_burst = popCC_readArbitation_translated_payload_burst; + assign io_pop_payload_lock = popCC_readArbitation_translated_payload_lock; + assign io_pop_payload_cache = popCC_readArbitation_translated_payload_cache; + assign io_pop_payload_prot = popCC_readArbitation_translated_payload_prot; + assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); + assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); + assign _zz_io_popOccupancy_1 = popCC_pushPtrGray[2]; + assign io_popOccupancy = ({_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}} - popCC_ptrToOccupancy); + assign pushToPopGray = pushCC_pushPtrGray; + assign popToPushGray = popCC_ptrToPush; + always @(posedge axiInClk or negedge axiInRstn) begin + if(!axiInRstn) begin + pushCC_pushPtr <= 3'b000; + pushCC_pushPtrGray <= 3'b000; + end else begin + if(io_push_fire) begin + pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); + end + if(io_push_fire) begin + pushCC_pushPtr <= pushCC_pushPtrPlus; + end + end + end + + always @(posedge axiOutClk or negedge awFifo_toplevel_axiInRstn_syncronized) begin + if(!awFifo_toplevel_axiInRstn_syncronized) begin + popCC_popPtr <= 3'b000; + popCC_addressGen_rValid <= 1'b0; + popCC_ptrToPush <= 3'b000; + popCC_ptrToOccupancy <= 3'b000; + end else begin + if(popCC_addressGen_fire) begin + popCC_popPtr <= popCC_popPtrPlus; + end + if(popCC_addressGen_ready) begin + popCC_addressGen_rValid <= popCC_addressGen_valid; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToPush <= popCC_popPtrGray; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToOccupancy <= popCC_popPtr; + end + end + end + + always @(posedge axiOutClk) begin + if(popCC_addressGen_ready) begin + popCC_addressGen_rData <= popCC_addressGen_payload; + end + end + + +endmodule + +module StreamFifoCC_2 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [4:0] io_push_payload_id, + input wire [1:0] io_push_payload_resp, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [4:0] io_pop_payload_id, + output wire [1:0] io_pop_payload_resp, + output wire [2:0] io_pushOccupancy, + output wire [2:0] io_popOccupancy, + input wire axiOutClk, + input wire axiOutRstn, + input wire axiInClk, + output wire bFifo_toplevel_axiOutRstn_syncronized_1 +); + + wire bufferCC_12_io_dataIn; + reg [6:0] _zz_ram_port1; + wire [2:0] popToPushGray_buffercc_io_dataOut; + wire bufferCC_12_io_dataOut; + wire [2:0] pushToPopGray_buffercc_io_dataOut; + wire [2:0] _zz_pushCC_pushPtrGray; + wire [1:0] _zz_ram_port; + wire [6:0] _zz_ram_port_1; + wire [2:0] _zz_popCC_popPtrGray; + reg _zz_1; + wire [2:0] popToPushGray; + wire [2:0] pushToPopGray; + reg [2:0] pushCC_pushPtr; + wire [2:0] pushCC_pushPtrPlus; + wire io_push_fire; + reg [2:0] pushCC_pushPtrGray; + wire [2:0] pushCC_popPtrGray; + wire pushCC_full; + wire _zz_io_pushOccupancy; + wire _zz_io_pushOccupancy_1; + wire bFifo_toplevel_axiOutRstn_syncronized; + reg [2:0] popCC_popPtr; + (* keep , syn_keep *) wire [2:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; + wire [2:0] popCC_popPtrGray; + wire [2:0] popCC_pushPtrGray; + wire popCC_addressGen_valid; + reg popCC_addressGen_ready; + wire [1:0] popCC_addressGen_payload; + wire popCC_empty; + wire popCC_addressGen_fire; + wire popCC_readArbitation_valid; + wire popCC_readArbitation_ready; + wire [1:0] popCC_readArbitation_payload; + reg popCC_addressGen_rValid; + reg [1:0] popCC_addressGen_rData; + wire when_Stream_l369; + wire popCC_readPort_cmd_valid; + wire [1:0] popCC_readPort_cmd_payload; + wire [4:0] popCC_readPort_rsp_id; + wire [1:0] popCC_readPort_rsp_resp; + wire [6:0] _zz_popCC_readPort_rsp_id; + wire popCC_readArbitation_translated_valid; + wire popCC_readArbitation_translated_ready; + wire [4:0] popCC_readArbitation_translated_payload_id; + wire [1:0] popCC_readArbitation_translated_payload_resp; + wire popCC_readArbitation_fire; + reg [2:0] popCC_ptrToPush; + reg [2:0] popCC_ptrToOccupancy; + wire _zz_io_popOccupancy; + wire _zz_io_popOccupancy_1; + reg [6:0] ram [0:3]; + + assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); + assign _zz_ram_port = pushCC_pushPtr[1:0]; + assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); + assign _zz_ram_port_1 = {io_push_payload_resp,io_push_payload_id}; + always @(posedge axiOutClk) begin + if(_zz_1) begin + ram[_zz_ram_port] <= _zz_ram_port_1; + end + end + + always @(posedge axiInClk) begin + if(popCC_readPort_cmd_valid) begin + _zz_ram_port1 <= ram[popCC_readPort_cmd_payload]; + end + end + + BufferCC_4 popToPushGray_buffercc ( + .io_dataIn (popToPushGray[2:0] ), //i + .io_dataOut (popToPushGray_buffercc_io_dataOut[2:0]), //o + .axiOutClk (axiOutClk ), //i + .axiOutRstn (axiOutRstn ) //i + ); + BufferCC_5 bufferCC_12 ( + .io_dataIn (bufferCC_12_io_dataIn ), //i + .io_dataOut (bufferCC_12_io_dataOut), //o + .axiInClk (axiInClk ), //i + .axiOutRstn (axiOutRstn ) //i + ); + BufferCC_6 pushToPopGray_buffercc ( + .io_dataIn (pushToPopGray[2:0] ), //i + .io_dataOut (pushToPopGray_buffercc_io_dataOut[2:0]), //o + .axiInClk (axiInClk ), //i + .bFifo_toplevel_axiOutRstn_syncronized (bFifo_toplevel_axiOutRstn_syncronized ) //i + ); + always @(*) begin + _zz_1 = 1'b0; + if(io_push_fire) begin + _zz_1 = 1'b1; + end + end + + assign pushCC_pushPtrPlus = (pushCC_pushPtr + 3'b001); + assign io_push_fire = (io_push_valid && io_push_ready); + assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; + assign pushCC_full = ((pushCC_pushPtrGray[2 : 1] == (~ pushCC_popPtrGray[2 : 1])) && (pushCC_pushPtrGray[0 : 0] == pushCC_popPtrGray[0 : 0])); + assign io_push_ready = (! pushCC_full); + assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); + assign _zz_io_pushOccupancy_1 = pushCC_popPtrGray[2]; + assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}); + assign bufferCC_12_io_dataIn = (1'b1 ^ 1'b0); + assign bFifo_toplevel_axiOutRstn_syncronized = bufferCC_12_io_dataOut; + assign popCC_popPtrPlus = (popCC_popPtr + 3'b001); + assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); + assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; + assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); + assign popCC_addressGen_valid = (! popCC_empty); + assign popCC_addressGen_payload = popCC_popPtr[1:0]; + assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); + always @(*) begin + popCC_addressGen_ready = popCC_readArbitation_ready; + if(when_Stream_l369) begin + popCC_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l369 = (! popCC_readArbitation_valid); + assign popCC_readArbitation_valid = popCC_addressGen_rValid; + assign popCC_readArbitation_payload = popCC_addressGen_rData; + assign _zz_popCC_readPort_rsp_id = _zz_ram_port1; + assign popCC_readPort_rsp_id = _zz_popCC_readPort_rsp_id[4 : 0]; + assign popCC_readPort_rsp_resp = _zz_popCC_readPort_rsp_id[6 : 5]; + assign popCC_readPort_cmd_valid = popCC_addressGen_fire; + assign popCC_readPort_cmd_payload = popCC_addressGen_payload; + assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; + assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; + assign popCC_readArbitation_translated_payload_id = popCC_readPort_rsp_id; + assign popCC_readArbitation_translated_payload_resp = popCC_readPort_rsp_resp; + assign io_pop_valid = popCC_readArbitation_translated_valid; + assign popCC_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_id = popCC_readArbitation_translated_payload_id; + assign io_pop_payload_resp = popCC_readArbitation_translated_payload_resp; + assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); + assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); + assign _zz_io_popOccupancy_1 = popCC_pushPtrGray[2]; + assign io_popOccupancy = ({_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}} - popCC_ptrToOccupancy); + assign pushToPopGray = pushCC_pushPtrGray; + assign popToPushGray = popCC_ptrToPush; + assign bFifo_toplevel_axiOutRstn_syncronized_1 = bFifo_toplevel_axiOutRstn_syncronized; + always @(posedge axiOutClk or negedge axiOutRstn) begin + if(!axiOutRstn) begin + pushCC_pushPtr <= 3'b000; + pushCC_pushPtrGray <= 3'b000; + end else begin + if(io_push_fire) begin + pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); + end + if(io_push_fire) begin + pushCC_pushPtr <= pushCC_pushPtrPlus; + end + end + end + + always @(posedge axiInClk or negedge bFifo_toplevel_axiOutRstn_syncronized) begin + if(!bFifo_toplevel_axiOutRstn_syncronized) begin + popCC_popPtr <= 3'b000; + popCC_addressGen_rValid <= 1'b0; + popCC_ptrToPush <= 3'b000; + popCC_ptrToOccupancy <= 3'b000; + end else begin + if(popCC_addressGen_fire) begin + popCC_popPtr <= popCC_popPtrPlus; + end + if(popCC_addressGen_ready) begin + popCC_addressGen_rValid <= popCC_addressGen_valid; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToPush <= popCC_popPtrGray; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToOccupancy <= popCC_popPtr; + end + end + end + + always @(posedge axiInClk) begin + if(popCC_addressGen_ready) begin + popCC_addressGen_rData <= popCC_addressGen_payload; + end + end + + +endmodule + +module StreamFifoCC_1 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [31:0] io_push_payload_data, + input wire [3:0] io_push_payload_strb, + input wire io_push_payload_last, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [31:0] io_pop_payload_data, + output wire [3:0] io_pop_payload_strb, + output wire io_pop_payload_last, + output wire [3:0] io_pushOccupancy, + output wire [3:0] io_popOccupancy, + input wire axiInClk, + input wire axiInRstn, + input wire axiOutClk, + input wire awFifo_toplevel_axiInRstn_syncronized +); + + reg [36:0] _zz_ram_port1; + wire [3:0] popToPushGray_buffercc_io_dataOut; + wire [3:0] pushToPopGray_buffercc_io_dataOut; + wire [3:0] _zz_pushCC_pushPtrGray; + wire [2:0] _zz_ram_port; + wire [36:0] _zz_ram_port_1; + wire [3:0] _zz_popCC_popPtrGray; + reg _zz_1; + wire [3:0] popToPushGray; + wire [3:0] pushToPopGray; + reg [3:0] pushCC_pushPtr; + wire [3:0] pushCC_pushPtrPlus; + wire io_push_fire; + reg [3:0] pushCC_pushPtrGray; + wire [3:0] pushCC_popPtrGray; + wire pushCC_full; + wire _zz_io_pushOccupancy; + wire _zz_io_pushOccupancy_1; + wire _zz_io_pushOccupancy_2; + reg [3:0] popCC_popPtr; + (* keep , syn_keep *) wire [3:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; + wire [3:0] popCC_popPtrGray; + wire [3:0] popCC_pushPtrGray; + wire popCC_addressGen_valid; + reg popCC_addressGen_ready; + wire [2:0] popCC_addressGen_payload; + wire popCC_empty; + wire popCC_addressGen_fire; + wire popCC_readArbitation_valid; + wire popCC_readArbitation_ready; + wire [2:0] popCC_readArbitation_payload; + reg popCC_addressGen_rValid; + reg [2:0] popCC_addressGen_rData; + wire when_Stream_l369; + wire popCC_readPort_cmd_valid; + wire [2:0] popCC_readPort_cmd_payload; + wire [31:0] popCC_readPort_rsp_data; + wire [3:0] popCC_readPort_rsp_strb; + wire popCC_readPort_rsp_last; + wire [36:0] _zz_popCC_readPort_rsp_data; + wire popCC_readArbitation_translated_valid; + wire popCC_readArbitation_translated_ready; + wire [31:0] popCC_readArbitation_translated_payload_data; + wire [3:0] popCC_readArbitation_translated_payload_strb; + wire popCC_readArbitation_translated_payload_last; + wire popCC_readArbitation_fire; + reg [3:0] popCC_ptrToPush; + reg [3:0] popCC_ptrToOccupancy; + wire _zz_io_popOccupancy; + wire _zz_io_popOccupancy_1; + wire _zz_io_popOccupancy_2; + reg [36:0] ram [0:7]; + + assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); + assign _zz_ram_port = pushCC_pushPtr[2:0]; + assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); + assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_strb,io_push_payload_data}}; + always @(posedge axiInClk) begin + if(_zz_1) begin + ram[_zz_ram_port] <= _zz_ram_port_1; + end + end + + always @(posedge axiOutClk) begin + if(popCC_readPort_cmd_valid) begin + _zz_ram_port1 <= ram[popCC_readPort_cmd_payload]; + end + end + + BufferCC_7 popToPushGray_buffercc ( + .io_dataIn (popToPushGray[3:0] ), //i + .io_dataOut (popToPushGray_buffercc_io_dataOut[3:0]), //o + .axiInClk (axiInClk ), //i + .axiInRstn (axiInRstn ) //i + ); + BufferCC_8 pushToPopGray_buffercc ( + .io_dataIn (pushToPopGray[3:0] ), //i + .io_dataOut (pushToPopGray_buffercc_io_dataOut[3:0]), //o + .axiOutClk (axiOutClk ), //i + .awFifo_toplevel_axiInRstn_syncronized (awFifo_toplevel_axiInRstn_syncronized ) //i + ); + always @(*) begin + _zz_1 = 1'b0; + if(io_push_fire) begin + _zz_1 = 1'b1; + end + end + + assign pushCC_pushPtrPlus = (pushCC_pushPtr + 4'b0001); + assign io_push_fire = (io_push_valid && io_push_ready); + assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; + assign pushCC_full = ((pushCC_pushPtrGray[3 : 2] == (~ pushCC_popPtrGray[3 : 2])) && (pushCC_pushPtrGray[1 : 0] == pushCC_popPtrGray[1 : 0])); + assign io_push_ready = (! pushCC_full); + assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); + assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); + assign _zz_io_pushOccupancy_2 = pushCC_popPtrGray[3]; + assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}); + assign popCC_popPtrPlus = (popCC_popPtr + 4'b0001); + assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); + assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; + assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); + assign popCC_addressGen_valid = (! popCC_empty); + assign popCC_addressGen_payload = popCC_popPtr[2:0]; + assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); + always @(*) begin + popCC_addressGen_ready = popCC_readArbitation_ready; + if(when_Stream_l369) begin + popCC_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l369 = (! popCC_readArbitation_valid); + assign popCC_readArbitation_valid = popCC_addressGen_rValid; + assign popCC_readArbitation_payload = popCC_addressGen_rData; + assign _zz_popCC_readPort_rsp_data = _zz_ram_port1; + assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[31 : 0]; + assign popCC_readPort_rsp_strb = _zz_popCC_readPort_rsp_data[35 : 32]; + assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[36]; + assign popCC_readPort_cmd_valid = popCC_addressGen_fire; + assign popCC_readPort_cmd_payload = popCC_addressGen_payload; + assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; + assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; + assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; + assign popCC_readArbitation_translated_payload_strb = popCC_readPort_rsp_strb; + assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; + assign io_pop_valid = popCC_readArbitation_translated_valid; + assign popCC_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; + assign io_pop_payload_strb = popCC_readArbitation_translated_payload_strb; + assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; + assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); + assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); + assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); + assign _zz_io_popOccupancy_2 = popCC_pushPtrGray[3]; + assign io_popOccupancy = ({_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}} - popCC_ptrToOccupancy); + assign pushToPopGray = pushCC_pushPtrGray; + assign popToPushGray = popCC_ptrToPush; + always @(posedge axiInClk or negedge axiInRstn) begin + if(!axiInRstn) begin + pushCC_pushPtr <= 4'b0000; + pushCC_pushPtrGray <= 4'b0000; + end else begin + if(io_push_fire) begin + pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); + end + if(io_push_fire) begin + pushCC_pushPtr <= pushCC_pushPtrPlus; + end + end + end + + always @(posedge axiOutClk or negedge awFifo_toplevel_axiInRstn_syncronized) begin + if(!awFifo_toplevel_axiInRstn_syncronized) begin + popCC_popPtr <= 4'b0000; + popCC_addressGen_rValid <= 1'b0; + popCC_ptrToPush <= 4'b0000; + popCC_ptrToOccupancy <= 4'b0000; + end else begin + if(popCC_addressGen_fire) begin + popCC_popPtr <= popCC_popPtrPlus; + end + if(popCC_addressGen_ready) begin + popCC_addressGen_rValid <= popCC_addressGen_valid; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToPush <= popCC_popPtrGray; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToOccupancy <= popCC_popPtr; + end + end + end + + always @(posedge axiOutClk) begin + if(popCC_addressGen_ready) begin + popCC_addressGen_rData <= popCC_addressGen_payload; + end + end + + +endmodule + +module StreamFifoCC ( + input wire io_push_valid, + output wire io_push_ready, + input wire [31:0] io_push_payload_addr, + input wire [4:0] io_push_payload_id, + input wire [7:0] io_push_payload_len, + input wire [2:0] io_push_payload_size, + input wire [1:0] io_push_payload_burst, + input wire [0:0] io_push_payload_lock, + input wire [3:0] io_push_payload_cache, + input wire [2:0] io_push_payload_prot, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [31:0] io_pop_payload_addr, + output wire [4:0] io_pop_payload_id, + output wire [7:0] io_pop_payload_len, + output wire [2:0] io_pop_payload_size, + output wire [1:0] io_pop_payload_burst, + output wire [0:0] io_pop_payload_lock, + output wire [3:0] io_pop_payload_cache, + output wire [2:0] io_pop_payload_prot, + output wire [2:0] io_pushOccupancy, + output wire [2:0] io_popOccupancy, + input wire axiInClk, + input wire axiInRstn, + input wire axiOutClk, + output wire awFifo_toplevel_axiInRstn_syncronized_1 +); + + wire bufferCC_12_io_dataIn; + reg [57:0] _zz_ram_port1; + wire [2:0] popToPushGray_buffercc_io_dataOut; + wire bufferCC_12_io_dataOut; + wire [2:0] pushToPopGray_buffercc_io_dataOut; + wire [2:0] _zz_pushCC_pushPtrGray; + wire [1:0] _zz_ram_port; + wire [57:0] _zz_ram_port_1; + wire [2:0] _zz_popCC_popPtrGray; + reg _zz_1; + wire [2:0] popToPushGray; + wire [2:0] pushToPopGray; + reg [2:0] pushCC_pushPtr; + wire [2:0] pushCC_pushPtrPlus; + wire io_push_fire; + reg [2:0] pushCC_pushPtrGray; + wire [2:0] pushCC_popPtrGray; + wire pushCC_full; + wire _zz_io_pushOccupancy; + wire _zz_io_pushOccupancy_1; + wire awFifo_toplevel_axiInRstn_syncronized; + reg [2:0] popCC_popPtr; + (* keep , syn_keep *) wire [2:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; + wire [2:0] popCC_popPtrGray; + wire [2:0] popCC_pushPtrGray; + wire popCC_addressGen_valid; + reg popCC_addressGen_ready; + wire [1:0] popCC_addressGen_payload; + wire popCC_empty; + wire popCC_addressGen_fire; + wire popCC_readArbitation_valid; + wire popCC_readArbitation_ready; + wire [1:0] popCC_readArbitation_payload; + reg popCC_addressGen_rValid; + reg [1:0] popCC_addressGen_rData; + wire when_Stream_l369; + wire popCC_readPort_cmd_valid; + wire [1:0] popCC_readPort_cmd_payload; + wire [31:0] popCC_readPort_rsp_addr; + wire [4:0] popCC_readPort_rsp_id; + wire [7:0] popCC_readPort_rsp_len; + wire [2:0] popCC_readPort_rsp_size; + wire [1:0] popCC_readPort_rsp_burst; + wire [0:0] popCC_readPort_rsp_lock; + wire [3:0] popCC_readPort_rsp_cache; + wire [2:0] popCC_readPort_rsp_prot; + wire [57:0] _zz_popCC_readPort_rsp_addr; + wire popCC_readArbitation_translated_valid; + wire popCC_readArbitation_translated_ready; + wire [31:0] popCC_readArbitation_translated_payload_addr; + wire [4:0] popCC_readArbitation_translated_payload_id; + wire [7:0] popCC_readArbitation_translated_payload_len; + wire [2:0] popCC_readArbitation_translated_payload_size; + wire [1:0] popCC_readArbitation_translated_payload_burst; + wire [0:0] popCC_readArbitation_translated_payload_lock; + wire [3:0] popCC_readArbitation_translated_payload_cache; + wire [2:0] popCC_readArbitation_translated_payload_prot; + wire popCC_readArbitation_fire; + reg [2:0] popCC_ptrToPush; + reg [2:0] popCC_ptrToOccupancy; + wire _zz_io_popOccupancy; + wire _zz_io_popOccupancy_1; + reg [57:0] ram [0:3]; + + assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); + assign _zz_ram_port = pushCC_pushPtr[1:0]; + assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); + assign _zz_ram_port_1 = {io_push_payload_prot,{io_push_payload_cache,{io_push_payload_lock,{io_push_payload_burst,{io_push_payload_size,{io_push_payload_len,{io_push_payload_id,io_push_payload_addr}}}}}}}; + always @(posedge axiInClk) begin + if(_zz_1) begin + ram[_zz_ram_port] <= _zz_ram_port_1; + end + end + + always @(posedge axiOutClk) begin + if(popCC_readPort_cmd_valid) begin + _zz_ram_port1 <= ram[popCC_readPort_cmd_payload]; + end + end + + BufferCC_9 popToPushGray_buffercc ( + .io_dataIn (popToPushGray[2:0] ), //i + .io_dataOut (popToPushGray_buffercc_io_dataOut[2:0]), //o + .axiInClk (axiInClk ), //i + .axiInRstn (axiInRstn ) //i + ); + BufferCC_10 bufferCC_12 ( + .io_dataIn (bufferCC_12_io_dataIn ), //i + .io_dataOut (bufferCC_12_io_dataOut), //o + .axiOutClk (axiOutClk ), //i + .axiInRstn (axiInRstn ) //i + ); + BufferCC_11 pushToPopGray_buffercc ( + .io_dataIn (pushToPopGray[2:0] ), //i + .io_dataOut (pushToPopGray_buffercc_io_dataOut[2:0]), //o + .axiOutClk (axiOutClk ), //i + .awFifo_toplevel_axiInRstn_syncronized (awFifo_toplevel_axiInRstn_syncronized ) //i + ); + always @(*) begin + _zz_1 = 1'b0; + if(io_push_fire) begin + _zz_1 = 1'b1; + end + end + + assign pushCC_pushPtrPlus = (pushCC_pushPtr + 3'b001); + assign io_push_fire = (io_push_valid && io_push_ready); + assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; + assign pushCC_full = ((pushCC_pushPtrGray[2 : 1] == (~ pushCC_popPtrGray[2 : 1])) && (pushCC_pushPtrGray[0 : 0] == pushCC_popPtrGray[0 : 0])); + assign io_push_ready = (! pushCC_full); + assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); + assign _zz_io_pushOccupancy_1 = pushCC_popPtrGray[2]; + assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}); + assign bufferCC_12_io_dataIn = (1'b1 ^ 1'b0); + assign awFifo_toplevel_axiInRstn_syncronized = bufferCC_12_io_dataOut; + assign popCC_popPtrPlus = (popCC_popPtr + 3'b001); + assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); + assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; + assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); + assign popCC_addressGen_valid = (! popCC_empty); + assign popCC_addressGen_payload = popCC_popPtr[1:0]; + assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); + always @(*) begin + popCC_addressGen_ready = popCC_readArbitation_ready; + if(when_Stream_l369) begin + popCC_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l369 = (! popCC_readArbitation_valid); + assign popCC_readArbitation_valid = popCC_addressGen_rValid; + assign popCC_readArbitation_payload = popCC_addressGen_rData; + assign _zz_popCC_readPort_rsp_addr = _zz_ram_port1; + assign popCC_readPort_rsp_addr = _zz_popCC_readPort_rsp_addr[31 : 0]; + assign popCC_readPort_rsp_id = _zz_popCC_readPort_rsp_addr[36 : 32]; + assign popCC_readPort_rsp_len = _zz_popCC_readPort_rsp_addr[44 : 37]; + assign popCC_readPort_rsp_size = _zz_popCC_readPort_rsp_addr[47 : 45]; + assign popCC_readPort_rsp_burst = _zz_popCC_readPort_rsp_addr[49 : 48]; + assign popCC_readPort_rsp_lock = _zz_popCC_readPort_rsp_addr[50 : 50]; + assign popCC_readPort_rsp_cache = _zz_popCC_readPort_rsp_addr[54 : 51]; + assign popCC_readPort_rsp_prot = _zz_popCC_readPort_rsp_addr[57 : 55]; + assign popCC_readPort_cmd_valid = popCC_addressGen_fire; + assign popCC_readPort_cmd_payload = popCC_addressGen_payload; + assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; + assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; + assign popCC_readArbitation_translated_payload_addr = popCC_readPort_rsp_addr; + assign popCC_readArbitation_translated_payload_id = popCC_readPort_rsp_id; + assign popCC_readArbitation_translated_payload_len = popCC_readPort_rsp_len; + assign popCC_readArbitation_translated_payload_size = popCC_readPort_rsp_size; + assign popCC_readArbitation_translated_payload_burst = popCC_readPort_rsp_burst; + assign popCC_readArbitation_translated_payload_lock = popCC_readPort_rsp_lock; + assign popCC_readArbitation_translated_payload_cache = popCC_readPort_rsp_cache; + assign popCC_readArbitation_translated_payload_prot = popCC_readPort_rsp_prot; + assign io_pop_valid = popCC_readArbitation_translated_valid; + assign popCC_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_addr = popCC_readArbitation_translated_payload_addr; + assign io_pop_payload_id = popCC_readArbitation_translated_payload_id; + assign io_pop_payload_len = popCC_readArbitation_translated_payload_len; + assign io_pop_payload_size = popCC_readArbitation_translated_payload_size; + assign io_pop_payload_burst = popCC_readArbitation_translated_payload_burst; + assign io_pop_payload_lock = popCC_readArbitation_translated_payload_lock; + assign io_pop_payload_cache = popCC_readArbitation_translated_payload_cache; + assign io_pop_payload_prot = popCC_readArbitation_translated_payload_prot; + assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); + assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); + assign _zz_io_popOccupancy_1 = popCC_pushPtrGray[2]; + assign io_popOccupancy = ({_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}} - popCC_ptrToOccupancy); + assign pushToPopGray = pushCC_pushPtrGray; + assign popToPushGray = popCC_ptrToPush; + assign awFifo_toplevel_axiInRstn_syncronized_1 = awFifo_toplevel_axiInRstn_syncronized; + always @(posedge axiInClk or negedge axiInRstn) begin + if(!axiInRstn) begin + pushCC_pushPtr <= 3'b000; + pushCC_pushPtrGray <= 3'b000; + end else begin + if(io_push_fire) begin + pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); + end + if(io_push_fire) begin + pushCC_pushPtr <= pushCC_pushPtrPlus; + end + end + end + + always @(posedge axiOutClk or negedge awFifo_toplevel_axiInRstn_syncronized) begin + if(!awFifo_toplevel_axiInRstn_syncronized) begin + popCC_popPtr <= 3'b000; + popCC_addressGen_rValid <= 1'b0; + popCC_ptrToPush <= 3'b000; + popCC_ptrToOccupancy <= 3'b000; + end else begin + if(popCC_addressGen_fire) begin + popCC_popPtr <= popCC_popPtrPlus; + end + if(popCC_addressGen_ready) begin + popCC_addressGen_rValid <= popCC_addressGen_valid; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToPush <= popCC_popPtrGray; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToOccupancy <= popCC_popPtr; + end + end + end + + always @(posedge axiOutClk) begin + if(popCC_addressGen_ready) begin + popCC_addressGen_rData <= popCC_addressGen_payload; + end + end + + +endmodule + +module BufferCC_1 ( + input wire [3:0] io_dataIn, + output wire [3:0] io_dataOut, + input wire axiInClk, + input wire bFifo_toplevel_axiOutRstn_syncronized +); + + (* async_reg = "true" *) reg [3:0] buffers_0; + (* async_reg = "true" *) reg [3:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge axiInClk or negedge bFifo_toplevel_axiOutRstn_syncronized) begin + if(!bFifo_toplevel_axiOutRstn_syncronized) begin + buffers_0 <= 4'b0000; + buffers_1 <= 4'b0000; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module BufferCC ( + input wire [3:0] io_dataIn, + output wire [3:0] io_dataOut, + input wire axiOutClk, + input wire axiOutRstn +); + + (* async_reg = "true" *) reg [3:0] buffers_0; + (* async_reg = "true" *) reg [3:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge axiOutClk or negedge axiOutRstn) begin + if(!axiOutRstn) begin + buffers_0 <= 4'b0000; + buffers_1 <= 4'b0000; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +//BufferCC_3 replaced by BufferCC_11 + +//BufferCC_2 replaced by BufferCC_9 + +module BufferCC_6 ( + input wire [2:0] io_dataIn, + output wire [2:0] io_dataOut, + input wire axiInClk, + input wire bFifo_toplevel_axiOutRstn_syncronized +); + + (* async_reg = "true" *) reg [2:0] buffers_0; + (* async_reg = "true" *) reg [2:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge axiInClk or negedge bFifo_toplevel_axiOutRstn_syncronized) begin + if(!bFifo_toplevel_axiOutRstn_syncronized) begin + buffers_0 <= 3'b000; + buffers_1 <= 3'b000; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module BufferCC_5 ( + input wire io_dataIn, + output wire io_dataOut, + input wire axiInClk, + input wire axiOutRstn +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge axiInClk or negedge axiOutRstn) begin + if(!axiOutRstn) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module BufferCC_4 ( + input wire [2:0] io_dataIn, + output wire [2:0] io_dataOut, + input wire axiOutClk, + input wire axiOutRstn +); + + (* async_reg = "true" *) reg [2:0] buffers_0; + (* async_reg = "true" *) reg [2:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge axiOutClk or negedge axiOutRstn) begin + if(!axiOutRstn) begin + buffers_0 <= 3'b000; + buffers_1 <= 3'b000; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module BufferCC_8 ( + input wire [3:0] io_dataIn, + output wire [3:0] io_dataOut, + input wire axiOutClk, + input wire awFifo_toplevel_axiInRstn_syncronized +); + + (* async_reg = "true" *) reg [3:0] buffers_0; + (* async_reg = "true" *) reg [3:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge axiOutClk or negedge awFifo_toplevel_axiInRstn_syncronized) begin + if(!awFifo_toplevel_axiInRstn_syncronized) begin + buffers_0 <= 4'b0000; + buffers_1 <= 4'b0000; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module BufferCC_7 ( + input wire [3:0] io_dataIn, + output wire [3:0] io_dataOut, + input wire axiInClk, + input wire axiInRstn +); + + (* async_reg = "true" *) reg [3:0] buffers_0; + (* async_reg = "true" *) reg [3:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge axiInClk or negedge axiInRstn) begin + if(!axiInRstn) begin + buffers_0 <= 4'b0000; + buffers_1 <= 4'b0000; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module BufferCC_11 ( + input wire [2:0] io_dataIn, + output wire [2:0] io_dataOut, + input wire axiOutClk, + input wire awFifo_toplevel_axiInRstn_syncronized +); + + (* async_reg = "true" *) reg [2:0] buffers_0; + (* async_reg = "true" *) reg [2:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge axiOutClk or negedge awFifo_toplevel_axiInRstn_syncronized) begin + if(!awFifo_toplevel_axiInRstn_syncronized) begin + buffers_0 <= 3'b000; + buffers_1 <= 3'b000; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module BufferCC_10 ( + input wire io_dataIn, + output wire io_dataOut, + input wire axiOutClk, + input wire axiInRstn +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge axiOutClk or negedge axiInRstn) begin + if(!axiInRstn) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module BufferCC_9 ( + input wire [2:0] io_dataIn, + output wire [2:0] io_dataOut, + input wire axiInClk, + input wire axiInRstn +); + + (* async_reg = "true" *) reg [2:0] buffers_0; + (* async_reg = "true" *) reg [2:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge axiInClk or negedge axiInRstn) begin + if(!axiInRstn) begin + buffers_0 <= 3'b000; + buffers_1 <= 3'b000; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule diff --git a/rtl/ip/Bus_interconnects/axi2sram_dp.v b/rtl/ip/Bus_interconnects/axi2sram_dp.v new file mode 100644 index 0000000..d4463bb --- /dev/null +++ b/rtl/ip/Bus_interconnects/axi2sram_dp.v @@ -0,0 +1,520 @@ +//+FHDR----------------------------------------------------------------- +// (C) Copyright Loongson Technology Corporation Limited. All rights reserved +// Loongson Confidential Proprietary +//-FHDR----------------------------------------------------------------- +module axi2sram_dp#( + parameter BUS_WIDTH = 32, + parameter DATA_WIDTH = 64, + parameter CPU_WIDTH = 32 +) +( + input wire aclk , + input wire aresetn , + output wire [BUS_WIDTH-1 :0] ram_raddr, + input wire [DATA_WIDTH-1 :0] ram_rdata, + output wire ram_ren , + output wire [BUS_WIDTH-1 :0] ram_waddr, + output wire [DATA_WIDTH-1 :0] ram_wdata, + output wire [DATA_WIDTH/8-1 :0] ram_wen , + input wire [BUS_WIDTH-1 :0] m_araddr , + input wire [1 :0] m_arburst, + input wire [3 :0] m_arcache, + input wire [4 :0] m_arid , + input wire [3 :0] m_arlen , + input wire [1 :0] m_arlock , + input wire [2 :0] m_arprot , + output wire m_arready, + input wire [2 :0] m_arsize , + input wire m_arvalid, + input wire [BUS_WIDTH-1 :0] m_awaddr , + input wire [1 :0] m_awburst, + input wire [3 :0] m_awcache, + input wire [4 :0] m_awid , + input wire [3 :0] m_awlen , + input wire [1 :0] m_awlock , + input wire [2 :0] m_awprot , + output wire m_awready, + input wire [2 :0] m_awsize , + input wire m_awvalid, + output wire [4 :0] m_bid , + input wire m_bready , + output wire [1 :0] m_bresp , + output wire m_bvalid , + output wire [DATA_WIDTH-1 :0] m_rdata , + output wire [4 :0] m_rid , + output wire m_rlast , + input wire m_rready , + output wire [1 :0] m_rresp , + output wire m_rvalid , + input wire [DATA_WIDTH-1 :0] m_wdata , + input wire m_wlast , + output wire m_wready , + input wire [DATA_WIDTH/8-1 :0] m_wstrb , + input wire m_wvalid +); +localparam ADDR_INCR_BASE=($clog2(DATA_WIDTH) - 3); + +wire [BUS_WIDTH+13-1 :0] ram_r_a_data ; +reg [BUS_WIDTH-1 :0] ram_r_a_data_araddr ; +wire [BUS_WIDTH-1 :0] ram_r_a_data_araddr_fixed ; +wire [BUS_WIDTH-1 :0] ram_r_a_data_araddr_incr ; +wire [BUS_WIDTH-1 :0] ram_r_a_data_araddr_next ; +wire ram_r_a_data_araddr_update ; +wire [BUS_WIDTH-1 :0] ram_r_a_data_araddr_wrap ; +reg [1 :0] ram_r_a_data_arburst ; +wire ram_r_a_data_arburst_fixed ; +wire ram_r_a_data_arburst_incr ; +wire ram_r_a_data_arburst_wrap ; +reg [4 :0] ram_r_a_data_arid ; +reg [3 :0] ram_r_a_data_arlen ; +wire ram_r_a_data_arlen_last ; +reg [2 :0] ram_r_a_data_arsize ; +wire ram_r_a_data_push ; +wire ram_r_a_full ; +wire ram_r_a_pop ; +wire ram_r_a_push ; +wire [BUS_WIDTH+14-1 :0] ram_r_a_push_data ; +reg [BUS_WIDTH+14-1 :0] ram_r_a_queue_datas ; +wire [BUS_WIDTH-1 :0] ram_r_a_queue_datas_araddr ; +wire [1 :0] ram_r_a_queue_datas_arburst; +wire [4 :0] ram_r_a_queue_datas_arid ; +wire [3 :0] ram_r_a_queue_datas_arlen ; +wire [2 :0] ram_r_a_queue_datas_arsize ; +wire ram_r_a_queue_empty ; +wire ram_r_a_queue_full ; +wire ram_r_a_queue_pop ; +wire ram_r_a_queue_push ; +reg ram_r_a_queue_valid ; +reg ram_r_a_valid ; +wire [BUS_WIDTH-1 :0] ram_r_addr ; +wire ram_r_allow_out ; +wire [DATA_WIDTH-1 :0] ram_r_data ; +wire ram_r_en ; +reg [3 :0] ram_r_rcur ; +wire ram_r_rcur_reset ; +reg [4 :0] ram_r_rid ; +reg ram_r_rlast ; +reg ram_r_rvalid ; +wire [BUS_WIDTH+13-1 :0] ram_w_a_data ; +reg [BUS_WIDTH-1 :0] ram_w_a_data_awaddr ; +wire [BUS_WIDTH-1 :0] ram_w_a_data_awaddr_fixed ; +wire [BUS_WIDTH-1 :0] ram_w_a_data_awaddr_incr ; +wire [BUS_WIDTH-1 :0] ram_w_a_data_awaddr_next ; +wire ram_w_a_data_awaddr_update ; +wire [BUS_WIDTH-1 :0] ram_w_a_data_awaddr_wrap ; +reg [1 :0] ram_w_a_data_awburst ; +wire ram_w_a_data_awburst_fixed ; +wire ram_w_a_data_awburst_incr ; +wire ram_w_a_data_awburst_wrap ; +reg [4 :0] ram_w_a_data_awid ; +reg [3 :0] ram_w_a_data_awlen ; +reg [2 :0] ram_w_a_data_awsize ; +wire ram_w_a_data_push ; +wire ram_w_a_full ; +wire ram_w_a_pop ; +wire ram_w_a_push ; +wire [BUS_WIDTH+14-1 :0] ram_w_a_push_data ; +reg [BUS_WIDTH+14-1 :0] ram_w_a_queue_datas ; +wire [BUS_WIDTH-1 :0] ram_w_a_queue_datas_awaddr ; +wire [1 :0] ram_w_a_queue_datas_awburst; +wire [4 :0] ram_w_a_queue_datas_awid ; +wire [3 :0] ram_w_a_queue_datas_awlen ; +wire [2 :0] ram_w_a_queue_datas_awsize ; +wire ram_w_a_queue_empty ; +wire ram_w_a_queue_full ; +wire ram_w_a_queue_pop ; +wire ram_w_a_queue_push ; +reg ram_w_a_queue_valid ; +reg ram_w_a_valid ; +wire [BUS_WIDTH-1 :0] ram_w_addr ; +wire ram_w_allow_out ; +reg [4 :0] ram_w_b_data ; +wire ram_w_b_data_push ; +wire ram_w_b_full ; +wire ram_w_b_pop ; +wire ram_w_b_push ; +reg [4 :0] ram_w_b_queue_datas ; +wire ram_w_b_queue_empty ; +wire ram_w_b_queue_full ; +wire ram_w_b_queue_pop ; +wire ram_w_b_queue_push ; +reg ram_w_b_queue_valid ; +reg ram_w_b_valid ; +wire ram_w_en ; +wire ram_w_go ; +wire [DATA_WIDTH/8-1 :0] ram_w_strb ; +reg [DATA_WIDTH-1 :0] ram_w_wdata ; +reg ram_w_wlast ; +reg [DATA_WIDTH/8-1 :0] ram_w_wstrb ; +reg ram_w_wvalid ; +assign m_arready = !ram_r_a_full; +assign m_awready = !ram_w_a_full; +assign m_bid = ram_w_b_data; +assign m_bresp = 2'h0; +assign m_bvalid = ram_w_b_valid; +assign m_rdata = ram_rdata ; +assign m_rid = ram_r_rid ; +assign m_rlast = ram_r_rlast ; +assign m_rresp = 2'h0; +assign m_rvalid = ram_r_rvalid; +assign m_wready = ram_w_allow_out || !ram_w_wvalid; +assign ram_r_a_data = {ram_r_a_data_arburst,ram_r_a_data_arsize,ram_r_a_data_arlen,ram_r_a_data_araddr,ram_r_a_data_arid}; +assign ram_r_a_data_araddr_fixed = ram_r_a_data_araddr; +assign ram_r_a_data_araddr_incr [ADDR_INCR_BASE-1:0] = ram_r_a_data_araddr[ADDR_INCR_BASE-1:0]; +assign ram_r_a_data_araddr_incr [BUS_WIDTH-1 :ADDR_INCR_BASE ] = ram_r_a_data_araddr[BUS_WIDTH-1:ADDR_INCR_BASE] + {{BUS_WIDTH-ADDR_INCR_BASE-1{1'b0}},1'b1}; +assign ram_r_a_data_araddr_next = {BUS_WIDTH{ram_r_a_data_arburst_fixed}} & ram_r_a_data_araddr_fixed + | {BUS_WIDTH{ram_r_a_data_arburst_incr }} & ram_r_a_data_araddr_incr + | {BUS_WIDTH{ram_r_a_data_arburst_wrap }} & ram_r_a_data_araddr_wrap ; +assign ram_r_a_data_araddr_update = ram_r_en && !ram_r_a_data_arlen_last; +assign ram_r_a_data_araddr_wrap [ADDR_INCR_BASE-1 :0] = ram_r_a_data_araddr[ADDR_INCR_BASE-1 :0]; +assign ram_r_a_data_araddr_wrap [BUS_WIDTH-1:ADDR_INCR_BASE+4] = ram_r_a_data_araddr[BUS_WIDTH-1:ADDR_INCR_BASE+4]; +assign ram_r_a_data_araddr_wrap [ADDR_INCR_BASE+3 :ADDR_INCR_BASE] = ram_r_a_data_araddr[ADDR_INCR_BASE+3:ADDR_INCR_BASE] & ~ram_r_a_data_arlen | ram_r_a_data_arlen & ram_r_a_data_araddr[ADDR_INCR_BASE+3:ADDR_INCR_BASE] + 4'h1; +assign ram_r_a_data_arburst_fixed = ram_r_a_data_arburst == 2'h0; +assign ram_r_a_data_arburst_incr = ram_r_a_data_arburst == 2'h1; +assign ram_r_a_data_arburst_wrap = ram_r_a_data_arburst == 2'h2; +assign ram_r_a_data_arlen_last = ram_r_a_data_arlen == ram_r_rcur; +assign ram_r_a_data_push = ram_r_a_push && (ram_r_a_pop || !ram_r_a_valid); +assign ram_r_a_full = ram_r_a_queue_full; +assign ram_r_a_pop = ram_r_en && ram_r_a_data_arlen_last; +assign ram_r_a_push = m_arvalid && !ram_r_a_full ; +//assign ram_r_a_push_data = {m_arburst,m_arsize ,m_arlen,m_araddr,m_arid}; +assign ram_r_a_push_data = {m_araddr,m_arburst,m_arsize,m_arlen,m_arid}; +assign ram_r_a_queue_datas_araddr = ram_r_a_queue_datas[BUS_WIDTH-1+14:14]; +assign ram_r_a_queue_datas_arburst = ram_r_a_queue_datas[13 :12]; +assign ram_r_a_queue_datas_arid = ram_r_a_queue_datas[4 : 0]; +assign ram_r_a_queue_datas_arlen = ram_r_a_queue_datas[8 : 5]; +assign ram_r_a_queue_datas_arsize = ram_r_a_queue_datas[11 : 9]; +assign ram_r_a_queue_empty = !ram_r_a_queue_valid; +assign ram_r_a_queue_full = ram_r_a_queue_valid; +assign ram_r_a_queue_pop = ram_r_a_pop && !ram_r_a_queue_empty; +assign ram_r_a_queue_push = ram_r_a_push && ram_r_a_valid && !ram_r_a_pop && !ram_r_a_queue_full; +assign ram_r_addr = ram_r_a_data_araddr; +assign ram_r_allow_out = m_rready || !m_rvalid; +assign ram_r_data = ram_rdata; +assign ram_r_en = ram_r_a_valid && ram_r_allow_out; +assign ram_r_rcur_reset = !aresetn || ram_r_a_pop; +assign ram_w_a_data = {ram_w_a_data_awaddr,ram_w_a_data_awburst,ram_w_a_data_awsize ,ram_w_a_data_awlen,ram_w_a_data_awid}; +assign ram_w_a_data_awaddr_fixed = ram_w_a_data_awaddr; +assign ram_w_a_data_awaddr_incr [ADDR_INCR_BASE-1 :0] = ram_w_a_data_awaddr[ADDR_INCR_BASE-1:0]; +assign ram_w_a_data_awaddr_incr [BUS_WIDTH-1:ADDR_INCR_BASE] = ram_w_a_data_awaddr[BUS_WIDTH-1:ADDR_INCR_BASE] + {{BUS_WIDTH-ADDR_INCR_BASE-1{1'b0}},1'b1}; +assign ram_w_a_data_awaddr_next = {BUS_WIDTH{ram_w_a_data_awburst_fixed}} & ram_w_a_data_awaddr_fixed + | {BUS_WIDTH{ram_w_a_data_awburst_incr }} & ram_w_a_data_awaddr_incr + | {BUS_WIDTH{ram_w_a_data_awburst_wrap }} & ram_w_a_data_awaddr_wrap ; +assign ram_w_a_data_awaddr_update = ram_w_en && !ram_w_wlast; +assign ram_w_a_data_awaddr_wrap [ADDR_INCR_BASE-1 :0] = ram_w_a_data_awaddr[ADDR_INCR_BASE-1 :0]; +assign ram_w_a_data_awaddr_wrap [BUS_WIDTH-1:ADDR_INCR_BASE+4] = ram_w_a_data_awaddr[BUS_WIDTH-1:ADDR_INCR_BASE+4]; +assign ram_w_a_data_awaddr_wrap [ADDR_INCR_BASE+3:ADDR_INCR_BASE] = ram_w_a_data_awaddr[ADDR_INCR_BASE+3:ADDR_INCR_BASE] & ~ram_w_a_data_awlen | ram_w_a_data_awlen & ram_w_a_data_awaddr[ADDR_INCR_BASE+3:ADDR_INCR_BASE] + 4'h1; +assign ram_w_a_data_awburst_fixed = ram_w_a_data_awburst == 2'h0; +assign ram_w_a_data_awburst_incr = ram_w_a_data_awburst == 2'h1; +assign ram_w_a_data_awburst_wrap = ram_w_a_data_awburst == 2'h2; +assign ram_w_a_data_push = ram_w_a_push && (ram_w_a_pop || !ram_w_a_valid); +assign ram_w_a_full = ram_w_a_queue_full; +assign ram_w_a_pop = ram_w_en && ram_w_wlast ; +assign ram_w_a_push = m_awvalid && !ram_w_a_full; +assign ram_w_a_push_data = {m_awaddr,m_awburst,m_awsize ,m_awlen,m_awid}; +assign ram_w_a_queue_datas_awaddr = ram_w_a_queue_datas[BUS_WIDTH-1+14:14]; +assign ram_w_a_queue_datas_awburst = ram_w_a_queue_datas[13 :12]; +assign ram_w_a_queue_datas_awid = ram_w_a_queue_datas[4 : 0]; +assign ram_w_a_queue_datas_awlen = ram_w_a_queue_datas[8 : 5]; +assign ram_w_a_queue_datas_awsize = ram_w_a_queue_datas[11 : 9]; +assign ram_w_a_queue_empty = !ram_w_a_queue_valid; +assign ram_w_a_queue_full = ram_w_a_queue_valid; +assign ram_w_a_queue_pop = ram_w_a_pop && !ram_w_a_queue_empty; +assign ram_w_a_queue_push = ram_w_a_push && ram_w_a_valid && !ram_w_a_pop && !ram_w_a_queue_full; +assign ram_w_addr = ram_w_a_data_awaddr; +assign ram_w_allow_out = ram_w_a_valid && !ram_w_b_full; +assign ram_w_b_data_push = ram_w_b_push && (ram_w_b_pop || !ram_w_b_valid); +assign ram_w_b_full = ram_w_b_queue_full; +assign ram_w_b_pop = m_bready && ram_w_b_valid; +assign ram_w_b_push = ram_w_a_pop ; +assign ram_w_b_queue_empty = !ram_w_b_queue_valid; +assign ram_w_b_queue_full = ram_w_b_queue_valid; +assign ram_w_b_queue_pop = ram_w_b_pop && !ram_w_b_queue_empty; +assign ram_w_b_queue_push = ram_w_b_push && ram_w_b_valid && !ram_w_b_pop && !ram_w_b_queue_full; +assign ram_w_en = ram_w_wvalid && ram_w_allow_out && aresetn; +assign ram_w_go = m_wvalid && m_wready; +assign ram_w_strb = ram_w_wstrb; +assign ram_raddr = ram_r_addr ; +assign ram_ren = ram_r_en ; +assign ram_waddr = ram_w_addr ; +assign ram_wdata = ram_w_wdata; +assign ram_wen = ram_w_strb & {DATA_WIDTH/8{ram_w_en}}; +always@(posedge aclk) +begin + if(ram_r_rcur_reset) + begin + ram_r_rcur<=4'h0; + end + else + if(ram_r_en) + begin + ram_r_rcur<=ram_r_rcur + 4'h1; + end +end +always@(posedge aclk) +begin + if(ram_r_en) + begin + ram_r_rid<=ram_r_a_data_arid; + end +end +always@(posedge aclk) +begin + if(ram_r_en) + begin + ram_r_rlast<=ram_r_a_data_arlen_last; + end +end +always@(posedge aclk) +begin + if(!aresetn) + begin + ram_r_rvalid<=1'h0; + end + else + if(ram_r_en) + begin + ram_r_rvalid<=1'h1; + end + else + if(m_rready) + begin + ram_r_rvalid<=1'h0; + end +end +always@(posedge aclk) +begin + if(!aresetn) + begin + ram_r_a_valid<=1'h0; + end + else + if(ram_r_a_push) + begin + ram_r_a_valid<=1'h1; + end + else + if(ram_r_a_pop) + begin + ram_r_a_valid<=ram_r_a_queue_valid; + end +end +always@(posedge aclk) +begin + if(!aresetn) + begin + ram_r_a_queue_valid<=1'h0; + end + else + if(ram_r_a_queue_push) + begin + ram_r_a_queue_valid<=1'h1; + end + else + if(ram_r_a_queue_pop) + begin + ram_r_a_queue_valid<=1'h0; + end +end +always@(posedge aclk) +begin + if(ram_r_a_queue_push) + begin + ram_r_a_queue_datas<=ram_r_a_push_data; + end +end +always@(posedge aclk) +begin + if(ram_r_a_data_push) + begin + ram_r_a_data_arburst<=m_arburst; + ram_r_a_data_arid <=m_arid ; + ram_r_a_data_arlen <=m_arlen ; + ram_r_a_data_arsize <=m_arsize ; + end + else + if(ram_r_a_pop) + begin + ram_r_a_data_arburst<=ram_r_a_queue_datas_arburst; + ram_r_a_data_arid <=ram_r_a_queue_datas_arid ; + ram_r_a_data_arlen <=ram_r_a_queue_datas_arlen ; + ram_r_a_data_arsize <=ram_r_a_queue_datas_arsize ; + end +end +always@(posedge aclk) +begin + if(ram_r_a_data_push) + begin + ram_r_a_data_araddr<=m_araddr; + end + else + if(ram_r_a_pop) + begin + ram_r_a_data_araddr<=ram_r_a_queue_datas_araddr; + end + else + begin + if(ram_r_a_data_araddr_update) + begin + ram_r_a_data_araddr<=ram_r_a_data_araddr_next; + end + end +end +always@(posedge aclk) +begin + if(ram_w_go) + begin + ram_w_wdata<=m_wdata; + ram_w_wlast<=m_wlast; + ram_w_wstrb<=m_wstrb; + end +end +always@(posedge aclk) +begin + if(!aresetn) + begin + ram_w_wvalid<=1'h0; + end + else + if(ram_w_go) + begin + ram_w_wvalid<=1'h1; + end + else + if(ram_w_en) + begin + ram_w_wvalid<=1'h0; + end +end +always@(posedge aclk) +begin + if(!aresetn) + begin + ram_w_a_valid<=1'h0; + end + else + if(ram_w_a_push) + begin + ram_w_a_valid<=1'h1; + end + else + if(ram_w_a_pop) + begin + ram_w_a_valid<=ram_w_a_queue_valid; + end +end +always@(posedge aclk) +begin + if(!aresetn) + begin + ram_w_a_queue_valid<=1'h0; + end + else + if(ram_w_a_queue_push) + begin + ram_w_a_queue_valid<=1'h1; + end + else + if(ram_w_a_queue_pop) + begin + ram_w_a_queue_valid<=1'h0; + end +end +always@(posedge aclk) +begin + if(ram_w_a_queue_push) + begin + ram_w_a_queue_datas<=ram_w_a_push_data; + end +end +always@(posedge aclk) +begin + if(ram_w_a_data_push) + begin + ram_w_a_data_awburst<=m_awburst; + ram_w_a_data_awid <=m_awid ; + ram_w_a_data_awlen <=m_awlen ; + ram_w_a_data_awsize <=m_awsize ; + end + else + if(ram_w_a_pop) + begin + ram_w_a_data_awburst<=ram_w_a_queue_datas_awburst; + ram_w_a_data_awid <=ram_w_a_queue_datas_awid ; + ram_w_a_data_awlen <=ram_w_a_queue_datas_awlen ; + ram_w_a_data_awsize <=ram_w_a_queue_datas_awsize ; + end +end +always@(posedge aclk) +begin + if(ram_w_a_data_push) + begin + ram_w_a_data_awaddr<=m_awaddr; + end + else + if(ram_w_a_pop) + begin + ram_w_a_data_awaddr<=ram_w_a_queue_datas_awaddr; + end + else + begin + if(ram_w_a_data_awaddr_update) + begin + ram_w_a_data_awaddr<=ram_w_a_data_awaddr_next; + end + end +end +always@(posedge aclk) +begin + if(!aresetn) + begin + ram_w_b_valid<=1'h0; + end + else + if(ram_w_b_push) + begin + ram_w_b_valid<=1'h1; + end + else + if(ram_w_b_pop) + begin + ram_w_b_valid<=ram_w_b_queue_valid; + end +end +always@(posedge aclk) +begin + if(!aresetn) + begin + ram_w_b_queue_valid<=1'h0; + end + else + if(ram_w_b_queue_push) + begin + ram_w_b_queue_valid<=1'h1; + end + else + if(ram_w_b_queue_pop) + begin + ram_w_b_queue_valid<=1'h0; + end +end +always@(posedge aclk) +begin + if(ram_w_b_queue_push) + begin + ram_w_b_queue_datas<=ram_w_a_data_awid; + end +end +always@(posedge aclk) +begin + if(ram_w_b_data_push) + begin + ram_w_b_data<=ram_w_a_data_awid; + end + else + if(ram_w_b_pop) + begin + ram_w_b_data<=ram_w_b_queue_datas; + end +end +endmodule // soc_axi_sram_bridge diff --git a/rtl/ip/Bus_interconnects/axi2sram_sp.v b/rtl/ip/Bus_interconnects/axi2sram_sp.v new file mode 100644 index 0000000..78ed1d2 --- /dev/null +++ b/rtl/ip/Bus_interconnects/axi2sram_sp.v @@ -0,0 +1,350 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// ---------------------------- +// AXI to SRAM Adapter +// ---------------------------- +// Author: Florian Zaruba (zarubaf@iis.ee.ethz.ch) +// +// Description: Manages AXI transactions +// Supports all burst accesses but only on aligned addresses and with full data width. +// Assertions should guide you if there is something unsupported happening. +// +module axi2sram_sp #( + parameter AXI_ID_WIDTH = 5, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 32 +)( + input clk, + input resetn, + + input [AXI_ADDR_WIDTH-1:0] s_araddr , + input [1 :0] s_arburst, + input [3 :0] s_arcache, + input [AXI_ID_WIDTH-1 :0] s_arid , + input [3 :0] s_arlen , + input [1 :0] s_arlock , + input [2 :0] s_arprot , + output reg s_arready, + input [2 :0] s_arsize , + input s_arvalid, + input [AXI_ADDR_WIDTH-1:0] s_awaddr , + input [1 :0] s_awburst, + input [3 :0] s_awcache, + input [AXI_ID_WIDTH :0] s_awid , + input [3 :0] s_awlen , + input [1 :0] s_awlock , + input [2 :0] s_awprot , + output reg s_awready, + input [2 :0] s_awsize , + input s_awvalid, + output reg [AXI_ID_WIDTH-1 :0] s_bid , + input s_bready , + output reg [1 :0] s_bresp , + output reg s_bvalid , + output reg [AXI_DATA_WIDTH-1:0] s_rdata , + output reg [AXI_ID_WIDTH :0] s_rid , + output reg s_rlast , + input s_rready , + output reg [1 :0] s_rresp , + output reg s_rvalid , + input [AXI_DATA_WIDTH-1:0] s_wdata , + input s_wlast , + output reg s_wready , + input [AXI_DATA_WIDTH/8-1:0] s_wstrb , + input s_wvalid , + + output reg req_o, + output reg we_o, + output reg [AXI_ADDR_WIDTH-1:0] addr_o, + output reg [AXI_DATA_WIDTH/8-1:0] be_o, + output reg [AXI_DATA_WIDTH-1:0] data_o, + input [AXI_DATA_WIDTH-1:0] data_i +); + // AXI has the following rules governing the use of bursts: + // - for wrapping bursts, the burst length must be 2, 4, 8, or 16 + // - a burst must not cross a 4KB address boundary + // - early termination of bursts is not supported. + + localparam LOG_NR_BYTES = $clog2(AXI_DATA_WIDTH/8); + + reg [AXI_ID_WIDTH-1:0] ax_req_d_id; + reg [AXI_ADDR_WIDTH-1:0] ax_req_d_addr; + reg [7:0] ax_req_d_len; + reg [2:0] ax_req_d_size; + reg [1:0] ax_req_d_burst; + + reg [AXI_ID_WIDTH-1:0] ax_req_q_id; + reg [AXI_ADDR_WIDTH-1:0] ax_req_q_addr; + reg [7:0] ax_req_q_len; + reg [2:0] ax_req_q_size; + reg [1:0] ax_req_q_burst; + + reg [2:0] state_d; + reg [2:0] state_q; + + localparam IDLE = 3'h0; + localparam READ = 3'h1; + localparam WRITE = 3'h2; + localparam SEND_B = 3'h3; + localparam WAIT_WVALID = 3'h4; + + localparam FIXED = 2'b00; + localparam INCR = 2'b01; + localparam WRAP = 2'b10; + + reg [AXI_ADDR_WIDTH-1:0] req_addr_d, req_addr_q; + reg [7:0] cnt_d, cnt_q; + + function automatic [AXI_ADDR_WIDTH-1:0] get_wrap_boundary; + input [AXI_ADDR_WIDTH-1:0] unaligned_address; + input [7:0] len; + begin + get_wrap_boundary = 'h0; + // for wrapping transfers ax_len can only be of size 1, 3, 7 or 15 + if (len == 4'b1) + get_wrap_boundary[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES]; + else if (len == 4'b11) + get_wrap_boundary[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES]; + else if (len == 4'b111) + get_wrap_boundary[AXI_ADDR_WIDTH-1:3+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:2+LOG_NR_BYTES]; + else if (len == 4'b1111) + get_wrap_boundary[AXI_ADDR_WIDTH-1:4+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:4+LOG_NR_BYTES]; + end + endfunction + + reg [AXI_ADDR_WIDTH-1:0] aligned_address; + reg [AXI_ADDR_WIDTH-1:0] wrap_boundary; + reg [AXI_ADDR_WIDTH-1:0] upper_wrap_boundary; + reg [AXI_ADDR_WIDTH-1:0] cons_addr; + + always @ (*) begin + // address generation + aligned_address = {ax_req_q_addr[AXI_ADDR_WIDTH-1:LOG_NR_BYTES], {{LOG_NR_BYTES}{1'b0}}}; + wrap_boundary = get_wrap_boundary(ax_req_q_addr, ax_req_q_len); + // this will overflow + upper_wrap_boundary = wrap_boundary + ((ax_req_q_len + 1) << LOG_NR_BYTES); + // calculate consecutive address + cons_addr = aligned_address + (cnt_q << LOG_NR_BYTES); + + // Transaction attributes + // default assignments + state_d = state_q; + ax_req_d_id = ax_req_q_id; + ax_req_d_addr = ax_req_q_addr; + ax_req_d_len = ax_req_q_len; + ax_req_d_size = ax_req_q_size; + ax_req_d_burst = ax_req_q_burst; + req_addr_d = req_addr_q; + cnt_d = cnt_q; + // Memory default assignments + data_o = s_wdata; + be_o = s_wstrb; + we_o = 1'b0; + req_o = 1'b0; + addr_o = 'h0; + // AXI assignments + // request + s_awready = 1'b0; + s_arready = 1'b0; + // read response channel + s_rvalid = 1'b0; + s_rdata = data_i; + s_rresp = 'h0; + s_rlast = 'h0; + s_rid = ax_req_q_id; + // slave write data channel + s_wready = 1'b0; + // write response channel + s_bvalid = 1'b0; + s_bresp = 1'b0; + s_bid = 1'b0; + + case (state_q) + + IDLE: begin + // Wait for a read or write + // ------------ + // Read + // ------------ + if (s_arvalid) begin + s_arready = 1'b1; + // sample ax + ax_req_d_id = s_arid; + ax_req_d_addr = s_araddr; + ax_req_d_len = s_arlen; + ax_req_d_size = s_arsize; + ax_req_d_burst = s_arburst; + state_d = READ; + // we can request the first address, this saves us time + req_o = 1'b1; + addr_o = s_araddr; + // save the address + req_addr_d = s_araddr; + // save the ar_len + cnt_d = 1; + // ------------ + // Write + // ------------ + end else if (s_awvalid) begin + s_awready = 1'b1; + s_wready = 1'b1; + addr_o = s_awaddr; + // sample ax + ax_req_d_id = s_awid; + ax_req_d_addr = s_awaddr; + ax_req_d_len = s_awlen; + ax_req_d_size = s_awsize; + ax_req_d_burst = s_awburst; + // we've got our first w_valid so start the write process + if (s_wvalid) begin + req_o = 1'b1; + we_o = 1'b1; + state_d = (s_wlast) ? SEND_B : WRITE; + cnt_d = 1; + // we still have to wait for the first w_valid to arrive + end else + state_d = WAIT_WVALID; + end + end + + // ~> we are still missing a w_valid + WAIT_WVALID: begin + s_wready = 1'b1; + addr_o = ax_req_q_addr; + // we can now make our first request + if (s_wvalid) begin + req_o = 1'b1; + we_o = 1'b1; + state_d = (s_wlast) ? SEND_B : WRITE; + cnt_d = 1; + end + end + + READ: begin + // keep request to memory high + req_o = 1'b1; + addr_o = req_addr_q; + // send the response + s_rvalid = 1'b1; + s_rdata = data_i; + s_rid = ax_req_q_id; + s_rlast = (cnt_q == ax_req_q_len + 1); + + // check that the master is ready, the slave must not wait on this + if (s_rready) begin + // ---------------------------- + // Next address generation + // ---------------------------- + // handle the correct burst type + case (ax_req_q_burst) + FIXED, INCR: addr_o = cons_addr; + WRAP: begin + // check if the address reached warp boundary + if (cons_addr == upper_wrap_boundary) begin + addr_o = wrap_boundary; + // address warped beyond boundary + end else if (cons_addr > upper_wrap_boundary) begin + addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES); + // we are still in the incremental regime + end else begin + addr_o = cons_addr; + end + end + endcase + // we need to change the address here for the upcoming request + // we sent the last byte -> go back to idle + if (s_rlast) begin + state_d = IDLE; + // we already got everything + req_o = 1'b0; + end + // save the request address for the next cycle + req_addr_d = addr_o; + // we can decrease the counter as the master has consumed the read data + cnt_d = cnt_q + 1; + // TODO: configure correct byte-lane + end + end + // ~> we already wrote the first word here + WRITE: begin + + s_wready = 1'b1; + + // consume a word here + if (s_wvalid) begin + req_o = 1'b1; + we_o = 1'b1; + // ---------------------------- + // Next address generation + // ---------------------------- + // handle the correct burst type + case (ax_req_q_burst) + + FIXED, INCR: addr_o = cons_addr; + WRAP: begin + // check if the address reached warp boundary + if (cons_addr == upper_wrap_boundary) begin + addr_o = wrap_boundary; + // address warped beyond boundary + end else if (cons_addr > upper_wrap_boundary) begin + addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES); + // we are still in the incremental regime + end else begin + addr_o = cons_addr; + end + end + endcase + // save the request address for the next cycle + req_addr_d = addr_o; + // we can decrease the counter as the master has consumed the read data + cnt_d = cnt_q + 1; + + if (s_wlast) + state_d = SEND_B; + end + end + // ~> send a write acknowledge back + SEND_B: begin + s_bvalid = 1'b1; + s_bid = ax_req_q_id; + if (s_bready) + state_d = IDLE; + end + + endcase + end + + // -------------- + // Registers + // -------------- + always @(posedge clk or negedge resetn) begin + if (~resetn) begin + state_q <= IDLE; + ax_req_q_addr <= 32'h0; + ax_req_q_burst <= 2'h0; + ax_req_q_id <= 'h0; + ax_req_q_len <= 8'h0; + ax_req_q_size <= 3'h0; + req_addr_q <= 'h0; + cnt_q <= 8'h0; + end else begin + state_q <= state_d; + ax_req_q_addr <= ax_req_d_addr; + ax_req_q_burst <= ax_req_d_burst; + ax_req_q_id <= ax_req_d_id; + ax_req_q_len <= ax_req_d_len; + ax_req_q_size <= ax_req_d_size; + req_addr_q <= req_addr_d; + cnt_q <= cnt_d; + end + end +endmodule + diff --git a/rtl/ip/Bus_interconnects/axi2sram_sp_external.v b/rtl/ip/Bus_interconnects/axi2sram_sp_external.v new file mode 100644 index 0000000..1bb30d1 --- /dev/null +++ b/rtl/ip/Bus_interconnects/axi2sram_sp_external.v @@ -0,0 +1,380 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// ---------------------------- +// AXI to SRAM Adapter +// ---------------------------- +// Author: Florian Zaruba (zarubaf@iis.ee.ethz.ch) +// +// Description: Manages AXI transactions +// Supports all burst accesses but only on aligned addresses and with full data width. +// Assertions should guide you if there is something unsupported happening. +// +module axi2sram_sp_external #( + parameter AXI_ID_WIDTH = 5, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 32 +)( + input clk, + input resetn, + + input [AXI_ADDR_WIDTH-1:0] s_araddr , + input [1 :0] s_arburst, + input [3 :0] s_arcache, + input [AXI_ID_WIDTH-1 :0] s_arid , + input [7 :0] s_arlen , + input s_arlock , + input [2 :0] s_arprot , + output reg s_arready, + input [2 :0] s_arsize , + input s_arvalid, + input [AXI_ADDR_WIDTH-1:0] s_awaddr , + input [1 :0] s_awburst, + input [3 :0] s_awcache, + input [AXI_ID_WIDTH-1 :0] s_awid , + input [7 :0] s_awlen , + input s_awlock , + input [2 :0] s_awprot , + output reg s_awready, + input [2 :0] s_awsize , + input s_awvalid, + output reg [AXI_ID_WIDTH-1 :0] s_bid , + input s_bready , + output reg [1 :0] s_bresp , + output reg s_bvalid , + output reg [AXI_DATA_WIDTH-1:0] s_rdata , + output reg [AXI_ID_WIDTH-1 :0] s_rid , + output reg s_rlast , + input s_rready , + output reg [1 :0] s_rresp , + output reg s_rvalid , + input [AXI_DATA_WIDTH-1:0] s_wdata , + input s_wlast , + output reg s_wready , + input [AXI_DATA_WIDTH/8-1:0] s_wstrb , + input s_wvalid , + + output reg req_o, + output reg we_o, + output reg [AXI_ADDR_WIDTH-1:0] addr_o, + output reg [AXI_DATA_WIDTH/8-1:0] be_o, + output reg [AXI_DATA_WIDTH-1:0] data_o, + input [AXI_DATA_WIDTH-1:0] data_i +); + // AXI has the following rules governing the use of bursts: + // - for wrapping bursts, the burst length must be 2, 4, 8, or 16 + // - a burst must not cross a 4KB address boundary + // - early termination of bursts is not supported. + + localparam LOG_NR_BYTES = $clog2(AXI_DATA_WIDTH/8); + + reg [AXI_ID_WIDTH-1:0] ax_req_d_id; + reg [AXI_ADDR_WIDTH-1:0] ax_req_d_addr; + reg [7:0] ax_req_d_len; + reg [2:0] ax_req_d_size; + reg [1:0] ax_req_d_burst; + + reg [AXI_ID_WIDTH-1:0] ax_req_q_id; + reg [AXI_ADDR_WIDTH-1:0] ax_req_q_addr; + reg [7:0] ax_req_q_len; + reg [2:0] ax_req_q_size; + reg [1:0] ax_req_q_burst; + + reg [2:0] state_d; + reg [2:0] state_q; + + localparam IDLE = 3'h0; + localparam READ = 3'h1; + localparam WRITE = 3'h2; + localparam SEND_B = 3'h3; + localparam WAIT_WVALID = 3'h4; + localparam WRITE_NOP = 3'h5; + localparam READ_ADDR = 3'h6; + + localparam FIXED = 2'b00; + localparam INCR = 2'b01; + localparam WRAP = 2'b10; + + reg [AXI_ADDR_WIDTH-1:0] req_addr_d, req_addr_q; + reg [7:0] cnt_d, cnt_q; + + function automatic [AXI_ADDR_WIDTH-1:0] get_wrap_boundary; + input [AXI_ADDR_WIDTH-1:0] unaligned_address; + input [7:0] len; + begin + get_wrap_boundary = 'h0; + // for wrapping transfers ax_len can only be of size 1, 3, 7 or 15 + if (len == 4'b1) + get_wrap_boundary[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES]; + else if (len == 4'b11) + get_wrap_boundary[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES]; + else if (len == 4'b111) + get_wrap_boundary[AXI_ADDR_WIDTH-1:3+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:2+LOG_NR_BYTES]; + else if (len == 4'b1111) + get_wrap_boundary[AXI_ADDR_WIDTH-1:4+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:4+LOG_NR_BYTES]; + end + endfunction + + reg [AXI_ADDR_WIDTH-1:0] aligned_address; + reg [AXI_ADDR_WIDTH-1:0] wrap_boundary; + reg [AXI_ADDR_WIDTH-1:0] upper_wrap_boundary; + reg [AXI_ADDR_WIDTH-1:0] cons_addr; + + always @ (*) begin + // address generation + aligned_address = {ax_req_q_addr[AXI_ADDR_WIDTH-1:LOG_NR_BYTES], {{LOG_NR_BYTES}{1'b0}}}; + wrap_boundary = get_wrap_boundary(ax_req_q_addr, ax_req_q_len); + // this will overflow + upper_wrap_boundary = wrap_boundary + ((ax_req_q_len + 1) << LOG_NR_BYTES); + // calculate consecutive address + cons_addr = aligned_address + (cnt_q << LOG_NR_BYTES); + + // Transaction attributes + // default assignments + state_d = state_q; + ax_req_d_id = ax_req_q_id; + ax_req_d_addr = ax_req_q_addr; + ax_req_d_len = ax_req_q_len; + ax_req_d_size = ax_req_q_size; + ax_req_d_burst = ax_req_q_burst; + req_addr_d = req_addr_q; + cnt_d = cnt_q; + // Memory default assignments + data_o = s_wdata; + be_o = s_wstrb; + we_o = 1'b0; + req_o = 1'b0; + addr_o = 'h0; + // AXI assignments + // request + s_awready = 1'b0; + s_arready = 1'b0; + // read response channel + s_rvalid = 1'b0; + s_rresp = 'h0; + s_rlast = 'h0; + s_rid = ax_req_q_id; + // slave write data channel + s_wready = 1'b0; + // write response channel + s_bvalid = 1'b0; + s_bresp = 1'b0; + s_bid = 1'b0; + + case (state_q) + + IDLE: begin + // Wait for a read or write + // ------------ + // Read + // ------------ + if (s_arvalid) begin + s_arready = 1'b1; + // sample ax + ax_req_d_id = s_arid; + ax_req_d_addr = s_araddr; + ax_req_d_len = s_arlen; + ax_req_d_size = s_arsize; + ax_req_d_burst = s_arburst; + state_d = READ; + // we can request the first address, this saves us time + req_o = 1'b1; + addr_o = s_araddr; + // save the address + req_addr_d = s_araddr; + // save the ar_len + cnt_d = 1; + // ------------ + // Write + // ------------ + end else if (s_awvalid) begin + s_awready = 1'b1; + s_wready = 1'b1; + addr_o = s_awaddr; + // sample ax + ax_req_d_id = s_awid; + ax_req_d_addr = s_awaddr; + ax_req_d_len = s_awlen; + ax_req_d_size = s_awsize; + ax_req_d_burst = s_awburst; + // we've got our first w_valid so start the write process + if (s_wvalid) begin + req_o = 1'b1; + we_o = 1'b1; + state_d = (s_wlast) ? SEND_B : WRITE_NOP; + cnt_d = 1; + // we still have to wait for the first w_valid to arrive + end else + state_d = WAIT_WVALID; + end + end + + // ~> we are still missing a w_valid + WAIT_WVALID: begin + s_wready = 1'b1; + addr_o = ax_req_q_addr; + // we can now make our first request + if (s_wvalid) begin + req_o = 1'b1; + we_o = 1'b1; + state_d = (s_wlast) ? SEND_B : WRITE; + cnt_d = 1; + end + end + + READ: begin + // keep request to memory high + req_o = 1'b1; + addr_o = req_addr_q; + // send the response + s_rvalid = 1'b1; + s_rdata = data_i; + s_rid = ax_req_q_id; + s_rlast = (cnt_q == ax_req_q_len + 1); + // check that the master is ready, the slave must not wait on this + if (s_rready) begin + // we sent the last byte -> go back to idle + if (s_rlast) begin + state_d = IDLE; + // we already got everything + end + else begin + state_d = READ_ADDR; + end + end + end + + READ_ADDR: begin + // keep request to memory high + req_o = 1'b1; + // send the response + s_rvalid = 1'b0; + // ---------------------------- + // Next address generation + // ---------------------------- + // handle the correct burst type + case (ax_req_q_burst) + FIXED, INCR: addr_o = cons_addr; + WRAP: begin + // check if the address reached warp boundary + if (cons_addr == upper_wrap_boundary) begin + addr_o = wrap_boundary; + // address warped beyond boundary + end else if (cons_addr > upper_wrap_boundary) begin + addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES); + // we are still in the incremental regime + end else begin + addr_o = cons_addr; + end + end + endcase + // we need to change the address here for the upcoming request + // we can decrease the counter as the master has consumed the read data + cnt_d = cnt_q + 1; + // save the request address for the next cycle + req_addr_d = addr_o; + state_d = READ; + end + + //ext SRAM need nop between continuous write operations + WRITE_NOP: begin + s_wready = 1'b0; + state_d = WRITE; + end + + // ~> we already wrote the first word here + WRITE: begin + + s_wready = 1'b1; + state_d = WRITE_NOP; + + // consume a word here + if (s_wvalid) begin + req_o = 1'b1; + we_o = 1'b1; + // ---------------------------- + // Next address generation + // ---------------------------- + // handle the correct burst type + case (ax_req_q_burst) + + FIXED, INCR: addr_o = cons_addr; + WRAP: begin + // check if the address reached warp boundary + if (cons_addr == upper_wrap_boundary) begin + addr_o = wrap_boundary; + // address warped beyond boundary + end else if (cons_addr > upper_wrap_boundary) begin + addr_o = ax_req_q_addr + ((cnt_q - ax_req_q_len) << LOG_NR_BYTES); + // we are still in the incremental regime + end else begin + addr_o = cons_addr; + end + end + endcase + // save the request address for the next cycle + req_addr_d = addr_o; + // we can decrease the counter as the master has consumed the read data + cnt_d = cnt_q + 1; + + if (s_wlast) + state_d = SEND_B; + end + end + // ~> send a write acknowledge back + SEND_B: begin + s_bvalid = 1'b1; + s_bid = ax_req_q_id; + if (s_bready) + state_d = IDLE; + end + + endcase + end + + // -------------- + // Registers + // -------------- + always @(posedge clk or negedge resetn) begin + if (~resetn) begin + state_q <= IDLE; + ax_req_q_addr <= 32'h0; + ax_req_q_burst <= 2'h0; + ax_req_q_id <= 'h0; + ax_req_q_len <= 8'h0; + ax_req_q_size <= 3'h0; + req_addr_q <= 'h0; + cnt_q <= 8'h0; + end else begin + state_q <= state_d; + ax_req_q_addr <= ax_req_d_addr; + ax_req_q_burst <= ax_req_d_burst; + ax_req_q_id <= ax_req_d_id; + ax_req_q_len <= ax_req_d_len; + ax_req_q_size <= ax_req_d_size; + req_addr_q <= req_addr_d; + cnt_q <= cnt_d; + end + end + + + // always @(posedge clk or negedge resetn) begin + // if (~resetn) begin + // s_rdata <= 'h0; + // end else begin + // if(req_o == 1'b1 && we_o == 1'b0) + // s_rdata <= data_i; + // else + // s_rdata <= s_rdata; + // end + // end + +endmodule + diff --git a/rtl/ip/DVI/axi_dvi.v b/rtl/ip/DVI/axi_dvi.v new file mode 100644 index 0000000..b77b165 --- /dev/null +++ b/rtl/ip/DVI/axi_dvi.v @@ -0,0 +1,258 @@ +module axi_dvi # +( + parameter WIDTH = 12, // hdata and vdata width (in bits) + parameter HSIZE = 800, // Horizontal size of visible area + parameter HFP = 856, // Horizontal front porch + parameter HSP = 976, // Horizontal sync pulse + parameter HMAX = 1040, // Horizontal total size + parameter VSIZE = 600, // Vertical size of visible area + parameter VFP = 637, // Vertical front porch + parameter VSP = 643, // Vertical sync pulse + parameter VMAX = 666, // Vertical total size + parameter HSPP = 1, // Horizontal sync pulse polarity (1 for positive) + parameter VSPP = 1 // Vertical sync pulse polarity (1 for positive) +) +( + input s_awvalid, + output s_awready, + input [31:0] s_awaddr, + input [4:0] s_awid, + input [7:0] s_awlen, + input [2:0] s_awsize, + input [1:0] s_awburst, + input [0:0] s_awlock, + input [3:0] s_awcache, + input [2:0] s_awprot, + input s_wvalid, + output s_wready, + input [31:0] s_wdata, + input [3:0] s_wstrb, + input s_wlast, + output s_bvalid, + input s_bready, + output [4:0] s_bid, + output [1:0] s_bresp, + input s_arvalid, + output s_arready, + input [31:0] s_araddr, + input [4:0] s_arid, + input [7:0] s_arlen, + input [2:0] s_arsize, + input [1:0] s_arburst, + input [0:0] s_arlock, + input [3:0] s_arcache, + input [2:0] s_arprot, + output s_rvalid, + input s_rready, + output [31:0] s_rdata, + output [4:0] s_rid, + output [1:0] s_rresp, + output s_rlast, + + output video_clk, // Video clock signal + output hsync, // Horizontal sync signal + output vsync, // Vertical sync signal + output data_enable, // Data enable signal + output [2:0] video_red, // Red color signal (3 bits) + output [2:0] video_green, // Green color signal (3 bits) + output [1:0] video_blue, // Blue color signal (2 bits) + + input aclk, + input aresetn +); + + reg [31:0] DVI_RECT_DIR,DVI_RECT_L_W,DVI_SQU_DIR,DVI_SQU_R; + + reg busy,write,R_or_W; + reg s_wready; + + wire ar_enter = s_arvalid & s_arready; + wire r_retire = s_rvalid & s_rready & s_rlast; + wire aw_enter = s_awvalid & s_awready; + wire w_enter = s_wvalid & s_wready & s_wlast; + wire b_retire = s_bvalid & s_bready; + + assign s_arready = ~busy & (!R_or_W| !s_awvalid); + assign s_awready = ~busy & ( R_or_W| !s_arvalid); + + always@(posedge aclk) + if(~aresetn) busy <= 1'b0; + else if(ar_enter|aw_enter) busy <= 1'b1; + else if(r_retire|b_retire) busy <= 1'b0; + + reg [3 :0] buf_id; + reg [31:0] buf_addr; + reg [7 :0] buf_len; + reg [2 :0] buf_size; + reg [1 :0] buf_burst; + reg buf_lock; + reg [3 :0] buf_cache; + reg [2 :0] buf_prot; + + always@(posedge aclk) begin + if(~aresetn) begin + R_or_W <= 1'b0; + buf_id <= 'b0; + buf_addr <= 'b0; + buf_len <= 'b0; + buf_size <= 'b0; + buf_burst <= 'b0; + buf_lock <= 'b0; + buf_cache <= 'b0; + buf_prot <= 'b0; + end + else + if(ar_enter | aw_enter) begin + R_or_W <= ar_enter; + buf_id <= ar_enter ? s_arid : s_awid ; + buf_addr <= ar_enter ? s_araddr : s_awaddr ; + buf_len <= ar_enter ? s_arlen : s_awlen ; + buf_size <= ar_enter ? s_arsize : s_awsize ; + buf_burst <= ar_enter ? s_arburst: s_awburst; + buf_lock <= ar_enter ? s_arlock : s_awlock ; + buf_cache <= ar_enter ? s_arcache: s_awcache; + buf_prot <= ar_enter ? s_arprot : s_awprot ; + end + end + + always@(posedge aclk) + if(~aresetn) write <= 1'b0; + else if(aw_enter) write <= 1'b1; + else if(ar_enter) write <= 1'b0; + + always@(posedge aclk) + if(~aresetn) s_wready <= 1'b0; + else if(aw_enter) s_wready <= 1'b1; + else if(w_enter & s_wlast) s_wready <= 1'b0; + + + reg [31:0] s_rdata; + reg s_rvalid,s_rlast; + wire [31:0] rdata_d = buf_addr[15:0] == 16'h0 ? DVI_RECT_DIR : + buf_addr[15:0] == 16'h4 ? DVI_RECT_L_W : + buf_addr[15:0] == 16'h8 ? DVI_SQU_DIR : + buf_addr[15:0] == 16'hc ? DVI_SQU_R : + 32'd0; + + always@(posedge aclk)begin + if(~aresetn) begin + s_rdata <= 'b0; + s_rvalid <= 1'b0; + s_rlast <= 1'b0; + end + else if(busy & !write & !r_retire) + begin + s_rdata <= rdata_d; + s_rvalid <= 1'b1; + s_rlast <= 1'b1; + end + else if(r_retire) + begin + s_rvalid <= 1'b0; + end + end + + reg s_bvalid; + always@(posedge aclk) begin + if(~aresetn) s_bvalid <= 1'b0; + else if(w_enter) s_bvalid <= 1'b1; + else if(b_retire) s_bvalid <= 1'b0; + end + assign s_rid = buf_id; + assign s_bid = buf_id; + assign s_bresp = 2'b0; + assign s_rresp = 2'b0; + + +//-------------------------------{dvi controller}begin----------------------------// + wire write_reg_en[3:0]; + assign write_reg_en[0] = w_enter & (buf_addr[15:0]==16'h0); + assign write_reg_en[1] = w_enter & (buf_addr[15:0]==16'h4); + assign write_reg_en[2] = w_enter & (buf_addr[15:0]==16'h8); + assign write_reg_en[3] = w_enter & (buf_addr[15:0]==16'hc); + + always @(posedge aclk) begin + if(!aresetn) begin + DVI_RECT_DIR <= 32'h0; + end + else if (write_reg_en[0]) begin + DVI_RECT_DIR <= s_wdata; + end + end + + always @(posedge aclk) begin + if(!aresetn) begin + DVI_RECT_L_W <= 32'h0; + end + else if (write_reg_en[1]) begin + DVI_RECT_L_W <= s_wdata; + end + end + + always @(posedge aclk) begin + if(!aresetn) begin + DVI_SQU_DIR <= 32'h0; + end + else if (write_reg_en[2]) begin + DVI_SQU_DIR <= s_wdata; + end + end + + always @(posedge aclk) begin + if(!aresetn) begin + DVI_SQU_R <= 32'h0; + end + else if (write_reg_en[3]) begin + DVI_SQU_R <= s_wdata; + end + end + + reg [WIDTH-1:0] hdata = 0; // Horizontal position counter + reg [WIDTH-1:0] vdata = 0; // Vertical position counter + + wire hdata_in_range; + wire vdata_in_range; + + wire hdata1_in_range; + wire vdata1_in_range; + + always @(posedge aclk) begin + if (hdata == (HMAX - 1)) // If horizontal counter reaches max + hdata <= 0; // Reset horizontal counter + else + hdata <= hdata + 1; // Increment horizontal counter + end + + // Vertical counter (vdata) logic + always @(posedge aclk) begin + if (hdata == (HMAX - 1)) begin + if (vdata == (VMAX - 1)) // If vertical counter reaches max + vdata <= 0; // Reset vertical counter + else + vdata <= vdata + 1; // Increment vertical counter + end + end + + // Horizontal sync signal generation (hsync) + assign video_clk = aclk; // Example: using input clock as video clock + assign hsync = ((hdata >= HFP) && (hdata < HSP)) ? HSPP : !HSPP; + assign vsync = ((vdata >= VFP) && (vdata < VSP)) ? VSPP : !VSPP; + assign data_enable = ((hdata < HSIZE) & (vdata < VSIZE)); + + assign hdata_in_range = (hdata > (DVI_RECT_DIR[31:16]-DVI_RECT_L_W[31:16])) && (hdata < (DVI_RECT_DIR[31:16]+DVI_RECT_L_W[31:16])); + // Check if vdata is in the range specified by DVI_RECT_L_W + assign vdata_in_range = (vdata > DVI_RECT_DIR[15:0]) && (vdata <(DVI_RECT_DIR[15:0]+DVI_RECT_L_W[15:0])); + + assign hdata1_in_range = (hdata > (DVI_SQU_DIR[31:16]-DVI_SQU_R[31:16])) && (hdata < (DVI_SQU_DIR[31:16]+DVI_SQU_R[31:16])); + // Check if vdata is in the range specified by DVI_RECT_L_W + assign vdata1_in_range = (vdata > (DVI_SQU_DIR[15:0]-DVI_SQU_R[15:0])) && (vdata <(DVI_SQU_DIR[15:0]+DVI_SQU_R[15:0])); + + // Set video output colors based on conditions + assign video_red = ((hdata_in_range && vdata_in_range)||(hdata1_in_range && vdata1_in_range)) ? 3'b111 : 3'b0; + assign video_green = 3'b0; + assign video_blue = 2'b0; + +//--------------------------------{dvi controller}end-----------------------------// + + +endmodule \ No newline at end of file diff --git a/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v b/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v new file mode 100644 index 0000000..bf7a3d9 --- /dev/null +++ b/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v @@ -0,0 +1,224 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 +// Date : Tue Jun 23 00:27:14 2026 +// Host : fedora running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v +// Design : clk_pll +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a200tfbg676-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module clk_pll + (cpu_clk, + sys_clk, + resetn, + locked, + clk_in1); + output cpu_clk; + output sys_clk; + input resetn; + output locked; + input clk_in1; + + (* IBUF_LOW_PWR *) wire clk_in1; + wire cpu_clk; + wire locked; + wire resetn; + wire sys_clk; + + clk_pll_clk_pll_clk_wiz inst + (.clk_in1(clk_in1), + .cpu_clk(cpu_clk), + .locked(locked), + .resetn(resetn), + .sys_clk(sys_clk)); +endmodule + +(* ORIG_REF_NAME = "clk_pll_clk_wiz" *) +module clk_pll_clk_pll_clk_wiz + (cpu_clk, + sys_clk, + resetn, + locked, + clk_in1); + output cpu_clk; + output sys_clk; + input resetn; + output locked; + input clk_in1; + + wire clk_in1; + wire clk_in1_clk_pll; + wire clkfbout_buf_clk_pll; + wire clkfbout_clk_pll; + wire cpu_clk; + wire cpu_clk_clk_pll; + wire locked; + wire reset_high; + wire resetn; + wire sys_clk; + wire sys_clk_clk_pll; + wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_plle2_adv_inst_DRDY_UNCONNECTED; + wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_clk_pll), + .O(clkfbout_buf_clk_pll)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF #( + .IOSTANDARD("DEFAULT")) + clkin1_ibufg + (.I(clk_in1), + .O(clk_in1_clk_pll)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(cpu_clk_clk_pll), + .O(cpu_clk)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout2_buf + (.I(sys_clk_clk_pll), + .O(sys_clk)); + (* BOX_TYPE = "PRIMITIVE" *) + PLLE2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT(31), + .CLKFBOUT_PHASE(0.000000), + .CLKIN1_PERIOD(20.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE(47), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT1_DIVIDE(31), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(1), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .STARTUP_WAIT("FALSE")) + plle2_adv_inst + (.CLKFBIN(clkfbout_buf_clk_pll), + .CLKFBOUT(clkfbout_clk_pll), + .CLKIN1(clk_in1_clk_pll), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKOUT0(cpu_clk_clk_pll), + .CLKOUT1(sys_clk_clk_pll), + .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(locked), + .PWRDWN(1'b0), + .RST(reset_high)); + LUT1 #( + .INIT(2'h1)) + plle2_adv_inst_i_1 + (.I0(resetn), + .O(reset_high)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl b/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl new file mode 100644 index 0000000..39ea676 --- /dev/null +++ b/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl @@ -0,0 +1,170 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 +-- Date : Tue Jun 23 00:27:14 2026 +-- Host : fedora running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl +-- Design : clk_pll +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7a200tfbg676-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity clk_pll_clk_pll_clk_wiz is + port ( + cpu_clk : out STD_LOGIC; + sys_clk : out STD_LOGIC; + resetn : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of clk_pll_clk_pll_clk_wiz : entity is "clk_pll_clk_wiz"; +end clk_pll_clk_pll_clk_wiz; + +architecture STRUCTURE of clk_pll_clk_pll_clk_wiz is + signal clk_in1_clk_pll : STD_LOGIC; + signal clkfbout_buf_clk_pll : STD_LOGIC; + signal clkfbout_clk_pll : STD_LOGIC; + signal cpu_clk_clk_pll : STD_LOGIC; + signal reset_high : STD_LOGIC; + signal sys_clk_clk_pll : STD_LOGIC; + signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; + attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE"; +begin +clkf_buf: unisim.vcomponents.BUFG + port map ( + I => clkfbout_clk_pll, + O => clkfbout_buf_clk_pll + ); +clkin1_ibufg: unisim.vcomponents.IBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => clk_in1, + O => clk_in1_clk_pll + ); +clkout1_buf: unisim.vcomponents.BUFG + port map ( + I => cpu_clk_clk_pll, + O => cpu_clk + ); +clkout2_buf: unisim.vcomponents.BUFG + port map ( + I => sys_clk_clk_pll, + O => sys_clk + ); +plle2_adv_inst: unisim.vcomponents.PLLE2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT => 31, + CLKFBOUT_PHASE => 0.000000, + CLKIN1_PERIOD => 20.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE => 47, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT1_DIVIDE => 31, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + COMPENSATION => "ZHOLD", + DIVCLK_DIVIDE => 1, + IS_CLKINSEL_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + STARTUP_WAIT => "FALSE" + ) + port map ( + CLKFBIN => clkfbout_buf_clk_pll, + CLKFBOUT => clkfbout_clk_pll, + CLKIN1 => clk_in1_clk_pll, + CLKIN2 => '0', + CLKINSEL => '1', + CLKOUT0 => cpu_clk_clk_pll, + CLKOUT1 => sys_clk_clk_pll, + CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED, + CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED, + CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => locked, + PWRDWN => '0', + RST => reset_high + ); +plle2_adv_inst_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => resetn, + O => reset_high + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity clk_pll is + port ( + cpu_clk : out STD_LOGIC; + sys_clk : out STD_LOGIC; + resetn : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of clk_pll : entity is true; +end clk_pll; + +architecture STRUCTURE of clk_pll is +begin +inst: entity work.clk_pll_clk_pll_clk_wiz + port map ( + clk_in1 => clk_in1, + cpu_clk => cpu_clk, + locked => locked, + resetn => resetn, + sys_clk => sys_clk + ); +end STRUCTURE; diff --git a/rtl/ip/PLL_2019_2/clk_pll_stub.v b/rtl/ip/PLL_2019_2/clk_pll_stub.v new file mode 100644 index 0000000..d6ce4de --- /dev/null +++ b/rtl/ip/PLL_2019_2/clk_pll_stub.v @@ -0,0 +1,23 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 +// Date : Tue Jun 23 00:27:14 2026 +// Host : fedora running 64-bit unknown +// Command : write_verilog -force -mode synth_stub +// /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.v +// Design : clk_pll +// Purpose : Stub declaration of top-level module interface +// Device : xc7a200tfbg676-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module clk_pll(cpu_clk, sys_clk, resetn, locked, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="cpu_clk,sys_clk,resetn,locked,clk_in1" */; + output cpu_clk; + output sys_clk; + input resetn; + output locked; + input clk_in1; +endmodule diff --git a/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl b/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl new file mode 100644 index 0000000..e5ecdc3 --- /dev/null +++ b/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 +-- Date : Tue Jun 23 00:27:14 2026 +-- Host : fedora running 64-bit unknown +-- Command : write_vhdl -force -mode synth_stub +-- /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl +-- Design : clk_pll +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7a200tfbg676-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_pll is + Port ( + cpu_clk : out STD_LOGIC; + sys_clk : out STD_LOGIC; + resetn : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + +end clk_pll; + +architecture stub of clk_pll is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "cpu_clk,sys_clk,resetn,locked,clk_in1"; +begin +end; diff --git a/rtl/ip/axi_axil_adapter/axi_axil_adapter.v b/rtl/ip/axi_axil_adapter/axi_axil_adapter.v new file mode 100644 index 0000000..4593ea3 --- /dev/null +++ b/rtl/ip/axi_axil_adapter/axi_axil_adapter.v @@ -0,0 +1,223 @@ +/* + +Copyright (c) 2019 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 to AXI4-Lite adapter + */ +module axi_axil_adapter # +( + // Width of address bus in bits + parameter ADDR_WIDTH = 32, + // Width of input (slave) AXI interface data bus in bits + parameter AXI_DATA_WIDTH = 32, + // Width of input (slave) AXI interface wstrb (width of data bus in words) + parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8), + // Width of AXI ID signal + parameter AXI_ID_WIDTH = 8, + // Width of output (master) AXI lite interface data bus in bits + parameter AXIL_DATA_WIDTH = 32, + // Width of output (master) AXI lite interface wstrb (width of data bus in words) + parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8), + // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible + parameter CONVERT_BURST = 1, + // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible + parameter CONVERT_NARROW_BURST = 0 +) +( + input wire clk, + input wire rst, + + /* + * AXI slave interface + */ + input wire [AXI_ID_WIDTH-1:0] s_axi_awid, + input wire [ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [7:0] s_axi_awlen, + input wire [2:0] s_axi_awsize, + input wire [1:0] s_axi_awburst, + input wire s_axi_awlock, + input wire [3:0] s_axi_awcache, + input wire [2:0] s_axi_awprot, + input wire s_axi_awvalid, + output wire s_axi_awready, + input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, + input wire [AXI_STRB_WIDTH-1:0] s_axi_wstrb, + input wire s_axi_wlast, + input wire s_axi_wvalid, + output wire s_axi_wready, + output wire [AXI_ID_WIDTH-1:0] s_axi_bid, + output wire [1:0] s_axi_bresp, + output wire s_axi_bvalid, + input wire s_axi_bready, + input wire [AXI_ID_WIDTH-1:0] s_axi_arid, + input wire [ADDR_WIDTH-1:0] s_axi_araddr, + input wire [7:0] s_axi_arlen, + input wire [2:0] s_axi_arsize, + input wire [1:0] s_axi_arburst, + input wire s_axi_arlock, + input wire [3:0] s_axi_arcache, + input wire [2:0] s_axi_arprot, + input wire s_axi_arvalid, + output wire s_axi_arready, + output wire [AXI_ID_WIDTH-1:0] s_axi_rid, + output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, + output wire [1:0] s_axi_rresp, + output wire s_axi_rlast, + output wire s_axi_rvalid, + input wire s_axi_rready, + + /* + * AXI lite master interface + */ + output wire [ADDR_WIDTH-1:0] m_axil_awaddr, + output wire [2:0] m_axil_awprot, + output wire m_axil_awvalid, + input wire m_axil_awready, + output wire [AXIL_DATA_WIDTH-1:0] m_axil_wdata, + output wire [AXIL_STRB_WIDTH-1:0] m_axil_wstrb, + output wire m_axil_wvalid, + input wire m_axil_wready, + input wire [1:0] m_axil_bresp, + input wire m_axil_bvalid, + output wire m_axil_bready, + output wire [ADDR_WIDTH-1:0] m_axil_araddr, + output wire [2:0] m_axil_arprot, + output wire m_axil_arvalid, + input wire m_axil_arready, + input wire [AXIL_DATA_WIDTH-1:0] m_axil_rdata, + input wire [1:0] m_axil_rresp, + input wire m_axil_rvalid, + output wire m_axil_rready +); + + +axi_axil_adapter_wr #( + .ADDR_WIDTH(ADDR_WIDTH), + .AXI_DATA_WIDTH(AXI_DATA_WIDTH), + .AXI_STRB_WIDTH(AXI_STRB_WIDTH), + .AXI_ID_WIDTH(AXI_ID_WIDTH), + .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), + .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), + .CONVERT_BURST(CONVERT_BURST), + .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST) +) +axi_axil_adapter_wr_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI slave interface + */ + .s_axi_awid(s_axi_awid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awlen(s_axi_awlen), + .s_axi_awsize(s_axi_awsize), + .s_axi_awburst(s_axi_awburst), + .s_axi_awlock(s_axi_awlock), + .s_axi_awcache(s_axi_awcache), + .s_axi_awprot(s_axi_awprot), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awready(s_axi_awready), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wlast(s_axi_wlast), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wready(s_axi_wready), + .s_axi_bid(s_axi_bid), + .s_axi_bresp(s_axi_bresp), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bready(s_axi_bready), + + /* + * AXI lite master interface + */ + .m_axil_awaddr(m_axil_awaddr), + .m_axil_awprot(m_axil_awprot), + .m_axil_awvalid(m_axil_awvalid), + .m_axil_awready(m_axil_awready), + .m_axil_wdata(m_axil_wdata), + .m_axil_wstrb(m_axil_wstrb), + .m_axil_wvalid(m_axil_wvalid), + .m_axil_wready(m_axil_wready), + .m_axil_bresp(m_axil_bresp), + .m_axil_bvalid(m_axil_bvalid), + .m_axil_bready(m_axil_bready) +); + +axi_axil_adapter_rd #( + .ADDR_WIDTH(ADDR_WIDTH), + .AXI_DATA_WIDTH(AXI_DATA_WIDTH), + .AXI_STRB_WIDTH(AXI_STRB_WIDTH), + .AXI_ID_WIDTH(AXI_ID_WIDTH), + .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), + .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), + .CONVERT_BURST(CONVERT_BURST), + .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST) +) +axi_axil_adapter_rd_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI slave interface + */ + .s_axi_arid(s_axi_arid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arlen(s_axi_arlen), + .s_axi_arsize(s_axi_arsize), + .s_axi_arburst(s_axi_arburst), + .s_axi_arlock(s_axi_arlock), + .s_axi_arcache(s_axi_arcache), + .s_axi_arprot(s_axi_arprot), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_arready(s_axi_arready), + .s_axi_rid(s_axi_rid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rresp(s_axi_rresp), + .s_axi_rlast(s_axi_rlast), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_rready(s_axi_rready), + + /* + * AXI lite master interface + */ + .m_axil_araddr(m_axil_araddr), + .m_axil_arprot(m_axil_arprot), + .m_axil_arvalid(m_axil_arvalid), + .m_axil_arready(m_axil_arready), + .m_axil_rdata(m_axil_rdata), + .m_axil_rresp(m_axil_rresp), + .m_axil_rvalid(m_axil_rvalid), + .m_axil_rready(m_axil_rready) +); + +endmodule + +`resetall diff --git a/rtl/ip/axi_axil_adapter/axi_axil_adapter_rd.v b/rtl/ip/axi_axil_adapter/axi_axil_adapter_rd.v new file mode 100644 index 0000000..e27dfa4 --- /dev/null +++ b/rtl/ip/axi_axil_adapter/axi_axil_adapter_rd.v @@ -0,0 +1,507 @@ +/* + +Copyright (c) 2019 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 to AXI4-Lite adapter (read) + */ +module axi_axil_adapter_rd # +( + // Width of address bus in bits + parameter ADDR_WIDTH = 32, + // Width of input (slave) AXI interface data bus in bits + parameter AXI_DATA_WIDTH = 32, + // Width of input (slave) AXI interface wstrb (width of data bus in words) + parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8), + // Width of AXI ID signal + parameter AXI_ID_WIDTH = 8, + // Width of output (master) AXI lite interface data bus in bits + parameter AXIL_DATA_WIDTH = 32, + // Width of output (master) AXI lite interface wstrb (width of data bus in words) + parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8), + // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible + parameter CONVERT_BURST = 1, + // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible + parameter CONVERT_NARROW_BURST = 0 +) +( + input wire clk, + input wire rst, + + /* + * AXI slave interface + */ + input wire [AXI_ID_WIDTH-1:0] s_axi_arid, + input wire [ADDR_WIDTH-1:0] s_axi_araddr, + input wire [7:0] s_axi_arlen, + input wire [2:0] s_axi_arsize, + input wire [1:0] s_axi_arburst, + input wire s_axi_arlock, + input wire [3:0] s_axi_arcache, + input wire [2:0] s_axi_arprot, + input wire s_axi_arvalid, + output wire s_axi_arready, + output wire [AXI_ID_WIDTH-1:0] s_axi_rid, + output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, + output wire [1:0] s_axi_rresp, + output wire s_axi_rlast, + output wire s_axi_rvalid, + input wire s_axi_rready, + + /* + * AXI lite master interface + */ + output wire [ADDR_WIDTH-1:0] m_axil_araddr, + output wire [2:0] m_axil_arprot, + output wire m_axil_arvalid, + input wire m_axil_arready, + input wire [AXIL_DATA_WIDTH-1:0] m_axil_rdata, + input wire [1:0] m_axil_rresp, + input wire m_axil_rvalid, + output wire m_axil_rready +); + +parameter AXI_ADDR_BIT_OFFSET = $clog2(AXI_STRB_WIDTH); +parameter AXIL_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_WIDTH); +parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH; +parameter AXIL_WORD_WIDTH = AXIL_STRB_WIDTH; +parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH; +parameter AXIL_WORD_SIZE = AXIL_DATA_WIDTH/AXIL_WORD_WIDTH; +parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH); +parameter AXIL_BURST_SIZE = $clog2(AXIL_STRB_WIDTH); + +// output bus is wider +parameter EXPAND = AXIL_STRB_WIDTH > AXI_STRB_WIDTH; +parameter DATA_WIDTH = EXPAND ? AXIL_DATA_WIDTH : AXI_DATA_WIDTH; +parameter STRB_WIDTH = EXPAND ? AXIL_STRB_WIDTH : AXI_STRB_WIDTH; +// required number of segments in wider bus +parameter SEGMENT_COUNT = EXPAND ? (AXIL_STRB_WIDTH / AXI_STRB_WIDTH) : (AXI_STRB_WIDTH / AXIL_STRB_WIDTH); +// data width and keep width per segment +parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT; +parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT; + +// bus width assertions +initial begin + if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin + $error("Error: AXI slave interface data width not evenly divisble (instance %m)"); + $finish; + end + + if (AXIL_WORD_SIZE * AXIL_STRB_WIDTH != AXIL_DATA_WIDTH) begin + $error("Error: AXI lite master interface data width not evenly divisble (instance %m)"); + $finish; + end + + if (AXI_WORD_SIZE != AXIL_WORD_SIZE) begin + $error("Error: word size mismatch (instance %m)"); + $finish; + end + + if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin + $error("Error: AXI slave interface word width must be even power of two (instance %m)"); + $finish; + end + + if (2**$clog2(AXIL_WORD_WIDTH) != AXIL_WORD_WIDTH) begin + $error("Error: AXI lite master interface word width must be even power of two (instance %m)"); + $finish; + end +end + +localparam SAFE_EXP_MSB = (AXIL_ADDR_BIT_OFFSET > AXI_ADDR_BIT_OFFSET) ? AXIL_ADDR_BIT_OFFSET - 1 : AXI_ADDR_BIT_OFFSET; +localparam SAFE_EXP_LSB = AXI_ADDR_BIT_OFFSET; + +localparam SAFE_NAR_MSB = (AXI_ADDR_BIT_OFFSET > AXIL_ADDR_BIT_OFFSET) ? AXI_ADDR_BIT_OFFSET - 1 : AXIL_ADDR_BIT_OFFSET; +localparam SAFE_NAR_LSB = AXIL_ADDR_BIT_OFFSET; + +localparam [1:0] + STATE_IDLE = 2'd0, + STATE_DATA = 2'd1, + STATE_DATA_READ = 2'd2, + STATE_DATA_SPLIT = 2'd3; + +reg [1:0] state_reg = STATE_IDLE, state_next; + +reg [AXI_ID_WIDTH-1:0] id_reg = {AXI_ID_WIDTH{1'b0}}, id_next; +reg [ADDR_WIDTH-1:0] addr_reg = {ADDR_WIDTH{1'b0}}, addr_next; +reg [DATA_WIDTH-1:0] data_reg = {DATA_WIDTH{1'b0}}, data_next; +reg [1:0] resp_reg = 2'd0, resp_next; +reg [7:0] burst_reg = 8'd0, burst_next; +reg [2:0] burst_size_reg = 3'd0, burst_size_next; +reg [7:0] master_burst_reg = 8'd0, master_burst_next; +reg [2:0] master_burst_size_reg = 3'd0, master_burst_size_next; + +reg s_axi_arready_reg = 1'b0, s_axi_arready_next; +reg [AXI_ID_WIDTH-1:0] s_axi_rid_reg = {AXI_ID_WIDTH{1'b0}}, s_axi_rid_next; +reg [AXI_DATA_WIDTH-1:0] s_axi_rdata_reg = {AXI_DATA_WIDTH{1'b0}}, s_axi_rdata_next; +reg [1:0] s_axi_rresp_reg = 2'd0, s_axi_rresp_next; +reg s_axi_rlast_reg = 1'b0, s_axi_rlast_next; +reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next; + +reg [ADDR_WIDTH-1:0] m_axil_araddr_reg = {ADDR_WIDTH{1'b0}}, m_axil_araddr_next; +reg [2:0] m_axil_arprot_reg = 3'd0, m_axil_arprot_next; +reg m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next; +reg m_axil_rready_reg = 1'b0, m_axil_rready_next; + +assign s_axi_arready = s_axi_arready_reg; +assign s_axi_rid = s_axi_rid_reg; +assign s_axi_rdata = s_axi_rdata_reg; +assign s_axi_rresp = s_axi_rresp_reg; +assign s_axi_rlast = s_axi_rlast_reg; +assign s_axi_rvalid = s_axi_rvalid_reg; + +assign m_axil_araddr = m_axil_araddr_reg; +assign m_axil_arprot = m_axil_arprot_reg; +assign m_axil_arvalid = m_axil_arvalid_reg; +assign m_axil_rready = m_axil_rready_reg; + +always @* begin + state_next = STATE_IDLE; + + id_next = id_reg; + addr_next = addr_reg; + data_next = data_reg; + resp_next = resp_reg; + burst_next = burst_reg; + burst_size_next = burst_size_reg; + master_burst_next = master_burst_reg; + master_burst_size_next = master_burst_size_reg; + + s_axi_arready_next = 1'b0; + s_axi_rid_next = s_axi_rid_reg; + s_axi_rdata_next = s_axi_rdata_reg; + s_axi_rresp_next = s_axi_rresp_reg; + s_axi_rlast_next = s_axi_rlast_reg; + s_axi_rvalid_next = s_axi_rvalid_reg && !s_axi_rready; + m_axil_araddr_next = m_axil_araddr_reg; + m_axil_arprot_next = m_axil_arprot_reg; + m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_arready; + m_axil_rready_next = 1'b0; + + if (SEGMENT_COUNT == 1) begin + // master output is same width; direct transfer with no splitting/merging + case (state_reg) + STATE_IDLE: begin + // idle state; wait for new burst + s_axi_arready_next = !m_axil_arvalid; + + if (s_axi_arready && s_axi_arvalid) begin + s_axi_arready_next = 1'b0; + id_next = s_axi_arid; + m_axil_araddr_next = s_axi_araddr; + addr_next = s_axi_araddr; + burst_next = s_axi_arlen; + burst_size_next = s_axi_arsize; + m_axil_arprot_next = s_axi_arprot; + m_axil_arvalid_next = 1'b1; + m_axil_rready_next = 1'b0; + state_next = STATE_DATA; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + // data state; transfer read data + m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid; + + if (m_axil_rready && m_axil_rvalid) begin + s_axi_rid_next = id_reg; + s_axi_rdata_next = m_axil_rdata; + s_axi_rresp_next = m_axil_rresp; + s_axi_rlast_next = 1'b0; + s_axi_rvalid_next = 1'b1; + burst_next = burst_reg - 1; + addr_next = addr_reg + (1 << burst_size_reg); + if (burst_reg == 0) begin + // last data word, return to idle + m_axil_rready_next = 1'b0; + s_axi_rlast_next = 1'b1; + s_axi_arready_next = !m_axil_arvalid; + state_next = STATE_IDLE; + end else begin + // start new AXI lite read + m_axil_araddr_next = addr_next; + m_axil_arvalid_next = 1'b1; + m_axil_rready_next = 1'b0; + state_next = STATE_DATA; + end + end else begin + state_next = STATE_DATA; + end + end + endcase + end else if (EXPAND) begin + // master output is wider; split reads + case (state_reg) + STATE_IDLE: begin + // idle state; wait for new burst + s_axi_arready_next = !m_axil_arvalid; + + if (s_axi_arready && s_axi_arvalid) begin + s_axi_arready_next = 1'b0; + id_next = s_axi_arid; + m_axil_araddr_next = s_axi_araddr; + addr_next = s_axi_araddr; + burst_next = s_axi_arlen; + burst_size_next = s_axi_arsize; + if (CONVERT_BURST && s_axi_arcache[1] && (CONVERT_NARROW_BURST || s_axi_arsize == AXI_BURST_SIZE)) begin + // split reads + // require CONVERT_BURST and arcache[1] set + master_burst_size_next = AXIL_BURST_SIZE; + state_next = STATE_DATA_READ; + end else begin + // output narrow burst + master_burst_size_next = s_axi_arsize; + state_next = STATE_DATA; + end + m_axil_arprot_next = s_axi_arprot; + m_axil_arvalid_next = 1'b1; + m_axil_rready_next = 1'b0; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid; + + if (m_axil_rready && m_axil_rvalid) begin + s_axi_rid_next = id_reg; + s_axi_rdata_next = m_axil_rdata >> (addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB] * AXI_DATA_WIDTH); + s_axi_rresp_next = m_axil_rresp; + s_axi_rlast_next = 1'b0; + s_axi_rvalid_next = 1'b1; + burst_next = burst_reg - 1; + addr_next = addr_reg + (1 << burst_size_reg); + if (burst_reg == 0) begin + // last data word, return to idle + m_axil_rready_next = 1'b0; + s_axi_rlast_next = 1'b1; + s_axi_arready_next = !m_axil_arvalid; + state_next = STATE_IDLE; + end else begin + // start new AXI lite read + m_axil_araddr_next = addr_next; + m_axil_arvalid_next = 1'b1; + m_axil_rready_next = 1'b0; + state_next = STATE_DATA; + end + end else begin + state_next = STATE_DATA; + end + end + STATE_DATA_READ: begin + m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid; + + if (m_axil_rready && m_axil_rvalid) begin + s_axi_rid_next = id_reg; + data_next = m_axil_rdata; + resp_next = m_axil_rresp; + s_axi_rdata_next = m_axil_rdata >> (addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB] * AXI_DATA_WIDTH); + s_axi_rresp_next = m_axil_rresp; + s_axi_rlast_next = 1'b0; + s_axi_rvalid_next = 1'b1; + burst_next = burst_reg - 1; + addr_next = addr_reg + (1 << burst_size_reg); + if (burst_reg == 0) begin + m_axil_rready_next = 1'b0; + s_axi_arready_next = !m_axil_arvalid; + s_axi_rlast_next = 1'b1; + state_next = STATE_IDLE; + end else if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin + // start new AXI lite read + m_axil_araddr_next = addr_next; + m_axil_arvalid_next = 1'b1; + m_axil_rready_next = 1'b0; + state_next = STATE_DATA_READ; + end else begin + m_axil_rready_next = 1'b0; + state_next = STATE_DATA_SPLIT; + end + end else begin + state_next = STATE_DATA_READ; + end + end + STATE_DATA_SPLIT: begin + m_axil_rready_next = 1'b0; + + if (s_axi_rready || !s_axi_rvalid) begin + s_axi_rid_next = id_reg; + s_axi_rdata_next = data_reg >> (addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB] * AXI_DATA_WIDTH); + s_axi_rresp_next = resp_reg; + s_axi_rlast_next = 1'b0; + s_axi_rvalid_next = 1'b1; + burst_next = burst_reg - 1; + addr_next = addr_reg + (1 << burst_size_reg); + if (burst_reg == 0) begin + s_axi_arready_next = !m_axil_arvalid; + s_axi_rlast_next = 1'b1; + state_next = STATE_IDLE; + end else if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin + // start new AXI lite read + m_axil_araddr_next = addr_next; + m_axil_arvalid_next = 1'b1; + m_axil_rready_next = 1'b0; + state_next = STATE_DATA_READ; + end else begin + state_next = STATE_DATA_SPLIT; + end + end else begin + state_next = STATE_DATA_SPLIT; + end + end + endcase + end else begin + // master output is narrower; merge reads and possibly split burst + case (state_reg) + STATE_IDLE: begin + // idle state; wait for new burst + s_axi_arready_next = !m_axil_arvalid; + + resp_next = 2'd0; + + if (s_axi_arready && s_axi_arvalid) begin + s_axi_arready_next = 1'b0; + id_next = s_axi_arid; + m_axil_araddr_next = s_axi_araddr; + addr_next = s_axi_araddr; + burst_next = s_axi_arlen; + burst_size_next = s_axi_arsize; + if (s_axi_arsize > AXIL_BURST_SIZE) begin + // need to adjust burst size + if (s_axi_arlen >> (8+AXIL_BURST_SIZE-s_axi_arsize) != 0) begin + // limit burst length to max + master_burst_next = (8'd255 << (s_axi_arsize-AXIL_BURST_SIZE)) | ((~s_axi_araddr & (8'hff >> (8-s_axi_arsize))) >> AXIL_BURST_SIZE); + end else begin + master_burst_next = (s_axi_arlen << (s_axi_arsize-AXIL_BURST_SIZE)) | ((~s_axi_araddr & (8'hff >> (8-s_axi_arsize))) >> AXIL_BURST_SIZE); + end + master_burst_size_next = AXIL_BURST_SIZE; + end else begin + // pass through narrow (enough) burst + master_burst_next = s_axi_arlen; + master_burst_size_next = s_axi_arsize; + end + m_axil_arprot_next = s_axi_arprot; + m_axil_arvalid_next = 1'b1; + m_axil_rready_next = 1'b0; + state_next = STATE_DATA; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid; + + if (m_axil_rready && m_axil_rvalid) begin + data_next[addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axil_rdata; + if (m_axil_rresp) begin + resp_next = m_axil_rresp; + end + s_axi_rid_next = id_reg; + s_axi_rdata_next = data_next; + s_axi_rresp_next = resp_next; + s_axi_rlast_next = 1'b0; + s_axi_rvalid_next = 1'b0; + master_burst_next = master_burst_reg - 1; + addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg); + m_axil_araddr_next = addr_next; + if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin + data_next = {DATA_WIDTH{1'b0}}; + burst_next = burst_reg - 1; + s_axi_rvalid_next = 1'b1; + end + if (master_burst_reg == 0) begin + if (burst_next >> (8+AXIL_BURST_SIZE-burst_size_reg) != 0) begin + // limit burst length to max + master_burst_next = 8'd255; + end else begin + master_burst_next = (burst_next << (burst_size_reg-AXIL_BURST_SIZE)) | (8'hff >> (8-burst_size_reg) >> AXIL_BURST_SIZE); + end + + if (burst_reg == 0) begin + m_axil_rready_next = 1'b0; + s_axi_rlast_next = 1'b1; + s_axi_rvalid_next = 1'b1; + s_axi_arready_next = !m_axil_arvalid; + state_next = STATE_IDLE; + end else begin + m_axil_arvalid_next = 1'b1; + m_axil_rready_next = 1'b0; + state_next = STATE_DATA; + end + end else begin + m_axil_arvalid_next = 1'b1; + m_axil_rready_next = 1'b0; + state_next = STATE_DATA; + end + end else begin + state_next = STATE_DATA; + end + end + endcase + end +end + +always @(posedge clk) begin + state_reg <= state_next; + + id_reg <= id_next; + addr_reg <= addr_next; + data_reg <= data_next; + resp_reg <= resp_next; + burst_reg <= burst_next; + burst_size_reg <= burst_size_next; + master_burst_reg <= master_burst_next; + master_burst_size_reg <= master_burst_size_next; + + s_axi_arready_reg <= s_axi_arready_next; + s_axi_rid_reg <= s_axi_rid_next; + s_axi_rdata_reg <= s_axi_rdata_next; + s_axi_rresp_reg <= s_axi_rresp_next; + s_axi_rlast_reg <= s_axi_rlast_next; + s_axi_rvalid_reg <= s_axi_rvalid_next; + + m_axil_araddr_reg <= m_axil_araddr_next; + m_axil_arprot_reg <= m_axil_arprot_next; + m_axil_arvalid_reg <= m_axil_arvalid_next; + m_axil_rready_reg <= m_axil_rready_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_axi_arready_reg <= 1'b0; + s_axi_rvalid_reg <= 1'b0; + + m_axil_arvalid_reg <= 1'b0; + m_axil_rready_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/rtl/ip/axi_axil_adapter/axi_axil_adapter_wr.v b/rtl/ip/axi_axil_adapter/axi_axil_adapter_wr.v new file mode 100644 index 0000000..44822d5 --- /dev/null +++ b/rtl/ip/axi_axil_adapter/axi_axil_adapter_wr.v @@ -0,0 +1,570 @@ +/* + +Copyright (c) 2019 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 to AXI4-Lite adapter (write) + */ +module axi_axil_adapter_wr # +( + // Width of address bus in bits + parameter ADDR_WIDTH = 32, + // Width of input (slave) AXI interface data bus in bits + parameter AXI_DATA_WIDTH = 32, + // Width of input (slave) AXI interface wstrb (width of data bus in words) + parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8), + // Width of AXI ID signal + parameter AXI_ID_WIDTH = 8, + // Width of output (master) AXI lite interface data bus in bits + parameter AXIL_DATA_WIDTH = 32, + // Width of output (master) AXI lite interface wstrb (width of data bus in words) + parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8), + // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible + parameter CONVERT_BURST = 1, + // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible + parameter CONVERT_NARROW_BURST = 0 +) +( + input wire clk, + input wire rst, + + /* + * AXI slave interface + */ + input wire [AXI_ID_WIDTH-1:0] s_axi_awid, + input wire [ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [7:0] s_axi_awlen, + input wire [2:0] s_axi_awsize, + input wire [1:0] s_axi_awburst, + input wire s_axi_awlock, + input wire [3:0] s_axi_awcache, + input wire [2:0] s_axi_awprot, + input wire s_axi_awvalid, + output wire s_axi_awready, + input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, + input wire [AXI_STRB_WIDTH-1:0] s_axi_wstrb, + input wire s_axi_wlast, + input wire s_axi_wvalid, + output wire s_axi_wready, + output wire [AXI_ID_WIDTH-1:0] s_axi_bid, + output wire [1:0] s_axi_bresp, + output wire s_axi_bvalid, + input wire s_axi_bready, + + /* + * AXI lite master interface + */ + output wire [ADDR_WIDTH-1:0] m_axil_awaddr, + output wire [2:0] m_axil_awprot, + output wire m_axil_awvalid, + input wire m_axil_awready, + output wire [AXIL_DATA_WIDTH-1:0] m_axil_wdata, + output wire [AXIL_STRB_WIDTH-1:0] m_axil_wstrb, + output wire m_axil_wvalid, + input wire m_axil_wready, + input wire [1:0] m_axil_bresp, + input wire m_axil_bvalid, + output wire m_axil_bready +); + +parameter AXI_ADDR_BIT_OFFSET = $clog2(AXI_STRB_WIDTH); +parameter AXIL_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_WIDTH); +parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH; +parameter AXIL_WORD_WIDTH = AXIL_STRB_WIDTH; +parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH; +parameter AXIL_WORD_SIZE = AXIL_DATA_WIDTH/AXIL_WORD_WIDTH; +parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH); +parameter AXIL_BURST_SIZE = $clog2(AXIL_STRB_WIDTH); + +// output bus is wider +parameter EXPAND = AXIL_STRB_WIDTH > AXI_STRB_WIDTH; +parameter DATA_WIDTH = EXPAND ? AXIL_DATA_WIDTH : AXI_DATA_WIDTH; +parameter STRB_WIDTH = EXPAND ? AXIL_STRB_WIDTH : AXI_STRB_WIDTH; +// required number of segments in wider bus +parameter SEGMENT_COUNT = EXPAND ? (AXIL_STRB_WIDTH / AXI_STRB_WIDTH) : (AXI_STRB_WIDTH / AXIL_STRB_WIDTH); +// data width and keep width per segment +parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT; +parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT; + +// bus width assertions +initial begin + if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin + $error("Error: AXI slave interface data width not evenly divisble (instance %m)"); + $finish; + end + + if (AXIL_WORD_SIZE * AXIL_STRB_WIDTH != AXIL_DATA_WIDTH) begin + $error("Error: AXI lite master interface data width not evenly divisble (instance %m)"); + $finish; + end + + if (AXI_WORD_SIZE != AXIL_WORD_SIZE) begin + $error("Error: word size mismatch (instance %m)"); + $finish; + end + + if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin + $error("Error: AXI slave interface word width must be even power of two (instance %m)"); + $finish; + end + + if (2**$clog2(AXIL_WORD_WIDTH) != AXIL_WORD_WIDTH) begin + $error("Error: AXI lite master interface word width must be even power of two (instance %m)"); + $finish; + end +end + +localparam [1:0] + STATE_IDLE = 2'd0, + STATE_DATA = 2'd1, + STATE_DATA_2 = 2'd2, + STATE_RESP = 2'd3; + +// 添加安全的位选边界，防止 ModelSim 报 Range Reversed 错误 +localparam SAFE_EXP_MSB = (AXIL_ADDR_BIT_OFFSET > AXI_ADDR_BIT_OFFSET) ? AXIL_ADDR_BIT_OFFSET - 1 : AXI_ADDR_BIT_OFFSET; +localparam SAFE_EXP_LSB = AXI_ADDR_BIT_OFFSET; + +localparam SAFE_NAR_MSB = (AXI_ADDR_BIT_OFFSET > AXIL_ADDR_BIT_OFFSET) ? AXI_ADDR_BIT_OFFSET - 1 : AXIL_ADDR_BIT_OFFSET; +localparam SAFE_NAR_LSB = AXIL_ADDR_BIT_OFFSET; +reg [1:0] state_reg = STATE_IDLE, state_next; + +reg [AXI_ID_WIDTH-1:0] id_reg = {AXI_ID_WIDTH{1'b0}}, id_next; +reg [ADDR_WIDTH-1:0] addr_reg = {ADDR_WIDTH{1'b0}}, addr_next; +reg [DATA_WIDTH-1:0] data_reg = {DATA_WIDTH{1'b0}}, data_next; +reg [STRB_WIDTH-1:0] strb_reg = {STRB_WIDTH{1'b0}}, strb_next; +reg [7:0] burst_reg = 8'd0, burst_next; +reg [2:0] burst_size_reg = 3'd0, burst_size_next; +reg [2:0] master_burst_size_reg = 3'd0, master_burst_size_next; +reg burst_active_reg = 1'b0, burst_active_next; +reg convert_burst_reg = 1'b0, convert_burst_next; +reg first_transfer_reg = 1'b0, first_transfer_next; +reg last_segment_reg = 1'b0, last_segment_next; + +reg s_axi_awready_reg = 1'b0, s_axi_awready_next; +reg s_axi_wready_reg = 1'b0, s_axi_wready_next; +reg [AXI_ID_WIDTH-1:0] s_axi_bid_reg = {AXI_ID_WIDTH{1'b0}}, s_axi_bid_next; +reg [1:0] s_axi_bresp_reg = 2'd0, s_axi_bresp_next; +reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next; + +reg [ADDR_WIDTH-1:0] m_axil_awaddr_reg = {ADDR_WIDTH{1'b0}}, m_axil_awaddr_next; +reg [2:0] m_axil_awprot_reg = 3'd0, m_axil_awprot_next; +reg m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next; +reg [AXIL_DATA_WIDTH-1:0] m_axil_wdata_reg = {AXIL_DATA_WIDTH{1'b0}}, m_axil_wdata_next; +reg [AXIL_STRB_WIDTH-1:0] m_axil_wstrb_reg = {AXIL_STRB_WIDTH{1'b0}}, m_axil_wstrb_next; +reg m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next; +reg m_axil_bready_reg = 1'b0, m_axil_bready_next; + +assign s_axi_awready = s_axi_awready_reg; +assign s_axi_wready = s_axi_wready_reg; +assign s_axi_bid = s_axi_bid_reg; +assign s_axi_bresp = s_axi_bresp_reg; +assign s_axi_bvalid = s_axi_bvalid_reg; + +assign m_axil_awaddr = m_axil_awaddr_reg; +//assign m_axil_awlen = m_axil_awlen_reg; +//assign m_axil_awsize = m_axil_awsize_reg; +//assign m_axil_awburst = m_axil_awburst_reg; +assign m_axil_awprot = m_axil_awprot_reg; +assign m_axil_awvalid = m_axil_awvalid_reg; +assign m_axil_wdata = m_axil_wdata_reg; +assign m_axil_wstrb = m_axil_wstrb_reg; +assign m_axil_wvalid = m_axil_wvalid_reg; +assign m_axil_bready = m_axil_bready_reg; + +integer i; + +always @* begin + state_next = STATE_IDLE; + + id_next = id_reg; + addr_next = addr_reg; + data_next = data_reg; + strb_next = strb_reg; + burst_next = burst_reg; + burst_size_next = burst_size_reg; + master_burst_size_next = master_burst_size_reg; + burst_active_next = burst_active_reg; + convert_burst_next = convert_burst_reg; + first_transfer_next = first_transfer_reg; + last_segment_next = last_segment_reg; + + s_axi_awready_next = 1'b0; + s_axi_wready_next = 1'b0; + s_axi_bid_next = s_axi_bid_reg; + s_axi_bresp_next = s_axi_bresp_reg; + s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_bready; + m_axil_awaddr_next = m_axil_awaddr_reg; + m_axil_awprot_next = m_axil_awprot_reg; + m_axil_awvalid_next = m_axil_awvalid_reg && !m_axil_awready; + m_axil_wdata_next = m_axil_wdata_reg; + m_axil_wstrb_next = m_axil_wstrb_reg; + m_axil_wvalid_next = m_axil_wvalid_reg && !m_axil_wready; + m_axil_bready_next = 1'b0; + + if (SEGMENT_COUNT == 1) begin + // master output is same width; direct transfer with no splitting/merging + case (state_reg) + STATE_IDLE: begin + // idle state; wait for new burst + s_axi_awready_next = !m_axil_awvalid; + first_transfer_next = 1'b1; + + if (s_axi_awready && s_axi_awvalid) begin + s_axi_awready_next = 1'b0; + id_next = s_axi_awid; + m_axil_awaddr_next = s_axi_awaddr; + addr_next = s_axi_awaddr; + burst_next = s_axi_awlen; + burst_size_next = s_axi_awsize; + burst_active_next = 1'b1; + m_axil_awprot_next = s_axi_awprot; + m_axil_awvalid_next = 1'b1; + s_axi_wready_next = !m_axil_wvalid; + state_next = STATE_DATA; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + // data state; transfer write data + s_axi_wready_next = !m_axil_wvalid; + + if (s_axi_wready && s_axi_wvalid) begin + m_axil_wdata_next = s_axi_wdata; + m_axil_wstrb_next = s_axi_wstrb; + m_axil_wvalid_next = 1'b1; + burst_next = burst_reg - 1; + burst_active_next = burst_reg != 0; + addr_next = addr_reg + (1 << burst_size_reg); + s_axi_wready_next = 1'b0; + m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid; + state_next = STATE_RESP; + end else begin + state_next = STATE_DATA; + end + end + STATE_RESP: begin + // resp state; transfer write response + m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid; + + if (m_axil_bready && m_axil_bvalid) begin + m_axil_bready_next = 1'b0; + s_axi_bid_next = id_reg; + first_transfer_next = 1'b0; + if (first_transfer_reg || m_axil_bresp != 0) begin + s_axi_bresp_next = m_axil_bresp; + end + if (burst_active_reg) begin + // burst on slave interface still active; start new AXI lite write + m_axil_awaddr_next = addr_reg; + m_axil_awvalid_next = 1'b1; + s_axi_wready_next = !m_axil_wvalid; + state_next = STATE_DATA; + end else begin + // burst on slave interface finished; return to idle + s_axi_bvalid_next = 1'b1; + s_axi_awready_next = !m_axil_awvalid; + state_next = STATE_IDLE; + end + end else begin + state_next = STATE_RESP; + end + end + endcase + end else if (EXPAND) begin + // master output is wider; merge writes + case (state_reg) + STATE_IDLE: begin + // idle state; wait for new burst + s_axi_awready_next = !m_axil_awvalid; + + first_transfer_next = 1'b1; + + data_next = {DATA_WIDTH{1'b0}}; + strb_next = {STRB_WIDTH{1'b0}}; + + if (s_axi_awready && s_axi_awvalid) begin + s_axi_awready_next = 1'b0; + id_next = s_axi_awid; + m_axil_awaddr_next = s_axi_awaddr; + addr_next = s_axi_awaddr; + burst_next = s_axi_awlen; + burst_size_next = s_axi_awsize; + if (CONVERT_BURST && s_axi_awcache[1] && (CONVERT_NARROW_BURST || s_axi_awsize == AXI_BURST_SIZE)) begin + // merge writes + // require CONVERT_BURST and awcache[1] set + convert_burst_next = 1'b1; + master_burst_size_next = AXIL_BURST_SIZE; + state_next = STATE_DATA_2; + end else begin + // output narrow burst + convert_burst_next = 1'b0; + master_burst_size_next = s_axi_awsize; + state_next = STATE_DATA; + end + m_axil_awprot_next = s_axi_awprot; + m_axil_awvalid_next = 1'b1; + s_axi_wready_next = !m_axil_wvalid; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + // data state; transfer write data + s_axi_wready_next = !m_axil_wvalid || m_axil_wready; + + if (s_axi_wready && s_axi_wvalid) begin + m_axil_wdata_next = {(AXIL_WORD_WIDTH/AXI_WORD_WIDTH){s_axi_wdata}}; + m_axil_wstrb_next = s_axi_wstrb << (addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB] * AXI_STRB_WIDTH); + m_axil_wvalid_next = 1'b1; + burst_next = burst_reg - 1; + burst_active_next = burst_reg != 0; + addr_next = addr_reg + (1 << burst_size_reg); + s_axi_wready_next = 1'b0; + m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid; + state_next = STATE_RESP; + end else begin + state_next = STATE_DATA; + end + end + STATE_DATA_2: begin + s_axi_wready_next = !m_axil_wvalid; + + if (s_axi_wready && s_axi_wvalid) begin + if (CONVERT_NARROW_BURST) begin + for (i = 0; i < AXI_WORD_WIDTH; i = i + 1) begin + if (s_axi_wstrb[i]) begin + data_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_DATA_WIDTH+i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE] = s_axi_wdata[i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE]; + strb_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_STRB_WIDTH+i] = 1'b1; + end + end + end else begin + data_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = s_axi_wdata; + strb_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_STRB_WIDTH +: SEGMENT_STRB_WIDTH] = s_axi_wstrb; + end + m_axil_wdata_next = data_next; + m_axil_wstrb_next = strb_next; + burst_next = burst_reg - 1; + burst_active_next = burst_reg != 0; + addr_next = addr_reg + (1 << burst_size_reg); + if (burst_reg == 0 || addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin + data_next = {DATA_WIDTH{1'b0}}; + strb_next = {STRB_WIDTH{1'b0}}; + m_axil_wvalid_next = 1'b1; + s_axi_wready_next = 1'b0; + m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid; + state_next = STATE_RESP; + end else begin + state_next = STATE_DATA_2; + end + end else begin + state_next = STATE_DATA_2; + end + end + STATE_RESP: begin + // resp state; transfer write response + m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid; + + if (m_axil_bready && m_axil_bvalid) begin + m_axil_bready_next = 1'b0; + s_axi_bid_next = id_reg; + first_transfer_next = 1'b0; + if (first_transfer_reg || m_axil_bresp != 0) begin + s_axi_bresp_next = m_axil_bresp; + end + if (burst_active_reg) begin + // burst on slave interface still active; start new AXI lite write + m_axil_awaddr_next = addr_reg; + m_axil_awvalid_next = 1'b1; + s_axi_wready_next = !m_axil_wvalid || m_axil_wready; + if (convert_burst_reg) begin + state_next = STATE_DATA_2; + end else begin + state_next = STATE_DATA; + end + end else begin + // burst on slave interface finished; return to idle + s_axi_bvalid_next = 1'b1; + s_axi_awready_next = !m_axil_awvalid; + state_next = STATE_IDLE; + end + end else begin + state_next = STATE_RESP; + end + end + endcase + end else begin + // master output is narrower; split writes, and possibly split burst + case (state_reg) + STATE_IDLE: begin + // idle state; wait for new burst + s_axi_awready_next = !m_axil_awvalid; + + first_transfer_next = 1'b1; + + if (s_axi_awready && s_axi_awvalid) begin + s_axi_awready_next = 1'b0; + id_next = s_axi_awid; + m_axil_awaddr_next = s_axi_awaddr; + addr_next = s_axi_awaddr; + burst_next = s_axi_awlen; + burst_size_next = s_axi_awsize; + burst_active_next = 1'b1; + if (s_axi_awsize > AXIL_BURST_SIZE) begin + // need to adjust burst size + master_burst_size_next = AXIL_BURST_SIZE; + end else begin + // pass through narrow (enough) burst + master_burst_size_next = s_axi_awsize; + end + m_axil_awprot_next = s_axi_awprot; + m_axil_awvalid_next = 1'b1; + s_axi_wready_next = !m_axil_wvalid; + state_next = STATE_DATA; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + s_axi_wready_next = !m_axil_wvalid; + + if (s_axi_wready && s_axi_wvalid) begin + data_next = s_axi_wdata; + strb_next = s_axi_wstrb; + m_axil_wdata_next = s_axi_wdata >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_DATA_WIDTH); + m_axil_wstrb_next = s_axi_wstrb >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_STRB_WIDTH); + m_axil_wvalid_next = 1'b1; + burst_next = burst_reg - 1; + burst_active_next = burst_reg != 0; + addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg); + last_segment_next = addr_next[burst_size_reg] != addr_reg[burst_size_reg]; + s_axi_wready_next = 1'b0; + m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid; + state_next = STATE_RESP; + end else begin + state_next = STATE_DATA; + end + end + STATE_DATA_2: begin + s_axi_wready_next = 1'b0; + + if (!m_axil_wvalid || m_axil_wready) begin + m_axil_wdata_next = data_reg >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_DATA_WIDTH); + m_axil_wstrb_next = strb_reg >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_STRB_WIDTH); + m_axil_wvalid_next = 1'b1; + addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg); + last_segment_next = addr_next[burst_size_reg] != addr_reg[burst_size_reg]; + s_axi_wready_next = 1'b0; + m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid; + state_next = STATE_RESP; + end else begin + state_next = STATE_DATA_2; + end + end + STATE_RESP: begin + // resp state; transfer write response + m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid; + + if (m_axil_bready && m_axil_bvalid) begin + first_transfer_next = 1'b0; + m_axil_awaddr_next = addr_reg; + m_axil_bready_next = 1'b0; + s_axi_bid_next = id_reg; + if (first_transfer_reg || m_axil_bresp != 0) begin + s_axi_bresp_next = m_axil_bresp; + end + if (burst_active_reg || !last_segment_reg) begin + // burst on slave interface still active; start new burst + m_axil_awvalid_next = 1'b1; + if (last_segment_reg) begin + s_axi_wready_next = !m_axil_wvalid; + state_next = STATE_DATA; + end else begin + s_axi_wready_next = 1'b0; + state_next = STATE_DATA_2; + end + end else begin + // burst on slave interface finished; return to idle + s_axi_bvalid_next = 1'b1; + s_axi_awready_next = !m_axil_awvalid; + state_next = STATE_IDLE; + end + end else begin + state_next = STATE_RESP; + end + end + endcase + end +end + +always @(posedge clk) begin + state_reg <= state_next; + + id_reg <= id_next; + addr_reg <= addr_next; + data_reg <= data_next; + strb_reg <= strb_next; + burst_reg <= burst_next; + burst_size_reg <= burst_size_next; + master_burst_size_reg <= master_burst_size_next; + burst_active_reg <= burst_active_next; + convert_burst_reg <= convert_burst_next; + first_transfer_reg <= first_transfer_next; + last_segment_reg <= last_segment_next; + + s_axi_awready_reg <= s_axi_awready_next; + s_axi_wready_reg <= s_axi_wready_next; + s_axi_bid_reg <= s_axi_bid_next; + s_axi_bresp_reg <= s_axi_bresp_next; + s_axi_bvalid_reg <= s_axi_bvalid_next; + + m_axil_awaddr_reg <= m_axil_awaddr_next; + m_axil_awprot_reg <= m_axil_awprot_next; + m_axil_awvalid_reg <= m_axil_awvalid_next; + m_axil_wdata_reg <= m_axil_wdata_next; + m_axil_wstrb_reg <= m_axil_wstrb_next; + m_axil_wvalid_reg <= m_axil_wvalid_next; + m_axil_bready_reg <= m_axil_bready_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_axi_awready_reg <= 1'b0; + s_axi_wready_reg <= 1'b0; + s_axi_bvalid_reg <= 1'b0; + + m_axil_awvalid_reg <= 1'b0; + m_axil_wvalid_reg <= 1'b0; + m_axil_bready_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/rtl/ip/bram0/my_bram0.v b/rtl/ip/bram0/my_bram0.v new file mode 100644 index 0000000..e6fb4f1 --- /dev/null +++ b/rtl/ip/bram0/my_bram0.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps + +module my_bram0 #( + parameter DATA_WIDTH = 32, // 数据位宽，默认 32 bit + parameter ADDR_WIDTH = 10 // 地址位宽 10 bit，对应深度 1024 +)( + // ======== Port A (Write Only) ======== + input wire clka, + input wire ena, + input wire wea, + input wire [ADDR_WIDTH-1:0] addra, + input wire [DATA_WIDTH-1:0] dina, + + // ======== Port B (Read Only) ======== + input wire clkb, + input wire enb, + input wire [ADDR_WIDTH-1:0] addrb, + output reg [DATA_WIDTH-1:0] doutb +); + + // 声明二维数组作为存储介质 + // 使用 (* ram_style = "block" *) 强制 Vivado 综合器将其映射为 BRAM 资源 + (* ram_style = "block" *) reg [DATA_WIDTH-1:0] ram [0:(1<>1); + end + + always_ff @(posedge rclk or negedge rrst_n) + if(!rrst_n) begin + rd_addr <= (ADDR_W+1)'(0); + rgray <= (ADDR_W+1)'(0); + end + else if(lcl_read && !lcl_rd_empty) begin + rd_addr <= next_rd_addr; + rgray <= next_rd_addr ^ (next_rd_addr>>1); + end + + + always_ff @(posedge wclk) + mem[wr_addr[ADDR_W-1:0]] <= wdata; + + + assign next_rd_addr = rd_addr + 1'b1; + assign lcl_rd_data = mem[rd_addr[ADDR_W-1:0]]; + + always_ff @(posedge wclk or negedge wrst_n) + if(!wrst_n) begin + wr_rgray <= (ADDR_W+1)'(0); + rgray_cross <= (ADDR_W+1)'(0); + end + else begin + {wr_rgray, rgray_cross} <= {rgray_cross, rgray}; + end + + always_ff @(posedge rclk or negedge rrst_n) + if(!rrst_n) begin + rd_wgray <= (ADDR_W+1)'(0); + wgray_cross <= (ADDR_W+1)'(0); + rd_n_items <= (ADDR_W+1)'(0); + end + else begin + {rd_wgray, wgray_cross} <= {wgray_cross, wgray}; + rd_n_items <= (rd_wbin - rd_addr) & ((1 << (ADDR_W + 1)) - 1); + end + + always_comb begin + rd_wbin[ADDR_W] = rd_wgray[ADDR_W]; + for (int i = ADDR_W-1; i >= 0; i--) begin + rd_wbin[i] = rd_wbin[i+1] ^ rd_wgray[i]; + end + end + + assign wfull = wr_rgray == {~wgray[ADDR_W], wgray[ADDR_W-1:0]}; + assign lcl_rd_empty = rd_wgray == rgray; + assign lcl_read = rempty || rd_en; + + always_ff @(posedge rclk or negedge rrst_n) + if(!rrst_n) begin + rempty <= 1'b1; + end + else if(lcl_read) begin + rempty <= lcl_rd_empty; + end + + always_ff @(posedge rclk) + if(lcl_read) + rdata <= lcl_rd_data; + + +endmodule: snix_async_fifo diff --git a/rtl/ip/cdma/snix_axi_cdma.sv b/rtl/ip/cdma/snix_axi_cdma.sv new file mode 100644 index 0000000..c09c6d0 --- /dev/null +++ b/rtl/ip/cdma/snix_axi_cdma.sv @@ -0,0 +1,219 @@ +// ============================================================================ +// snix_axi_cdma.sv +// Central DMA — memory-to-memory transfers via snix_axi_mm2mm +// +// Instantiates: +// snix_axi_cdma_csr — AXI-Lite register interface +// snix_axi_mm2mm — read-then-write AXI4 engine +// +// Software register map (see snix_axi_cdma_csr.sv for full detail): +// 0x00 CDMA_CTRL [0]=start [1]=stop [5:3]=size [13:6]=len +// 0x04 CDMA_NUM_BYTES [31:0]=transfer_len +// 0x08 CDMA_SRC_ADDR [31:0]=source base address +// 0x0C CDMA_DST_ADDR [31:0]=destination base address +// 0x10 STATUS [0]=done (sticky, read-only) +// ============================================================================ +module snix_axi_cdma #( + parameter int ADDR_WIDTH = 32, + parameter int DATA_WIDTH = 64, + parameter int AXIL_ADDR_WIDTH = 32, + parameter int AXIL_DATA_WIDTH = 32, + parameter int ID_WIDTH = 4, + parameter int USER_WIDTH = 1) + (// Global signals + input logic clk, + input logic rst_n, + // AXI-Lite CSR interface + input logic [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr, + input logic s_axil_awvalid, + output logic s_axil_awready, + input logic [AXIL_DATA_WIDTH-1:0] s_axil_wdata, + input logic [AXIL_DATA_WIDTH/8-1:0] s_axil_wstrb, + input logic s_axil_wvalid, + output logic s_axil_wready, + output logic [1:0] s_axil_bresp, + output logic s_axil_bvalid, + input logic s_axil_bready, + input logic [AXIL_ADDR_WIDTH-1:0] s_axil_araddr, + input logic s_axil_arvalid, + output logic s_axil_arready, + output logic [AXIL_DATA_WIDTH-1:0] s_axil_rdata, + output logic [1:0] s_axil_rresp, + output logic s_axil_rvalid, + input logic s_axil_rready, + // AXI4 memory port — AW channel + output logic [ID_WIDTH-1:0] mm2mm_awid, + output logic [ADDR_WIDTH-1:0] mm2mm_awaddr, + output logic [7:0] mm2mm_awlen, + output logic [2:0] mm2mm_awsize, + output logic [1:0] mm2mm_awburst, + output logic mm2mm_awlock, + output logic [3:0] mm2mm_awcache, + output logic [2:0] mm2mm_awprot, + output logic [3:0] mm2mm_awqos, + output logic [USER_WIDTH-1:0] mm2mm_awuser, + output logic mm2mm_awvalid, + input logic mm2mm_awready, + // W channel + output logic [DATA_WIDTH-1:0] mm2mm_wdata, + output logic [DATA_WIDTH/8-1:0] mm2mm_wstrb, + output logic mm2mm_wlast, + output logic [USER_WIDTH-1:0] mm2mm_wuser, + output logic mm2mm_wvalid, + input logic mm2mm_wready, + // B channel + input logic [ID_WIDTH-1:0] mm2mm_bid, + input logic [1:0] mm2mm_bresp, + input logic [USER_WIDTH-1:0] mm2mm_buser, + input logic mm2mm_bvalid, + output logic mm2mm_bready, + // AR channel + output logic [ID_WIDTH-1:0] mm2mm_arid, + output logic [ADDR_WIDTH-1:0] mm2mm_araddr, + output logic [7:0] mm2mm_arlen, + output logic [2:0] mm2mm_arsize, + output logic [1:0] mm2mm_arburst, + output logic mm2mm_arlock, + output logic [3:0] mm2mm_arcache, + output logic [2:0] mm2mm_arprot, + output logic [3:0] mm2mm_arqos, + output logic [USER_WIDTH-1:0] mm2mm_aruser, + output logic mm2mm_arvalid, + input logic mm2mm_arready, + // R channel + input logic [ID_WIDTH-1:0] mm2mm_rid, + input logic [DATA_WIDTH-1:0] mm2mm_rdata, + input logic [1:0] mm2mm_rresp, + input logic mm2mm_rlast, + input logic [USER_WIDTH-1:0] mm2mm_ruser, + input logic mm2mm_rvalid, + output logic mm2mm_rready, + + output logic dma_finish); + +localparam int NUM_REGS = 8; +localparam int FIFO_DEPTH = 16; + +localparam int CDMA_CTRL_IDX = 0; +localparam int CDMA_NUM_BYTES_IDX = 1; +localparam int CDMA_SRC_ADDR_IDX = 2; +localparam int CDMA_DST_ADDR_IDX = 3; +// Index 4 = STATUS — write-protected inside snix_axi_cdma_csr + + logic [NUM_REGS-1:0][AXIL_DATA_WIDTH-1:0] config_status_reg; + logic [AXIL_DATA_WIDTH-1:0] read_status_reg; + +// ------------------------------------------------------------------------- +// Decode control registers +// ------------------------------------------------------------------------- + logic ctrl_start, ctrl_stop; + logic [2:0] ctrl_size; + logic [7:0] ctrl_len; + logic [31:0] ctrl_transfer_len; + logic [ADDR_WIDTH-1:0] ctrl_src_addr, ctrl_dst_addr; + logic ctrl_done; + +assign ctrl_start = config_status_reg[CDMA_CTRL_IDX][0]; +assign ctrl_stop = config_status_reg[CDMA_CTRL_IDX][1]; +assign ctrl_size = config_status_reg[CDMA_CTRL_IDX][5:3]; +assign ctrl_len = config_status_reg[CDMA_CTRL_IDX][13:6]; +assign ctrl_transfer_len = config_status_reg[CDMA_NUM_BYTES_IDX]; +assign ctrl_src_addr = config_status_reg[CDMA_SRC_ADDR_IDX][ADDR_WIDTH-1:0]; +assign ctrl_dst_addr = config_status_reg[CDMA_DST_ADDR_IDX][ADDR_WIDTH-1:0]; + +assign read_status_reg = {{(AXIL_DATA_WIDTH-1){1'b0}}, ctrl_done}; +assign dma_finish = ctrl_done; +// ------------------------------------------------------------------------- +// CSR +// ------------------------------------------------------------------------- +snix_axi_cdma_csr #( + .DATA_WIDTH(AXIL_DATA_WIDTH), + .ADDR_WIDTH(AXIL_ADDR_WIDTH), + .NUM_REGS (NUM_REGS)) +cdma_csr ( + .clk (clk), + .rst_n (rst_n), + .s_axil_awaddr (s_axil_awaddr), + .s_axil_awvalid (s_axil_awvalid), + .s_axil_awready (s_axil_awready), + .s_axil_wdata (s_axil_wdata), + .s_axil_wstrb (s_axil_wstrb), + .s_axil_wvalid (s_axil_wvalid), + .s_axil_wready (s_axil_wready), + .s_axil_bresp (s_axil_bresp), + .s_axil_bvalid (s_axil_bvalid), + .s_axil_bready (s_axil_bready), + .s_axil_araddr (s_axil_araddr), + .s_axil_arvalid (s_axil_arvalid), + .s_axil_arready (s_axil_arready), + .s_axil_rdata (s_axil_rdata), + .s_axil_rresp (s_axil_rresp), + .s_axil_rvalid (s_axil_rvalid), + .s_axil_rready (s_axil_rready), + .read_status_reg (read_status_reg), + .config_status_reg (config_status_reg)); + +// ------------------------------------------------------------------------- +// MM2MM engine +// ------------------------------------------------------------------------- +snix_axi_mm2mm #( + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH (ID_WIDTH), + .USER_WIDTH(USER_WIDTH), + .FIFO_DEPTH(FIFO_DEPTH)) +axi_mm2mm ( + .clk (clk), + .rst_n (rst_n), + .ctrl_start (ctrl_start), + .ctrl_stop (ctrl_stop), + .ctrl_src_addr (ctrl_src_addr), + .ctrl_dst_addr (ctrl_dst_addr), + .ctrl_len (ctrl_len), + .ctrl_size (ctrl_size), + .ctrl_transfer_len(ctrl_transfer_len), + .ctrl_done (ctrl_done), + .mm2mm_awid (mm2mm_awid), + .mm2mm_awaddr (mm2mm_awaddr), + .mm2mm_awlen (mm2mm_awlen), + .mm2mm_awsize (mm2mm_awsize), + .mm2mm_awburst (mm2mm_awburst), + .mm2mm_awlock (mm2mm_awlock), + .mm2mm_awcache (mm2mm_awcache), + .mm2mm_awprot (mm2mm_awprot), + .mm2mm_awqos (mm2mm_awqos), + .mm2mm_awuser (mm2mm_awuser), + .mm2mm_awvalid (mm2mm_awvalid), + .mm2mm_awready (mm2mm_awready), + .mm2mm_wdata (mm2mm_wdata), + .mm2mm_wstrb (mm2mm_wstrb), + .mm2mm_wlast (mm2mm_wlast), + .mm2mm_wuser (mm2mm_wuser), + .mm2mm_wvalid (mm2mm_wvalid), + .mm2mm_wready (mm2mm_wready), + .mm2mm_bid (mm2mm_bid), + .mm2mm_bresp (mm2mm_bresp), + .mm2mm_buser (mm2mm_buser), + .mm2mm_bvalid (mm2mm_bvalid), + .mm2mm_bready (mm2mm_bready), + .mm2mm_arid (mm2mm_arid), + .mm2mm_araddr (mm2mm_araddr), + .mm2mm_arlen (mm2mm_arlen), + .mm2mm_arsize (mm2mm_arsize), + .mm2mm_arburst (mm2mm_arburst), + .mm2mm_arlock (mm2mm_arlock), + .mm2mm_arcache (mm2mm_arcache), + .mm2mm_arprot (mm2mm_arprot), + .mm2mm_arqos (mm2mm_arqos), + .mm2mm_aruser (mm2mm_aruser), + .mm2mm_arvalid (mm2mm_arvalid), + .mm2mm_arready (mm2mm_arready), + .mm2mm_rid (mm2mm_rid), + .mm2mm_rdata (mm2mm_rdata), + .mm2mm_rresp (mm2mm_rresp), + .mm2mm_rlast (mm2mm_rlast), + .mm2mm_ruser (mm2mm_ruser), + .mm2mm_rvalid (mm2mm_rvalid), + .mm2mm_rready (mm2mm_rready)); + +endmodule : snix_axi_cdma diff --git a/rtl/ip/cdma/snix_axi_cdma_csr.sv b/rtl/ip/cdma/snix_axi_cdma_csr.sv new file mode 100644 index 0000000..880cf01 --- /dev/null +++ b/rtl/ip/cdma/snix_axi_cdma_csr.sv @@ -0,0 +1,192 @@ +// ============================================================================ +// snix_axi_cdma_csr.sv +// AXI-Lite CSR for snix_axi_cdma (memory-to-memory central DMA) +// +// Register Map (word-addressed, 32-bit registers): +// +// Offset Index Name Bits +// 0x00 0 CDMA_CTRL [0] = start (write-1 pulse) +// [1] = stop (write-1 pulse) +// [5:3] = size (AXI AxSIZE) +// [13:6] = len (AXI AxLEN) +// [31:14] = reserved +// 0x04 1 CDMA_NUM_BYTES [31:0] = transfer_len (byte count) +// 0x08 2 CDMA_SRC_ADDR [31:0] = source base address +// 0x0C 3 CDMA_DST_ADDR [31:0] = destination base address +// 0x10 4 STATUS (read-only) [0] = done (sticky; cleared on start) +// [31:1] = reserved +// 0x14– 5–7 Reserved +// +// Differences from snix_axi_dma_csr: +// - Single CTRL register (no separate WR/RD paths) +// - Separate SRC_ADDR and DST_ADDR registers +// - STATUS[0] is write-protected; hardware sets it, start clears it +// ============================================================================ +module snix_axi_cdma_csr #( + parameter int DATA_WIDTH = 32, + parameter int ADDR_WIDTH = 4, + parameter int NUM_REGS = 8) + (input logic clk, + input logic rst_n, + // AXI-Lite interface + input logic [ADDR_WIDTH-1:0] s_axil_awaddr, + input logic s_axil_awvalid, + output logic s_axil_awready, + input logic [DATA_WIDTH-1:0] s_axil_wdata, + input logic [DATA_WIDTH/8-1:0] s_axil_wstrb, + input logic s_axil_wvalid, + output logic s_axil_wready, + output logic [1:0] s_axil_bresp, + output logic s_axil_bvalid, + input logic s_axil_bready, + input logic [ADDR_WIDTH-1:0] s_axil_araddr, + input logic s_axil_arvalid, + output logic s_axil_arready, + output logic [DATA_WIDTH-1:0] s_axil_rdata, + output logic [1:0] s_axil_rresp, + output logic s_axil_rvalid, + input logic s_axil_rready, + // Status from mm2mm engine: [0] = ctrl_done (single-cycle pulse) + input logic [DATA_WIDTH-1:0] read_status_reg, + // Register file + output logic [NUM_REGS-1:0][DATA_WIDTH-1:0] config_status_reg); + +localparam int AXIL_DATA_WIDTH = DATA_WIDTH; +localparam int AXIL_ADDR_WIDTH = ADDR_WIDTH; +localparam int ADDRLSB = $clog2(AXIL_DATA_WIDTH / 8); +localparam int REG_INDEX_WIDTH = $clog2(NUM_REGS); + +localparam int CDMA_CTRL_IDX = 0; // 0x00 used: pulse-clear start/stop bits +//localparam int CDMA_NUM_BYTES_IDX = 1; // 0x04 decoded in snix_axi_cdma top +//localparam int CDMA_SRC_ADDR_IDX = 2; // 0x08 decoded in snix_axi_cdma top +//localparam int CDMA_DST_ADDR_IDX = 3; // 0x0C decoded in snix_axi_cdma top +localparam int STATUS_IDX = 4; // 0x10 used: write-protect + done latch + +// ------------------------------------------------------------------------- +// AXI-Lite skid-buffer register slices (same topology as snix_axi_dma_csr) +// ------------------------------------------------------------------------- + logic s_axil_awvalid_reg; + logic [AXIL_ADDR_WIDTH-ADDRLSB-1:0] s_axil_awaddr_reg; + logic s_axil_arvalid_reg; + logic [AXIL_ADDR_WIDTH-ADDRLSB-1:0] s_axil_araddr_reg; + logic s_axil_wvalid_reg; + logic [AXIL_DATA_WIDTH-1:0] s_axil_wdata_reg; + logic [AXIL_DATA_WIDTH/8-1:0] s_axil_wstrb_reg; + + logic s_axil_write_ready, s_axil_read_ready; + logic [31:0] awaddr_index, araddr_index; + +assign s_axil_write_ready = s_axil_awvalid_reg & s_axil_wvalid_reg & + (!s_axil_bvalid | s_axil_bready); +assign s_axil_read_ready = s_axil_arvalid_reg & (!s_axil_rvalid | s_axil_rready); + +assign awaddr_index = {{(32-REG_INDEX_WIDTH){1'b0}}, s_axil_awaddr_reg[REG_INDEX_WIDTH-1:0]}; +assign araddr_index = {{(32-REG_INDEX_WIDTH){1'b0}}, s_axil_araddr_reg[REG_INDEX_WIDTH-1:0]}; + +snix_register_slice #(.DATA_WIDTH(AXIL_ADDR_WIDTH - ADDRLSB)) reg_slice_u0 ( + .clk (clk), + .rst_n (rst_n), + .s_axis_tdata (s_axil_awaddr[AXIL_ADDR_WIDTH-1:ADDRLSB]), + .s_axis_tvalid(s_axil_awvalid), + .s_axis_tready(s_axil_awready), + .m_axis_tdata (s_axil_awaddr_reg), + .m_axis_tvalid(s_axil_awvalid_reg), + .m_axis_tready(s_axil_write_ready)); + +snix_register_slice #(.DATA_WIDTH(AXIL_DATA_WIDTH + AXIL_DATA_WIDTH/8)) reg_slice_u1 ( + .clk (clk), + .rst_n (rst_n), + .s_axis_tdata ({s_axil_wdata, s_axil_wstrb}), + .s_axis_tvalid(s_axil_wvalid), + .s_axis_tready(s_axil_wready), + .m_axis_tdata ({s_axil_wdata_reg, s_axil_wstrb_reg}), + .m_axis_tvalid(s_axil_wvalid_reg), + .m_axis_tready(s_axil_write_ready)); + +snix_register_slice #(.DATA_WIDTH(AXIL_ADDR_WIDTH - ADDRLSB)) reg_slice_u2 ( + .clk (clk), + .rst_n (rst_n), + .s_axis_tdata (s_axil_araddr[AXIL_ADDR_WIDTH-1:ADDRLSB]), + .s_axis_tvalid(s_axil_arvalid), + .s_axis_tready(s_axil_arready), + .m_axis_tdata (s_axil_araddr_reg), + .m_axis_tvalid(s_axil_arvalid_reg), + .m_axis_tready(s_axil_read_ready)); + +// ------------------------------------------------------------------------- +// B channel +// ------------------------------------------------------------------------- +always_ff @(posedge clk or negedge rst_n) + if (!rst_n) s_axil_bvalid <= 1'b0; + else if (s_axil_write_ready) s_axil_bvalid <= 1'b1; + else if (s_axil_bready) s_axil_bvalid <= 1'b0; + +// ------------------------------------------------------------------------- +// R channel +// ------------------------------------------------------------------------- +always_ff @(posedge clk or negedge rst_n) + if (!rst_n) s_axil_rvalid <= 1'b0; + else if (s_axil_read_ready) s_axil_rvalid <= 1'b1; + else if (s_axil_rready) s_axil_rvalid <= 1'b0; + +// ------------------------------------------------------------------------- +// Control / status signal aliases (combinatorial from register file) +// ------------------------------------------------------------------------- + logic ctrl_start, ctrl_stop, ctrl_done; + +assign ctrl_start = config_status_reg[CDMA_CTRL_IDX][0]; +assign ctrl_stop = config_status_reg[CDMA_CTRL_IDX][1]; +assign ctrl_done = read_status_reg[0]; + +// ------------------------------------------------------------------------- +// Register file +// +// Write priority (highest to lowest within an always_ff block): +// 1. AXI-Lite write (byte-enable; STATUS_IDX is write-protected) +// 2. Pulse-clear: start[0] and stop[1] are single-cycle strobes +// 3. STATUS latch: done bit set by hardware, cleared when start fires +// +// Note on NBA priority: later assignments in program order win, so +// "config_status_reg <= config_status_reg" is safely overridden by +// the per-bit assignments that follow in the else branch. +// ------------------------------------------------------------------------- +always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + config_status_reg <= '0; + + end else if (s_axil_write_ready && + awaddr_index < NUM_REGS && + awaddr_index != STATUS_IDX) begin // STATUS is read-only + for (int i = 0; i < AXIL_DATA_WIDTH/8; i++) begin + config_status_reg[awaddr_index][8*i +: 8] <= + s_axil_wstrb_reg[i] ? s_axil_wdata_reg[8*i +: 8] + : config_status_reg[awaddr_index][8*i +: 8]; + end + + end else begin + config_status_reg <= config_status_reg; + + // Pulse-clear: start and stop are one-cycle strobes + if (ctrl_start) config_status_reg[CDMA_CTRL_IDX][0] <= 1'b0; + if (ctrl_stop) config_status_reg[CDMA_CTRL_IDX][1] <= 1'b0; + + // STATUS[0]: cleared when a new transfer starts; set sticky on done + if (ctrl_start) config_status_reg[STATUS_IDX][0] <= 1'b0; + if (ctrl_done) config_status_reg[STATUS_IDX][0] <= 1'b1; + end +end + +// ------------------------------------------------------------------------- +// Read data mux +// ------------------------------------------------------------------------- +always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) + s_axil_rdata <= '0; + else if (s_axil_read_ready && araddr_index < NUM_REGS) + s_axil_rdata <= config_status_reg[araddr_index]; +end + +assign s_axil_bresp = 2'b00; +assign s_axil_rresp = 2'b00; + +endmodule : snix_axi_cdma_csr diff --git a/rtl/ip/cdma/snix_axi_mm2mm.sv b/rtl/ip/cdma/snix_axi_mm2mm.sv new file mode 100644 index 0000000..4be1b3e --- /dev/null +++ b/rtl/ip/cdma/snix_axi_mm2mm.sv @@ -0,0 +1,455 @@ +module snix_axi_mm2mm #(parameter int ADDR_WIDTH = 32, + parameter int DATA_WIDTH = 64, + parameter int ID_WIDTH = 4, + parameter int USER_WIDTH = 1, + parameter int FIFO_DEPTH = 16) + (// Global signals + input logic clk, + input logic rst_n, + + // Control interface + input logic ctrl_start, + input logic ctrl_stop, + input logic [ADDR_WIDTH-1:0] ctrl_src_addr, + input logic [ADDR_WIDTH-1:0] ctrl_dst_addr, + input logic [7:0] ctrl_len, + input logic [2:0] ctrl_size, + input logic [31:0] ctrl_transfer_len, + output logic ctrl_done, + + // AW Channel + output logic [ID_WIDTH-1:0] mm2mm_awid, + output logic [ADDR_WIDTH-1:0] mm2mm_awaddr, + output logic [7:0] mm2mm_awlen, + output logic [2:0] mm2mm_awsize, + output logic [1:0] mm2mm_awburst, + output logic mm2mm_awlock, + output logic [3:0] mm2mm_awcache, + output logic [2:0] mm2mm_awprot, + output logic [3:0] mm2mm_awqos, + output logic [USER_WIDTH-1:0] mm2mm_awuser, + output logic mm2mm_awvalid, + input logic mm2mm_awready, + + // W Channel + output logic [DATA_WIDTH-1:0] mm2mm_wdata, + output logic [DATA_WIDTH/8-1:0] mm2mm_wstrb, + output logic mm2mm_wlast, + output logic [USER_WIDTH-1:0] mm2mm_wuser, + output logic mm2mm_wvalid, + input logic mm2mm_wready, + + // B Channel + input logic [ID_WIDTH-1:0] mm2mm_bid, + input logic [1:0] mm2mm_bresp, + input logic [USER_WIDTH-1:0] mm2mm_buser, + input logic mm2mm_bvalid, + output logic mm2mm_bready, + + // AR Channel + output logic [ID_WIDTH-1:0] mm2mm_arid, + output logic [ADDR_WIDTH-1:0] mm2mm_araddr, + output logic [7:0] mm2mm_arlen, + output logic [2:0] mm2mm_arsize, + output logic [1:0] mm2mm_arburst, + output logic mm2mm_arlock, + output logic [3:0] mm2mm_arcache, + output logic [2:0] mm2mm_arprot, + output logic [3:0] mm2mm_arqos, + output logic [USER_WIDTH-1:0] mm2mm_aruser, + output logic mm2mm_arvalid, + input logic mm2mm_arready, + + // R Channel + input logic [ID_WIDTH-1:0] mm2mm_rid, + input logic [DATA_WIDTH-1:0] mm2mm_rdata, + input logic [1:0] mm2mm_rresp, + input logic mm2mm_rlast, + input logic [USER_WIDTH-1:0] mm2mm_ruser, + input logic mm2mm_rvalid, + output logic mm2mm_rready + ); + + // ------------------------------------------------------------------------- + // Local parameters + // ------------------------------------------------------------------------- + localparam int STRB_WIDTH = DATA_WIDTH / 8; + localparam int STRB_IDX_WIDTH = $clog2(STRB_WIDTH) + 1; // +1 to hold full-width value + + // ------------------------------------------------------------------------- + // Start / stop edge detection + // ------------------------------------------------------------------------- + logic ctrl_start_r, wr_start_edge; + logic ctrl_stop_r, wr_stop_edge; + + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) begin + ctrl_start_r <= 1'b0; + ctrl_stop_r <= 1'b0; + end else begin + ctrl_start_r <= ctrl_start; + ctrl_stop_r <= ctrl_stop; + end + + assign wr_start_edge = ctrl_start & ~ctrl_start_r; + assign wr_stop_edge = ctrl_stop & ~ctrl_stop_r; + + // ------------------------------------------------------------------------- + // Abort latch — set on stop edge, cleared on start edge + // ------------------------------------------------------------------------- + logic wr_abort; + + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) wr_abort <= 1'b0; + else if (wr_stop_edge) wr_abort <= 1'b1; + else if (wr_start_edge) wr_abort <= 1'b0; + + // ------------------------------------------------------------------------- + // FSM + // ------------------------------------------------------------------------- + typedef enum logic [2:0] {IDLE, PREP1, PREP2, AR, READ, AW, WRITE, WAIT_BRESP} state_t; + state_t state, next_state; + + logic transfer_done; + + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) state <= IDLE; + else state <= next_state; + + always_comb begin + next_state = state; // default holds state; prevents latches + case (state) + IDLE: begin + next_state = (ctrl_start && !wr_abort) ? PREP1 : IDLE; + end + PREP1: begin + next_state = wr_abort ? IDLE : PREP2; + end + PREP2: begin + next_state = AR; + end + AR: begin + if (wr_abort) + next_state = IDLE; + else + next_state = (mm2mm_arvalid && mm2mm_arready) ? READ : AR; + end + READ: begin + next_state = (mm2mm_rvalid && mm2mm_rready && mm2mm_rlast) ? AW : READ; + end + AW: begin + if (wr_abort) + next_state = IDLE; + else + next_state = (mm2mm_awvalid && mm2mm_awready) ? WRITE : AW; + end + WRITE: begin + next_state = (mm2mm_wvalid && mm2mm_wready && mm2mm_wlast) ? WAIT_BRESP : WRITE; + end + WAIT_BRESP: begin + if (mm2mm_bvalid && mm2mm_bready) begin + if (wr_abort || transfer_done) + next_state = IDLE; + else + next_state = PREP1; + end + end + default: ; + endcase + end + + // ------------------------------------------------------------------------- + // 4K boundary & burst-length computation — pipelined across PREP1 / PREP2 + // + // Identical two-stage pipeline to s2mm / mm2s. The src address is used + // for the 4K check; burst_actual_bytes is applied to both pointers so + // they stay in lock-step. + // + // PREP1 [Stage 1]: max_len, next_size, src_axi_addr (all regs) + // → next_bytes → cross_4k → bytes_to_4k + // → register bytes_to_4k_r + // + // PREP2 [Stage 2]: bytes_to_4k_r, pending_bytes, next_size (all regs) + // → num_bytes_comb → next_len_o + // → register next_arlen / next_awlen | burst_actual_bytes + // ------------------------------------------------------------------------- + logic [7:0] max_len; + logic [2:0] next_size; + logic [ADDR_WIDTH-1:0] src_axi_addr; + logic [ADDR_WIDTH-1:0] dst_axi_addr; + logic [31:0] pending_bytes; + + // Stage 1 wires + logic [14:0] next_bytes; + logic cross_4k; + logic [14:0] bytes_to_4k; + // Stage 1 → Stage 2 pipeline register + logic [14:0] bytes_to_4k_r; + // Stage 2 wires + logic [14:0] num_bytes_comb; + logic [7:0] next_len_o; + + // Stage 1 combinatorial + assign next_bytes = compute_num_bytes(max_len, next_size); + assign cross_4k = ({1'b0, next_bytes} + {4'b0, src_axi_addr[11:0]}) >= 16'd4096; + assign bytes_to_4k = cross_4k ? (15'd4096 - {3'b0, src_axi_addr[11:0]}) : next_bytes; + + // Stage 2 combinatorial + assign num_bytes_comb = ({{17{1'b0}}, bytes_to_4k_r} <= pending_bytes) + ? bytes_to_4k_r + : pending_bytes[14:0]; + assign next_len_o = compute_next_len(num_bytes_comb, next_size); + + // ------------------------------------------------------------------------- + // Transfer-state registers + // ------------------------------------------------------------------------- + logic [31:0] transfer_len; + logic [31:0] copied_bytes; + logic [7:0] next_arlen; + logic [7:0] next_awlen; + logic [14:0] burst_actual_bytes; + + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) begin + src_axi_addr <= '0; + dst_axi_addr <= '0; + next_arlen <= '0; + next_awlen <= '0; + max_len <= '0; + next_size <= '0; + copied_bytes <= '0; + transfer_len <= '0; + bytes_to_4k_r <= '0; + burst_actual_bytes <= '0; + end else if (wr_start_edge) begin + src_axi_addr <= ctrl_src_addr; + dst_axi_addr <= ctrl_dst_addr; + next_arlen <= ctrl_len; + next_awlen <= ctrl_len; + max_len <= ctrl_len; + next_size <= ctrl_size; + copied_bytes <= '0; + transfer_len <= ctrl_transfer_len; + burst_actual_bytes <= '0; + end else if (state == PREP1) begin + bytes_to_4k_r <= bytes_to_4k; + end else if (state == PREP2) begin + next_arlen <= next_len_o; + next_awlen <= next_len_o; + burst_actual_bytes <= num_bytes_comb; + end else if (state == AR && mm2mm_arready) begin + src_axi_addr <= src_axi_addr + {{(ADDR_WIDTH-15){1'b0}}, burst_actual_bytes}; + end else if (state == AW && mm2mm_awready) begin + dst_axi_addr <= dst_axi_addr + {{(ADDR_WIDTH-15){1'b0}}, burst_actual_bytes}; + copied_bytes <= copied_bytes + {17'b0, burst_actual_bytes}; + end + + // pending_bytes — decremented in AR state after burst_actual_bytes is registered. + // TIMING FIX: reg(burst_actual_bytes) → subtractor → reg(pending_bytes) + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) + pending_bytes <= '0; + else if (wr_start_edge) + pending_bytes <= ctrl_transfer_len; + else if (state == AR && mm2mm_arready) + pending_bytes <= pending_bytes - {17'b0, burst_actual_bytes}; + + // ------------------------------------------------------------------------- + // Transfer-done flag + // ------------------------------------------------------------------------- + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) + transfer_done <= 1'b0; + else if (wr_start_edge || state == IDLE || state == AR || + state == PREP1 || state == PREP2) + transfer_done <= 1'b0; + else + transfer_done <= (copied_bytes == transfer_len) && (copied_bytes != '0); + + // ------------------------------------------------------------------------- + // ctrl_done — single-cycle pulse when FSM transitions into IDLE + // ------------------------------------------------------------------------- + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) ctrl_done <= 1'b0; + else ctrl_done <= (next_state == IDLE) && (state != IDLE); + + // ------------------------------------------------------------------------- + // Beat counter — drives wlast + // ------------------------------------------------------------------------- + logic [7:0] beat_cnt; + + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) + beat_cnt <= '0; + else if (state == AW && mm2mm_awready) + beat_cnt <= '0; + else if (mm2mm_wvalid && mm2mm_wready) + beat_cnt <= beat_cnt + 1'b1; + + // ------------------------------------------------------------------------- + // Write strobe generation for partial last beat + // + // partial_strb_mask uses a per-bit comparator loop rather than a hardcoded + // case statement, making it correct for any DATA_WIDTH (including 1024-bit). + // Synthesises as a parallel comparator tree with no barrel shifter. + // ------------------------------------------------------------------------- + logic [14:0] bytes_in_burst; + logic [STRB_WIDTH-1:0] wstrb_mask; + logic [STRB_IDX_WIDTH-1:0] valid_bytes; + + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) + bytes_in_burst <= '0; + else if (state == AW && mm2mm_awready) + bytes_in_burst <= burst_actual_bytes; + else if (mm2mm_wvalid && mm2mm_wready) + bytes_in_burst <= (bytes_in_burst > STRB_WIDTH[14:0]) + ? (bytes_in_burst - STRB_WIDTH[14:0]) + : '0; + + assign valid_bytes = (bytes_in_burst <= STRB_WIDTH[14:0]) + ? bytes_in_burst[STRB_IDX_WIDTH-1:0] + : STRB_WIDTH[STRB_IDX_WIDTH-1:0]; + + logic [STRB_WIDTH-1:0] partial_strb_mask; + + always_comb begin + for (int i = 0; i < STRB_WIDTH; i++) + partial_strb_mask[i] = (i < valid_bytes); + end + + always_comb begin + if (mm2mm_wlast && (bytes_in_burst < STRB_WIDTH[14:0]) && (bytes_in_burst != '0)) + wstrb_mask = partial_strb_mask; + else if (bytes_in_burst == '0) + wstrb_mask = '0; + else + wstrb_mask = {STRB_WIDTH{1'b1}}; + end + + // ------------------------------------------------------------------------- + // FIFO — bridges R channel (read path) to W channel (write path) + // + // R-channel data is accepted only in READ state to prevent beats arriving + // before READ is entered from being silently dropped (same fix as mm2s). + // The write side drains only in WRITE state for symmetric gating. + // ------------------------------------------------------------------------- + logic [DATA_WIDTH-1:0] fifo_tdata; + logic fifo_tvalid; + logic fifo_tlast; + logic fifo_tuser; + logic fifo_s_tready; + + assign mm2mm_rready = fifo_s_tready && (state == READ); + + snix_axis_fifo #( + .DATA_WIDTH(DATA_WIDTH), + .FIFO_DEPTH(FIFO_DEPTH) + ) axis_fifo_u0 ( + .clk (clk), + .rst_n (rst_n), + .s_axis_tdata (mm2mm_rdata), + .s_axis_tlast (mm2mm_rlast), + .s_axis_tuser (1'b0), + .s_axis_tvalid (mm2mm_rvalid && (state == READ)), + .s_axis_tready (fifo_s_tready), + .m_axis_tdata (fifo_tdata), + .m_axis_tlast (fifo_tlast), + .m_axis_tuser (fifo_tuser), + .m_axis_tvalid (fifo_tvalid), + .m_axis_tready (mm2mm_wready && (state == WRITE)) + ); + + // ------------------------------------------------------------------------- + // AXI output assignments — AR channel + // ------------------------------------------------------------------------- + assign mm2mm_arvalid = (state == AR); + assign mm2mm_araddr = src_axi_addr; + assign mm2mm_arlen = next_arlen; + assign mm2mm_arsize = next_size; + assign mm2mm_arburst = 2'b01; + assign mm2mm_arlock = 1'b0; + assign mm2mm_arcache = 4'b0; + assign mm2mm_arprot = 3'b0; + assign mm2mm_arqos = 4'b0; + assign mm2mm_arid = '0; + assign mm2mm_aruser = '0; + + // ------------------------------------------------------------------------- + // AXI output assignments — AW channel + // ------------------------------------------------------------------------- + assign mm2mm_awvalid = (state == AW); + assign mm2mm_awaddr = dst_axi_addr; + assign mm2mm_awlen = next_awlen; + assign mm2mm_awsize = next_size; + assign mm2mm_awburst = 2'b01; + assign mm2mm_awlock = 1'b0; + assign mm2mm_awcache = 4'b0; + assign mm2mm_awprot = 3'b0; + assign mm2mm_awqos = 4'b0; + assign mm2mm_awid = '0; + assign mm2mm_awuser = '0; + + // ------------------------------------------------------------------------- + // AXI output assignments — W channel + // ------------------------------------------------------------------------- + generate + for (genvar i = 0; i < STRB_WIDTH; i++) begin : gen_wdata_mask + assign mm2mm_wdata[i*8 +: 8] = wstrb_mask[i] ? fifo_tdata[i*8 +: 8] : 8'h00; + end + endgenerate + + assign mm2mm_wvalid = (state == WRITE) && fifo_tvalid; + assign mm2mm_wlast = (beat_cnt == next_awlen) && mm2mm_wvalid; + assign mm2mm_wstrb = wstrb_mask; + assign mm2mm_wuser = '0; + + // ------------------------------------------------------------------------- + // AXI output assignments — B channel + // ------------------------------------------------------------------------- + assign mm2mm_bready = (state == WAIT_BRESP); + + // ------------------------------------------------------------------------- + // Functions (identical to s2mm / mm2s) + // ------------------------------------------------------------------------- + + // Returns total byte count for an AXI burst: (len+1) << size. + function automatic [14:0] compute_num_bytes( + input logic [7:0] len, + input logic [2:0] size + ); + case (size) + 3'b000: compute_num_bytes = {7'b0, len + 1'b1}; + 3'b001: compute_num_bytes = {6'b0, len + 1'b1, 1'b0}; + 3'b010: compute_num_bytes = {5'b0, len + 1'b1, 2'b0}; + 3'b011: compute_num_bytes = {4'b0, len + 1'b1, 3'b0}; + 3'b100: compute_num_bytes = {3'b0, len + 1'b1, 4'b0}; + 3'b101: compute_num_bytes = {2'b0, len + 1'b1, 5'b0}; + 3'b110: compute_num_bytes = {1'b0, len + 1'b1, 6'b0}; + 3'b111: compute_num_bytes = { len + 1'b1, 7'b0}; + endcase + endfunction + + // Returns arlen/awlen = ceil(bytes / beat_size) - 1. + function automatic [7:0] compute_next_len( + input logic [14:0] bytes_i, + input logic [2:0] size + ); + logic [14:0] num_beats; + case (size) + 3'b000: num_beats = bytes_i; + 3'b001: num_beats = (bytes_i + 15'd1) >> 1; + 3'b010: num_beats = (bytes_i + 15'd3) >> 2; + 3'b011: num_beats = (bytes_i + 15'd7) >> 3; + 3'b100: num_beats = (bytes_i + 15'd15) >> 4; + 3'b101: num_beats = (bytes_i + 15'd31) >> 5; + 3'b110: num_beats = (bytes_i + 15'd63) >> 6; + 3'b111: num_beats = (bytes_i + 15'd127) >> 7; + endcase + if (num_beats == 15'd0) + compute_next_len = 8'd0; + else + compute_next_len = num_beats[7:0] - 8'd1; + endfunction + +endmodule : snix_axi_mm2mm diff --git a/rtl/ip/cdma/snix_axil_cdma_mux.sv b/rtl/ip/cdma/snix_axil_cdma_mux.sv new file mode 100644 index 0000000..ba82421 --- /dev/null +++ b/rtl/ip/cdma/snix_axil_cdma_mux.sv @@ -0,0 +1,381 @@ +// ============================================================================ +// snix_axil_cdma_mux.sv +// Multi-Channel AXI-Lite MUX Wrapper for snix_axi_mm2mm engine +// +// Register Map (per channel, offset 0x40): +// 0x00: READ_ADDR (Source Address) +// 0x04: WRITE_ADDR (Destination Address) +// 0x08: LENGTH (Transfer length in bytes) +// 0x0C: TAG (User tag, purely for software tracking) +// 0x10: CTRL (Write 1 to bit 0 to trigger) +// [5:3] = AXI AxSIZE (0=1B, 1=2B, 2=4B, 3=8B...) +// [13:6] = AXI AxLEN (0=1 beat, 15=16 beats...) +// 0x14: STATUS (Bit 0: Busy RO, Bit 1: Done W1C) +// ============================================================================ +`timescale 1ns / 1ps + +module snix_axil_cdma_mux #( + parameter int ADDR_WIDTH = 32, + parameter int DATA_WIDTH = 32, // Matches engine default + parameter int AXIL_ADDR_WIDTH = 32, + parameter int AXIL_DATA_WIDTH = 32, + parameter int ID_WIDTH = 4, + parameter int USER_WIDTH = 1, + parameter int PORTS = 8, + parameter int FIFO_DEPTH = 16 +) ( + input logic clk, + input logic rst_n, + + // ========================================== + // AXI-Lite Slave Interface (CPU CSR Access) + // ========================================== + input logic [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr, + input logic s_axil_awvalid, + output logic s_axil_awready, + input logic [AXIL_DATA_WIDTH-1:0] s_axil_wdata, + input logic [AXIL_DATA_WIDTH/8-1:0] s_axil_wstrb, + input logic s_axil_wvalid, + output logic s_axil_wready, + output logic [1:0] s_axil_bresp, + output logic s_axil_bvalid, + input logic s_axil_bready, + input logic [AXIL_ADDR_WIDTH-1:0] s_axil_araddr, + input logic s_axil_arvalid, + output logic s_axil_arready, + output logic [AXIL_DATA_WIDTH-1:0] s_axil_rdata, + output logic [1:0] s_axil_rresp, + output logic s_axil_rvalid, + input logic s_axil_rready, + + // ========================================== + // AXI4 Master Interface (To Crossbar/Memory) + // ========================================== + output logic [ID_WIDTH-1:0] mm2mm_awid, + output logic [ADDR_WIDTH-1:0] mm2mm_awaddr, + output logic [7:0] mm2mm_awlen, + output logic [2:0] mm2mm_awsize, + output logic [1:0] mm2mm_awburst, + output logic mm2mm_awlock, + output logic [3:0] mm2mm_awcache, + output logic [2:0] mm2mm_awprot, + output logic [3:0] mm2mm_awqos, + output logic [USER_WIDTH-1:0] mm2mm_awuser, + output logic mm2mm_awvalid, + input logic mm2mm_awready, + output logic [DATA_WIDTH-1:0] mm2mm_wdata, + output logic [DATA_WIDTH/8-1:0] mm2mm_wstrb, + output logic mm2mm_wlast, + output logic [USER_WIDTH-1:0] mm2mm_wuser, + output logic mm2mm_wvalid, + input logic mm2mm_wready, + input logic [ID_WIDTH-1:0] mm2mm_bid, + input logic [1:0] mm2mm_bresp, + input logic [USER_WIDTH-1:0] mm2mm_buser, + input logic mm2mm_bvalid, + output logic mm2mm_bready, + output logic [ID_WIDTH-1:0] mm2mm_arid, + output logic [ADDR_WIDTH-1:0] mm2mm_araddr, + output logic [7:0] mm2mm_arlen, + output logic [2:0] mm2mm_arsize, + output logic [1:0] mm2mm_arburst, + output logic mm2mm_arlock, + output logic [3:0] mm2mm_arcache, + output logic [2:0] mm2mm_arprot, + output logic [3:0] mm2mm_arqos, + output logic [USER_WIDTH-1:0] mm2mm_aruser, + output logic mm2mm_arvalid, + input logic mm2mm_arready, + input logic [ID_WIDTH-1:0] mm2mm_rid, + input logic [DATA_WIDTH-1:0] mm2mm_rdata, + input logic [1:0] mm2mm_rresp, + input logic mm2mm_rlast, + input logic [USER_WIDTH-1:0] mm2mm_ruser, + input logic mm2mm_rvalid, + output logic mm2mm_rready, + + // Global Interrupt (OR'd from all channels) + output logic dma_finish +); + + // ========================================== + // Local Parameters & Utilities + // ========================================== + localparam int CH_BITS = $clog2(PORTS); + + // Function to safely apply WSTRB to 32-bit registers + function automatic logic [31:0] apply_wstrb( + input logic [31:0] old_val, + input logic [31:0] new_val, + input logic [3:0] wstrb + ); + logic [31:0] res; + res[7:0] = wstrb[0] ? new_val[7:0] : old_val[7:0]; + res[15:8] = wstrb[1] ? new_val[15:8] : old_val[15:8]; + res[23:16] = wstrb[2] ? new_val[23:16] : old_val[23:16]; + res[31:24] = wstrb[3] ? new_val[31:24] : old_val[31:24]; + return res; + endfunction + + // ========================================== + // Internal Registers (Per Channel) + // ========================================== + logic [ADDR_WIDTH-1:0] ch_src_addr [PORTS]; + logic [ADDR_WIDTH-1:0] ch_dst_addr [PORTS]; + logic [31:0] ch_len [PORTS]; + logic [31:0] ch_tag [PORTS]; + logic [31:0] ch_ctrl [PORTS]; + + logic [PORTS-1:0] ch_req; // Pending requests (Busy) + logic [PORTS-1:0] ch_done; // Completion flags + + logic [PORTS-1:0] arb_set_done; // From Arbiter to CSR + + // ========================================== + // Address Decoding (0x40 offset per channel) + // ========================================== + wire [CH_BITS-1:0] wr_ch = s_axil_awaddr[6 +: CH_BITS]; + wire [5:0] wr_reg = s_axil_awaddr[5:0]; + wire [CH_BITS-1:0] rd_ch = s_axil_araddr[6 +: CH_BITS]; + wire [5:0] rd_reg = s_axil_araddr[5:0]; + + // ========================================== + // AXI-Lite Slave Logic (Robust Backpressure) + // ========================================== + assign s_axil_bresp = 2'b00; + assign s_axil_rresp = 2'b00; + + // Write Path Handshake + always_ff @(posedge clk) begin + if (!rst_n) begin + s_axil_awready <= 1'b0; + s_axil_wready <= 1'b0; + end else begin + if (s_axil_awvalid && s_axil_wvalid && !s_axil_awready && (!s_axil_bvalid || s_axil_bready)) begin + s_axil_awready <= 1'b1; + s_axil_wready <= 1'b1; + end else begin + s_axil_awready <= 1'b0; + s_axil_wready <= 1'b0; + end + end + end + + wire do_write = s_axil_awready && s_axil_awvalid && s_axil_wready && s_axil_wvalid; + + always_ff @(posedge clk) begin + if (!rst_n) begin + s_axil_bvalid <= 1'b0; + end else begin + if (do_write) begin + s_axil_bvalid <= 1'b1; + end else if (s_axil_bready && s_axil_bvalid) begin + s_axil_bvalid <= 1'b0; + end + end + end + + // Read Path Handshake + always_ff @(posedge clk) begin + if (!rst_n) begin + s_axil_arready <= 1'b0; + end else begin + if (s_axil_arvalid && !s_axil_arready && (!s_axil_rvalid || s_axil_rready)) begin + s_axil_arready <= 1'b1; + end else begin + s_axil_arready <= 1'b0; + end + end + end + + wire do_read = s_axil_arready && s_axil_arvalid; + + always_ff @(posedge clk) begin + if (!rst_n) begin + s_axil_rvalid <= 1'b0; + s_axil_rdata <= '0; + end else begin + if (do_read) begin + s_axil_rvalid <= 1'b1; + if (rd_ch < PORTS) begin + case (rd_reg) + 6'h00: s_axil_rdata <= ch_src_addr[rd_ch]; + 6'h04: s_axil_rdata <= ch_dst_addr[rd_ch]; + 6'h08: s_axil_rdata <= ch_len[rd_ch]; + 6'h0C: s_axil_rdata <= ch_tag[rd_ch]; + 6'h10: s_axil_rdata <= ch_ctrl[rd_ch]; + 6'h14: s_axil_rdata <= {30'd0, ch_done[rd_ch], ch_req[rd_ch]}; + default: s_axil_rdata <= 32'd0; + endcase + end else begin + s_axil_rdata <= 32'd0; // Out of bounds + end + end else if (s_axil_rready && s_axil_rvalid) begin + s_axil_rvalid <= 1'b0; + end + end + end + + // ========================================== + // Register File Write Logic + // ========================================== + assign dma_finish = |ch_done; + + always_ff @(posedge clk) begin + if (!rst_n) begin + ch_req <= '0; + ch_done <= '0; + for (int i=0; i= PORTS) ? (check_ch_ext - PORTS) : check_ch_ext[CH_BITS-1:0]; + + if (ch_req[check_ch] && !arb_set_done[check_ch]) begin + cur_ch <= check_ch; + rr_ptr <= (check_ch == (PORTS - 1)) ? '0 : (check_ch + 1); + engine_start <= 1'b1; + state <= RUN; + break; + end + end + end + + RUN: begin + if (engine_done) begin + arb_set_done[cur_ch] <= 1'b1; + state <= IDLE; + end + // Optional: Add a watchdog timeout counter here if dealing with untrusted PCIe/AXI endpoints + end + endcase + end + end + + // ========================================== + // Instantiate The Original Core Engine + // ========================================== + snix_axi_mm2mm #( + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH (ID_WIDTH), + .USER_WIDTH(USER_WIDTH), + .FIFO_DEPTH(FIFO_DEPTH) + ) u_core_engine ( + .clk (clk), + .rst_n (rst_n), + .ctrl_start (engine_start), + .ctrl_stop (1'b0), // Tied off; can be wired if global abort is needed + .ctrl_src_addr (engine_src), + .ctrl_dst_addr (engine_dst), + .ctrl_len (engine_len), + .ctrl_size (engine_size), + .ctrl_transfer_len (engine_bytes), + .ctrl_done (engine_done), + // AXI4 Port Connections + .mm2mm_awid (mm2mm_awid), .mm2mm_awaddr (mm2mm_awaddr), + .mm2mm_awlen (mm2mm_awlen), .mm2mm_awsize (mm2mm_awsize), + .mm2mm_awburst(mm2mm_awburst),.mm2mm_awlock (mm2mm_awlock), + .mm2mm_awcache(mm2mm_awcache),.mm2mm_awprot (mm2mm_awprot), + .mm2mm_awqos (mm2mm_awqos), .mm2mm_awuser (mm2mm_awuser), + .mm2mm_awvalid(mm2mm_awvalid),.mm2mm_awready(mm2mm_awready), + .mm2mm_wdata (mm2mm_wdata), .mm2mm_wstrb (mm2mm_wstrb), + .mm2mm_wlast (mm2mm_wlast), .mm2mm_wuser (mm2mm_wuser), + .mm2mm_wvalid (mm2mm_wvalid), .mm2mm_wready (mm2mm_wready), + .mm2mm_bid (mm2mm_bid), .mm2mm_bresp (mm2mm_bresp), + .mm2mm_buser (mm2mm_buser), .mm2mm_bvalid (mm2mm_bvalid), + .mm2mm_bready (mm2mm_bready), + .mm2mm_arid (mm2mm_arid), .mm2mm_araddr (mm2mm_araddr), + .mm2mm_arlen (mm2mm_arlen), .mm2mm_arsize (mm2mm_arsize), + .mm2mm_arburst(mm2mm_arburst),.mm2mm_arlock (mm2mm_arlock), + .mm2mm_arcache(mm2mm_arcache),.mm2mm_arprot (mm2mm_arprot), + .mm2mm_arqos (mm2mm_arqos), .mm2mm_aruser (mm2mm_aruser), + .mm2mm_arvalid(mm2mm_arvalid),.mm2mm_arready(mm2mm_arready), + .mm2mm_rid (mm2mm_rid), .mm2mm_rdata (mm2mm_rdata), + .mm2mm_rresp (mm2mm_rresp), .mm2mm_rlast (mm2mm_rlast), + .mm2mm_ruser (mm2mm_ruser), .mm2mm_rvalid (mm2mm_rvalid), + .mm2mm_rready (mm2mm_rready) + ); + +endmodule \ No newline at end of file diff --git a/rtl/ip/cdma/snix_axis_fifo.sv b/rtl/ip/cdma/snix_axis_fifo.sv new file mode 100644 index 0000000..ba6d824 --- /dev/null +++ b/rtl/ip/cdma/snix_axis_fifo.sv @@ -0,0 +1,113 @@ +// ============================================================================ +// snix_axis_fifo.sv +// +// AXI4-Stream FIFO with two operating modes selected by FRAME_FIFO: +// +// FRAME_FIFO = 0 (default) — streaming / cut-through +// Output valid asserts as soon as any data enters the FIFO. +// Downstream can begin reading before the full packet arrives. +// +// FRAME_FIFO = 1 — store-and-forward +// Output valid is suppressed until the complete packet (through tlast) +// has been written into the FIFO. Guarantees the downstream never +// sees a stalled mid-packet transfer. +// ============================================================================ +module snix_axis_fifo #( + parameter int DATA_WIDTH = 32, + parameter int USER_WIDTH = 1, + parameter int FIFO_DEPTH = 16, + parameter bit FRAME_FIFO = 0 // 0 = streaming, 1 = store-and-forward +) ( + input logic clk, + input logic rst_n, + + // AXI4-Stream slave (input) + input logic [DATA_WIDTH-1:0] s_axis_tdata, + input logic [USER_WIDTH-1:0] s_axis_tuser, + input logic s_axis_tvalid, + input logic s_axis_tlast, + output logic s_axis_tready, + + // AXI4-Stream master (output) + output logic [DATA_WIDTH-1:0] m_axis_tdata, + output logic [USER_WIDTH-1:0] m_axis_tuser, + output logic m_axis_tvalid, + output logic m_axis_tlast, + input logic m_axis_tready +); + + localparam int AWIDTH = $clog2(FIFO_DEPTH); + + // Internal FIFO signals + logic [DATA_WIDTH-1:0] fifo_tdata; + logic [USER_WIDTH-1:0] fifo_tuser; + logic fifo_tlast; + logic wr_en, rd_en; + logic fifo_full, fifo_empty; + logic [AWIDTH:0] fill_cnt; + + // Handshake strobes + assign s_axis_tready = ~fifo_full; + assign wr_en = s_axis_tvalid & s_axis_tready; + assign rd_en = m_axis_tvalid & m_axis_tready; + + // Output mapping + assign m_axis_tdata = fifo_tdata; + assign m_axis_tuser = fifo_tuser; + assign m_axis_tlast = fifo_tlast; + + // ------------------------------------------------------------------------- + // Output valid generation + // + // FRAME_FIFO = 1 : store-and-forward FSM + // IDLE -> STREAM when tlast is written into the FIFO + // STREAM -> IDLE when tlast is read out of the FIFO + // + // FRAME_FIFO = 0 : cut-through, valid tracks fifo_empty directly + // ------------------------------------------------------------------------- + generate + if (FRAME_FIFO) begin : gen_frame_mode + + typedef enum logic { IDLE, STREAM } state_t; + state_t state, nxt; + + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) state <= IDLE; + else state <= nxt; + + always_comb begin + nxt = state; + case (state) + IDLE: if (wr_en && s_axis_tlast) nxt = STREAM; + STREAM: if (rd_en && fifo_tlast) nxt = IDLE; + endcase + end + + assign m_axis_tvalid = ~fifo_empty & (state == STREAM); + + end else begin : gen_stream_mode + + assign m_axis_tvalid = ~fifo_empty; + + end + endgenerate + + // ------------------------------------------------------------------------- + // Sync FIFO instance — packs {tdata, tuser, tlast} into one word + // ------------------------------------------------------------------------- + snix_sync_fifo #( + .DATA_WIDTH (DATA_WIDTH + USER_WIDTH + 1), + .FIFO_DEPTH (FIFO_DEPTH) + ) u_fifo ( + .clk (clk), + .rst_n (rst_n), + .data_i ({s_axis_tdata, s_axis_tuser, s_axis_tlast}), + .wr_en (wr_en), + .rd_en (rd_en), + .data_o ({fifo_tdata, fifo_tuser, fifo_tlast}), + .fifo_full (fifo_full), + .fifo_empty (fifo_empty), + .fill_cnt (fill_cnt) + ); + +endmodule : snix_axis_fifo diff --git a/rtl/ip/cdma/snix_register_slice.sv b/rtl/ip/cdma/snix_register_slice.sv new file mode 100644 index 0000000..dedb4ad --- /dev/null +++ b/rtl/ip/cdma/snix_register_slice.sv @@ -0,0 +1,79 @@ +// ============================================================================ +// snix_register_slice.sv +// +// Generic ready/valid register slice (skid buffer). +// +// Same architecture as snix_axis_register but without tuser/tlast — +// used internally by the DMA and CDMA engines for pipeline decoupling +// on raw data paths. +// ============================================================================ +module snix_register_slice #( + parameter DATA_WIDTH = 32 +) ( + input logic clk, + input logic rst_n, + + // Input interface + input logic [DATA_WIDTH-1:0] s_axis_tdata, + input logic s_axis_tvalid, + output logic s_axis_tready, + + // Output interface + output logic [DATA_WIDTH-1:0] m_axis_tdata, + output logic m_axis_tvalid, + input logic m_axis_tready +); + + // Skid register + logic skid_valid; + logic [DATA_WIDTH-1:0] skid_data; + + wire s_hsk = s_axis_tvalid & s_axis_tready; + wire m_stall = m_axis_tvalid & ~m_axis_tready; + + // ----------------------------------------------------------------- + // Skid valid + // ----------------------------------------------------------------- + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) + skid_valid <= 1'b0; + else if (s_hsk & m_stall) + skid_valid <= 1'b1; + else if (m_axis_tready) + skid_valid <= 1'b0; + + // ----------------------------------------------------------------- + // Skid data + // ----------------------------------------------------------------- + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) + skid_data <= '0; + else if (s_hsk) + skid_data <= s_axis_tdata; + + // Ready when skid is empty + assign s_axis_tready = ~skid_valid; + + // ----------------------------------------------------------------- + // Output valid + // ----------------------------------------------------------------- + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) + m_axis_tvalid <= 1'b0; + else if (~m_axis_tvalid | m_axis_tready) + m_axis_tvalid <= s_axis_tvalid | skid_valid; + + // ----------------------------------------------------------------- + // Output data — skid has priority + // ----------------------------------------------------------------- + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) + m_axis_tdata <= '0; + else if (~m_axis_tvalid | m_axis_tready) begin + if (skid_valid) + m_axis_tdata <= skid_data; + else if (s_axis_tvalid) + m_axis_tdata <= s_axis_tdata; + end + +endmodule : snix_register_slice diff --git a/rtl/ip/cdma/snix_sync_fifo.sv b/rtl/ip/cdma/snix_sync_fifo.sv new file mode 100644 index 0000000..9a64927 --- /dev/null +++ b/rtl/ip/cdma/snix_sync_fifo.sv @@ -0,0 +1,130 @@ +// ============================================================================ +// snix_sync_fifo.sv +// +// Synchronous FIFO with first-word-fall-through (FWFT) bypass. +// +// Architecture: +// - Dual-pointer circular buffer with MSB wrap-bit for full detection +// - Write-through bypass path: when the FIFO is empty and a write arrives, +// data is forwarded directly to the output without a one-cycle read delay +// - Block-RAM inference hint for FPGA targets +// ============================================================================ +module snix_sync_fifo #( + parameter int DATA_WIDTH = 32, + parameter int FIFO_DEPTH = 16 +) ( + input logic clk, + input logic rst_n, + + // Write port + input logic [DATA_WIDTH-1:0] data_i, + input logic wr_en, + + // Read port + input logic rd_en, + output logic [DATA_WIDTH-1:0] data_o, + + // Status + output logic [$clog2(FIFO_DEPTH):0] fill_cnt, + output logic fifo_full, + output logic fifo_empty +); + + localparam int AWIDTH = $clog2(FIFO_DEPTH); + + // Storage + (* ram_style="block" *) + logic [DATA_WIDTH-1:0] mem [0:FIFO_DEPTH-1]; + + // Pointers — extra MSB for wrap-around detection + logic [AWIDTH:0] wptr, rptr; + + // Bypass (FWFT) path + logic [DATA_WIDTH-1:0] fwd_data; + logic fwd_valid; + + // Qualified strobes + wire do_wr = wr_en & ~fifo_full; + wire do_rd = rd_en & ~fifo_empty; + + // ----------------------------------------------------------------- + // Write pointer + // ----------------------------------------------------------------- + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) + wptr <= '0; + else if (do_wr) + wptr <= wptr + 1'b1; + + // ----------------------------------------------------------------- + // Read pointer + // ----------------------------------------------------------------- + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) + rptr <= '0; + else if (do_rd) + rptr <= rptr + 1'b1; + + // ----------------------------------------------------------------- + // Memory write + // ----------------------------------------------------------------- + always_ff @(posedge clk) + if (do_wr) + mem[wptr[AWIDTH-1:0]] <= data_i; + + // ----------------------------------------------------------------- + // Memory read — pre-fetch next location for FWFT + // ----------------------------------------------------------------- + logic [DATA_WIDTH-1:0] mem_rd; + + always_ff @(posedge clk) + if (do_rd) + mem_rd <= mem[rptr[AWIDTH-1:0] + 1'b1]; + + // ----------------------------------------------------------------- + // Fill counter and empty flag + // ----------------------------------------------------------------- + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) begin + fifo_empty <= 1'b1; + fill_cnt <= '0; + end else begin + case ({do_wr, do_rd}) + 2'b10: begin + fill_cnt <= fill_cnt + 1'b1; + fifo_empty <= 1'b0; + end + 2'b01: begin + fill_cnt <= fill_cnt - 1'b1; + fifo_empty <= (fill_cnt <= 1); + end + default: ; + endcase + end + + // Full flag — MSB of fill counter + assign fifo_full = fill_cnt[AWIDTH]; + + // ----------------------------------------------------------------- + // FWFT bypass — forward write data directly when FIFO is empty + // ----------------------------------------------------------------- + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) + fwd_valid <= 1'b0; + else if (fifo_empty || rd_en) begin + if (!wr_en) + fwd_valid <= 1'b0; + else if (fifo_empty || (rd_en && fill_cnt == 1)) + fwd_valid <= 1'b1; + else + fwd_valid <= 1'b0; + end + + always_ff @(posedge clk) + if (fifo_empty || rd_en) + fwd_data <= data_i; + + // Output mux — bypass path has priority + assign data_o = fwd_valid ? fwd_data : mem_rd; + +endmodule : snix_sync_fifo diff --git a/rtl/ip/confreg/confreg.v b/rtl/ip/confreg/confreg.v new file mode 100644 index 0000000..26ab8c0 --- /dev/null +++ b/rtl/ip/confreg/confreg.v @@ -0,0 +1,421 @@ +/*------------------------------------------------------------------------------ +-------------------------------------------------------------------------------- +Copyright (c) 2016, Loongson Technology Corporation Limited. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of Loongson Technology Corporation Limited nor the names of +its contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE +TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ +`define CONFREG_INT_ADDR 16'hf000 //1f20_f000 +`define TIMER_ADDR 16'hf100 //1f20_f100 +`define DIGITAL_ADDR 16'hf200 //1f20_f200 +`define LED_ADDR 16'hf300 //1f20_f300 +`define SWITCH_ADDR 16'hf400 //1f20_f400 +`define SIMU_FLAG_ADDR 16'hf500 //1f20_f500 + +module confreg #( + parameter SIMULATION=1'b0 +) +( + input aclk, + input aresetn, + + input cpu_clk, + input cpu_resetn, + + input [4 :0] s_awid, + input [31:0] s_awaddr, + input [7 :0] s_awlen, + input [2 :0] s_awsize, + input [1 :0] s_awburst, + input s_awlock, + input [3 :0] s_awcache, + input [2 :0] s_awprot, + input s_awvalid, + output s_awready, + input [4 :0] s_wid, + input [31:0] s_wdata, + input [3 :0] s_wstrb, + input s_wlast, + input s_wvalid, + output reg s_wready, + output [4 :0] s_bid, + output [1 :0] s_bresp, + output reg s_bvalid, + input s_bready, + input [4 :0] s_arid, + input [31:0] s_araddr, + input [7 :0] s_arlen, + input [2 :0] s_arsize, + input [1 :0] s_arburst, + input s_arlock, + input [3 :0] s_arcache, + input [2 :0] s_arprot, + input s_arvalid, + output s_arready, + output [4 :0] s_rid, + output reg [31:0] s_rdata, + output [1 :0] s_rresp, + output reg s_rlast, + output reg s_rvalid, + input s_rready, + + output [15:0] led, + output [7:0] dpy0, + output [7:0] dpy1, + input [31:0] switch, + input [3 :0] touch_btn, + + input uart0_int, + input dma_finish, + input fft_finish, + output confreg_int +); + +wire [3:0] touch_btn_data;//按键中断信号，上升沿触发 +reg [31:0] led_data; +wire [31:0] switch_data; +reg [31:0] simu_flag; + +reg [31:0] confreg_int_en,confreg_int_edge,confreg_int_pol,confreg_int_clr,confreg_int_set; +wire [31:0] confreg_int_state; + +reg [31:0] sys_timer,sys_timer_cmp; +reg sys_timer_en; +reg timer_int;//定时器中断信号，高电平触发 + +reg [31:0] digital_ctrl; +reg [31:0] digital_data; + + +reg busy,write,R_or_W; + +wire ar_enter = s_arvalid & s_arready; +wire r_retire = s_rvalid & s_rready & s_rlast; +wire aw_enter = s_awvalid & s_awready; +wire w_enter = s_wvalid & s_wready & s_wlast; +wire b_retire = s_bvalid & s_bready; + +assign s_arready = ~busy & (!R_or_W| !s_awvalid); +assign s_awready = ~busy & ( R_or_W| !s_arvalid); + +always@(posedge aclk) + if(~aresetn) busy <= 1'b0; + else if(ar_enter|aw_enter) busy <= 1'b1; + else if(r_retire|b_retire) busy <= 1'b0; + +reg [4 :0] buf_id; +reg [31:0] buf_addr; +reg [7 :0] buf_len; +reg [2 :0] buf_size; +reg [1 :0] buf_burst; +reg buf_lock; +reg [3 :0] buf_cache; +reg [2 :0] buf_prot; + +always@(posedge aclk) + if(~aresetn) begin + R_or_W <= 1'b0; + buf_id <= 'b0; + buf_addr <= 'b0; + buf_len <= 'b0; + buf_size <= 'b0; + buf_burst <= 'b0; + buf_lock <= 'b0; + buf_cache <= 'b0; + buf_prot <= 'b0; + end + else + if(ar_enter | aw_enter) begin + R_or_W <= ar_enter; + buf_id <= ar_enter ? s_arid : s_awid ; + buf_addr <= ar_enter ? s_araddr : s_awaddr ; + buf_len <= ar_enter ? s_arlen : s_awlen ; + buf_size <= ar_enter ? s_arsize : s_awsize ; + buf_burst <= ar_enter ? s_arburst: s_awburst; + buf_lock <= ar_enter ? s_arlock : s_awlock ; + buf_cache <= ar_enter ? s_arcache: s_awcache; + buf_prot <= ar_enter ? s_arprot : s_awprot ; + end + +always@(posedge aclk) + if(~aresetn) write <= 1'b0; + else if(aw_enter) write <= 1'b1; + else if(ar_enter) write <= 1'b0; + +always@(posedge aclk) + if(~aresetn) s_wready <= 1'b0; + else if(aw_enter) s_wready <= 1'b1; + else if(w_enter & s_wlast) s_wready <= 1'b0; + +wire [31:0] rdata_d = buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h0) ? confreg_int_en : + buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h4) ? confreg_int_edge : + buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h8) ? confreg_int_pol : + buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'hc) ? confreg_int_clr : + buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h10) ? confreg_int_set : + buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h14) ? confreg_int_state : + buf_addr[15:0] == (`TIMER_ADDR + 16'h0) ? sys_timer : + buf_addr[15:0] == (`TIMER_ADDR + 16'h4) ? sys_timer_cmp : + buf_addr[15:0] == (`TIMER_ADDR + 16'h8) ? sys_timer_en : + buf_addr[15:0] == (`DIGITAL_ADDR + 16'h0) ? digital_ctrl : + buf_addr[15:0] == (`DIGITAL_ADDR + 16'h4) ? digital_data : + buf_addr[15:0] == `LED_ADDR ? led_data : + buf_addr[15:0] == `SWITCH_ADDR ? switch_data : + buf_addr[15:0] == `SIMU_FLAG_ADDR ? simu_flag : + 32'd0; + +always@(posedge aclk) + if(~aresetn) begin + s_rdata <= 'b0; + s_rvalid <= 1'b0; + s_rlast <= 1'b0; + end + else if(busy & !write & !r_retire) + begin + s_rdata <= rdata_d; + s_rvalid <= 1'b1; + s_rlast <= 1'b1; + end + else if(r_retire) + begin + s_rvalid <= 1'b0; + end + +always@(posedge aclk) + if(~aresetn) s_bvalid <= 1'b0; + else if(w_enter) s_bvalid <= 1'b1; + else if(b_retire) s_bvalid <= 1'b0; + +assign s_rid = buf_id; +assign s_bid = buf_id; +assign s_bresp = 2'b0; +assign s_rresp = 2'b0; + + +//-------------------------------{touch_btn}begin----------------------------// +assign touch_btn_data = touch_btn; + + // genvar i; + // generate for(i=0;i<4;i=i+1) begin: generate_btn_debounce + // key_debounce u_key_debounce( + // .sys_clk(aclk), + // .key(touch_btn[i]), + // .key_out(touch_btn_data[i]) + // ); + // end + // endgenerate + + + + + +//--------------------------------{touch_btn}end-----------------------------// + +//-------------------------------{timer}begin----------------------------// + +wire write_timer_cmp = w_enter & (buf_addr[15:0]==`TIMER_ADDR+16'h4); +wire write_timer_en = w_enter & (buf_addr[15:0]==`TIMER_ADDR+16'h8); + +always @(posedge aclk) begin + if(!aresetn) begin + sys_timer_cmp <= 32'h0; + end + else if (write_timer_cmp) begin + sys_timer_cmp <= s_wdata; + end +end + +always @(posedge aclk) begin + if(!aresetn) begin + sys_timer_en <= 1'b0; + end + else if (write_timer_en) begin + sys_timer_en <= s_wdata[0]; + end +end + +always @(posedge aclk or negedge aresetn) begin + if (!aresetn) begin + sys_timer <= 32'h0; + timer_int <= 1'b0; + end + else if (sys_timer_en) begin + if (sys_timer >= sys_timer_cmp - 1) begin + sys_timer <= 32'h0; + timer_int <= 1'b1; + end else begin + sys_timer <= sys_timer + 1'b1; + end + end + else begin + sys_timer <= 32'h0; + timer_int <= 1'b0; + end +end +//--------------------------------{timer}end-----------------------------// + +//--------------------------------{led}begin-----------------------------// +//led display +//led_data[31:0] +wire write_led = w_enter & (buf_addr[15:0]==`LED_ADDR); +assign led = led_data[15:0]; +always @(posedge aclk) +begin + if(!aresetn) + begin + led_data <= 32'h0; + end + else if(write_led) + begin + led_data <= s_wdata[31:0]; + end +end +//---------------------------------{led}end------------------------------// + +//-------------------------------{switch}begin---------------------------// +//switch data +//switch_data[31:0] +assign switch_data = switch; +//--------------------------------{switch}end----------------------------// + + +//---------------------------{digital number}begin-----------------------// +wire write_digital_ctrl = w_enter & (buf_addr[15:0]==`DIGITAL_ADDR + 16'h0); +wire write_digital_data = w_enter & (buf_addr[15:0]==`DIGITAL_ADDR + 16'h4); + +always @(posedge aclk) begin + if(!aresetn) begin + digital_ctrl <= 32'd0; + end + else if (write_digital_ctrl) begin + digital_ctrl <= s_wdata; + end +end + +always @(posedge aclk) begin + if(!aresetn) begin + digital_data <= 32'd0; + end + else if (write_digital_data) begin + digital_data <= s_wdata; + end +end + +wire [31:0] digital_data_in = digital_data; +digitaltube_controller u_digitaltube_controller ( + .control_reg ( digital_ctrl ), + .clk ( aclk ), + .rst_n ( aresetn ), + + .dpy0 ( dpy0 ), + .dpy1 ( dpy1 ), + + .data_reg ( digital_data_in ) +); + +//----------------------------{digital number}end------------------------// + +//--------------------------{simulation flag}begin-----------------------// +always @(posedge aclk) +begin + if(!aresetn) begin + simu_flag <= {32{SIMULATION}}; + end + else begin + simu_flag <= {32{SIMULATION}}; + end +end +//---------------------------{simulation flag}end------------------------// + +//-------------------------------{int_ctrl}begin----------------------------// +//add your code +wire [31:0] int_in; +wire [31:0] int_out; + +wire write_int_en = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h0)); +wire write_int_edge = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h4)); +wire write_int_pol = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h8)); +wire write_int_clr = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'hc)); +wire write_int_set = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h10)); + +always @(posedge aclk) begin + if (!aresetn) begin + confreg_int_en <= 32'h0; + confreg_int_edge <= 32'h0; + confreg_int_pol <= 32'h0; + end else begin + if (write_int_en) confreg_int_en <= s_wdata; + if (write_int_edge) confreg_int_edge <= s_wdata; + if (write_int_pol) confreg_int_pol <= s_wdata; + end +end + +always @(posedge aclk) begin + if (!aresetn) begin + confreg_int_clr <= 32'h0; + confreg_int_set <= 32'h0; + end else begin + confreg_int_clr <= write_int_clr ? s_wdata : 32'h0; + confreg_int_set <= write_int_set ? s_wdata : 32'h0; + end +end + +assign int_in = {24'b0, dma_finish, fft_finish, uart0_int, timer_int, touch_btn_data}; + +int_ctrl u_int_ctrl ( + .clk (aclk), + .resetn (aresetn), + .int_en (confreg_int_en), + .int_edge (confreg_int_edge), + .int_pol (confreg_int_pol), + .int_in (int_in), + .int_clr (confreg_int_clr), + .int_set (confreg_int_set), + .int_out (int_out) +); + +assign confreg_int_state = int_out; + +// int_out 进行或操作，再经过延迟打拍处理 +reg int_out_or_q1; +reg int_out_or_q2; + +always @(posedge aclk) begin + if (!aresetn) begin + int_out_or_q1 <= 1'b0; + int_out_or_q2 <= 1'b0; + end else begin + int_out_or_q1 <= |int_out; + int_out_or_q2 <= int_out_or_q1; + end +end + +assign confreg_int = int_out_or_q2; + +//--------------------------------{int_ctrl}end-----------------------------// + +endmodule diff --git a/rtl/ip/confreg/digitaltube_controller.v b/rtl/ip/confreg/digitaltube_controller.v new file mode 100644 index 0000000..0cb1df3 --- /dev/null +++ b/rtl/ip/confreg/digitaltube_controller.v @@ -0,0 +1,101 @@ +module digitaltube_controller( + // üĴ Ĭ 32 λ + // [1:0] ұߵ 00 01ʾ 10ʾֺС + // [3:2] + input wire [31:0] control_reg, + + // ݼĴ [15:0] + // 0x0000_000X [3:0] ӦһƵʾ + // 0x0000_00X0 [7:4] ӦڶƵʾ + inout wire [31:0] data_reg, + + input wire clk, + input wire rst_n, + + output wire [7:0] dpy0, // dpy0 + output wire [7:0] dpy1 // dpy1 +); + + // ڲĴ + reg [7:0] dpy0_reg; + reg [7:0] dpy1_reg; + + assign dpy0 = dpy0_reg; + assign dpy1 = dpy1_reg; + + reg [3:0] dpy0_data; // dpy0 ʾݣ4 λ0-F + reg [3:0] dpy1_data; // dpy1 ʾݣ4 λ0-F + + // ܶ洢 + reg [6:0] seg_code [0:15]; // 洢 0-F ı + + // ʼܶ + always @(posedge clk or negedge rst_n) begin + if(!rst_n) begin + seg_code[0] <= 7'b1000000; // 0 + seg_code[1] <= 7'b1110110; // 1 + seg_code[2] <= 7'b0100001; // 2 + seg_code[3] <= 7'b0100100; // 3 + seg_code[4] <= 7'b0010110; // 4 + seg_code[5] <= 7'b0001100; // 5 + seg_code[6] <= 7'b0001000; // 6 + seg_code[7] <= 7'b1100110; // 7 + seg_code[8] <= 7'b0000000; // 8 + seg_code[9] <= 7'b0000110; // 9 + seg_code[10] <= 7'b0000010; // A + seg_code[11] <= 7'b0011000; // B + seg_code[12] <= 7'b1001001; // C + seg_code[13] <= 7'b0110000; // D + seg_code[14] <= 7'b0001001; // E + seg_code[15] <= 7'b0001011; // F + end + end + + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + dpy0_reg <= 8'b0000_0000; + end + else begin + // ݼĴеʾ + dpy0_data <= data_reg[3:0]; // dpy0 ʾ + + // control_reg ʾ + case (control_reg[1:0]) + 2'b01: begin + dpy0_reg <= {~seg_code[dpy0_data], 1'b0}; // ʾ dpy0 + end + 2'b10: begin + dpy0_reg <= {~seg_code[dpy0_data], 1'b1}; // ʾ dpy0С + end + default: begin + dpy0_reg <= 8'b0000_0000; + end + endcase + end + end + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + dpy1_reg <= 8'b0000_0000; + end + else begin + // ݼĴеʾ + dpy1_data <= data_reg[7:4]; // dpy0 ʾ + + // control_reg ʾ + case (control_reg[3:2]) + 2'b01: begin + dpy1_reg <= {~seg_code[dpy1_data], 1'b0}; // ʾ dpy0 + end + 2'b10: begin + dpy1_reg <= {~seg_code[dpy1_data], 1'b1}; // ʾ dpy0С + end + default: begin + dpy1_reg <= 8'b0000_0000; + end + endcase + end + end + +endmodule diff --git a/rtl/ip/confreg/int_ctrl.v b/rtl/ip/confreg/int_ctrl.v new file mode 100644 index 0000000..6f12fb9 --- /dev/null +++ b/rtl/ip/confreg/int_ctrl.v @@ -0,0 +1,61 @@ +module int_ctrl ( + input wire clk, + input wire resetn, + input wire [31:0] int_en, + input wire [31:0] int_edge, + input wire [31:0] int_pol, + input wire [31:0] int_in, + input wire [31:0] int_clr, + input wire [31:0] int_set, + output wire [31:0] int_out +); + + // 同步异步输入信号，防止亚稳态 + reg [31:0] int_in_sync_d1; + reg [31:0] int_in_sync_d2; + reg [31:0] int_in_sync_d3; // 用于边沿检测 + + always @(posedge clk or negedge resetn) begin + if (!resetn) begin + int_in_sync_d1 <= 32'b0; + int_in_sync_d2 <= 32'b0; + int_in_sync_d3 <= 32'b0; + end else begin + int_in_sync_d1 <= int_in; + int_in_sync_d2 <= int_in_sync_d1; + int_in_sync_d3 <= int_in_sync_d2; + end + end + + // 生成同步后的边沿信号 + wire [31:0] rising_edge = int_in_sync_d2 & ~int_in_sync_d3; + wire [31:0] falling_edge = ~int_in_sync_d2 & int_in_sync_d3; + + // 边沿触发状态寄存器 + reg [31:0] edge_int_state; + integer i; + always @(posedge clk or negedge resetn) begin + if (!resetn) begin + edge_int_state <= 32'b0; + end else begin + for (i = 0; i < 32; i = i + 1) begin + // 硬件检测优先级通常建议高于软件清除，防止丢失极窄脉冲 + if (int_edge[i]) begin + if ((int_pol[i] && rising_edge[i]) || (!int_pol[i] && falling_edge[i])) + edge_int_state[i] <= 1'b1; + else if (int_set[i]) + edge_int_state[i] <= 1'b1; + else if (int_clr[i]) + edge_int_state[i] <= 1'b0; + end + end + end + end + + // 电平触发逻辑 + wire [31:0] level_int_state = int_in_sync_d2 ^ ~int_pol; + + // 最终输出 + assign int_out = int_en & ((int_edge & edge_int_state) | (~int_edge & level_int_state)); + +endmodule \ No newline at end of file diff --git a/rtl/ip/confreg/key_debounce.v b/rtl/ip/confreg/key_debounce.v new file mode 100644 index 0000000..fbb2ae9 --- /dev/null +++ b/rtl/ip/confreg/key_debounce.v @@ -0,0 +1,40 @@ +module key_debounce( + input sys_clk, //外部时钟20M + + input key, //外部按键输入 + + output wire key_out //按键消抖后的数据 +); + + //reg define + reg [31:0] delay_cnt; //延时计数 + reg key_reg; + reg key_value = 1'b1; + +//***************************************************** +//** main code +//***************************************************** + always @(posedge sys_clk ) begin + key_reg <= key; + if(key_reg != key) //一旦检测到按键状态发生变化(有按键被按下或释放) + delay_cnt <= 32'd400000; //给延时计数器重新装载初始值（计数时间为 20ms） + else if(key_reg == key) begin //在按键状态稳定时，计数器递减，开始 20ms 倒计时 + if(delay_cnt > 32'd0) + delay_cnt <= delay_cnt - 1'b1; + else + delay_cnt <= delay_cnt; + end + end + + always @(posedge sys_clk ) begin + if(delay_cnt == 32'd1) begin //当计数器递减到 1 时，说明按键稳定状态维持了 20ms + key_value <= key; //并寄存此时按键的值 + end + else begin + key_value <= key_out; + end + end + + assign key_out = key & key_value ; + +endmodule \ No newline at end of file diff --git a/rtl/ip/fft/Butterfly.v b/rtl/ip/fft/Butterfly.v new file mode 100644 index 0000000..61df798 --- /dev/null +++ b/rtl/ip/fft/Butterfly.v @@ -0,0 +1,32 @@ +//---------------------------------------------------------------------- +// Butterfly: Add/Sub and Scaling +//---------------------------------------------------------------------- +module Butterfly #( + parameter WIDTH = 16, + parameter RH = 0 // Round Half Up +)( + input signed [WIDTH-1:0] x0_re, // Input Data #0 (Real) + input signed [WIDTH-1:0] x0_im, // Input Data #0 (Imag) + input signed [WIDTH-1:0] x1_re, // Input Data #1 (Real) + input signed [WIDTH-1:0] x1_im, // Input Data #1 (Imag) + output signed [WIDTH-1:0] y0_re, // Output Data #0 (Real) + output signed [WIDTH-1:0] y0_im, // Output Data #0 (Imag) + output signed [WIDTH-1:0] y1_re, // Output Data #1 (Real) + output signed [WIDTH-1:0] y1_im // Output Data #1 (Imag) +); + +wire signed [WIDTH:0] add_re, add_im, sub_re, sub_im; + +// Add/Sub +assign add_re = x0_re + x1_re; +assign add_im = x0_im + x1_im; +assign sub_re = x0_re - x1_re; +assign sub_im = x0_im - x1_im; + +// Scaling +assign y0_re = (add_re + RH) >>> 1; +assign y0_im = (add_im + RH) >>> 1; +assign y1_re = (sub_re + RH) >>> 1; +assign y1_im = (sub_im + RH) >>> 1; + +endmodule diff --git a/rtl/ip/fft/DelayBuffer.v b/rtl/ip/fft/DelayBuffer.v new file mode 100644 index 0000000..19bff72 --- /dev/null +++ b/rtl/ip/fft/DelayBuffer.v @@ -0,0 +1,32 @@ +//---------------------------------------------------------------------- +// DelayBuffer: Generate Constant Delay +//---------------------------------------------------------------------- +module DelayBuffer #( + parameter DEPTH = 32, + parameter WIDTH = 16 +)( + input clock, // Master Clock + input [WIDTH-1:0] di_re, // Data Input (Real) + input [WIDTH-1:0] di_im, // Data Input (Imag) + output [WIDTH-1:0] do_re, // Data Output (Real) + output [WIDTH-1:0] do_im // Data Output (Imag) +); + +reg [WIDTH-1:0] buf_re[0:DEPTH-1]; +reg [WIDTH-1:0] buf_im[0:DEPTH-1]; +integer n; + +// Shift Buffer +always @(posedge clock) begin + for (n = DEPTH-1; n > 0; n = n - 1) begin + buf_re[n] <= buf_re[n-1]; + buf_im[n] <= buf_im[n-1]; + end + buf_re[0] <= di_re; + buf_im[0] <= di_im; +end + +assign do_re = buf_re[DEPTH-1]; +assign do_im = buf_im[DEPTH-1]; + +endmodule diff --git a/rtl/ip/fft/FFT1024_32B.v b/rtl/ip/fft/FFT1024_32B.v new file mode 100644 index 0000000..2875ebc --- /dev/null +++ b/rtl/ip/fft/FFT1024_32B.v @@ -0,0 +1,89 @@ +//---------------------------------------------------------------------- +// FFT: 1024-Point FFT Using Radix-2^2 Single-Path Delay Feedback +//---------------------------------------------------------------------- +module FFT #( + parameter WIDTH = 32 +)( + input clock, // Master Clock + input reset, // Active High Asynchronous Reset + input di_en, // Input Data Enable + input [WIDTH-1:0] di_re, // Input Data (Real) + input [WIDTH-1:0] di_im, // Input Data (Imag) + output do_en, // Output Data Enable + output [WIDTH-1:0] do_re, // Output Data (Real) + output [WIDTH-1:0] do_im // Output Data (Imag) +); +//---------------------------------------------------------------------- +// Data must be input consecutively in natural order. +// The result is scaled to 1/N and output in bit-reversed order. +//---------------------------------------------------------------------- + +wire su1_do_en; +wire[WIDTH-1:0] su1_do_re; +wire[WIDTH-1:0] su1_do_im; +wire su2_do_en; +wire[WIDTH-1:0] su2_do_re; +wire[WIDTH-1:0] su2_do_im; +wire su3_do_en; +wire[WIDTH-1:0] su3_do_re; +wire[WIDTH-1:0] su3_do_im; +wire su4_do_en; +wire[WIDTH-1:0] su4_do_re; +wire[WIDTH-1:0] su4_do_im; + +SdfUnit #(.N(1024),.M(1024),.WIDTH(WIDTH)) SU1 ( + .clock (clock ), // i + .reset (reset ), // i + .di_en (di_en ), // i + .di_re (di_re ), // i + .di_im (di_im ), // i + .do_en (su1_do_en ), // o + .do_re (su1_do_re ), // o + .do_im (su1_do_im ) // o +); + +SdfUnit #(.N(1024),.M(256),.WIDTH(WIDTH)) SU2 ( + .clock (clock ), // i + .reset (reset ), // i + .di_en (su1_do_en ), // i + .di_re (su1_do_re ), // i + .di_im (su1_do_im ), // i + .do_en (su2_do_en ), // o + .do_re (su2_do_re ), // o + .do_im (su2_do_im ) // o +); + +SdfUnit #(.N(1024),.M(64),.WIDTH(WIDTH)) SU3 ( + .clock (clock ), // i + .reset (reset ), // i + .di_en (su2_do_en ), // i + .di_re (su2_do_re ), // i + .di_im (su2_do_im ), // i + .do_en (su3_do_en ), // o + .do_re (su3_do_re ), // o + .do_im (su3_do_im ) // o +); + +SdfUnit #(.N(1024),.M(16),.WIDTH(WIDTH)) SU4 ( + .clock (clock ), // i + .reset (reset ), // i + .di_en (su3_do_en ), // i + .di_re (su3_do_re ), // i + .di_im (su3_do_im ), // i + .do_en (su4_do_en ), // o + .do_re (su4_do_re ), // o + .do_im (su4_do_im ) // o +); + +SdfUnit #(.N(1024),.M(4),.WIDTH(WIDTH)) SU5 ( + .clock (clock ), // i + .reset (reset ), // i + .di_en (su4_do_en ), // i + .di_re (su4_do_re ), // i + .di_im (su4_do_im ), // i + .do_en (do_en ), // o + .do_re (do_re ), // o + .do_im (do_im ) // o +); + +endmodule diff --git a/rtl/ip/fft/Multiply.v b/rtl/ip/fft/Multiply.v new file mode 100644 index 0000000..6172571 --- /dev/null +++ b/rtl/ip/fft/Multiply.v @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Multiply: Complex Multiplier +//---------------------------------------------------------------------- +module Multiply #( + parameter WIDTH = 16 +)( + input signed [WIDTH-1:0] a_re, + input signed [WIDTH-1:0] a_im, + input signed [WIDTH-1:0] b_re, + input signed [WIDTH-1:0] b_im, + output signed [WIDTH-1:0] m_re, + output signed [WIDTH-1:0] m_im +); + +wire signed [WIDTH*2-1:0] arbr, arbi, aibr, aibi; +wire signed [WIDTH-1:0] sc_arbr, sc_arbi, sc_aibr, sc_aibi; + +// Signed Multiplication +assign arbr = a_re * b_re; +assign arbi = a_re * b_im; +assign aibr = a_im * b_re; +assign aibi = a_im * b_im; + +// Scaling +assign sc_arbr = arbr >>> (WIDTH-1); +assign sc_arbi = arbi >>> (WIDTH-1); +assign sc_aibr = aibr >>> (WIDTH-1); +assign sc_aibi = aibi >>> (WIDTH-1); + +// Sub/Add +// These sub/add may overflow if unnormalized data is input. +assign m_re = sc_arbr - sc_aibi; +assign m_im = sc_arbi + sc_aibr; + +endmodule diff --git a/rtl/ip/fft/SdfUnit.v b/rtl/ip/fft/SdfUnit.v new file mode 100644 index 0000000..67edc49 --- /dev/null +++ b/rtl/ip/fft/SdfUnit.v @@ -0,0 +1,277 @@ +//---------------------------------------------------------------------- +// SdfUnit: Radix-2^2 Single-Path Delay Feedback Unit for N-Point FFT +//---------------------------------------------------------------------- +module SdfUnit #( + parameter N = 64, // Number of FFT Point + parameter M = 64, // Twiddle Resolution + parameter WIDTH = 16 // Data Bit Length +)( + input clock, // Master Clock + input reset, // Active High Asynchronous Reset + input di_en, // Input Data Enable + input [WIDTH-1:0] di_re, // Input Data (Real) + input [WIDTH-1:0] di_im, // Input Data (Imag) + output do_en, // Output Data Enable + output [WIDTH-1:0] do_re, // Output Data (Real) + output [WIDTH-1:0] do_im // Output Data (Imag) +); + +// log2 constant function +function integer log2; + input integer x; + integer value; + begin + value = x-1; + for (log2=0; value>0; log2=log2+1) + value = value>>1; + end +endfunction + +localparam LOG_N = log2(N); // Bit Length of N +localparam LOG_M = log2(M); // Bit Length of M + +//---------------------------------------------------------------------- +// Internal Regs and Nets +//---------------------------------------------------------------------- +// 1st Butterfly +reg [LOG_N-1:0] di_count; // Input Data Count +wire bf1_bf; // Butterfly Add/Sub Enable +wire[WIDTH-1:0] bf1_x0_re; // Data #0 to Butterfly (Real) +wire[WIDTH-1:0] bf1_x0_im; // Data #0 to Butterfly (Imag) +wire[WIDTH-1:0] bf1_x1_re; // Data #1 to Butterfly (Real) +wire[WIDTH-1:0] bf1_x1_im; // Data #1 to Butterfly (Imag) +wire[WIDTH-1:0] bf1_y0_re; // Data #0 from Butterfly (Real) +wire[WIDTH-1:0] bf1_y0_im; // Data #0 from Butterfly (Imag) +wire[WIDTH-1:0] bf1_y1_re; // Data #1 from Butterfly (Real) +wire[WIDTH-1:0] bf1_y1_im; // Data #1 from Butterfly (Imag) +wire[WIDTH-1:0] db1_di_re; // Data to DelayBuffer (Real) +wire[WIDTH-1:0] db1_di_im; // Data to DelayBuffer (Imag) +wire[WIDTH-1:0] db1_do_re; // Data from DelayBuffer (Real) +wire[WIDTH-1:0] db1_do_im; // Data from DelayBuffer (Imag) +wire[WIDTH-1:0] bf1_sp_re; // Single-Path Data Output (Real) +wire[WIDTH-1:0] bf1_sp_im; // Single-Path Data Output (Imag) +reg bf1_sp_en; // Single-Path Data Enable +reg [LOG_N-1:0] bf1_count; // Single-Path Data Count +wire bf1_start; // Single-Path Output Trigger +wire bf1_end; // End of Single-Path Data +wire bf1_mj; // Twiddle (-j) Enable +reg [WIDTH-1:0] bf1_do_re; // 1st Butterfly Output Data (Real) +reg [WIDTH-1:0] bf1_do_im; // 1st Butterfly Output Data (Imag) + +// 2nd Butterfly +reg bf2_bf; // Butterfly Add/Sub Enable +wire[WIDTH-1:0] bf2_x0_re; // Data #0 to Butterfly (Real) +wire[WIDTH-1:0] bf2_x0_im; // Data #0 to Butterfly (Imag) +wire[WIDTH-1:0] bf2_x1_re; // Data #1 to Butterfly (Real) +wire[WIDTH-1:0] bf2_x1_im; // Data #1 to Butterfly (Imag) +wire[WIDTH-1:0] bf2_y0_re; // Data #0 from Butterfly (Real) +wire[WIDTH-1:0] bf2_y0_im; // Data #0 from Butterfly (Imag) +wire[WIDTH-1:0] bf2_y1_re; // Data #1 from Butterfly (Real) +wire[WIDTH-1:0] bf2_y1_im; // Data #1 from Butterfly (Imag) +wire[WIDTH-1:0] db2_di_re; // Data to DelayBuffer (Real) +wire[WIDTH-1:0] db2_di_im; // Data to DelayBuffer (Imag) +wire[WIDTH-1:0] db2_do_re; // Data from DelayBuffer (Real) +wire[WIDTH-1:0] db2_do_im; // Data from DelayBuffer (Imag) +wire[WIDTH-1:0] bf2_sp_re; // Single-Path Data Output (Real) +wire[WIDTH-1:0] bf2_sp_im; // Single-Path Data Output (Imag) +reg bf2_sp_en; // Single-Path Data Enable +reg [LOG_N-1:0] bf2_count; // Single-Path Data Count +reg bf2_start; // Single-Path Output Trigger +wire bf2_end; // End of Single-Path Data +reg [WIDTH-1:0] bf2_do_re; // 2nd Butterfly Output Data (Real) +reg [WIDTH-1:0] bf2_do_im; // 2nd Butterfly Output Data (Imag) +reg bf2_do_en; // 2nd Butterfly Output Data Enable + +// Multiplication +wire[1:0] tw_sel; // Twiddle Select (2n/n/3n) +wire[LOG_N-3:0] tw_num; // Twiddle Number (n) +wire[LOG_N-1:0] tw_addr; // Twiddle Table Address +wire[WIDTH-1:0] tw_re; // Twiddle Factor (Real) +wire[WIDTH-1:0] tw_im; // Twiddle Factor (Imag) +reg mu_en; // Multiplication Enable +wire[WIDTH-1:0] mu_a_re; // Multiplier Input (Real) +wire[WIDTH-1:0] mu_a_im; // Multiplier Input (Imag) +wire[WIDTH-1:0] mu_m_re; // Multiplier Output (Real) +wire[WIDTH-1:0] mu_m_im; // Multiplier Output (Imag) +reg [WIDTH-1:0] mu_do_re; // Multiplication Output Data (Real) +reg [WIDTH-1:0] mu_do_im; // Multiplication Output Data (Imag) +reg mu_do_en; // Multiplication Output Data Enable + +//---------------------------------------------------------------------- +// 1st Butterfly +//---------------------------------------------------------------------- +always @(posedge clock or posedge reset) begin + if (reset) begin + di_count <= {LOG_N{1'b0}}; + end else begin + di_count <= di_en ? (di_count + 1'b1) : {LOG_N{1'b0}}; + end +end +assign bf1_bf = di_count[LOG_M-1]; + +// Set unknown value x for verification +assign bf1_x0_re = bf1_bf ? db1_do_re : {WIDTH{1'bx}}; +assign bf1_x0_im = bf1_bf ? db1_do_im : {WIDTH{1'bx}}; +assign bf1_x1_re = bf1_bf ? di_re : {WIDTH{1'bx}}; +assign bf1_x1_im = bf1_bf ? di_im : {WIDTH{1'bx}}; + +Butterfly #(.WIDTH(WIDTH),.RH(0)) BF1 ( + .x0_re (bf1_x0_re ), // i + .x0_im (bf1_x0_im ), // i + .x1_re (bf1_x1_re ), // i + .x1_im (bf1_x1_im ), // i + .y0_re (bf1_y0_re ), // o + .y0_im (bf1_y0_im ), // o + .y1_re (bf1_y1_re ), // o + .y1_im (bf1_y1_im ) // o +); + +DelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 ( + .clock (clock ), // i + .di_re (db1_di_re ), // i + .di_im (db1_di_im ), // i + .do_re (db1_do_re ), // o + .do_im (db1_do_im ) // o +); + +assign db1_di_re = bf1_bf ? bf1_y1_re : di_re; +assign db1_di_im = bf1_bf ? bf1_y1_im : di_im; +assign bf1_sp_re = bf1_bf ? bf1_y0_re : bf1_mj ? db1_do_im : db1_do_re; +assign bf1_sp_im = bf1_bf ? bf1_y0_im : bf1_mj ? -db1_do_re : db1_do_im; + +always @(posedge clock or posedge reset) begin + if (reset) begin + bf1_sp_en <= 1'b0; + bf1_count <= {LOG_N{1'b0}}; + end else begin + bf1_sp_en <= bf1_start ? 1'b1 : bf1_end ? 1'b0 : bf1_sp_en; + bf1_count <= bf1_sp_en ? (bf1_count + 1'b1) : {LOG_N{1'b0}}; + end +end +assign bf1_start = (di_count == (2**(LOG_M-1)-1)); +assign bf1_end = (bf1_count == (2**LOG_N-1)); +assign bf1_mj = (bf1_count[LOG_M-1:LOG_M-2] == 2'd3); + +always @(posedge clock) begin + bf1_do_re <= bf1_sp_re; + bf1_do_im <= bf1_sp_im; +end + +//---------------------------------------------------------------------- +// 2nd Butterfly +//---------------------------------------------------------------------- +always @(posedge clock) begin + bf2_bf <= bf1_count[LOG_M-2]; +end + +// Set unknown value x for verification +assign bf2_x0_re = bf2_bf ? db2_do_re : {WIDTH{1'bx}}; +assign bf2_x0_im = bf2_bf ? db2_do_im : {WIDTH{1'bx}}; +assign bf2_x1_re = bf2_bf ? bf1_do_re : {WIDTH{1'bx}}; +assign bf2_x1_im = bf2_bf ? bf1_do_im : {WIDTH{1'bx}}; + +// Negative bias occurs when RH=0 and positive bias occurs when RH=1. +// Using both alternately reduces the overall rounding error. +Butterfly #(.WIDTH(WIDTH),.RH(1)) BF2 ( + .x0_re (bf2_x0_re ), // i + .x0_im (bf2_x0_im ), // i + .x1_re (bf2_x1_re ), // i + .x1_im (bf2_x1_im ), // i + .y0_re (bf2_y0_re ), // o + .y0_im (bf2_y0_im ), // o + .y1_re (bf2_y1_re ), // o + .y1_im (bf2_y1_im ) // o +); + +DelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 ( + .clock (clock ), // i + .di_re (db2_di_re ), // i + .di_im (db2_di_im ), // i + .do_re (db2_do_re ), // o + .do_im (db2_do_im ) // o +); + +assign db2_di_re = bf2_bf ? bf2_y1_re : bf1_do_re; +assign db2_di_im = bf2_bf ? bf2_y1_im : bf1_do_im; +assign bf2_sp_re = bf2_bf ? bf2_y0_re : db2_do_re; +assign bf2_sp_im = bf2_bf ? bf2_y0_im : db2_do_im; + +always @(posedge clock or posedge reset) begin + if (reset) begin + bf2_sp_en <= 1'b0; + bf2_count <= {LOG_N{1'b0}}; + end else begin + bf2_sp_en <= bf2_start ? 1'b1 : bf2_end ? 1'b0 : bf2_sp_en; + bf2_count <= bf2_sp_en ? (bf2_count + 1'b1) : {LOG_N{1'b0}}; + end +end + +always @(posedge clock) begin + bf2_start <= (bf1_count == (2**(LOG_M-2)-1)) & bf1_sp_en; +end +assign bf2_end = (bf2_count == (2**LOG_N-1)); + +always @(posedge clock) begin + bf2_do_re <= bf2_sp_re; + bf2_do_im <= bf2_sp_im; +end + +always @(posedge clock or posedge reset) begin + if (reset) begin + bf2_do_en <= 1'b0; + end else begin + bf2_do_en <= bf2_sp_en; + end +end + +//---------------------------------------------------------------------- +// Multiplication +//---------------------------------------------------------------------- +assign tw_sel[1] = bf2_count[LOG_M-2]; +assign tw_sel[0] = bf2_count[LOG_M-1]; +assign tw_num = bf2_count << (LOG_N-LOG_M); +assign tw_addr = tw_num * tw_sel; + +Twiddle TW ( + .clock (clock ), // i + .addr (tw_addr), // i + .tw_re (tw_re ), // o + .tw_im (tw_im ) // o +); + +// Multiplication is bypassed when twiddle address is 0. +always @(posedge clock) begin + mu_en <= (tw_addr != {LOG_N{1'b0}}); +end +// Set unknown value x for verification +assign mu_a_re = mu_en ? bf2_do_re : {WIDTH{1'bx}}; +assign mu_a_im = mu_en ? bf2_do_im : {WIDTH{1'bx}}; + +Multiply #(.WIDTH(WIDTH)) MU ( + .a_re (mu_a_re), // i + .a_im (mu_a_im), // i + .b_re (tw_re ), // i + .b_im (tw_im ), // i + .m_re (mu_m_re), // o + .m_im (mu_m_im) // o +); + +always @(posedge clock) begin + mu_do_re <= mu_en ? mu_m_re : bf2_do_re; + mu_do_im <= mu_en ? mu_m_im : bf2_do_im; +end + +always @(posedge clock or posedge reset) begin + if (reset) begin + mu_do_en <= 1'b0; + end else begin + mu_do_en <= bf2_do_en; + end +end + +// No multiplication required at final stage +assign do_en = (LOG_M == 2) ? bf2_do_en : mu_do_en; +assign do_re = (LOG_M == 2) ? bf2_do_re : mu_do_re; +assign do_im = (LOG_M == 2) ? bf2_do_im : mu_do_im; + +endmodule diff --git a/rtl/ip/fft/Twiddle1024_32B.v b/rtl/ip/fft/Twiddle1024_32B.v new file mode 100644 index 0000000..c6b438d --- /dev/null +++ b/rtl/ip/fft/Twiddle1024_32B.v @@ -0,0 +1,1064 @@ +//---------------------------------------------------------------------- +// Twiddle: 1024-Point Twiddle Table for Radix-2^2 Butterfly +//---------------------------------------------------------------------- +module Twiddle #( + parameter TW_FF = 1 // Use Output Register +)( + input clock, // Master Clock + input [9:0] addr, // Twiddle Factor Number + output [31:0] tw_re, // Twiddle Factor (Real) + output [31:0] tw_im // Twiddle Factor (Imag) +); + +wire[31:0] wn_re[0:1023]; // Twiddle Table (Real) +wire[31:0] wn_im[0:1023]; // Twiddle Table (Imag) +wire[31:0] mx_re; // Multiplexer output (Real) +wire[31:0] mx_im; // Multiplexer output (Imag) +reg [31:0] ff_re; // Register output (Real) +reg [31:0] ff_im; // Register output (Imag) + +assign mx_re = wn_re[addr]; +assign mx_im = wn_im[addr]; + +always @(posedge clock) begin + ff_re <= mx_re; + ff_im <= mx_im; +end + +assign tw_re = TW_FF ? ff_re : mx_re; +assign tw_im = TW_FF ? ff_im : mx_im; + +//---------------------------------------------------------------------- +// Twiddle Factor Value +//---------------------------------------------------------------------- +// Multiplication is bypassed when twiddle address is 0. +// Setting wn_re[0] = 0 and wn_im[0] = 0 makes it easier to check the waveform. +// It may also reduce power consumption slightly. +// +// wn_re = cos(-2pi*n/1024) wn_im = sin(-2pi*n/1024) +assign wn_re[ 0] = 32'h00000000; assign wn_im[ 0] = 32'h00000000; // 0 1.000 -0.000 +assign wn_re[ 1] = 32'h7FFF6216; assign wn_im[ 1] = 32'hFF36F078; // 1 1.000 -0.006 +assign wn_re[ 2] = 32'h7FFD885A; assign wn_im[ 2] = 32'hFE6DE2E0; // 2 1.000 -0.012 +assign wn_re[ 3] = 32'h7FFA72D1; assign wn_im[ 3] = 32'hFDA4D929; // 3 1.000 -0.018 +assign wn_re[ 4] = 32'h7FF62182; assign wn_im[ 4] = 32'hFCDBD541; // 4 1.000 -0.025 +assign wn_re[ 5] = 32'h7FF09478; assign wn_im[ 5] = 32'hFC12D91A; // 5 1.000 -0.031 +assign wn_re[ 6] = 32'h7FE9CBC0; assign wn_im[ 6] = 32'hFB49E6A3; // 6 0.999 -0.037 +assign wn_re[ 7] = 32'h7FE1C76B; assign wn_im[ 7] = 32'hFA80FFCB; // 7 0.999 -0.043 +assign wn_re[ 8] = 32'h7FD8878E; assign wn_im[ 8] = 32'hF9B82684; // 8 0.999 -0.049 +assign wn_re[ 9] = 32'h7FCE0C3E; assign wn_im[ 9] = 32'hF8EF5CBB; // 9 0.998 -0.055 +assign wn_re[10] = 32'h7FC25596; assign wn_im[10] = 32'hF826A462; // 10 0.998 -0.061 +assign wn_re[11] = 32'h7FB563B3; assign wn_im[11] = 32'hF75DFF66; // 11 0.998 -0.067 +assign wn_re[12] = 32'h7FA736B4; assign wn_im[12] = 32'hF6956FB7; // 12 0.997 -0.074 +assign wn_re[13] = 32'h7F97CEBD; assign wn_im[13] = 32'hF5CCF743; // 13 0.997 -0.080 +assign wn_re[14] = 32'h7F872BF3; assign wn_im[14] = 32'hF50497FB; // 14 0.996 -0.086 +assign wn_re[15] = 32'h7F754E80; assign wn_im[15] = 32'hF43C53CB; // 15 0.996 -0.092 +assign wn_re[16] = 32'h7F62368F; assign wn_im[16] = 32'hF3742CA2; // 16 0.995 -0.098 +assign wn_re[17] = 32'h7F4DE451; assign wn_im[17] = 32'hF2AC246E; // 17 0.995 -0.104 +assign wn_re[18] = 32'h7F3857F6; assign wn_im[18] = 32'hF1E43D1C; // 18 0.994 -0.110 +assign wn_re[19] = 32'h7F2191B4; assign wn_im[19] = 32'hF11C789A; // 19 0.993 -0.116 +assign wn_re[20] = 32'h7F0991C4; assign wn_im[20] = 32'hF054D8D5; // 20 0.992 -0.122 +assign wn_re[21] = 32'h7EF05860; assign wn_im[21] = 32'hEF8D5FB8; // 21 0.992 -0.128 +assign wn_re[22] = 32'h7ED5E5C6; assign wn_im[22] = 32'hEEC60F31; // 22 0.991 -0.135 +assign wn_re[23] = 32'h7EBA3A39; assign wn_im[23] = 32'hEDFEE92B; // 23 0.990 -0.141 +assign wn_re[24] = 32'h7E9D55FC; assign wn_im[24] = 32'hED37EF91; // 24 0.989 -0.147 +assign wn_re[25] = 32'h7E7F3957; assign wn_im[25] = 32'hEC71244F; // 25 0.988 -0.153 +assign wn_re[26] = 32'h7E5FE493; assign wn_im[26] = 32'hEBAA894F; // 26 0.987 -0.159 +assign wn_re[27] = 32'h7E3F57FF; assign wn_im[27] = 32'hEAE4207A; // 27 0.986 -0.165 +assign wn_re[28] = 32'h7E1D93EA; assign wn_im[28] = 32'hEA1DEBBB; // 28 0.985 -0.171 +assign wn_re[29] = 32'h7DFA98A8; assign wn_im[29] = 32'hE957ECFB; // 29 0.984 -0.177 +assign wn_re[30] = 32'h7DD6668F; assign wn_im[30] = 32'hE8922622; // 30 0.983 -0.183 +assign wn_re[31] = 32'h7DB0FDF8; assign wn_im[31] = 32'hE7CC9917; // 31 0.982 -0.189 +assign wn_re[32] = 32'h7D8A5F40; assign wn_im[32] = 32'hE70747C4; // 32 0.981 -0.195 +assign wn_re[33] = 32'h7D628AC6; assign wn_im[33] = 32'hE642340D; // 33 0.980 -0.201 +assign wn_re[34] = 32'h7D3980EC; assign wn_im[34] = 32'hE57D5FDA; // 34 0.978 -0.207 +assign wn_re[35] = 32'h7D0F4218; assign wn_im[35] = 32'hE4B8CD11; // 35 0.977 -0.213 +assign wn_re[36] = 32'h7CE3CEB2; assign wn_im[36] = 32'hE3F47D96; // 36 0.976 -0.219 +assign wn_re[37] = 32'h7CB72724; assign wn_im[37] = 32'hE330734D; // 37 0.974 -0.225 +assign wn_re[38] = 32'h7C894BDE; assign wn_im[38] = 32'hE26CB01B; // 38 0.973 -0.231 +assign wn_re[39] = 32'h7C5A3D50; assign wn_im[39] = 32'hE1A935E2; // 39 0.972 -0.237 +assign wn_re[40] = 32'h7C29FBEE; assign wn_im[40] = 32'hE0E60685; // 40 0.970 -0.243 +assign wn_re[41] = 32'h7BF88830; assign wn_im[41] = 32'hE02323E5; // 41 0.969 -0.249 +assign wn_re[42] = 32'h7BC5E290; assign wn_im[42] = 32'hDF608FE4; // 42 0.967 -0.255 +assign wn_re[43] = 32'h7B920B89; assign wn_im[43] = 32'hDE9E4C60; // 43 0.965 -0.261 +assign wn_re[44] = 32'h7B5D039E; assign wn_im[44] = 32'hDDDC5B3B; // 44 0.964 -0.267 +assign wn_re[45] = 32'h7B26CB4F; assign wn_im[45] = 32'hDD1ABE51; // 45 0.962 -0.273 +assign wn_re[46] = 32'h7AEF6323; assign wn_im[46] = 32'hDC597781; // 46 0.960 -0.279 +assign wn_re[47] = 32'h7AB6CBA4; assign wn_im[47] = 32'hDB9888A8; // 47 0.959 -0.284 +assign wn_re[48] = 32'h7A7D055B; assign wn_im[48] = 32'hDAD7F3A2; // 48 0.957 -0.290 +assign wn_re[49] = 32'h7A4210D8; assign wn_im[49] = 32'hDA17BA4A; // 49 0.955 -0.296 +assign wn_re[50] = 32'h7A05EEAD; assign wn_im[50] = 32'hD957DE7A; // 50 0.953 -0.302 +assign wn_re[51] = 32'h79C89F6E; assign wn_im[51] = 32'hD898620C; // 51 0.951 -0.308 +assign wn_re[52] = 32'h798A23B1; assign wn_im[52] = 32'hD7D946D8; // 52 0.950 -0.314 +assign wn_re[53] = 32'h794A7C12; assign wn_im[53] = 32'hD71A8EB5; // 53 0.948 -0.320 +assign wn_re[54] = 32'h7909A92D; assign wn_im[54] = 32'hD65C3B7B; // 54 0.946 -0.325 +assign wn_re[55] = 32'h78C7ABA2; assign wn_im[55] = 32'hD59E4EFF; // 55 0.944 -0.331 +assign wn_re[56] = 32'h78848414; assign wn_im[56] = 32'hD4E0CB15; // 56 0.942 -0.337 +assign wn_re[57] = 32'h78403329; assign wn_im[57] = 32'hD423B191; // 57 0.939 -0.343 +assign wn_re[58] = 32'h77FAB989; assign wn_im[58] = 32'hD3670446; // 58 0.937 -0.348 +assign wn_re[59] = 32'h77B417DF; assign wn_im[59] = 32'hD2AAC504; // 59 0.935 -0.354 +assign wn_re[60] = 32'h776C4EDB; assign wn_im[60] = 32'hD1EEF59E; // 60 0.933 -0.360 +assign wn_re[61] = 32'h77235F2D; assign wn_im[61] = 32'hD13397E2; // 61 0.931 -0.366 +assign wn_re[62] = 32'h76D94989; assign wn_im[62] = 32'hD078AD9E; // 62 0.929 -0.371 +assign wn_re[63] = 32'h768E0EA6; assign wn_im[63] = 32'hCFBE389F; // 63 0.926 -0.377 +assign wn_re[64] = 32'h7641AF3D; assign wn_im[64] = 32'hCF043AB3; // 64 0.924 -0.383 +assign wn_re[65] = 32'h75F42C0B; assign wn_im[65] = 32'hCE4AB5A2; // 65 0.922 -0.388 +assign wn_re[66] = 32'h75A585CF; assign wn_im[66] = 32'hCD91AB39; // 66 0.919 -0.394 +assign wn_re[67] = 32'h7555BD4C; assign wn_im[67] = 32'hCCD91D3D; // 67 0.917 -0.400 +assign wn_re[68] = 32'h7504D345; assign wn_im[68] = 32'hCC210D79; // 68 0.914 -0.405 +assign wn_re[69] = 32'h74B2C884; assign wn_im[69] = 32'hCB697DB0; // 69 0.912 -0.411 +assign wn_re[70] = 32'h745F9DD1; assign wn_im[70] = 32'hCAB26FA9; // 70 0.909 -0.416 +assign wn_re[71] = 32'h740B53FB; assign wn_im[71] = 32'hC9FBE527; // 71 0.907 -0.422 +assign wn_re[72] = 32'h73B5EBD1; assign wn_im[72] = 32'hC945DFEC; // 72 0.904 -0.428 +assign wn_re[73] = 32'h735F6626; assign wn_im[73] = 32'hC89061BA; // 73 0.901 -0.433 +assign wn_re[74] = 32'h7307C3D0; assign wn_im[74] = 32'hC7DB6C50; // 74 0.899 -0.439 +assign wn_re[75] = 32'h72AF05A7; assign wn_im[75] = 32'hC727016D; // 75 0.896 -0.444 +assign wn_re[76] = 32'h72552C85; assign wn_im[76] = 32'hC67322CE; // 76 0.893 -0.450 +assign wn_re[77] = 32'h71FA3949; assign wn_im[77] = 32'hC5BFD22E; // 77 0.890 -0.455 +assign wn_re[78] = 32'h719E2CD2; assign wn_im[78] = 32'hC50D1149; // 78 0.888 -0.461 +assign wn_re[79] = 32'h71410805; assign wn_im[79] = 32'hC45AE1D7; // 79 0.885 -0.466 +assign wn_re[80] = 32'h70E2CBC6; assign wn_im[80] = 32'hC3A94590; // 80 0.882 -0.471 +assign wn_re[81] = 32'h708378FF; assign wn_im[81] = 32'hC2F83E2A; // 81 0.879 -0.477 +assign wn_re[82] = 32'h7023109A; assign wn_im[82] = 32'hC247CD5A; // 82 0.876 -0.482 +assign wn_re[83] = 32'h6FC19385; assign wn_im[83] = 32'hC197F4D4; // 83 0.873 -0.488 +assign wn_re[84] = 32'h6F5F02B2; assign wn_im[84] = 32'hC0E8B648; // 84 0.870 -0.493 +assign wn_re[85] = 32'h6EFB5F12; assign wn_im[85] = 32'hC03A1368; // 85 0.867 -0.498 +assign wn_re[86] = 32'h6E96A99D; assign wn_im[86] = 32'hBF8C0DE3; // 86 0.864 -0.504 +assign wn_re[87] = 32'h6E30E34A; assign wn_im[87] = 32'hBEDEA765; // 87 0.861 -0.509 +assign wn_re[88] = 32'h6DCA0D14; assign wn_im[88] = 32'hBE31E19B; // 88 0.858 -0.514 +assign wn_re[89] = 32'h6D6227FA; assign wn_im[89] = 32'hBD85BE30; // 89 0.855 -0.519 +assign wn_re[90] = 32'h6CF934FC; assign wn_im[90] = 32'hBCDA3ECB; // 90 0.851 -0.525 +assign wn_re[91] = 32'h6C8F351C; assign wn_im[91] = 32'hBC2F6513; // 91 0.848 -0.530 +assign wn_re[92] = 32'h6C242960; assign wn_im[92] = 32'hBB8532B0; // 92 0.845 -0.535 +assign wn_re[93] = 32'h6BB812D1; assign wn_im[93] = 32'hBADBA943; // 93 0.842 -0.540 +assign wn_re[94] = 32'h6B4AF279; assign wn_im[94] = 32'hBA32CA71; // 94 0.838 -0.545 +assign wn_re[95] = 32'h6ADCC964; assign wn_im[95] = 32'hB98A97D8; // 95 0.835 -0.550 +assign wn_re[96] = 32'h6A6D98A4; assign wn_im[96] = 32'hB8E31319; // 96 0.831 -0.556 +assign wn_re[97] = 32'h69FD614A; assign wn_im[97] = 32'hB83C3DD1; // 97 0.828 -0.561 +assign wn_re[98] = 32'h698C246C; assign wn_im[98] = 32'hB796199B; // 98 0.825 -0.566 +assign wn_re[99] = 32'h6919E320; assign wn_im[99] = 32'hB6F0A812; // 99 0.821 -0.571 +assign wn_re[100] = 32'h68A69E81; assign wn_im[100] = 32'hB64BEACD; // 100 0.818 -0.576 +assign wn_re[101] = 32'h683257AB; assign wn_im[101] = 32'hB5A7E362; // 101 0.814 -0.581 +assign wn_re[102] = 32'h67BD0FBD; assign wn_im[102] = 32'hB5049368; // 102 0.810 -0.586 +assign wn_re[103] = 32'h6746C7D8; assign wn_im[103] = 32'hB461FC70; // 103 0.807 -0.591 +assign wn_re[104] = 32'h66CF8120; assign wn_im[104] = 32'hB3C0200C; // 104 0.803 -0.596 +assign wn_re[105] = 32'h66573CBB; assign wn_im[105] = 32'hB31EFFCC; // 105 0.800 -0.601 +assign wn_re[106] = 32'h65DDFBD3; assign wn_im[106] = 32'hB27E9D3C; // 106 0.796 -0.606 +assign wn_re[107] = 32'h6563BF92; assign wn_im[107] = 32'hB1DEF9E9; // 107 0.792 -0.610 +assign wn_re[108] = 32'h64E88926; assign wn_im[108] = 32'hB140175B; // 108 0.788 -0.615 +assign wn_re[109] = 32'h646C59BF; assign wn_im[109] = 32'hB0A1F71D; // 109 0.785 -0.620 +assign wn_re[110] = 32'h63EF3290; assign wn_im[110] = 32'hB0049AB3; // 110 0.781 -0.625 +assign wn_re[111] = 32'h637114CC; assign wn_im[111] = 32'hAF6803A2; // 111 0.777 -0.630 +assign wn_re[112] = 32'h62F201AC; assign wn_im[112] = 32'hAECC336C; // 112 0.773 -0.634 +assign wn_re[113] = 32'h6271FA69; assign wn_im[113] = 32'hAE312B92; // 113 0.769 -0.639 +assign wn_re[114] = 32'h61F1003F; assign wn_im[114] = 32'hAD96ED92; // 114 0.765 -0.644 +assign wn_re[115] = 32'h616F146C; assign wn_im[115] = 32'hACFD7AE8; // 115 0.761 -0.649 +assign wn_re[116] = 32'h60EC3830; assign wn_im[116] = 32'hAC64D510; // 116 0.757 -0.653 +assign wn_re[117] = 32'h60686CCF; assign wn_im[117] = 32'hABCCFD83; // 117 0.753 -0.658 +assign wn_re[118] = 32'h5FE3B38D; assign wn_im[118] = 32'hAB35F5B5; // 118 0.749 -0.662 +assign wn_re[119] = 32'h5F5E0DB3; assign wn_im[119] = 32'hAA9FBF1E; // 119 0.745 -0.667 +assign wn_re[120] = 32'h5ED77C8A; assign wn_im[120] = 32'hAA0A5B2E; // 120 0.741 -0.672 +assign wn_re[121] = 32'h5E50015D; assign wn_im[121] = 32'hA975CB57; // 121 0.737 -0.676 +assign wn_re[122] = 32'h5DC79D7C; assign wn_im[122] = 32'hA8E21106; // 122 0.733 -0.681 +assign wn_re[123] = 32'h5D3E5237; assign wn_im[123] = 32'hA84F2DAA; // 123 0.728 -0.685 +assign wn_re[124] = 32'h5CB420E0; assign wn_im[124] = 32'hA7BD22AC; // 124 0.724 -0.690 +assign wn_re[125] = 32'h5C290ACC; assign wn_im[125] = 32'hA72BF174; // 125 0.720 -0.694 +assign wn_re[126] = 32'h5B9D1154; assign wn_im[126] = 32'hA69B9B68; // 126 0.716 -0.698 +assign wn_re[127] = 32'h5B1035CF; assign wn_im[127] = 32'hA60C21EE; // 127 0.711 -0.703 +assign wn_re[128] = 32'h5A82799A; assign wn_im[128] = 32'hA57D8666; // 128 0.707 -0.707 +assign wn_re[129] = 32'h59F3DE12; assign wn_im[129] = 32'hA4EFCA31; // 129 0.703 -0.711 +assign wn_re[130] = 32'h59646498; assign wn_im[130] = 32'hA462EEAC; // 130 0.698 -0.716 +assign wn_re[131] = 32'h58D40E8C; assign wn_im[131] = 32'hA3D6F534; // 131 0.694 -0.720 +assign wn_re[132] = 32'h5842DD54; assign wn_im[132] = 32'hA34BDF20; // 132 0.690 -0.724 +assign wn_re[133] = 32'h57B0D256; assign wn_im[133] = 32'hA2C1ADC9; // 133 0.685 -0.728 +assign wn_re[134] = 32'h571DEEFA; assign wn_im[134] = 32'hA2386284; // 134 0.681 -0.733 +assign wn_re[135] = 32'h568A34A9; assign wn_im[135] = 32'hA1AFFEA3; // 135 0.676 -0.737 +assign wn_re[136] = 32'h55F5A4D2; assign wn_im[136] = 32'hA1288376; // 136 0.672 -0.741 +assign wn_re[137] = 32'h556040E2; assign wn_im[137] = 32'hA0A1F24D; // 137 0.667 -0.745 +assign wn_re[138] = 32'h54CA0A4B; assign wn_im[138] = 32'hA01C4C73; // 138 0.662 -0.749 +assign wn_re[139] = 32'h5433027D; assign wn_im[139] = 32'h9F979331; // 139 0.658 -0.753 +assign wn_re[140] = 32'h539B2AF0; assign wn_im[140] = 32'h9F13C7D0; // 140 0.653 -0.757 +assign wn_re[141] = 32'h53028518; assign wn_im[141] = 32'h9E90EB94; // 141 0.649 -0.761 +assign wn_re[142] = 32'h5269126E; assign wn_im[142] = 32'h9E0EFFC1; // 142 0.644 -0.765 +assign wn_re[143] = 32'h51CED46E; assign wn_im[143] = 32'h9D8E0597; // 143 0.639 -0.769 +assign wn_re[144] = 32'h5133CC94; assign wn_im[144] = 32'h9D0DFE54; // 144 0.634 -0.773 +assign wn_re[145] = 32'h5097FC5E; assign wn_im[145] = 32'h9C8EEB34; // 145 0.630 -0.777 +assign wn_re[146] = 32'h4FFB654D; assign wn_im[146] = 32'h9C10CD70; // 146 0.625 -0.781 +assign wn_re[147] = 32'h4F5E08E3; assign wn_im[147] = 32'h9B93A641; // 147 0.620 -0.785 +assign wn_re[148] = 32'h4EBFE8A5; assign wn_im[148] = 32'h9B1776DA; // 148 0.615 -0.788 +assign wn_re[149] = 32'h4E210617; assign wn_im[149] = 32'h9A9C406E; // 149 0.610 -0.792 +assign wn_re[150] = 32'h4D8162C4; assign wn_im[150] = 32'h9A22042D; // 150 0.606 -0.796 +assign wn_re[151] = 32'h4CE10034; assign wn_im[151] = 32'h99A8C345; // 151 0.601 -0.800 +assign wn_re[152] = 32'h4C3FDFF4; assign wn_im[152] = 32'h99307EE0; // 152 0.596 -0.803 +assign wn_re[153] = 32'h4B9E0390; assign wn_im[153] = 32'h98B93828; // 153 0.591 -0.807 +assign wn_re[154] = 32'h4AFB6C98; assign wn_im[154] = 32'h9842F043; // 154 0.586 -0.810 +assign wn_re[155] = 32'h4A581C9E; assign wn_im[155] = 32'h97CDA855; // 155 0.581 -0.814 +assign wn_re[156] = 32'h49B41533; assign wn_im[156] = 32'h9759617F; // 156 0.576 -0.818 +assign wn_re[157] = 32'h490F57EE; assign wn_im[157] = 32'h96E61CE0; // 157 0.571 -0.821 +assign wn_re[158] = 32'h4869E665; assign wn_im[158] = 32'h9673DB94; // 158 0.566 -0.825 +assign wn_re[159] = 32'h47C3C22F; assign wn_im[159] = 32'h96029EB6; // 159 0.561 -0.828 +assign wn_re[160] = 32'h471CECE7; assign wn_im[160] = 32'h9592675C; // 160 0.556 -0.831 +assign wn_re[161] = 32'h46756828; assign wn_im[161] = 32'h9523369C; // 161 0.550 -0.835 +assign wn_re[162] = 32'h45CD358F; assign wn_im[162] = 32'h94B50D87; // 162 0.545 -0.838 +assign wn_re[163] = 32'h452456BD; assign wn_im[163] = 32'h9447ED2F; // 163 0.540 -0.842 +assign wn_re[164] = 32'h447ACD50; assign wn_im[164] = 32'h93DBD6A0; // 164 0.535 -0.845 +assign wn_re[165] = 32'h43D09AED; assign wn_im[165] = 32'h9370CAE4; // 165 0.530 -0.848 +assign wn_re[166] = 32'h4325C135; assign wn_im[166] = 32'h9306CB04; // 166 0.525 -0.851 +assign wn_re[167] = 32'h427A41D0; assign wn_im[167] = 32'h929DD806; // 167 0.519 -0.855 +assign wn_re[168] = 32'h41CE1E65; assign wn_im[168] = 32'h9235F2EC; // 168 0.514 -0.858 +assign wn_re[169] = 32'h4121589B; assign wn_im[169] = 32'h91CF1CB6; // 169 0.509 -0.861 +assign wn_re[170] = 32'h4073F21D; assign wn_im[170] = 32'h91695663; // 170 0.504 -0.864 +assign wn_re[171] = 32'h3FC5EC98; assign wn_im[171] = 32'h9104A0EE; // 171 0.498 -0.867 +assign wn_re[172] = 32'h3F1749B8; assign wn_im[172] = 32'h90A0FD4E; // 172 0.493 -0.870 +assign wn_re[173] = 32'h3E680B2C; assign wn_im[173] = 32'h903E6C7B; // 173 0.488 -0.873 +assign wn_re[174] = 32'h3DB832A6; assign wn_im[174] = 32'h8FDCEF66; // 174 0.482 -0.876 +assign wn_re[175] = 32'h3D07C1D6; assign wn_im[175] = 32'h8F7C8701; // 175 0.477 -0.879 +assign wn_re[176] = 32'h3C56BA70; assign wn_im[176] = 32'h8F1D343A; // 176 0.471 -0.882 +assign wn_re[177] = 32'h3BA51E29; assign wn_im[177] = 32'h8EBEF7FB; // 177 0.466 -0.885 +assign wn_re[178] = 32'h3AF2EEB7; assign wn_im[178] = 32'h8E61D32E; // 178 0.461 -0.888 +assign wn_re[179] = 32'h3A402DD2; assign wn_im[179] = 32'h8E05C6B7; // 179 0.455 -0.890 +assign wn_re[180] = 32'h398CDD32; assign wn_im[180] = 32'h8DAAD37B; // 180 0.450 -0.893 +assign wn_re[181] = 32'h38D8FE93; assign wn_im[181] = 32'h8D50FA59; // 181 0.444 -0.896 +assign wn_re[182] = 32'h382493B0; assign wn_im[182] = 32'h8CF83C30; // 182 0.439 -0.899 +assign wn_re[183] = 32'h376F9E46; assign wn_im[183] = 32'h8CA099DA; // 183 0.433 -0.901 +assign wn_re[184] = 32'h36BA2014; assign wn_im[184] = 32'h8C4A142F; // 184 0.428 -0.904 +assign wn_re[185] = 32'h36041AD9; assign wn_im[185] = 32'h8BF4AC05; // 185 0.422 -0.907 +assign wn_re[186] = 32'h354D9057; assign wn_im[186] = 32'h8BA0622F; // 186 0.416 -0.909 +assign wn_re[187] = 32'h34968250; assign wn_im[187] = 32'h8B4D377C; // 187 0.411 -0.912 +assign wn_re[188] = 32'h33DEF287; assign wn_im[188] = 32'h8AFB2CBB; // 188 0.405 -0.914 +assign wn_re[189] = 32'h3326E2C3; assign wn_im[189] = 32'h8AAA42B4; // 189 0.400 -0.917 +assign wn_re[190] = 32'h326E54C7; assign wn_im[190] = 32'h8A5A7A31; // 190 0.394 -0.919 +assign wn_re[191] = 32'h31B54A5E; assign wn_im[191] = 32'h8A0BD3F5; // 191 0.388 -0.922 +assign wn_re[192] = 32'h30FBC54D; assign wn_im[192] = 32'h89BE50C3; // 192 0.383 -0.924 +assign wn_re[193] = 32'h3041C761; assign wn_im[193] = 32'h8971F15A; // 193 0.377 -0.926 +assign wn_re[194] = 32'h2F875262; assign wn_im[194] = 32'h8926B677; // 194 0.371 -0.929 +assign wn_re[195] = 32'h2ECC681E; assign wn_im[195] = 32'h88DCA0D3; // 195 0.366 -0.931 +assign wn_re[196] = 32'h2E110A62; assign wn_im[196] = 32'h8893B125; // 196 0.360 -0.933 +assign wn_re[197] = 32'h2D553AFC; assign wn_im[197] = 32'h884BE821; // 197 0.354 -0.935 +assign wn_re[198] = 32'h2C98FBBA; assign wn_im[198] = 32'h88054677; // 198 0.348 -0.937 +assign wn_re[199] = 32'h2BDC4E6F; assign wn_im[199] = 32'h87BFCCD7; // 199 0.343 -0.939 +assign wn_re[200] = 32'h2B1F34EB; assign wn_im[200] = 32'h877B7BEC; // 200 0.337 -0.942 +assign wn_re[201] = 32'h2A61B101; assign wn_im[201] = 32'h8738545E; // 201 0.331 -0.944 +assign wn_re[202] = 32'h29A3C485; assign wn_im[202] = 32'h86F656D3; // 202 0.325 -0.946 +assign wn_re[203] = 32'h28E5714B; assign wn_im[203] = 32'h86B583EE; // 203 0.320 -0.948 +assign wn_re[204] = 32'h2826B928; assign wn_im[204] = 32'h8675DC4F; // 204 0.314 -0.950 +assign wn_re[205] = 32'h27679DF4; assign wn_im[205] = 32'h86376092; // 205 0.308 -0.951 +assign wn_re[206] = 32'h26A82186; assign wn_im[206] = 32'h85FA1153; // 206 0.302 -0.953 +assign wn_re[207] = 32'h25E845B6; assign wn_im[207] = 32'h85BDEF28; // 207 0.296 -0.955 +assign wn_re[208] = 32'h25280C5E; assign wn_im[208] = 32'h8582FAA5; // 208 0.290 -0.957 +assign wn_re[209] = 32'h24677758; assign wn_im[209] = 32'h8549345C; // 209 0.284 -0.959 +assign wn_re[210] = 32'h23A6887F; assign wn_im[210] = 32'h85109CDD; // 210 0.279 -0.960 +assign wn_re[211] = 32'h22E541AF; assign wn_im[211] = 32'h84D934B1; // 211 0.273 -0.962 +assign wn_re[212] = 32'h2223A4C5; assign wn_im[212] = 32'h84A2FC62; // 212 0.267 -0.964 +assign wn_re[213] = 32'h2161B3A0; assign wn_im[213] = 32'h846DF477; // 213 0.261 -0.965 +assign wn_re[214] = 32'h209F701C; assign wn_im[214] = 32'h843A1D70; // 214 0.255 -0.967 +assign wn_re[215] = 32'h1FDCDC1B; assign wn_im[215] = 32'h840777D0; // 215 0.249 -0.969 +assign wn_re[216] = 32'h1F19F97B; assign wn_im[216] = 32'h83D60412; // 216 0.243 -0.970 +assign wn_re[217] = 32'h1E56CA1E; assign wn_im[217] = 32'h83A5C2B0; // 217 0.237 -0.972 +assign wn_re[218] = 32'h1D934FE5; assign wn_im[218] = 32'h8376B422; // 218 0.231 -0.973 +assign wn_re[219] = 32'h1CCF8CB3; assign wn_im[219] = 32'h8348D8DC; // 219 0.225 -0.974 +assign wn_re[220] = 32'h1C0B826A; assign wn_im[220] = 32'h831C314E; // 220 0.219 -0.976 +assign wn_re[221] = 32'h1B4732EF; assign wn_im[221] = 32'h82F0BDE8; // 221 0.213 -0.977 +assign wn_re[222] = 32'h1A82A026; assign wn_im[222] = 32'h82C67F14; // 222 0.207 -0.978 +assign wn_re[223] = 32'h19BDCBF3; assign wn_im[223] = 32'h829D753A; // 223 0.201 -0.980 +assign wn_re[224] = 32'h18F8B83C; assign wn_im[224] = 32'h8275A0C0; // 224 0.195 -0.981 +assign wn_re[225] = 32'h183366E9; assign wn_im[225] = 32'h824F0208; // 225 0.189 -0.982 +assign wn_re[226] = 32'h176DD9DE; assign wn_im[226] = 32'h82299971; // 226 0.183 -0.983 +assign wn_re[227] = 32'h16A81305; assign wn_im[227] = 32'h82056758; // 227 0.177 -0.984 +assign wn_re[228] = 32'h15E21445; assign wn_im[228] = 32'h81E26C16; // 228 0.171 -0.985 +assign wn_re[229] = 32'h151BDF86; assign wn_im[229] = 32'h81C0A801; // 229 0.165 -0.986 +assign wn_re[230] = 32'h145576B1; assign wn_im[230] = 32'h81A01B6D; // 230 0.159 -0.987 +assign wn_re[231] = 32'h138EDBB1; assign wn_im[231] = 32'h8180C6A9; // 231 0.153 -0.988 +assign wn_re[232] = 32'h12C8106F; assign wn_im[232] = 32'h8162AA04; // 232 0.147 -0.989 +assign wn_re[233] = 32'h120116D5; assign wn_im[233] = 32'h8145C5C7; // 233 0.141 -0.990 +assign wn_re[234] = 32'h1139F0CF; assign wn_im[234] = 32'h812A1A3A; // 234 0.135 -0.991 +assign wn_re[235] = 32'h1072A048; assign wn_im[235] = 32'h810FA7A0; // 235 0.128 -0.992 +assign wn_re[236] = 32'h0FAB272B; assign wn_im[236] = 32'h80F66E3C; // 236 0.122 -0.992 +assign wn_re[237] = 32'h0EE38766; assign wn_im[237] = 32'h80DE6E4C; // 237 0.116 -0.993 +assign wn_re[238] = 32'h0E1BC2E4; assign wn_im[238] = 32'h80C7A80A; // 238 0.110 -0.994 +assign wn_re[239] = 32'h0D53DB92; assign wn_im[239] = 32'h80B21BAF; // 239 0.104 -0.995 +assign wn_re[240] = 32'h0C8BD35E; assign wn_im[240] = 32'h809DC971; // 240 0.098 -0.995 +assign wn_re[241] = 32'h0BC3AC35; assign wn_im[241] = 32'h808AB180; // 241 0.092 -0.996 +assign wn_re[242] = 32'h0AFB6805; assign wn_im[242] = 32'h8078D40D; // 242 0.086 -0.996 +assign wn_re[243] = 32'h0A3308BD; assign wn_im[243] = 32'h80683143; // 243 0.080 -0.997 +assign wn_re[244] = 32'h096A9049; assign wn_im[244] = 32'h8058C94C; // 244 0.074 -0.997 +assign wn_re[245] = 32'h08A2009A; assign wn_im[245] = 32'h804A9C4D; // 245 0.067 -0.998 +assign wn_re[246] = 32'h07D95B9E; assign wn_im[246] = 32'h803DAA6A; // 246 0.061 -0.998 +assign wn_re[247] = 32'h0710A345; assign wn_im[247] = 32'h8031F3C2; // 247 0.055 -0.998 +assign wn_re[248] = 32'h0647D97C; assign wn_im[248] = 32'h80277872; // 248 0.049 -0.999 +assign wn_re[249] = 32'h057F0035; assign wn_im[249] = 32'h801E3895; // 249 0.043 -0.999 +assign wn_re[250] = 32'h04B6195D; assign wn_im[250] = 32'h80163440; // 250 0.037 -0.999 +assign wn_re[251] = 32'h03ED26E6; assign wn_im[251] = 32'h800F6B88; // 251 0.031 -1.000 +assign wn_re[252] = 32'h03242ABF; assign wn_im[252] = 32'h8009DE7E; // 252 0.025 -1.000 +assign wn_re[253] = 32'h025B26D7; assign wn_im[253] = 32'h80058D2F; // 253 0.018 -1.000 +assign wn_re[254] = 32'h01921D20; assign wn_im[254] = 32'h800277A6; // 254 0.012 -1.000 +assign wn_re[255] = 32'h00C90F88; assign wn_im[255] = 32'h80009DEA; // 255 0.006 -1.000 +assign wn_re[256] = 32'h00000000; assign wn_im[256] = 32'h80000000; // 256 0.000 -1.000 +assign wn_re[257] = 32'hxxxxxxxx; assign wn_im[257] = 32'hxxxxxxxx; // 257 -0.006 -1.000 +assign wn_re[258] = 32'hFE6DE2E0; assign wn_im[258] = 32'h800277A6; // 258 -0.012 -1.000 +assign wn_re[259] = 32'hxxxxxxxx; assign wn_im[259] = 32'hxxxxxxxx; // 259 -0.018 -1.000 +assign wn_re[260] = 32'hFCDBD541; assign wn_im[260] = 32'h8009DE7E; // 260 -0.025 -1.000 +assign wn_re[261] = 32'hFC12D91A; assign wn_im[261] = 32'h800F6B88; // 261 -0.031 -1.000 +assign wn_re[262] = 32'hFB49E6A3; assign wn_im[262] = 32'h80163440; // 262 -0.037 -0.999 +assign wn_re[263] = 32'hxxxxxxxx; assign wn_im[263] = 32'hxxxxxxxx; // 263 -0.043 -0.999 +assign wn_re[264] = 32'hF9B82684; assign wn_im[264] = 32'h80277872; // 264 -0.049 -0.999 +assign wn_re[265] = 32'hxxxxxxxx; assign wn_im[265] = 32'hxxxxxxxx; // 265 -0.055 -0.998 +assign wn_re[266] = 32'hF826A462; assign wn_im[266] = 32'h803DAA6A; // 266 -0.061 -0.998 +assign wn_re[267] = 32'hF75DFF66; assign wn_im[267] = 32'h804A9C4D; // 267 -0.067 -0.998 +assign wn_re[268] = 32'hF6956FB7; assign wn_im[268] = 32'h8058C94C; // 268 -0.074 -0.997 +assign wn_re[269] = 32'hxxxxxxxx; assign wn_im[269] = 32'hxxxxxxxx; // 269 -0.080 -0.997 +assign wn_re[270] = 32'hF50497FB; assign wn_im[270] = 32'h8078D40D; // 270 -0.086 -0.996 +assign wn_re[271] = 32'hxxxxxxxx; assign wn_im[271] = 32'hxxxxxxxx; // 271 -0.092 -0.996 +assign wn_re[272] = 32'hF3742CA2; assign wn_im[272] = 32'h809DC971; // 272 -0.098 -0.995 +assign wn_re[273] = 32'hF2AC246E; assign wn_im[273] = 32'h80B21BAF; // 273 -0.104 -0.995 +assign wn_re[274] = 32'hF1E43D1C; assign wn_im[274] = 32'h80C7A80A; // 274 -0.110 -0.994 +assign wn_re[275] = 32'hxxxxxxxx; assign wn_im[275] = 32'hxxxxxxxx; // 275 -0.116 -0.993 +assign wn_re[276] = 32'hF054D8D5; assign wn_im[276] = 32'h80F66E3C; // 276 -0.122 -0.992 +assign wn_re[277] = 32'hxxxxxxxx; assign wn_im[277] = 32'hxxxxxxxx; // 277 -0.128 -0.992 +assign wn_re[278] = 32'hEEC60F31; assign wn_im[278] = 32'h812A1A3A; // 278 -0.135 -0.991 +assign wn_re[279] = 32'hEDFEE92B; assign wn_im[279] = 32'h8145C5C7; // 279 -0.141 -0.990 +assign wn_re[280] = 32'hED37EF91; assign wn_im[280] = 32'h8162AA04; // 280 -0.147 -0.989 +assign wn_re[281] = 32'hxxxxxxxx; assign wn_im[281] = 32'hxxxxxxxx; // 281 -0.153 -0.988 +assign wn_re[282] = 32'hEBAA894F; assign wn_im[282] = 32'h81A01B6D; // 282 -0.159 -0.987 +assign wn_re[283] = 32'hxxxxxxxx; assign wn_im[283] = 32'hxxxxxxxx; // 283 -0.165 -0.986 +assign wn_re[284] = 32'hEA1DEBBB; assign wn_im[284] = 32'h81E26C16; // 284 -0.171 -0.985 +assign wn_re[285] = 32'hE957ECFB; assign wn_im[285] = 32'h82056758; // 285 -0.177 -0.984 +assign wn_re[286] = 32'hE8922622; assign wn_im[286] = 32'h82299971; // 286 -0.183 -0.983 +assign wn_re[287] = 32'hxxxxxxxx; assign wn_im[287] = 32'hxxxxxxxx; // 287 -0.189 -0.982 +assign wn_re[288] = 32'hE70747C4; assign wn_im[288] = 32'h8275A0C0; // 288 -0.195 -0.981 +assign wn_re[289] = 32'hxxxxxxxx; assign wn_im[289] = 32'hxxxxxxxx; // 289 -0.201 -0.980 +assign wn_re[290] = 32'hE57D5FDA; assign wn_im[290] = 32'h82C67F14; // 290 -0.207 -0.978 +assign wn_re[291] = 32'hE4B8CD11; assign wn_im[291] = 32'h82F0BDE8; // 291 -0.213 -0.977 +assign wn_re[292] = 32'hE3F47D96; assign wn_im[292] = 32'h831C314E; // 292 -0.219 -0.976 +assign wn_re[293] = 32'hxxxxxxxx; assign wn_im[293] = 32'hxxxxxxxx; // 293 -0.225 -0.974 +assign wn_re[294] = 32'hE26CB01B; assign wn_im[294] = 32'h8376B422; // 294 -0.231 -0.973 +assign wn_re[295] = 32'hxxxxxxxx; assign wn_im[295] = 32'hxxxxxxxx; // 295 -0.237 -0.972 +assign wn_re[296] = 32'hE0E60685; assign wn_im[296] = 32'h83D60412; // 296 -0.243 -0.970 +assign wn_re[297] = 32'hE02323E5; assign wn_im[297] = 32'h840777D0; // 297 -0.249 -0.969 +assign wn_re[298] = 32'hDF608FE4; assign wn_im[298] = 32'h843A1D70; // 298 -0.255 -0.967 +assign wn_re[299] = 32'hxxxxxxxx; assign wn_im[299] = 32'hxxxxxxxx; // 299 -0.261 -0.965 +assign wn_re[300] = 32'hDDDC5B3B; assign wn_im[300] = 32'h84A2FC62; // 300 -0.267 -0.964 +assign wn_re[301] = 32'hxxxxxxxx; assign wn_im[301] = 32'hxxxxxxxx; // 301 -0.273 -0.962 +assign wn_re[302] = 32'hDC597781; assign wn_im[302] = 32'h85109CDD; // 302 -0.279 -0.960 +assign wn_re[303] = 32'hDB9888A8; assign wn_im[303] = 32'h8549345C; // 303 -0.284 -0.959 +assign wn_re[304] = 32'hDAD7F3A2; assign wn_im[304] = 32'h8582FAA5; // 304 -0.290 -0.957 +assign wn_re[305] = 32'hxxxxxxxx; assign wn_im[305] = 32'hxxxxxxxx; // 305 -0.296 -0.955 +assign wn_re[306] = 32'hD957DE7A; assign wn_im[306] = 32'h85FA1153; // 306 -0.302 -0.953 +assign wn_re[307] = 32'hxxxxxxxx; assign wn_im[307] = 32'hxxxxxxxx; // 307 -0.308 -0.951 +assign wn_re[308] = 32'hD7D946D8; assign wn_im[308] = 32'h8675DC4F; // 308 -0.314 -0.950 +assign wn_re[309] = 32'hD71A8EB5; assign wn_im[309] = 32'h86B583EE; // 309 -0.320 -0.948 +assign wn_re[310] = 32'hD65C3B7B; assign wn_im[310] = 32'h86F656D3; // 310 -0.325 -0.946 +assign wn_re[311] = 32'hxxxxxxxx; assign wn_im[311] = 32'hxxxxxxxx; // 311 -0.331 -0.944 +assign wn_re[312] = 32'hD4E0CB15; assign wn_im[312] = 32'h877B7BEC; // 312 -0.337 -0.942 +assign wn_re[313] = 32'hxxxxxxxx; assign wn_im[313] = 32'hxxxxxxxx; // 313 -0.343 -0.939 +assign wn_re[314] = 32'hD3670446; assign wn_im[314] = 32'h88054677; // 314 -0.348 -0.937 +assign wn_re[315] = 32'hD2AAC504; assign wn_im[315] = 32'h884BE821; // 315 -0.354 -0.935 +assign wn_re[316] = 32'hD1EEF59E; assign wn_im[316] = 32'h8893B125; // 316 -0.360 -0.933 +assign wn_re[317] = 32'hxxxxxxxx; assign wn_im[317] = 32'hxxxxxxxx; // 317 -0.366 -0.931 +assign wn_re[318] = 32'hD078AD9E; assign wn_im[318] = 32'h8926B677; // 318 -0.371 -0.929 +assign wn_re[319] = 32'hxxxxxxxx; assign wn_im[319] = 32'hxxxxxxxx; // 319 -0.377 -0.926 +assign wn_re[320] = 32'hCF043AB3; assign wn_im[320] = 32'h89BE50C3; // 320 -0.383 -0.924 +assign wn_re[321] = 32'hCE4AB5A2; assign wn_im[321] = 32'h8A0BD3F5; // 321 -0.388 -0.922 +assign wn_re[322] = 32'hCD91AB39; assign wn_im[322] = 32'h8A5A7A31; // 322 -0.394 -0.919 +assign wn_re[323] = 32'hxxxxxxxx; assign wn_im[323] = 32'hxxxxxxxx; // 323 -0.400 -0.917 +assign wn_re[324] = 32'hCC210D79; assign wn_im[324] = 32'h8AFB2CBB; // 324 -0.405 -0.914 +assign wn_re[325] = 32'hxxxxxxxx; assign wn_im[325] = 32'hxxxxxxxx; // 325 -0.411 -0.912 +assign wn_re[326] = 32'hCAB26FA9; assign wn_im[326] = 32'h8BA0622F; // 326 -0.416 -0.909 +assign wn_re[327] = 32'hC9FBE527; assign wn_im[327] = 32'h8BF4AC05; // 327 -0.422 -0.907 +assign wn_re[328] = 32'hC945DFEC; assign wn_im[328] = 32'h8C4A142F; // 328 -0.428 -0.904 +assign wn_re[329] = 32'hxxxxxxxx; assign wn_im[329] = 32'hxxxxxxxx; // 329 -0.433 -0.901 +assign wn_re[330] = 32'hC7DB6C50; assign wn_im[330] = 32'h8CF83C30; // 330 -0.439 -0.899 +assign wn_re[331] = 32'hxxxxxxxx; assign wn_im[331] = 32'hxxxxxxxx; // 331 -0.444 -0.896 +assign wn_re[332] = 32'hC67322CE; assign wn_im[332] = 32'h8DAAD37B; // 332 -0.450 -0.893 +assign wn_re[333] = 32'hC5BFD22E; assign wn_im[333] = 32'h8E05C6B7; // 333 -0.455 -0.890 +assign wn_re[334] = 32'hC50D1149; assign wn_im[334] = 32'h8E61D32E; // 334 -0.461 -0.888 +assign wn_re[335] = 32'hxxxxxxxx; assign wn_im[335] = 32'hxxxxxxxx; // 335 -0.466 -0.885 +assign wn_re[336] = 32'hC3A94590; assign wn_im[336] = 32'h8F1D343A; // 336 -0.471 -0.882 +assign wn_re[337] = 32'hxxxxxxxx; assign wn_im[337] = 32'hxxxxxxxx; // 337 -0.477 -0.879 +assign wn_re[338] = 32'hC247CD5A; assign wn_im[338] = 32'h8FDCEF66; // 338 -0.482 -0.876 +assign wn_re[339] = 32'hC197F4D4; assign wn_im[339] = 32'h903E6C7B; // 339 -0.488 -0.873 +assign wn_re[340] = 32'hC0E8B648; assign wn_im[340] = 32'h90A0FD4E; // 340 -0.493 -0.870 +assign wn_re[341] = 32'hxxxxxxxx; assign wn_im[341] = 32'hxxxxxxxx; // 341 -0.498 -0.867 +assign wn_re[342] = 32'hBF8C0DE3; assign wn_im[342] = 32'h91695663; // 342 -0.504 -0.864 +assign wn_re[343] = 32'hxxxxxxxx; assign wn_im[343] = 32'hxxxxxxxx; // 343 -0.509 -0.861 +assign wn_re[344] = 32'hBE31E19B; assign wn_im[344] = 32'h9235F2EC; // 344 -0.514 -0.858 +assign wn_re[345] = 32'hBD85BE30; assign wn_im[345] = 32'h929DD806; // 345 -0.519 -0.855 +assign wn_re[346] = 32'hBCDA3ECB; assign wn_im[346] = 32'h9306CB04; // 346 -0.525 -0.851 +assign wn_re[347] = 32'hxxxxxxxx; assign wn_im[347] = 32'hxxxxxxxx; // 347 -0.530 -0.848 +assign wn_re[348] = 32'hBB8532B0; assign wn_im[348] = 32'h93DBD6A0; // 348 -0.535 -0.845 +assign wn_re[349] = 32'hxxxxxxxx; assign wn_im[349] = 32'hxxxxxxxx; // 349 -0.540 -0.842 +assign wn_re[350] = 32'hBA32CA71; assign wn_im[350] = 32'h94B50D87; // 350 -0.545 -0.838 +assign wn_re[351] = 32'hB98A97D8; assign wn_im[351] = 32'h9523369C; // 351 -0.550 -0.835 +assign wn_re[352] = 32'hB8E31319; assign wn_im[352] = 32'h9592675C; // 352 -0.556 -0.831 +assign wn_re[353] = 32'hxxxxxxxx; assign wn_im[353] = 32'hxxxxxxxx; // 353 -0.561 -0.828 +assign wn_re[354] = 32'hB796199B; assign wn_im[354] = 32'h9673DB94; // 354 -0.566 -0.825 +assign wn_re[355] = 32'hxxxxxxxx; assign wn_im[355] = 32'hxxxxxxxx; // 355 -0.571 -0.821 +assign wn_re[356] = 32'hB64BEACD; assign wn_im[356] = 32'h9759617F; // 356 -0.576 -0.818 +assign wn_re[357] = 32'hB5A7E362; assign wn_im[357] = 32'h97CDA855; // 357 -0.581 -0.814 +assign wn_re[358] = 32'hB5049368; assign wn_im[358] = 32'h9842F043; // 358 -0.586 -0.810 +assign wn_re[359] = 32'hxxxxxxxx; assign wn_im[359] = 32'hxxxxxxxx; // 359 -0.591 -0.807 +assign wn_re[360] = 32'hB3C0200C; assign wn_im[360] = 32'h99307EE0; // 360 -0.596 -0.803 +assign wn_re[361] = 32'hxxxxxxxx; assign wn_im[361] = 32'hxxxxxxxx; // 361 -0.601 -0.800 +assign wn_re[362] = 32'hB27E9D3C; assign wn_im[362] = 32'h9A22042D; // 362 -0.606 -0.796 +assign wn_re[363] = 32'hB1DEF9E9; assign wn_im[363] = 32'h9A9C406E; // 363 -0.610 -0.792 +assign wn_re[364] = 32'hB140175B; assign wn_im[364] = 32'h9B1776DA; // 364 -0.615 -0.788 +assign wn_re[365] = 32'hxxxxxxxx; assign wn_im[365] = 32'hxxxxxxxx; // 365 -0.620 -0.785 +assign wn_re[366] = 32'hB0049AB3; assign wn_im[366] = 32'h9C10CD70; // 366 -0.625 -0.781 +assign wn_re[367] = 32'hxxxxxxxx; assign wn_im[367] = 32'hxxxxxxxx; // 367 -0.630 -0.777 +assign wn_re[368] = 32'hAECC336C; assign wn_im[368] = 32'h9D0DFE54; // 368 -0.634 -0.773 +assign wn_re[369] = 32'hAE312B92; assign wn_im[369] = 32'h9D8E0597; // 369 -0.639 -0.769 +assign wn_re[370] = 32'hAD96ED92; assign wn_im[370] = 32'h9E0EFFC1; // 370 -0.644 -0.765 +assign wn_re[371] = 32'hxxxxxxxx; assign wn_im[371] = 32'hxxxxxxxx; // 371 -0.649 -0.761 +assign wn_re[372] = 32'hAC64D510; assign wn_im[372] = 32'h9F13C7D0; // 372 -0.653 -0.757 +assign wn_re[373] = 32'hxxxxxxxx; assign wn_im[373] = 32'hxxxxxxxx; // 373 -0.658 -0.753 +assign wn_re[374] = 32'hAB35F5B5; assign wn_im[374] = 32'hA01C4C73; // 374 -0.662 -0.749 +assign wn_re[375] = 32'hAA9FBF1E; assign wn_im[375] = 32'hA0A1F24D; // 375 -0.667 -0.745 +assign wn_re[376] = 32'hAA0A5B2E; assign wn_im[376] = 32'hA1288376; // 376 -0.672 -0.741 +assign wn_re[377] = 32'hxxxxxxxx; assign wn_im[377] = 32'hxxxxxxxx; // 377 -0.676 -0.737 +assign wn_re[378] = 32'hA8E21106; assign wn_im[378] = 32'hA2386284; // 378 -0.681 -0.733 +assign wn_re[379] = 32'hxxxxxxxx; assign wn_im[379] = 32'hxxxxxxxx; // 379 -0.685 -0.728 +assign wn_re[380] = 32'hA7BD22AC; assign wn_im[380] = 32'hA34BDF20; // 380 -0.690 -0.724 +assign wn_re[381] = 32'hA72BF174; assign wn_im[381] = 32'hA3D6F534; // 381 -0.694 -0.720 +assign wn_re[382] = 32'hA69B9B68; assign wn_im[382] = 32'hA462EEAC; // 382 -0.698 -0.716 +assign wn_re[383] = 32'hxxxxxxxx; assign wn_im[383] = 32'hxxxxxxxx; // 383 -0.703 -0.711 +assign wn_re[384] = 32'hA57D8666; assign wn_im[384] = 32'hA57D8666; // 384 -0.707 -0.707 +assign wn_re[385] = 32'hxxxxxxxx; assign wn_im[385] = 32'hxxxxxxxx; // 385 -0.711 -0.703 +assign wn_re[386] = 32'hA462EEAC; assign wn_im[386] = 32'hA69B9B68; // 386 -0.716 -0.698 +assign wn_re[387] = 32'hA3D6F534; assign wn_im[387] = 32'hA72BF174; // 387 -0.720 -0.694 +assign wn_re[388] = 32'hA34BDF20; assign wn_im[388] = 32'hA7BD22AC; // 388 -0.724 -0.690 +assign wn_re[389] = 32'hxxxxxxxx; assign wn_im[389] = 32'hxxxxxxxx; // 389 -0.728 -0.685 +assign wn_re[390] = 32'hA2386284; assign wn_im[390] = 32'hA8E21106; // 390 -0.733 -0.681 +assign wn_re[391] = 32'hxxxxxxxx; assign wn_im[391] = 32'hxxxxxxxx; // 391 -0.737 -0.676 +assign wn_re[392] = 32'hA1288376; assign wn_im[392] = 32'hAA0A5B2E; // 392 -0.741 -0.672 +assign wn_re[393] = 32'hA0A1F24D; assign wn_im[393] = 32'hAA9FBF1E; // 393 -0.745 -0.667 +assign wn_re[394] = 32'hA01C4C73; assign wn_im[394] = 32'hAB35F5B5; // 394 -0.749 -0.662 +assign wn_re[395] = 32'hxxxxxxxx; assign wn_im[395] = 32'hxxxxxxxx; // 395 -0.753 -0.658 +assign wn_re[396] = 32'h9F13C7D0; assign wn_im[396] = 32'hAC64D510; // 396 -0.757 -0.653 +assign wn_re[397] = 32'hxxxxxxxx; assign wn_im[397] = 32'hxxxxxxxx; // 397 -0.761 -0.649 +assign wn_re[398] = 32'h9E0EFFC1; assign wn_im[398] = 32'hAD96ED92; // 398 -0.765 -0.644 +assign wn_re[399] = 32'h9D8E0597; assign wn_im[399] = 32'hAE312B92; // 399 -0.769 -0.639 +assign wn_re[400] = 32'h9D0DFE54; assign wn_im[400] = 32'hAECC336C; // 400 -0.773 -0.634 +assign wn_re[401] = 32'hxxxxxxxx; assign wn_im[401] = 32'hxxxxxxxx; // 401 -0.777 -0.630 +assign wn_re[402] = 32'h9C10CD70; assign wn_im[402] = 32'hB0049AB3; // 402 -0.781 -0.625 +assign wn_re[403] = 32'hxxxxxxxx; assign wn_im[403] = 32'hxxxxxxxx; // 403 -0.785 -0.620 +assign wn_re[404] = 32'h9B1776DA; assign wn_im[404] = 32'hB140175B; // 404 -0.788 -0.615 +assign wn_re[405] = 32'h9A9C406E; assign wn_im[405] = 32'hB1DEF9E9; // 405 -0.792 -0.610 +assign wn_re[406] = 32'h9A22042D; assign wn_im[406] = 32'hB27E9D3C; // 406 -0.796 -0.606 +assign wn_re[407] = 32'hxxxxxxxx; assign wn_im[407] = 32'hxxxxxxxx; // 407 -0.800 -0.601 +assign wn_re[408] = 32'h99307EE0; assign wn_im[408] = 32'hB3C0200C; // 408 -0.803 -0.596 +assign wn_re[409] = 32'hxxxxxxxx; assign wn_im[409] = 32'hxxxxxxxx; // 409 -0.807 -0.591 +assign wn_re[410] = 32'h9842F043; assign wn_im[410] = 32'hB5049368; // 410 -0.810 -0.586 +assign wn_re[411] = 32'h97CDA855; assign wn_im[411] = 32'hB5A7E362; // 411 -0.814 -0.581 +assign wn_re[412] = 32'h9759617F; assign wn_im[412] = 32'hB64BEACD; // 412 -0.818 -0.576 +assign wn_re[413] = 32'hxxxxxxxx; assign wn_im[413] = 32'hxxxxxxxx; // 413 -0.821 -0.571 +assign wn_re[414] = 32'h9673DB94; assign wn_im[414] = 32'hB796199B; // 414 -0.825 -0.566 +assign wn_re[415] = 32'hxxxxxxxx; assign wn_im[415] = 32'hxxxxxxxx; // 415 -0.828 -0.561 +assign wn_re[416] = 32'h9592675C; assign wn_im[416] = 32'hB8E31319; // 416 -0.831 -0.556 +assign wn_re[417] = 32'h9523369C; assign wn_im[417] = 32'hB98A97D8; // 417 -0.835 -0.550 +assign wn_re[418] = 32'h94B50D87; assign wn_im[418] = 32'hBA32CA71; // 418 -0.838 -0.545 +assign wn_re[419] = 32'hxxxxxxxx; assign wn_im[419] = 32'hxxxxxxxx; // 419 -0.842 -0.540 +assign wn_re[420] = 32'h93DBD6A0; assign wn_im[420] = 32'hBB8532B0; // 420 -0.845 -0.535 +assign wn_re[421] = 32'hxxxxxxxx; assign wn_im[421] = 32'hxxxxxxxx; // 421 -0.848 -0.530 +assign wn_re[422] = 32'h9306CB04; assign wn_im[422] = 32'hBCDA3ECB; // 422 -0.851 -0.525 +assign wn_re[423] = 32'h929DD806; assign wn_im[423] = 32'hBD85BE30; // 423 -0.855 -0.519 +assign wn_re[424] = 32'h9235F2EC; assign wn_im[424] = 32'hBE31E19B; // 424 -0.858 -0.514 +assign wn_re[425] = 32'hxxxxxxxx; assign wn_im[425] = 32'hxxxxxxxx; // 425 -0.861 -0.509 +assign wn_re[426] = 32'h91695663; assign wn_im[426] = 32'hBF8C0DE3; // 426 -0.864 -0.504 +assign wn_re[427] = 32'hxxxxxxxx; assign wn_im[427] = 32'hxxxxxxxx; // 427 -0.867 -0.498 +assign wn_re[428] = 32'h90A0FD4E; assign wn_im[428] = 32'hC0E8B648; // 428 -0.870 -0.493 +assign wn_re[429] = 32'h903E6C7B; assign wn_im[429] = 32'hC197F4D4; // 429 -0.873 -0.488 +assign wn_re[430] = 32'h8FDCEF66; assign wn_im[430] = 32'hC247CD5A; // 430 -0.876 -0.482 +assign wn_re[431] = 32'hxxxxxxxx; assign wn_im[431] = 32'hxxxxxxxx; // 431 -0.879 -0.477 +assign wn_re[432] = 32'h8F1D343A; assign wn_im[432] = 32'hC3A94590; // 432 -0.882 -0.471 +assign wn_re[433] = 32'hxxxxxxxx; assign wn_im[433] = 32'hxxxxxxxx; // 433 -0.885 -0.466 +assign wn_re[434] = 32'h8E61D32E; assign wn_im[434] = 32'hC50D1149; // 434 -0.888 -0.461 +assign wn_re[435] = 32'h8E05C6B7; assign wn_im[435] = 32'hC5BFD22E; // 435 -0.890 -0.455 +assign wn_re[436] = 32'h8DAAD37B; assign wn_im[436] = 32'hC67322CE; // 436 -0.893 -0.450 +assign wn_re[437] = 32'hxxxxxxxx; assign wn_im[437] = 32'hxxxxxxxx; // 437 -0.896 -0.444 +assign wn_re[438] = 32'h8CF83C30; assign wn_im[438] = 32'hC7DB6C50; // 438 -0.899 -0.439 +assign wn_re[439] = 32'hxxxxxxxx; assign wn_im[439] = 32'hxxxxxxxx; // 439 -0.901 -0.433 +assign wn_re[440] = 32'h8C4A142F; assign wn_im[440] = 32'hC945DFEC; // 440 -0.904 -0.428 +assign wn_re[441] = 32'h8BF4AC05; assign wn_im[441] = 32'hC9FBE527; // 441 -0.907 -0.422 +assign wn_re[442] = 32'h8BA0622F; assign wn_im[442] = 32'hCAB26FA9; // 442 -0.909 -0.416 +assign wn_re[443] = 32'hxxxxxxxx; assign wn_im[443] = 32'hxxxxxxxx; // 443 -0.912 -0.411 +assign wn_re[444] = 32'h8AFB2CBB; assign wn_im[444] = 32'hCC210D79; // 444 -0.914 -0.405 +assign wn_re[445] = 32'hxxxxxxxx; assign wn_im[445] = 32'hxxxxxxxx; // 445 -0.917 -0.400 +assign wn_re[446] = 32'h8A5A7A31; assign wn_im[446] = 32'hCD91AB39; // 446 -0.919 -0.394 +assign wn_re[447] = 32'h8A0BD3F5; assign wn_im[447] = 32'hCE4AB5A2; // 447 -0.922 -0.388 +assign wn_re[448] = 32'h89BE50C3; assign wn_im[448] = 32'hCF043AB3; // 448 -0.924 -0.383 +assign wn_re[449] = 32'hxxxxxxxx; assign wn_im[449] = 32'hxxxxxxxx; // 449 -0.926 -0.377 +assign wn_re[450] = 32'h8926B677; assign wn_im[450] = 32'hD078AD9E; // 450 -0.929 -0.371 +assign wn_re[451] = 32'hxxxxxxxx; assign wn_im[451] = 32'hxxxxxxxx; // 451 -0.931 -0.366 +assign wn_re[452] = 32'h8893B125; assign wn_im[452] = 32'hD1EEF59E; // 452 -0.933 -0.360 +assign wn_re[453] = 32'h884BE821; assign wn_im[453] = 32'hD2AAC504; // 453 -0.935 -0.354 +assign wn_re[454] = 32'h88054677; assign wn_im[454] = 32'hD3670446; // 454 -0.937 -0.348 +assign wn_re[455] = 32'hxxxxxxxx; assign wn_im[455] = 32'hxxxxxxxx; // 455 -0.939 -0.343 +assign wn_re[456] = 32'h877B7BEC; assign wn_im[456] = 32'hD4E0CB15; // 456 -0.942 -0.337 +assign wn_re[457] = 32'hxxxxxxxx; assign wn_im[457] = 32'hxxxxxxxx; // 457 -0.944 -0.331 +assign wn_re[458] = 32'h86F656D3; assign wn_im[458] = 32'hD65C3B7B; // 458 -0.946 -0.325 +assign wn_re[459] = 32'h86B583EE; assign wn_im[459] = 32'hD71A8EB5; // 459 -0.948 -0.320 +assign wn_re[460] = 32'h8675DC4F; assign wn_im[460] = 32'hD7D946D8; // 460 -0.950 -0.314 +assign wn_re[461] = 32'hxxxxxxxx; assign wn_im[461] = 32'hxxxxxxxx; // 461 -0.951 -0.308 +assign wn_re[462] = 32'h85FA1153; assign wn_im[462] = 32'hD957DE7A; // 462 -0.953 -0.302 +assign wn_re[463] = 32'hxxxxxxxx; assign wn_im[463] = 32'hxxxxxxxx; // 463 -0.955 -0.296 +assign wn_re[464] = 32'h8582FAA5; assign wn_im[464] = 32'hDAD7F3A2; // 464 -0.957 -0.290 +assign wn_re[465] = 32'h8549345C; assign wn_im[465] = 32'hDB9888A8; // 465 -0.959 -0.284 +assign wn_re[466] = 32'h85109CDD; assign wn_im[466] = 32'hDC597781; // 466 -0.960 -0.279 +assign wn_re[467] = 32'hxxxxxxxx; assign wn_im[467] = 32'hxxxxxxxx; // 467 -0.962 -0.273 +assign wn_re[468] = 32'h84A2FC62; assign wn_im[468] = 32'hDDDC5B3B; // 468 -0.964 -0.267 +assign wn_re[469] = 32'hxxxxxxxx; assign wn_im[469] = 32'hxxxxxxxx; // 469 -0.965 -0.261 +assign wn_re[470] = 32'h843A1D70; assign wn_im[470] = 32'hDF608FE4; // 470 -0.967 -0.255 +assign wn_re[471] = 32'h840777D0; assign wn_im[471] = 32'hE02323E5; // 471 -0.969 -0.249 +assign wn_re[472] = 32'h83D60412; assign wn_im[472] = 32'hE0E60685; // 472 -0.970 -0.243 +assign wn_re[473] = 32'hxxxxxxxx; assign wn_im[473] = 32'hxxxxxxxx; // 473 -0.972 -0.237 +assign wn_re[474] = 32'h8376B422; assign wn_im[474] = 32'hE26CB01B; // 474 -0.973 -0.231 +assign wn_re[475] = 32'hxxxxxxxx; assign wn_im[475] = 32'hxxxxxxxx; // 475 -0.974 -0.225 +assign wn_re[476] = 32'h831C314E; assign wn_im[476] = 32'hE3F47D96; // 476 -0.976 -0.219 +assign wn_re[477] = 32'h82F0BDE8; assign wn_im[477] = 32'hE4B8CD11; // 477 -0.977 -0.213 +assign wn_re[478] = 32'h82C67F14; assign wn_im[478] = 32'hE57D5FDA; // 478 -0.978 -0.207 +assign wn_re[479] = 32'hxxxxxxxx; assign wn_im[479] = 32'hxxxxxxxx; // 479 -0.980 -0.201 +assign wn_re[480] = 32'h8275A0C0; assign wn_im[480] = 32'hE70747C4; // 480 -0.981 -0.195 +assign wn_re[481] = 32'hxxxxxxxx; assign wn_im[481] = 32'hxxxxxxxx; // 481 -0.982 -0.189 +assign wn_re[482] = 32'h82299971; assign wn_im[482] = 32'hE8922622; // 482 -0.983 -0.183 +assign wn_re[483] = 32'h82056758; assign wn_im[483] = 32'hE957ECFB; // 483 -0.984 -0.177 +assign wn_re[484] = 32'h81E26C16; assign wn_im[484] = 32'hEA1DEBBB; // 484 -0.985 -0.171 +assign wn_re[485] = 32'hxxxxxxxx; assign wn_im[485] = 32'hxxxxxxxx; // 485 -0.986 -0.165 +assign wn_re[486] = 32'h81A01B6D; assign wn_im[486] = 32'hEBAA894F; // 486 -0.987 -0.159 +assign wn_re[487] = 32'hxxxxxxxx; assign wn_im[487] = 32'hxxxxxxxx; // 487 -0.988 -0.153 +assign wn_re[488] = 32'h8162AA04; assign wn_im[488] = 32'hED37EF91; // 488 -0.989 -0.147 +assign wn_re[489] = 32'h8145C5C7; assign wn_im[489] = 32'hEDFEE92B; // 489 -0.990 -0.141 +assign wn_re[490] = 32'h812A1A3A; assign wn_im[490] = 32'hEEC60F31; // 490 -0.991 -0.135 +assign wn_re[491] = 32'hxxxxxxxx; assign wn_im[491] = 32'hxxxxxxxx; // 491 -0.992 -0.128 +assign wn_re[492] = 32'h80F66E3C; assign wn_im[492] = 32'hF054D8D5; // 492 -0.992 -0.122 +assign wn_re[493] = 32'hxxxxxxxx; assign wn_im[493] = 32'hxxxxxxxx; // 493 -0.993 -0.116 +assign wn_re[494] = 32'h80C7A80A; assign wn_im[494] = 32'hF1E43D1C; // 494 -0.994 -0.110 +assign wn_re[495] = 32'h80B21BAF; assign wn_im[495] = 32'hF2AC246E; // 495 -0.995 -0.104 +assign wn_re[496] = 32'h809DC971; assign wn_im[496] = 32'hF3742CA2; // 496 -0.995 -0.098 +assign wn_re[497] = 32'hxxxxxxxx; assign wn_im[497] = 32'hxxxxxxxx; // 497 -0.996 -0.092 +assign wn_re[498] = 32'h8078D40D; assign wn_im[498] = 32'hF50497FB; // 498 -0.996 -0.086 +assign wn_re[499] = 32'hxxxxxxxx; assign wn_im[499] = 32'hxxxxxxxx; // 499 -0.997 -0.080 +assign wn_re[500] = 32'h8058C94C; assign wn_im[500] = 32'hF6956FB7; // 500 -0.997 -0.074 +assign wn_re[501] = 32'h804A9C4D; assign wn_im[501] = 32'hF75DFF66; // 501 -0.998 -0.067 +assign wn_re[502] = 32'h803DAA6A; assign wn_im[502] = 32'hF826A462; // 502 -0.998 -0.061 +assign wn_re[503] = 32'hxxxxxxxx; assign wn_im[503] = 32'hxxxxxxxx; // 503 -0.998 -0.055 +assign wn_re[504] = 32'h80277872; assign wn_im[504] = 32'hF9B82684; // 504 -0.999 -0.049 +assign wn_re[505] = 32'hxxxxxxxx; assign wn_im[505] = 32'hxxxxxxxx; // 505 -0.999 -0.043 +assign wn_re[506] = 32'h80163440; assign wn_im[506] = 32'hFB49E6A3; // 506 -0.999 -0.037 +assign wn_re[507] = 32'h800F6B88; assign wn_im[507] = 32'hFC12D91A; // 507 -1.000 -0.031 +assign wn_re[508] = 32'h8009DE7E; assign wn_im[508] = 32'hFCDBD541; // 508 -1.000 -0.025 +assign wn_re[509] = 32'hxxxxxxxx; assign wn_im[509] = 32'hxxxxxxxx; // 509 -1.000 -0.018 +assign wn_re[510] = 32'h800277A6; assign wn_im[510] = 32'hFE6DE2E0; // 510 -1.000 -0.012 +assign wn_re[511] = 32'hxxxxxxxx; assign wn_im[511] = 32'hxxxxxxxx; // 511 -1.000 -0.006 +assign wn_re[512] = 32'hxxxxxxxx; assign wn_im[512] = 32'hxxxxxxxx; // 512 -1.000 -0.000 +assign wn_re[513] = 32'h80009DEA; assign wn_im[513] = 32'h00C90F88; // 513 -1.000 0.006 +assign wn_re[514] = 32'hxxxxxxxx; assign wn_im[514] = 32'hxxxxxxxx; // 514 -1.000 0.012 +assign wn_re[515] = 32'hxxxxxxxx; assign wn_im[515] = 32'hxxxxxxxx; // 515 -1.000 0.018 +assign wn_re[516] = 32'h8009DE7E; assign wn_im[516] = 32'h03242ABF; // 516 -1.000 0.025 +assign wn_re[517] = 32'hxxxxxxxx; assign wn_im[517] = 32'hxxxxxxxx; // 517 -1.000 0.031 +assign wn_re[518] = 32'hxxxxxxxx; assign wn_im[518] = 32'hxxxxxxxx; // 518 -0.999 0.037 +assign wn_re[519] = 32'h801E3895; assign wn_im[519] = 32'h057F0035; // 519 -0.999 0.043 +assign wn_re[520] = 32'hxxxxxxxx; assign wn_im[520] = 32'hxxxxxxxx; // 520 -0.999 0.049 +assign wn_re[521] = 32'hxxxxxxxx; assign wn_im[521] = 32'hxxxxxxxx; // 521 -0.998 0.055 +assign wn_re[522] = 32'h803DAA6A; assign wn_im[522] = 32'h07D95B9E; // 522 -0.998 0.061 +assign wn_re[523] = 32'hxxxxxxxx; assign wn_im[523] = 32'hxxxxxxxx; // 523 -0.998 0.067 +assign wn_re[524] = 32'hxxxxxxxx; assign wn_im[524] = 32'hxxxxxxxx; // 524 -0.997 0.074 +assign wn_re[525] = 32'h80683143; assign wn_im[525] = 32'h0A3308BD; // 525 -0.997 0.080 +assign wn_re[526] = 32'hxxxxxxxx; assign wn_im[526] = 32'hxxxxxxxx; // 526 -0.996 0.086 +assign wn_re[527] = 32'hxxxxxxxx; assign wn_im[527] = 32'hxxxxxxxx; // 527 -0.996 0.092 +assign wn_re[528] = 32'h809DC971; assign wn_im[528] = 32'h0C8BD35E; // 528 -0.995 0.098 +assign wn_re[529] = 32'hxxxxxxxx; assign wn_im[529] = 32'hxxxxxxxx; // 529 -0.995 0.104 +assign wn_re[530] = 32'hxxxxxxxx; assign wn_im[530] = 32'hxxxxxxxx; // 530 -0.994 0.110 +assign wn_re[531] = 32'h80DE6E4C; assign wn_im[531] = 32'h0EE38766; // 531 -0.993 0.116 +assign wn_re[532] = 32'hxxxxxxxx; assign wn_im[532] = 32'hxxxxxxxx; // 532 -0.992 0.122 +assign wn_re[533] = 32'hxxxxxxxx; assign wn_im[533] = 32'hxxxxxxxx; // 533 -0.992 0.128 +assign wn_re[534] = 32'h812A1A3A; assign wn_im[534] = 32'h1139F0CF; // 534 -0.991 0.135 +assign wn_re[535] = 32'hxxxxxxxx; assign wn_im[535] = 32'hxxxxxxxx; // 535 -0.990 0.141 +assign wn_re[536] = 32'hxxxxxxxx; assign wn_im[536] = 32'hxxxxxxxx; // 536 -0.989 0.147 +assign wn_re[537] = 32'h8180C6A9; assign wn_im[537] = 32'h138EDBB1; // 537 -0.988 0.153 +assign wn_re[538] = 32'hxxxxxxxx; assign wn_im[538] = 32'hxxxxxxxx; // 538 -0.987 0.159 +assign wn_re[539] = 32'hxxxxxxxx; assign wn_im[539] = 32'hxxxxxxxx; // 539 -0.986 0.165 +assign wn_re[540] = 32'h81E26C16; assign wn_im[540] = 32'h15E21445; // 540 -0.985 0.171 +assign wn_re[541] = 32'hxxxxxxxx; assign wn_im[541] = 32'hxxxxxxxx; // 541 -0.984 0.177 +assign wn_re[542] = 32'hxxxxxxxx; assign wn_im[542] = 32'hxxxxxxxx; // 542 -0.983 0.183 +assign wn_re[543] = 32'h824F0208; assign wn_im[543] = 32'h183366E9; // 543 -0.982 0.189 +assign wn_re[544] = 32'hxxxxxxxx; assign wn_im[544] = 32'hxxxxxxxx; // 544 -0.981 0.195 +assign wn_re[545] = 32'hxxxxxxxx; assign wn_im[545] = 32'hxxxxxxxx; // 545 -0.980 0.201 +assign wn_re[546] = 32'h82C67F14; assign wn_im[546] = 32'h1A82A026; // 546 -0.978 0.207 +assign wn_re[547] = 32'hxxxxxxxx; assign wn_im[547] = 32'hxxxxxxxx; // 547 -0.977 0.213 +assign wn_re[548] = 32'hxxxxxxxx; assign wn_im[548] = 32'hxxxxxxxx; // 548 -0.976 0.219 +assign wn_re[549] = 32'h8348D8DC; assign wn_im[549] = 32'h1CCF8CB3; // 549 -0.974 0.225 +assign wn_re[550] = 32'hxxxxxxxx; assign wn_im[550] = 32'hxxxxxxxx; // 550 -0.973 0.231 +assign wn_re[551] = 32'hxxxxxxxx; assign wn_im[551] = 32'hxxxxxxxx; // 551 -0.972 0.237 +assign wn_re[552] = 32'h83D60412; assign wn_im[552] = 32'h1F19F97B; // 552 -0.970 0.243 +assign wn_re[553] = 32'hxxxxxxxx; assign wn_im[553] = 32'hxxxxxxxx; // 553 -0.969 0.249 +assign wn_re[554] = 32'hxxxxxxxx; assign wn_im[554] = 32'hxxxxxxxx; // 554 -0.967 0.255 +assign wn_re[555] = 32'h846DF477; assign wn_im[555] = 32'h2161B3A0; // 555 -0.965 0.261 +assign wn_re[556] = 32'hxxxxxxxx; assign wn_im[556] = 32'hxxxxxxxx; // 556 -0.964 0.267 +assign wn_re[557] = 32'hxxxxxxxx; assign wn_im[557] = 32'hxxxxxxxx; // 557 -0.962 0.273 +assign wn_re[558] = 32'h85109CDD; assign wn_im[558] = 32'h23A6887F; // 558 -0.960 0.279 +assign wn_re[559] = 32'hxxxxxxxx; assign wn_im[559] = 32'hxxxxxxxx; // 559 -0.959 0.284 +assign wn_re[560] = 32'hxxxxxxxx; assign wn_im[560] = 32'hxxxxxxxx; // 560 -0.957 0.290 +assign wn_re[561] = 32'h85BDEF28; assign wn_im[561] = 32'h25E845B6; // 561 -0.955 0.296 +assign wn_re[562] = 32'hxxxxxxxx; assign wn_im[562] = 32'hxxxxxxxx; // 562 -0.953 0.302 +assign wn_re[563] = 32'hxxxxxxxx; assign wn_im[563] = 32'hxxxxxxxx; // 563 -0.951 0.308 +assign wn_re[564] = 32'h8675DC4F; assign wn_im[564] = 32'h2826B928; // 564 -0.950 0.314 +assign wn_re[565] = 32'hxxxxxxxx; assign wn_im[565] = 32'hxxxxxxxx; // 565 -0.948 0.320 +assign wn_re[566] = 32'hxxxxxxxx; assign wn_im[566] = 32'hxxxxxxxx; // 566 -0.946 0.325 +assign wn_re[567] = 32'h8738545E; assign wn_im[567] = 32'h2A61B101; // 567 -0.944 0.331 +assign wn_re[568] = 32'hxxxxxxxx; assign wn_im[568] = 32'hxxxxxxxx; // 568 -0.942 0.337 +assign wn_re[569] = 32'hxxxxxxxx; assign wn_im[569] = 32'hxxxxxxxx; // 569 -0.939 0.343 +assign wn_re[570] = 32'h88054677; assign wn_im[570] = 32'h2C98FBBA; // 570 -0.937 0.348 +assign wn_re[571] = 32'hxxxxxxxx; assign wn_im[571] = 32'hxxxxxxxx; // 571 -0.935 0.354 +assign wn_re[572] = 32'hxxxxxxxx; assign wn_im[572] = 32'hxxxxxxxx; // 572 -0.933 0.360 +assign wn_re[573] = 32'h88DCA0D3; assign wn_im[573] = 32'h2ECC681E; // 573 -0.931 0.366 +assign wn_re[574] = 32'hxxxxxxxx; assign wn_im[574] = 32'hxxxxxxxx; // 574 -0.929 0.371 +assign wn_re[575] = 32'hxxxxxxxx; assign wn_im[575] = 32'hxxxxxxxx; // 575 -0.926 0.377 +assign wn_re[576] = 32'h89BE50C3; assign wn_im[576] = 32'h30FBC54D; // 576 -0.924 0.383 +assign wn_re[577] = 32'hxxxxxxxx; assign wn_im[577] = 32'hxxxxxxxx; // 577 -0.922 0.388 +assign wn_re[578] = 32'hxxxxxxxx; assign wn_im[578] = 32'hxxxxxxxx; // 578 -0.919 0.394 +assign wn_re[579] = 32'h8AAA42B4; assign wn_im[579] = 32'h3326E2C3; // 579 -0.917 0.400 +assign wn_re[580] = 32'hxxxxxxxx; assign wn_im[580] = 32'hxxxxxxxx; // 580 -0.914 0.405 +assign wn_re[581] = 32'hxxxxxxxx; assign wn_im[581] = 32'hxxxxxxxx; // 581 -0.912 0.411 +assign wn_re[582] = 32'h8BA0622F; assign wn_im[582] = 32'h354D9057; // 582 -0.909 0.416 +assign wn_re[583] = 32'hxxxxxxxx; assign wn_im[583] = 32'hxxxxxxxx; // 583 -0.907 0.422 +assign wn_re[584] = 32'hxxxxxxxx; assign wn_im[584] = 32'hxxxxxxxx; // 584 -0.904 0.428 +assign wn_re[585] = 32'h8CA099DA; assign wn_im[585] = 32'h376F9E46; // 585 -0.901 0.433 +assign wn_re[586] = 32'hxxxxxxxx; assign wn_im[586] = 32'hxxxxxxxx; // 586 -0.899 0.439 +assign wn_re[587] = 32'hxxxxxxxx; assign wn_im[587] = 32'hxxxxxxxx; // 587 -0.896 0.444 +assign wn_re[588] = 32'h8DAAD37B; assign wn_im[588] = 32'h398CDD32; // 588 -0.893 0.450 +assign wn_re[589] = 32'hxxxxxxxx; assign wn_im[589] = 32'hxxxxxxxx; // 589 -0.890 0.455 +assign wn_re[590] = 32'hxxxxxxxx; assign wn_im[590] = 32'hxxxxxxxx; // 590 -0.888 0.461 +assign wn_re[591] = 32'h8EBEF7FB; assign wn_im[591] = 32'h3BA51E29; // 591 -0.885 0.466 +assign wn_re[592] = 32'hxxxxxxxx; assign wn_im[592] = 32'hxxxxxxxx; // 592 -0.882 0.471 +assign wn_re[593] = 32'hxxxxxxxx; assign wn_im[593] = 32'hxxxxxxxx; // 593 -0.879 0.477 +assign wn_re[594] = 32'h8FDCEF66; assign wn_im[594] = 32'h3DB832A6; // 594 -0.876 0.482 +assign wn_re[595] = 32'hxxxxxxxx; assign wn_im[595] = 32'hxxxxxxxx; // 595 -0.873 0.488 +assign wn_re[596] = 32'hxxxxxxxx; assign wn_im[596] = 32'hxxxxxxxx; // 596 -0.870 0.493 +assign wn_re[597] = 32'h9104A0EE; assign wn_im[597] = 32'h3FC5EC98; // 597 -0.867 0.498 +assign wn_re[598] = 32'hxxxxxxxx; assign wn_im[598] = 32'hxxxxxxxx; // 598 -0.864 0.504 +assign wn_re[599] = 32'hxxxxxxxx; assign wn_im[599] = 32'hxxxxxxxx; // 599 -0.861 0.509 +assign wn_re[600] = 32'h9235F2EC; assign wn_im[600] = 32'h41CE1E65; // 600 -0.858 0.514 +assign wn_re[601] = 32'hxxxxxxxx; assign wn_im[601] = 32'hxxxxxxxx; // 601 -0.855 0.519 +assign wn_re[602] = 32'hxxxxxxxx; assign wn_im[602] = 32'hxxxxxxxx; // 602 -0.851 0.525 +assign wn_re[603] = 32'h9370CAE4; assign wn_im[603] = 32'h43D09AED; // 603 -0.848 0.530 +assign wn_re[604] = 32'hxxxxxxxx; assign wn_im[604] = 32'hxxxxxxxx; // 604 -0.845 0.535 +assign wn_re[605] = 32'hxxxxxxxx; assign wn_im[605] = 32'hxxxxxxxx; // 605 -0.842 0.540 +assign wn_re[606] = 32'h94B50D87; assign wn_im[606] = 32'h45CD358F; // 606 -0.838 0.545 +assign wn_re[607] = 32'hxxxxxxxx; assign wn_im[607] = 32'hxxxxxxxx; // 607 -0.835 0.550 +assign wn_re[608] = 32'hxxxxxxxx; assign wn_im[608] = 32'hxxxxxxxx; // 608 -0.831 0.556 +assign wn_re[609] = 32'h96029EB6; assign wn_im[609] = 32'h47C3C22F; // 609 -0.828 0.561 +assign wn_re[610] = 32'hxxxxxxxx; assign wn_im[610] = 32'hxxxxxxxx; // 610 -0.825 0.566 +assign wn_re[611] = 32'hxxxxxxxx; assign wn_im[611] = 32'hxxxxxxxx; // 611 -0.821 0.571 +assign wn_re[612] = 32'h9759617F; assign wn_im[612] = 32'h49B41533; // 612 -0.818 0.576 +assign wn_re[613] = 32'hxxxxxxxx; assign wn_im[613] = 32'hxxxxxxxx; // 613 -0.814 0.581 +assign wn_re[614] = 32'hxxxxxxxx; assign wn_im[614] = 32'hxxxxxxxx; // 614 -0.810 0.586 +assign wn_re[615] = 32'h98B93828; assign wn_im[615] = 32'h4B9E0390; // 615 -0.807 0.591 +assign wn_re[616] = 32'hxxxxxxxx; assign wn_im[616] = 32'hxxxxxxxx; // 616 -0.803 0.596 +assign wn_re[617] = 32'hxxxxxxxx; assign wn_im[617] = 32'hxxxxxxxx; // 617 -0.800 0.601 +assign wn_re[618] = 32'h9A22042D; assign wn_im[618] = 32'h4D8162C4; // 618 -0.796 0.606 +assign wn_re[619] = 32'hxxxxxxxx; assign wn_im[619] = 32'hxxxxxxxx; // 619 -0.792 0.610 +assign wn_re[620] = 32'hxxxxxxxx; assign wn_im[620] = 32'hxxxxxxxx; // 620 -0.788 0.615 +assign wn_re[621] = 32'h9B93A641; assign wn_im[621] = 32'h4F5E08E3; // 621 -0.785 0.620 +assign wn_re[622] = 32'hxxxxxxxx; assign wn_im[622] = 32'hxxxxxxxx; // 622 -0.781 0.625 +assign wn_re[623] = 32'hxxxxxxxx; assign wn_im[623] = 32'hxxxxxxxx; // 623 -0.777 0.630 +assign wn_re[624] = 32'h9D0DFE54; assign wn_im[624] = 32'h5133CC94; // 624 -0.773 0.634 +assign wn_re[625] = 32'hxxxxxxxx; assign wn_im[625] = 32'hxxxxxxxx; // 625 -0.769 0.639 +assign wn_re[626] = 32'hxxxxxxxx; assign wn_im[626] = 32'hxxxxxxxx; // 626 -0.765 0.644 +assign wn_re[627] = 32'h9E90EB94; assign wn_im[627] = 32'h53028518; // 627 -0.761 0.649 +assign wn_re[628] = 32'hxxxxxxxx; assign wn_im[628] = 32'hxxxxxxxx; // 628 -0.757 0.653 +assign wn_re[629] = 32'hxxxxxxxx; assign wn_im[629] = 32'hxxxxxxxx; // 629 -0.753 0.658 +assign wn_re[630] = 32'hA01C4C73; assign wn_im[630] = 32'h54CA0A4B; // 630 -0.749 0.662 +assign wn_re[631] = 32'hxxxxxxxx; assign wn_im[631] = 32'hxxxxxxxx; // 631 -0.745 0.667 +assign wn_re[632] = 32'hxxxxxxxx; assign wn_im[632] = 32'hxxxxxxxx; // 632 -0.741 0.672 +assign wn_re[633] = 32'hA1AFFEA3; assign wn_im[633] = 32'h568A34A9; // 633 -0.737 0.676 +assign wn_re[634] = 32'hxxxxxxxx; assign wn_im[634] = 32'hxxxxxxxx; // 634 -0.733 0.681 +assign wn_re[635] = 32'hxxxxxxxx; assign wn_im[635] = 32'hxxxxxxxx; // 635 -0.728 0.685 +assign wn_re[636] = 32'hA34BDF20; assign wn_im[636] = 32'h5842DD54; // 636 -0.724 0.690 +assign wn_re[637] = 32'hxxxxxxxx; assign wn_im[637] = 32'hxxxxxxxx; // 637 -0.720 0.694 +assign wn_re[638] = 32'hxxxxxxxx; assign wn_im[638] = 32'hxxxxxxxx; // 638 -0.716 0.698 +assign wn_re[639] = 32'hA4EFCA31; assign wn_im[639] = 32'h59F3DE12; // 639 -0.711 0.703 +assign wn_re[640] = 32'hxxxxxxxx; assign wn_im[640] = 32'hxxxxxxxx; // 640 -0.707 0.707 +assign wn_re[641] = 32'hxxxxxxxx; assign wn_im[641] = 32'hxxxxxxxx; // 641 -0.703 0.711 +assign wn_re[642] = 32'hA69B9B68; assign wn_im[642] = 32'h5B9D1154; // 642 -0.698 0.716 +assign wn_re[643] = 32'hxxxxxxxx; assign wn_im[643] = 32'hxxxxxxxx; // 643 -0.694 0.720 +assign wn_re[644] = 32'hxxxxxxxx; assign wn_im[644] = 32'hxxxxxxxx; // 644 -0.690 0.724 +assign wn_re[645] = 32'hA84F2DAA; assign wn_im[645] = 32'h5D3E5237; // 645 -0.685 0.728 +assign wn_re[646] = 32'hxxxxxxxx; assign wn_im[646] = 32'hxxxxxxxx; // 646 -0.681 0.733 +assign wn_re[647] = 32'hxxxxxxxx; assign wn_im[647] = 32'hxxxxxxxx; // 647 -0.676 0.737 +assign wn_re[648] = 32'hAA0A5B2E; assign wn_im[648] = 32'h5ED77C8A; // 648 -0.672 0.741 +assign wn_re[649] = 32'hxxxxxxxx; assign wn_im[649] = 32'hxxxxxxxx; // 649 -0.667 0.745 +assign wn_re[650] = 32'hxxxxxxxx; assign wn_im[650] = 32'hxxxxxxxx; // 650 -0.662 0.749 +assign wn_re[651] = 32'hABCCFD83; assign wn_im[651] = 32'h60686CCF; // 651 -0.658 0.753 +assign wn_re[652] = 32'hxxxxxxxx; assign wn_im[652] = 32'hxxxxxxxx; // 652 -0.653 0.757 +assign wn_re[653] = 32'hxxxxxxxx; assign wn_im[653] = 32'hxxxxxxxx; // 653 -0.649 0.761 +assign wn_re[654] = 32'hAD96ED92; assign wn_im[654] = 32'h61F1003F; // 654 -0.644 0.765 +assign wn_re[655] = 32'hxxxxxxxx; assign wn_im[655] = 32'hxxxxxxxx; // 655 -0.639 0.769 +assign wn_re[656] = 32'hxxxxxxxx; assign wn_im[656] = 32'hxxxxxxxx; // 656 -0.634 0.773 +assign wn_re[657] = 32'hAF6803A2; assign wn_im[657] = 32'h637114CC; // 657 -0.630 0.777 +assign wn_re[658] = 32'hxxxxxxxx; assign wn_im[658] = 32'hxxxxxxxx; // 658 -0.625 0.781 +assign wn_re[659] = 32'hxxxxxxxx; assign wn_im[659] = 32'hxxxxxxxx; // 659 -0.620 0.785 +assign wn_re[660] = 32'hB140175B; assign wn_im[660] = 32'h64E88926; // 660 -0.615 0.788 +assign wn_re[661] = 32'hxxxxxxxx; assign wn_im[661] = 32'hxxxxxxxx; // 661 -0.610 0.792 +assign wn_re[662] = 32'hxxxxxxxx; assign wn_im[662] = 32'hxxxxxxxx; // 662 -0.606 0.796 +assign wn_re[663] = 32'hB31EFFCC; assign wn_im[663] = 32'h66573CBB; // 663 -0.601 0.800 +assign wn_re[664] = 32'hxxxxxxxx; assign wn_im[664] = 32'hxxxxxxxx; // 664 -0.596 0.803 +assign wn_re[665] = 32'hxxxxxxxx; assign wn_im[665] = 32'hxxxxxxxx; // 665 -0.591 0.807 +assign wn_re[666] = 32'hB5049368; assign wn_im[666] = 32'h67BD0FBD; // 666 -0.586 0.810 +assign wn_re[667] = 32'hxxxxxxxx; assign wn_im[667] = 32'hxxxxxxxx; // 667 -0.581 0.814 +assign wn_re[668] = 32'hxxxxxxxx; assign wn_im[668] = 32'hxxxxxxxx; // 668 -0.576 0.818 +assign wn_re[669] = 32'hB6F0A812; assign wn_im[669] = 32'h6919E320; // 669 -0.571 0.821 +assign wn_re[670] = 32'hxxxxxxxx; assign wn_im[670] = 32'hxxxxxxxx; // 670 -0.566 0.825 +assign wn_re[671] = 32'hxxxxxxxx; assign wn_im[671] = 32'hxxxxxxxx; // 671 -0.561 0.828 +assign wn_re[672] = 32'hB8E31319; assign wn_im[672] = 32'h6A6D98A4; // 672 -0.556 0.831 +assign wn_re[673] = 32'hxxxxxxxx; assign wn_im[673] = 32'hxxxxxxxx; // 673 -0.550 0.835 +assign wn_re[674] = 32'hxxxxxxxx; assign wn_im[674] = 32'hxxxxxxxx; // 674 -0.545 0.838 +assign wn_re[675] = 32'hBADBA943; assign wn_im[675] = 32'h6BB812D1; // 675 -0.540 0.842 +assign wn_re[676] = 32'hxxxxxxxx; assign wn_im[676] = 32'hxxxxxxxx; // 676 -0.535 0.845 +assign wn_re[677] = 32'hxxxxxxxx; assign wn_im[677] = 32'hxxxxxxxx; // 677 -0.530 0.848 +assign wn_re[678] = 32'hBCDA3ECB; assign wn_im[678] = 32'h6CF934FC; // 678 -0.525 0.851 +assign wn_re[679] = 32'hxxxxxxxx; assign wn_im[679] = 32'hxxxxxxxx; // 679 -0.519 0.855 +assign wn_re[680] = 32'hxxxxxxxx; assign wn_im[680] = 32'hxxxxxxxx; // 680 -0.514 0.858 +assign wn_re[681] = 32'hBEDEA765; assign wn_im[681] = 32'h6E30E34A; // 681 -0.509 0.861 +assign wn_re[682] = 32'hxxxxxxxx; assign wn_im[682] = 32'hxxxxxxxx; // 682 -0.504 0.864 +assign wn_re[683] = 32'hxxxxxxxx; assign wn_im[683] = 32'hxxxxxxxx; // 683 -0.498 0.867 +assign wn_re[684] = 32'hC0E8B648; assign wn_im[684] = 32'h6F5F02B2; // 684 -0.493 0.870 +assign wn_re[685] = 32'hxxxxxxxx; assign wn_im[685] = 32'hxxxxxxxx; // 685 -0.488 0.873 +assign wn_re[686] = 32'hxxxxxxxx; assign wn_im[686] = 32'hxxxxxxxx; // 686 -0.482 0.876 +assign wn_re[687] = 32'hC2F83E2A; assign wn_im[687] = 32'h708378FF; // 687 -0.477 0.879 +assign wn_re[688] = 32'hxxxxxxxx; assign wn_im[688] = 32'hxxxxxxxx; // 688 -0.471 0.882 +assign wn_re[689] = 32'hxxxxxxxx; assign wn_im[689] = 32'hxxxxxxxx; // 689 -0.466 0.885 +assign wn_re[690] = 32'hC50D1149; assign wn_im[690] = 32'h719E2CD2; // 690 -0.461 0.888 +assign wn_re[691] = 32'hxxxxxxxx; assign wn_im[691] = 32'hxxxxxxxx; // 691 -0.455 0.890 +assign wn_re[692] = 32'hxxxxxxxx; assign wn_im[692] = 32'hxxxxxxxx; // 692 -0.450 0.893 +assign wn_re[693] = 32'hC727016D; assign wn_im[693] = 32'h72AF05A7; // 693 -0.444 0.896 +assign wn_re[694] = 32'hxxxxxxxx; assign wn_im[694] = 32'hxxxxxxxx; // 694 -0.439 0.899 +assign wn_re[695] = 32'hxxxxxxxx; assign wn_im[695] = 32'hxxxxxxxx; // 695 -0.433 0.901 +assign wn_re[696] = 32'hC945DFEC; assign wn_im[696] = 32'h73B5EBD1; // 696 -0.428 0.904 +assign wn_re[697] = 32'hxxxxxxxx; assign wn_im[697] = 32'hxxxxxxxx; // 697 -0.422 0.907 +assign wn_re[698] = 32'hxxxxxxxx; assign wn_im[698] = 32'hxxxxxxxx; // 698 -0.416 0.909 +assign wn_re[699] = 32'hCB697DB0; assign wn_im[699] = 32'h74B2C884; // 699 -0.411 0.912 +assign wn_re[700] = 32'hxxxxxxxx; assign wn_im[700] = 32'hxxxxxxxx; // 700 -0.405 0.914 +assign wn_re[701] = 32'hxxxxxxxx; assign wn_im[701] = 32'hxxxxxxxx; // 701 -0.400 0.917 +assign wn_re[702] = 32'hCD91AB39; assign wn_im[702] = 32'h75A585CF; // 702 -0.394 0.919 +assign wn_re[703] = 32'hxxxxxxxx; assign wn_im[703] = 32'hxxxxxxxx; // 703 -0.388 0.922 +assign wn_re[704] = 32'hxxxxxxxx; assign wn_im[704] = 32'hxxxxxxxx; // 704 -0.383 0.924 +assign wn_re[705] = 32'hCFBE389F; assign wn_im[705] = 32'h768E0EA6; // 705 -0.377 0.926 +assign wn_re[706] = 32'hxxxxxxxx; assign wn_im[706] = 32'hxxxxxxxx; // 706 -0.371 0.929 +assign wn_re[707] = 32'hxxxxxxxx; assign wn_im[707] = 32'hxxxxxxxx; // 707 -0.366 0.931 +assign wn_re[708] = 32'hD1EEF59E; assign wn_im[708] = 32'h776C4EDB; // 708 -0.360 0.933 +assign wn_re[709] = 32'hxxxxxxxx; assign wn_im[709] = 32'hxxxxxxxx; // 709 -0.354 0.935 +assign wn_re[710] = 32'hxxxxxxxx; assign wn_im[710] = 32'hxxxxxxxx; // 710 -0.348 0.937 +assign wn_re[711] = 32'hD423B191; assign wn_im[711] = 32'h78403329; // 711 -0.343 0.939 +assign wn_re[712] = 32'hxxxxxxxx; assign wn_im[712] = 32'hxxxxxxxx; // 712 -0.337 0.942 +assign wn_re[713] = 32'hxxxxxxxx; assign wn_im[713] = 32'hxxxxxxxx; // 713 -0.331 0.944 +assign wn_re[714] = 32'hD65C3B7B; assign wn_im[714] = 32'h7909A92D; // 714 -0.325 0.946 +assign wn_re[715] = 32'hxxxxxxxx; assign wn_im[715] = 32'hxxxxxxxx; // 715 -0.320 0.948 +assign wn_re[716] = 32'hxxxxxxxx; assign wn_im[716] = 32'hxxxxxxxx; // 716 -0.314 0.950 +assign wn_re[717] = 32'hD898620C; assign wn_im[717] = 32'h79C89F6E; // 717 -0.308 0.951 +assign wn_re[718] = 32'hxxxxxxxx; assign wn_im[718] = 32'hxxxxxxxx; // 718 -0.302 0.953 +assign wn_re[719] = 32'hxxxxxxxx; assign wn_im[719] = 32'hxxxxxxxx; // 719 -0.296 0.955 +assign wn_re[720] = 32'hDAD7F3A2; assign wn_im[720] = 32'h7A7D055B; // 720 -0.290 0.957 +assign wn_re[721] = 32'hxxxxxxxx; assign wn_im[721] = 32'hxxxxxxxx; // 721 -0.284 0.959 +assign wn_re[722] = 32'hxxxxxxxx; assign wn_im[722] = 32'hxxxxxxxx; // 722 -0.279 0.960 +assign wn_re[723] = 32'hDD1ABE51; assign wn_im[723] = 32'h7B26CB4F; // 723 -0.273 0.962 +assign wn_re[724] = 32'hxxxxxxxx; assign wn_im[724] = 32'hxxxxxxxx; // 724 -0.267 0.964 +assign wn_re[725] = 32'hxxxxxxxx; assign wn_im[725] = 32'hxxxxxxxx; // 725 -0.261 0.965 +assign wn_re[726] = 32'hDF608FE4; assign wn_im[726] = 32'h7BC5E290; // 726 -0.255 0.967 +assign wn_re[727] = 32'hxxxxxxxx; assign wn_im[727] = 32'hxxxxxxxx; // 727 -0.249 0.969 +assign wn_re[728] = 32'hxxxxxxxx; assign wn_im[728] = 32'hxxxxxxxx; // 728 -0.243 0.970 +assign wn_re[729] = 32'hE1A935E2; assign wn_im[729] = 32'h7C5A3D50; // 729 -0.237 0.972 +assign wn_re[730] = 32'hxxxxxxxx; assign wn_im[730] = 32'hxxxxxxxx; // 730 -0.231 0.973 +assign wn_re[731] = 32'hxxxxxxxx; assign wn_im[731] = 32'hxxxxxxxx; // 731 -0.225 0.974 +assign wn_re[732] = 32'hE3F47D96; assign wn_im[732] = 32'h7CE3CEB2; // 732 -0.219 0.976 +assign wn_re[733] = 32'hxxxxxxxx; assign wn_im[733] = 32'hxxxxxxxx; // 733 -0.213 0.977 +assign wn_re[734] = 32'hxxxxxxxx; assign wn_im[734] = 32'hxxxxxxxx; // 734 -0.207 0.978 +assign wn_re[735] = 32'hE642340D; assign wn_im[735] = 32'h7D628AC6; // 735 -0.201 0.980 +assign wn_re[736] = 32'hxxxxxxxx; assign wn_im[736] = 32'hxxxxxxxx; // 736 -0.195 0.981 +assign wn_re[737] = 32'hxxxxxxxx; assign wn_im[737] = 32'hxxxxxxxx; // 737 -0.189 0.982 +assign wn_re[738] = 32'hE8922622; assign wn_im[738] = 32'h7DD6668F; // 738 -0.183 0.983 +assign wn_re[739] = 32'hxxxxxxxx; assign wn_im[739] = 32'hxxxxxxxx; // 739 -0.177 0.984 +assign wn_re[740] = 32'hxxxxxxxx; assign wn_im[740] = 32'hxxxxxxxx; // 740 -0.171 0.985 +assign wn_re[741] = 32'hEAE4207A; assign wn_im[741] = 32'h7E3F57FF; // 741 -0.165 0.986 +assign wn_re[742] = 32'hxxxxxxxx; assign wn_im[742] = 32'hxxxxxxxx; // 742 -0.159 0.987 +assign wn_re[743] = 32'hxxxxxxxx; assign wn_im[743] = 32'hxxxxxxxx; // 743 -0.153 0.988 +assign wn_re[744] = 32'hED37EF91; assign wn_im[744] = 32'h7E9D55FC; // 744 -0.147 0.989 +assign wn_re[745] = 32'hxxxxxxxx; assign wn_im[745] = 32'hxxxxxxxx; // 745 -0.141 0.990 +assign wn_re[746] = 32'hxxxxxxxx; assign wn_im[746] = 32'hxxxxxxxx; // 746 -0.135 0.991 +assign wn_re[747] = 32'hEF8D5FB8; assign wn_im[747] = 32'h7EF05860; // 747 -0.128 0.992 +assign wn_re[748] = 32'hxxxxxxxx; assign wn_im[748] = 32'hxxxxxxxx; // 748 -0.122 0.992 +assign wn_re[749] = 32'hxxxxxxxx; assign wn_im[749] = 32'hxxxxxxxx; // 749 -0.116 0.993 +assign wn_re[750] = 32'hF1E43D1C; assign wn_im[750] = 32'h7F3857F6; // 750 -0.110 0.994 +assign wn_re[751] = 32'hxxxxxxxx; assign wn_im[751] = 32'hxxxxxxxx; // 751 -0.104 0.995 +assign wn_re[752] = 32'hxxxxxxxx; assign wn_im[752] = 32'hxxxxxxxx; // 752 -0.098 0.995 +assign wn_re[753] = 32'hF43C53CB; assign wn_im[753] = 32'h7F754E80; // 753 -0.092 0.996 +assign wn_re[754] = 32'hxxxxxxxx; assign wn_im[754] = 32'hxxxxxxxx; // 754 -0.086 0.996 +assign wn_re[755] = 32'hxxxxxxxx; assign wn_im[755] = 32'hxxxxxxxx; // 755 -0.080 0.997 +assign wn_re[756] = 32'hF6956FB7; assign wn_im[756] = 32'h7FA736B4; // 756 -0.074 0.997 +assign wn_re[757] = 32'hxxxxxxxx; assign wn_im[757] = 32'hxxxxxxxx; // 757 -0.067 0.998 +assign wn_re[758] = 32'hxxxxxxxx; assign wn_im[758] = 32'hxxxxxxxx; // 758 -0.061 0.998 +assign wn_re[759] = 32'hF8EF5CBB; assign wn_im[759] = 32'h7FCE0C3E; // 759 -0.055 0.998 +assign wn_re[760] = 32'hxxxxxxxx; assign wn_im[760] = 32'hxxxxxxxx; // 760 -0.049 0.999 +assign wn_re[761] = 32'hxxxxxxxx; assign wn_im[761] = 32'hxxxxxxxx; // 761 -0.043 0.999 +assign wn_re[762] = 32'hFB49E6A3; assign wn_im[762] = 32'h7FE9CBC0; // 762 -0.037 0.999 +assign wn_re[763] = 32'hxxxxxxxx; assign wn_im[763] = 32'hxxxxxxxx; // 763 -0.031 1.000 +assign wn_re[764] = 32'hxxxxxxxx; assign wn_im[764] = 32'hxxxxxxxx; // 764 -0.025 1.000 +assign wn_re[765] = 32'hFDA4D929; assign wn_im[765] = 32'h7FFA72D1; // 765 -0.018 1.000 +assign wn_re[766] = 32'hxxxxxxxx; assign wn_im[766] = 32'hxxxxxxxx; // 766 -0.012 1.000 +assign wn_re[767] = 32'hxxxxxxxx; assign wn_im[767] = 32'hxxxxxxxx; // 767 -0.006 1.000 +assign wn_re[768] = 32'hxxxxxxxx; assign wn_im[768] = 32'hxxxxxxxx; // 768 -0.000 1.000 +assign wn_re[769] = 32'hxxxxxxxx; assign wn_im[769] = 32'hxxxxxxxx; // 769 0.006 1.000 +assign wn_re[770] = 32'hxxxxxxxx; assign wn_im[770] = 32'hxxxxxxxx; // 770 0.012 1.000 +assign wn_re[771] = 32'hxxxxxxxx; assign wn_im[771] = 32'hxxxxxxxx; // 771 0.018 1.000 +assign wn_re[772] = 32'hxxxxxxxx; assign wn_im[772] = 32'hxxxxxxxx; // 772 0.025 1.000 +assign wn_re[773] = 32'hxxxxxxxx; assign wn_im[773] = 32'hxxxxxxxx; // 773 0.031 1.000 +assign wn_re[774] = 32'hxxxxxxxx; assign wn_im[774] = 32'hxxxxxxxx; // 774 0.037 0.999 +assign wn_re[775] = 32'hxxxxxxxx; assign wn_im[775] = 32'hxxxxxxxx; // 775 0.043 0.999 +assign wn_re[776] = 32'hxxxxxxxx; assign wn_im[776] = 32'hxxxxxxxx; // 776 0.049 0.999 +assign wn_re[777] = 32'hxxxxxxxx; assign wn_im[777] = 32'hxxxxxxxx; // 777 0.055 0.998 +assign wn_re[778] = 32'hxxxxxxxx; assign wn_im[778] = 32'hxxxxxxxx; // 778 0.061 0.998 +assign wn_re[779] = 32'hxxxxxxxx; assign wn_im[779] = 32'hxxxxxxxx; // 779 0.067 0.998 +assign wn_re[780] = 32'hxxxxxxxx; assign wn_im[780] = 32'hxxxxxxxx; // 780 0.074 0.997 +assign wn_re[781] = 32'hxxxxxxxx; assign wn_im[781] = 32'hxxxxxxxx; // 781 0.080 0.997 +assign wn_re[782] = 32'hxxxxxxxx; assign wn_im[782] = 32'hxxxxxxxx; // 782 0.086 0.996 +assign wn_re[783] = 32'hxxxxxxxx; assign wn_im[783] = 32'hxxxxxxxx; // 783 0.092 0.996 +assign wn_re[784] = 32'hxxxxxxxx; assign wn_im[784] = 32'hxxxxxxxx; // 784 0.098 0.995 +assign wn_re[785] = 32'hxxxxxxxx; assign wn_im[785] = 32'hxxxxxxxx; // 785 0.104 0.995 +assign wn_re[786] = 32'hxxxxxxxx; assign wn_im[786] = 32'hxxxxxxxx; // 786 0.110 0.994 +assign wn_re[787] = 32'hxxxxxxxx; assign wn_im[787] = 32'hxxxxxxxx; // 787 0.116 0.993 +assign wn_re[788] = 32'hxxxxxxxx; assign wn_im[788] = 32'hxxxxxxxx; // 788 0.122 0.992 +assign wn_re[789] = 32'hxxxxxxxx; assign wn_im[789] = 32'hxxxxxxxx; // 789 0.128 0.992 +assign wn_re[790] = 32'hxxxxxxxx; assign wn_im[790] = 32'hxxxxxxxx; // 790 0.135 0.991 +assign wn_re[791] = 32'hxxxxxxxx; assign wn_im[791] = 32'hxxxxxxxx; // 791 0.141 0.990 +assign wn_re[792] = 32'hxxxxxxxx; assign wn_im[792] = 32'hxxxxxxxx; // 792 0.147 0.989 +assign wn_re[793] = 32'hxxxxxxxx; assign wn_im[793] = 32'hxxxxxxxx; // 793 0.153 0.988 +assign wn_re[794] = 32'hxxxxxxxx; assign wn_im[794] = 32'hxxxxxxxx; // 794 0.159 0.987 +assign wn_re[795] = 32'hxxxxxxxx; assign wn_im[795] = 32'hxxxxxxxx; // 795 0.165 0.986 +assign wn_re[796] = 32'hxxxxxxxx; assign wn_im[796] = 32'hxxxxxxxx; // 796 0.171 0.985 +assign wn_re[797] = 32'hxxxxxxxx; assign wn_im[797] = 32'hxxxxxxxx; // 797 0.177 0.984 +assign wn_re[798] = 32'hxxxxxxxx; assign wn_im[798] = 32'hxxxxxxxx; // 798 0.183 0.983 +assign wn_re[799] = 32'hxxxxxxxx; assign wn_im[799] = 32'hxxxxxxxx; // 799 0.189 0.982 +assign wn_re[800] = 32'hxxxxxxxx; assign wn_im[800] = 32'hxxxxxxxx; // 800 0.195 0.981 +assign wn_re[801] = 32'hxxxxxxxx; assign wn_im[801] = 32'hxxxxxxxx; // 801 0.201 0.980 +assign wn_re[802] = 32'hxxxxxxxx; assign wn_im[802] = 32'hxxxxxxxx; // 802 0.207 0.978 +assign wn_re[803] = 32'hxxxxxxxx; assign wn_im[803] = 32'hxxxxxxxx; // 803 0.213 0.977 +assign wn_re[804] = 32'hxxxxxxxx; assign wn_im[804] = 32'hxxxxxxxx; // 804 0.219 0.976 +assign wn_re[805] = 32'hxxxxxxxx; assign wn_im[805] = 32'hxxxxxxxx; // 805 0.225 0.974 +assign wn_re[806] = 32'hxxxxxxxx; assign wn_im[806] = 32'hxxxxxxxx; // 806 0.231 0.973 +assign wn_re[807] = 32'hxxxxxxxx; assign wn_im[807] = 32'hxxxxxxxx; // 807 0.237 0.972 +assign wn_re[808] = 32'hxxxxxxxx; assign wn_im[808] = 32'hxxxxxxxx; // 808 0.243 0.970 +assign wn_re[809] = 32'hxxxxxxxx; assign wn_im[809] = 32'hxxxxxxxx; // 809 0.249 0.969 +assign wn_re[810] = 32'hxxxxxxxx; assign wn_im[810] = 32'hxxxxxxxx; // 810 0.255 0.967 +assign wn_re[811] = 32'hxxxxxxxx; assign wn_im[811] = 32'hxxxxxxxx; // 811 0.261 0.965 +assign wn_re[812] = 32'hxxxxxxxx; assign wn_im[812] = 32'hxxxxxxxx; // 812 0.267 0.964 +assign wn_re[813] = 32'hxxxxxxxx; assign wn_im[813] = 32'hxxxxxxxx; // 813 0.273 0.962 +assign wn_re[814] = 32'hxxxxxxxx; assign wn_im[814] = 32'hxxxxxxxx; // 814 0.279 0.960 +assign wn_re[815] = 32'hxxxxxxxx; assign wn_im[815] = 32'hxxxxxxxx; // 815 0.284 0.959 +assign wn_re[816] = 32'hxxxxxxxx; assign wn_im[816] = 32'hxxxxxxxx; // 816 0.290 0.957 +assign wn_re[817] = 32'hxxxxxxxx; assign wn_im[817] = 32'hxxxxxxxx; // 817 0.296 0.955 +assign wn_re[818] = 32'hxxxxxxxx; assign wn_im[818] = 32'hxxxxxxxx; // 818 0.302 0.953 +assign wn_re[819] = 32'hxxxxxxxx; assign wn_im[819] = 32'hxxxxxxxx; // 819 0.308 0.951 +assign wn_re[820] = 32'hxxxxxxxx; assign wn_im[820] = 32'hxxxxxxxx; // 820 0.314 0.950 +assign wn_re[821] = 32'hxxxxxxxx; assign wn_im[821] = 32'hxxxxxxxx; // 821 0.320 0.948 +assign wn_re[822] = 32'hxxxxxxxx; assign wn_im[822] = 32'hxxxxxxxx; // 822 0.325 0.946 +assign wn_re[823] = 32'hxxxxxxxx; assign wn_im[823] = 32'hxxxxxxxx; // 823 0.331 0.944 +assign wn_re[824] = 32'hxxxxxxxx; assign wn_im[824] = 32'hxxxxxxxx; // 824 0.337 0.942 +assign wn_re[825] = 32'hxxxxxxxx; assign wn_im[825] = 32'hxxxxxxxx; // 825 0.343 0.939 +assign wn_re[826] = 32'hxxxxxxxx; assign wn_im[826] = 32'hxxxxxxxx; // 826 0.348 0.937 +assign wn_re[827] = 32'hxxxxxxxx; assign wn_im[827] = 32'hxxxxxxxx; // 827 0.354 0.935 +assign wn_re[828] = 32'hxxxxxxxx; assign wn_im[828] = 32'hxxxxxxxx; // 828 0.360 0.933 +assign wn_re[829] = 32'hxxxxxxxx; assign wn_im[829] = 32'hxxxxxxxx; // 829 0.366 0.931 +assign wn_re[830] = 32'hxxxxxxxx; assign wn_im[830] = 32'hxxxxxxxx; // 830 0.371 0.929 +assign wn_re[831] = 32'hxxxxxxxx; assign wn_im[831] = 32'hxxxxxxxx; // 831 0.377 0.926 +assign wn_re[832] = 32'hxxxxxxxx; assign wn_im[832] = 32'hxxxxxxxx; // 832 0.383 0.924 +assign wn_re[833] = 32'hxxxxxxxx; assign wn_im[833] = 32'hxxxxxxxx; // 833 0.388 0.922 +assign wn_re[834] = 32'hxxxxxxxx; assign wn_im[834] = 32'hxxxxxxxx; // 834 0.394 0.919 +assign wn_re[835] = 32'hxxxxxxxx; assign wn_im[835] = 32'hxxxxxxxx; // 835 0.400 0.917 +assign wn_re[836] = 32'hxxxxxxxx; assign wn_im[836] = 32'hxxxxxxxx; // 836 0.405 0.914 +assign wn_re[837] = 32'hxxxxxxxx; assign wn_im[837] = 32'hxxxxxxxx; // 837 0.411 0.912 +assign wn_re[838] = 32'hxxxxxxxx; assign wn_im[838] = 32'hxxxxxxxx; // 838 0.416 0.909 +assign wn_re[839] = 32'hxxxxxxxx; assign wn_im[839] = 32'hxxxxxxxx; // 839 0.422 0.907 +assign wn_re[840] = 32'hxxxxxxxx; assign wn_im[840] = 32'hxxxxxxxx; // 840 0.428 0.904 +assign wn_re[841] = 32'hxxxxxxxx; assign wn_im[841] = 32'hxxxxxxxx; // 841 0.433 0.901 +assign wn_re[842] = 32'hxxxxxxxx; assign wn_im[842] = 32'hxxxxxxxx; // 842 0.439 0.899 +assign wn_re[843] = 32'hxxxxxxxx; assign wn_im[843] = 32'hxxxxxxxx; // 843 0.444 0.896 +assign wn_re[844] = 32'hxxxxxxxx; assign wn_im[844] = 32'hxxxxxxxx; // 844 0.450 0.893 +assign wn_re[845] = 32'hxxxxxxxx; assign wn_im[845] = 32'hxxxxxxxx; // 845 0.455 0.890 +assign wn_re[846] = 32'hxxxxxxxx; assign wn_im[846] = 32'hxxxxxxxx; // 846 0.461 0.888 +assign wn_re[847] = 32'hxxxxxxxx; assign wn_im[847] = 32'hxxxxxxxx; // 847 0.466 0.885 +assign wn_re[848] = 32'hxxxxxxxx; assign wn_im[848] = 32'hxxxxxxxx; // 848 0.471 0.882 +assign wn_re[849] = 32'hxxxxxxxx; assign wn_im[849] = 32'hxxxxxxxx; // 849 0.477 0.879 +assign wn_re[850] = 32'hxxxxxxxx; assign wn_im[850] = 32'hxxxxxxxx; // 850 0.482 0.876 +assign wn_re[851] = 32'hxxxxxxxx; assign wn_im[851] = 32'hxxxxxxxx; // 851 0.488 0.873 +assign wn_re[852] = 32'hxxxxxxxx; assign wn_im[852] = 32'hxxxxxxxx; // 852 0.493 0.870 +assign wn_re[853] = 32'hxxxxxxxx; assign wn_im[853] = 32'hxxxxxxxx; // 853 0.498 0.867 +assign wn_re[854] = 32'hxxxxxxxx; assign wn_im[854] = 32'hxxxxxxxx; // 854 0.504 0.864 +assign wn_re[855] = 32'hxxxxxxxx; assign wn_im[855] = 32'hxxxxxxxx; // 855 0.509 0.861 +assign wn_re[856] = 32'hxxxxxxxx; assign wn_im[856] = 32'hxxxxxxxx; // 856 0.514 0.858 +assign wn_re[857] = 32'hxxxxxxxx; assign wn_im[857] = 32'hxxxxxxxx; // 857 0.519 0.855 +assign wn_re[858] = 32'hxxxxxxxx; assign wn_im[858] = 32'hxxxxxxxx; // 858 0.525 0.851 +assign wn_re[859] = 32'hxxxxxxxx; assign wn_im[859] = 32'hxxxxxxxx; // 859 0.530 0.848 +assign wn_re[860] = 32'hxxxxxxxx; assign wn_im[860] = 32'hxxxxxxxx; // 860 0.535 0.845 +assign wn_re[861] = 32'hxxxxxxxx; assign wn_im[861] = 32'hxxxxxxxx; // 861 0.540 0.842 +assign wn_re[862] = 32'hxxxxxxxx; assign wn_im[862] = 32'hxxxxxxxx; // 862 0.545 0.838 +assign wn_re[863] = 32'hxxxxxxxx; assign wn_im[863] = 32'hxxxxxxxx; // 863 0.550 0.835 +assign wn_re[864] = 32'hxxxxxxxx; assign wn_im[864] = 32'hxxxxxxxx; // 864 0.556 0.831 +assign wn_re[865] = 32'hxxxxxxxx; assign wn_im[865] = 32'hxxxxxxxx; // 865 0.561 0.828 +assign wn_re[866] = 32'hxxxxxxxx; assign wn_im[866] = 32'hxxxxxxxx; // 866 0.566 0.825 +assign wn_re[867] = 32'hxxxxxxxx; assign wn_im[867] = 32'hxxxxxxxx; // 867 0.571 0.821 +assign wn_re[868] = 32'hxxxxxxxx; assign wn_im[868] = 32'hxxxxxxxx; // 868 0.576 0.818 +assign wn_re[869] = 32'hxxxxxxxx; assign wn_im[869] = 32'hxxxxxxxx; // 869 0.581 0.814 +assign wn_re[870] = 32'hxxxxxxxx; assign wn_im[870] = 32'hxxxxxxxx; // 870 0.586 0.810 +assign wn_re[871] = 32'hxxxxxxxx; assign wn_im[871] = 32'hxxxxxxxx; // 871 0.591 0.807 +assign wn_re[872] = 32'hxxxxxxxx; assign wn_im[872] = 32'hxxxxxxxx; // 872 0.596 0.803 +assign wn_re[873] = 32'hxxxxxxxx; assign wn_im[873] = 32'hxxxxxxxx; // 873 0.601 0.800 +assign wn_re[874] = 32'hxxxxxxxx; assign wn_im[874] = 32'hxxxxxxxx; // 874 0.606 0.796 +assign wn_re[875] = 32'hxxxxxxxx; assign wn_im[875] = 32'hxxxxxxxx; // 875 0.610 0.792 +assign wn_re[876] = 32'hxxxxxxxx; assign wn_im[876] = 32'hxxxxxxxx; // 876 0.615 0.788 +assign wn_re[877] = 32'hxxxxxxxx; assign wn_im[877] = 32'hxxxxxxxx; // 877 0.620 0.785 +assign wn_re[878] = 32'hxxxxxxxx; assign wn_im[878] = 32'hxxxxxxxx; // 878 0.625 0.781 +assign wn_re[879] = 32'hxxxxxxxx; assign wn_im[879] = 32'hxxxxxxxx; // 879 0.630 0.777 +assign wn_re[880] = 32'hxxxxxxxx; assign wn_im[880] = 32'hxxxxxxxx; // 880 0.634 0.773 +assign wn_re[881] = 32'hxxxxxxxx; assign wn_im[881] = 32'hxxxxxxxx; // 881 0.639 0.769 +assign wn_re[882] = 32'hxxxxxxxx; assign wn_im[882] = 32'hxxxxxxxx; // 882 0.644 0.765 +assign wn_re[883] = 32'hxxxxxxxx; assign wn_im[883] = 32'hxxxxxxxx; // 883 0.649 0.761 +assign wn_re[884] = 32'hxxxxxxxx; assign wn_im[884] = 32'hxxxxxxxx; // 884 0.653 0.757 +assign wn_re[885] = 32'hxxxxxxxx; assign wn_im[885] = 32'hxxxxxxxx; // 885 0.658 0.753 +assign wn_re[886] = 32'hxxxxxxxx; assign wn_im[886] = 32'hxxxxxxxx; // 886 0.662 0.749 +assign wn_re[887] = 32'hxxxxxxxx; assign wn_im[887] = 32'hxxxxxxxx; // 887 0.667 0.745 +assign wn_re[888] = 32'hxxxxxxxx; assign wn_im[888] = 32'hxxxxxxxx; // 888 0.672 0.741 +assign wn_re[889] = 32'hxxxxxxxx; assign wn_im[889] = 32'hxxxxxxxx; // 889 0.676 0.737 +assign wn_re[890] = 32'hxxxxxxxx; assign wn_im[890] = 32'hxxxxxxxx; // 890 0.681 0.733 +assign wn_re[891] = 32'hxxxxxxxx; assign wn_im[891] = 32'hxxxxxxxx; // 891 0.685 0.728 +assign wn_re[892] = 32'hxxxxxxxx; assign wn_im[892] = 32'hxxxxxxxx; // 892 0.690 0.724 +assign wn_re[893] = 32'hxxxxxxxx; assign wn_im[893] = 32'hxxxxxxxx; // 893 0.694 0.720 +assign wn_re[894] = 32'hxxxxxxxx; assign wn_im[894] = 32'hxxxxxxxx; // 894 0.698 0.716 +assign wn_re[895] = 32'hxxxxxxxx; assign wn_im[895] = 32'hxxxxxxxx; // 895 0.703 0.711 +assign wn_re[896] = 32'hxxxxxxxx; assign wn_im[896] = 32'hxxxxxxxx; // 896 0.707 0.707 +assign wn_re[897] = 32'hxxxxxxxx; assign wn_im[897] = 32'hxxxxxxxx; // 897 0.711 0.703 +assign wn_re[898] = 32'hxxxxxxxx; assign wn_im[898] = 32'hxxxxxxxx; // 898 0.716 0.698 +assign wn_re[899] = 32'hxxxxxxxx; assign wn_im[899] = 32'hxxxxxxxx; // 899 0.720 0.694 +assign wn_re[900] = 32'hxxxxxxxx; assign wn_im[900] = 32'hxxxxxxxx; // 900 0.724 0.690 +assign wn_re[901] = 32'hxxxxxxxx; assign wn_im[901] = 32'hxxxxxxxx; // 901 0.728 0.685 +assign wn_re[902] = 32'hxxxxxxxx; assign wn_im[902] = 32'hxxxxxxxx; // 902 0.733 0.681 +assign wn_re[903] = 32'hxxxxxxxx; assign wn_im[903] = 32'hxxxxxxxx; // 903 0.737 0.676 +assign wn_re[904] = 32'hxxxxxxxx; assign wn_im[904] = 32'hxxxxxxxx; // 904 0.741 0.672 +assign wn_re[905] = 32'hxxxxxxxx; assign wn_im[905] = 32'hxxxxxxxx; // 905 0.745 0.667 +assign wn_re[906] = 32'hxxxxxxxx; assign wn_im[906] = 32'hxxxxxxxx; // 906 0.749 0.662 +assign wn_re[907] = 32'hxxxxxxxx; assign wn_im[907] = 32'hxxxxxxxx; // 907 0.753 0.658 +assign wn_re[908] = 32'hxxxxxxxx; assign wn_im[908] = 32'hxxxxxxxx; // 908 0.757 0.653 +assign wn_re[909] = 32'hxxxxxxxx; assign wn_im[909] = 32'hxxxxxxxx; // 909 0.761 0.649 +assign wn_re[910] = 32'hxxxxxxxx; assign wn_im[910] = 32'hxxxxxxxx; // 910 0.765 0.644 +assign wn_re[911] = 32'hxxxxxxxx; assign wn_im[911] = 32'hxxxxxxxx; // 911 0.769 0.639 +assign wn_re[912] = 32'hxxxxxxxx; assign wn_im[912] = 32'hxxxxxxxx; // 912 0.773 0.634 +assign wn_re[913] = 32'hxxxxxxxx; assign wn_im[913] = 32'hxxxxxxxx; // 913 0.777 0.630 +assign wn_re[914] = 32'hxxxxxxxx; assign wn_im[914] = 32'hxxxxxxxx; // 914 0.781 0.625 +assign wn_re[915] = 32'hxxxxxxxx; assign wn_im[915] = 32'hxxxxxxxx; // 915 0.785 0.620 +assign wn_re[916] = 32'hxxxxxxxx; assign wn_im[916] = 32'hxxxxxxxx; // 916 0.788 0.615 +assign wn_re[917] = 32'hxxxxxxxx; assign wn_im[917] = 32'hxxxxxxxx; // 917 0.792 0.610 +assign wn_re[918] = 32'hxxxxxxxx; assign wn_im[918] = 32'hxxxxxxxx; // 918 0.796 0.606 +assign wn_re[919] = 32'hxxxxxxxx; assign wn_im[919] = 32'hxxxxxxxx; // 919 0.800 0.601 +assign wn_re[920] = 32'hxxxxxxxx; assign wn_im[920] = 32'hxxxxxxxx; // 920 0.803 0.596 +assign wn_re[921] = 32'hxxxxxxxx; assign wn_im[921] = 32'hxxxxxxxx; // 921 0.807 0.591 +assign wn_re[922] = 32'hxxxxxxxx; assign wn_im[922] = 32'hxxxxxxxx; // 922 0.810 0.586 +assign wn_re[923] = 32'hxxxxxxxx; assign wn_im[923] = 32'hxxxxxxxx; // 923 0.814 0.581 +assign wn_re[924] = 32'hxxxxxxxx; assign wn_im[924] = 32'hxxxxxxxx; // 924 0.818 0.576 +assign wn_re[925] = 32'hxxxxxxxx; assign wn_im[925] = 32'hxxxxxxxx; // 925 0.821 0.571 +assign wn_re[926] = 32'hxxxxxxxx; assign wn_im[926] = 32'hxxxxxxxx; // 926 0.825 0.566 +assign wn_re[927] = 32'hxxxxxxxx; assign wn_im[927] = 32'hxxxxxxxx; // 927 0.828 0.561 +assign wn_re[928] = 32'hxxxxxxxx; assign wn_im[928] = 32'hxxxxxxxx; // 928 0.831 0.556 +assign wn_re[929] = 32'hxxxxxxxx; assign wn_im[929] = 32'hxxxxxxxx; // 929 0.835 0.550 +assign wn_re[930] = 32'hxxxxxxxx; assign wn_im[930] = 32'hxxxxxxxx; // 930 0.838 0.545 +assign wn_re[931] = 32'hxxxxxxxx; assign wn_im[931] = 32'hxxxxxxxx; // 931 0.842 0.540 +assign wn_re[932] = 32'hxxxxxxxx; assign wn_im[932] = 32'hxxxxxxxx; // 932 0.845 0.535 +assign wn_re[933] = 32'hxxxxxxxx; assign wn_im[933] = 32'hxxxxxxxx; // 933 0.848 0.530 +assign wn_re[934] = 32'hxxxxxxxx; assign wn_im[934] = 32'hxxxxxxxx; // 934 0.851 0.525 +assign wn_re[935] = 32'hxxxxxxxx; assign wn_im[935] = 32'hxxxxxxxx; // 935 0.855 0.519 +assign wn_re[936] = 32'hxxxxxxxx; assign wn_im[936] = 32'hxxxxxxxx; // 936 0.858 0.514 +assign wn_re[937] = 32'hxxxxxxxx; assign wn_im[937] = 32'hxxxxxxxx; // 937 0.861 0.509 +assign wn_re[938] = 32'hxxxxxxxx; assign wn_im[938] = 32'hxxxxxxxx; // 938 0.864 0.504 +assign wn_re[939] = 32'hxxxxxxxx; assign wn_im[939] = 32'hxxxxxxxx; // 939 0.867 0.498 +assign wn_re[940] = 32'hxxxxxxxx; assign wn_im[940] = 32'hxxxxxxxx; // 940 0.870 0.493 +assign wn_re[941] = 32'hxxxxxxxx; assign wn_im[941] = 32'hxxxxxxxx; // 941 0.873 0.488 +assign wn_re[942] = 32'hxxxxxxxx; assign wn_im[942] = 32'hxxxxxxxx; // 942 0.876 0.482 +assign wn_re[943] = 32'hxxxxxxxx; assign wn_im[943] = 32'hxxxxxxxx; // 943 0.879 0.477 +assign wn_re[944] = 32'hxxxxxxxx; assign wn_im[944] = 32'hxxxxxxxx; // 944 0.882 0.471 +assign wn_re[945] = 32'hxxxxxxxx; assign wn_im[945] = 32'hxxxxxxxx; // 945 0.885 0.466 +assign wn_re[946] = 32'hxxxxxxxx; assign wn_im[946] = 32'hxxxxxxxx; // 946 0.888 0.461 +assign wn_re[947] = 32'hxxxxxxxx; assign wn_im[947] = 32'hxxxxxxxx; // 947 0.890 0.455 +assign wn_re[948] = 32'hxxxxxxxx; assign wn_im[948] = 32'hxxxxxxxx; // 948 0.893 0.450 +assign wn_re[949] = 32'hxxxxxxxx; assign wn_im[949] = 32'hxxxxxxxx; // 949 0.896 0.444 +assign wn_re[950] = 32'hxxxxxxxx; assign wn_im[950] = 32'hxxxxxxxx; // 950 0.899 0.439 +assign wn_re[951] = 32'hxxxxxxxx; assign wn_im[951] = 32'hxxxxxxxx; // 951 0.901 0.433 +assign wn_re[952] = 32'hxxxxxxxx; assign wn_im[952] = 32'hxxxxxxxx; // 952 0.904 0.428 +assign wn_re[953] = 32'hxxxxxxxx; assign wn_im[953] = 32'hxxxxxxxx; // 953 0.907 0.422 +assign wn_re[954] = 32'hxxxxxxxx; assign wn_im[954] = 32'hxxxxxxxx; // 954 0.909 0.416 +assign wn_re[955] = 32'hxxxxxxxx; assign wn_im[955] = 32'hxxxxxxxx; // 955 0.912 0.411 +assign wn_re[956] = 32'hxxxxxxxx; assign wn_im[956] = 32'hxxxxxxxx; // 956 0.914 0.405 +assign wn_re[957] = 32'hxxxxxxxx; assign wn_im[957] = 32'hxxxxxxxx; // 957 0.917 0.400 +assign wn_re[958] = 32'hxxxxxxxx; assign wn_im[958] = 32'hxxxxxxxx; // 958 0.919 0.394 +assign wn_re[959] = 32'hxxxxxxxx; assign wn_im[959] = 32'hxxxxxxxx; // 959 0.922 0.388 +assign wn_re[960] = 32'hxxxxxxxx; assign wn_im[960] = 32'hxxxxxxxx; // 960 0.924 0.383 +assign wn_re[961] = 32'hxxxxxxxx; assign wn_im[961] = 32'hxxxxxxxx; // 961 0.926 0.377 +assign wn_re[962] = 32'hxxxxxxxx; assign wn_im[962] = 32'hxxxxxxxx; // 962 0.929 0.371 +assign wn_re[963] = 32'hxxxxxxxx; assign wn_im[963] = 32'hxxxxxxxx; // 963 0.931 0.366 +assign wn_re[964] = 32'hxxxxxxxx; assign wn_im[964] = 32'hxxxxxxxx; // 964 0.933 0.360 +assign wn_re[965] = 32'hxxxxxxxx; assign wn_im[965] = 32'hxxxxxxxx; // 965 0.935 0.354 +assign wn_re[966] = 32'hxxxxxxxx; assign wn_im[966] = 32'hxxxxxxxx; // 966 0.937 0.348 +assign wn_re[967] = 32'hxxxxxxxx; assign wn_im[967] = 32'hxxxxxxxx; // 967 0.939 0.343 +assign wn_re[968] = 32'hxxxxxxxx; assign wn_im[968] = 32'hxxxxxxxx; // 968 0.942 0.337 +assign wn_re[969] = 32'hxxxxxxxx; assign wn_im[969] = 32'hxxxxxxxx; // 969 0.944 0.331 +assign wn_re[970] = 32'hxxxxxxxx; assign wn_im[970] = 32'hxxxxxxxx; // 970 0.946 0.325 +assign wn_re[971] = 32'hxxxxxxxx; assign wn_im[971] = 32'hxxxxxxxx; // 971 0.948 0.320 +assign wn_re[972] = 32'hxxxxxxxx; assign wn_im[972] = 32'hxxxxxxxx; // 972 0.950 0.314 +assign wn_re[973] = 32'hxxxxxxxx; assign wn_im[973] = 32'hxxxxxxxx; // 973 0.951 0.308 +assign wn_re[974] = 32'hxxxxxxxx; assign wn_im[974] = 32'hxxxxxxxx; // 974 0.953 0.302 +assign wn_re[975] = 32'hxxxxxxxx; assign wn_im[975] = 32'hxxxxxxxx; // 975 0.955 0.296 +assign wn_re[976] = 32'hxxxxxxxx; assign wn_im[976] = 32'hxxxxxxxx; // 976 0.957 0.290 +assign wn_re[977] = 32'hxxxxxxxx; assign wn_im[977] = 32'hxxxxxxxx; // 977 0.959 0.284 +assign wn_re[978] = 32'hxxxxxxxx; assign wn_im[978] = 32'hxxxxxxxx; // 978 0.960 0.279 +assign wn_re[979] = 32'hxxxxxxxx; assign wn_im[979] = 32'hxxxxxxxx; // 979 0.962 0.273 +assign wn_re[980] = 32'hxxxxxxxx; assign wn_im[980] = 32'hxxxxxxxx; // 980 0.964 0.267 +assign wn_re[981] = 32'hxxxxxxxx; assign wn_im[981] = 32'hxxxxxxxx; // 981 0.965 0.261 +assign wn_re[982] = 32'hxxxxxxxx; assign wn_im[982] = 32'hxxxxxxxx; // 982 0.967 0.255 +assign wn_re[983] = 32'hxxxxxxxx; assign wn_im[983] = 32'hxxxxxxxx; // 983 0.969 0.249 +assign wn_re[984] = 32'hxxxxxxxx; assign wn_im[984] = 32'hxxxxxxxx; // 984 0.970 0.243 +assign wn_re[985] = 32'hxxxxxxxx; assign wn_im[985] = 32'hxxxxxxxx; // 985 0.972 0.237 +assign wn_re[986] = 32'hxxxxxxxx; assign wn_im[986] = 32'hxxxxxxxx; // 986 0.973 0.231 +assign wn_re[987] = 32'hxxxxxxxx; assign wn_im[987] = 32'hxxxxxxxx; // 987 0.974 0.225 +assign wn_re[988] = 32'hxxxxxxxx; assign wn_im[988] = 32'hxxxxxxxx; // 988 0.976 0.219 +assign wn_re[989] = 32'hxxxxxxxx; assign wn_im[989] = 32'hxxxxxxxx; // 989 0.977 0.213 +assign wn_re[990] = 32'hxxxxxxxx; assign wn_im[990] = 32'hxxxxxxxx; // 990 0.978 0.207 +assign wn_re[991] = 32'hxxxxxxxx; assign wn_im[991] = 32'hxxxxxxxx; // 991 0.980 0.201 +assign wn_re[992] = 32'hxxxxxxxx; assign wn_im[992] = 32'hxxxxxxxx; // 992 0.981 0.195 +assign wn_re[993] = 32'hxxxxxxxx; assign wn_im[993] = 32'hxxxxxxxx; // 993 0.982 0.189 +assign wn_re[994] = 32'hxxxxxxxx; assign wn_im[994] = 32'hxxxxxxxx; // 994 0.983 0.183 +assign wn_re[995] = 32'hxxxxxxxx; assign wn_im[995] = 32'hxxxxxxxx; // 995 0.984 0.177 +assign wn_re[996] = 32'hxxxxxxxx; assign wn_im[996] = 32'hxxxxxxxx; // 996 0.985 0.171 +assign wn_re[997] = 32'hxxxxxxxx; assign wn_im[997] = 32'hxxxxxxxx; // 997 0.986 0.165 +assign wn_re[998] = 32'hxxxxxxxx; assign wn_im[998] = 32'hxxxxxxxx; // 998 0.987 0.159 +assign wn_re[999] = 32'hxxxxxxxx; assign wn_im[999] = 32'hxxxxxxxx; // 999 0.988 0.153 +assign wn_re[1000] = 32'hxxxxxxxx; assign wn_im[1000] = 32'hxxxxxxxx; // 1000 0.989 0.147 +assign wn_re[1001] = 32'hxxxxxxxx; assign wn_im[1001] = 32'hxxxxxxxx; // 1001 0.990 0.141 +assign wn_re[1002] = 32'hxxxxxxxx; assign wn_im[1002] = 32'hxxxxxxxx; // 1002 0.991 0.135 +assign wn_re[1003] = 32'hxxxxxxxx; assign wn_im[1003] = 32'hxxxxxxxx; // 1003 0.992 0.128 +assign wn_re[1004] = 32'hxxxxxxxx; assign wn_im[1004] = 32'hxxxxxxxx; // 1004 0.992 0.122 +assign wn_re[1005] = 32'hxxxxxxxx; assign wn_im[1005] = 32'hxxxxxxxx; // 1005 0.993 0.116 +assign wn_re[1006] = 32'hxxxxxxxx; assign wn_im[1006] = 32'hxxxxxxxx; // 1006 0.994 0.110 +assign wn_re[1007] = 32'hxxxxxxxx; assign wn_im[1007] = 32'hxxxxxxxx; // 1007 0.995 0.104 +assign wn_re[1008] = 32'hxxxxxxxx; assign wn_im[1008] = 32'hxxxxxxxx; // 1008 0.995 0.098 +assign wn_re[1009] = 32'hxxxxxxxx; assign wn_im[1009] = 32'hxxxxxxxx; // 1009 0.996 0.092 +assign wn_re[1010] = 32'hxxxxxxxx; assign wn_im[1010] = 32'hxxxxxxxx; // 1010 0.996 0.086 +assign wn_re[1011] = 32'hxxxxxxxx; assign wn_im[1011] = 32'hxxxxxxxx; // 1011 0.997 0.080 +assign wn_re[1012] = 32'hxxxxxxxx; assign wn_im[1012] = 32'hxxxxxxxx; // 1012 0.997 0.074 +assign wn_re[1013] = 32'hxxxxxxxx; assign wn_im[1013] = 32'hxxxxxxxx; // 1013 0.998 0.067 +assign wn_re[1014] = 32'hxxxxxxxx; assign wn_im[1014] = 32'hxxxxxxxx; // 1014 0.998 0.061 +assign wn_re[1015] = 32'hxxxxxxxx; assign wn_im[1015] = 32'hxxxxxxxx; // 1015 0.998 0.055 +assign wn_re[1016] = 32'hxxxxxxxx; assign wn_im[1016] = 32'hxxxxxxxx; // 1016 0.999 0.049 +assign wn_re[1017] = 32'hxxxxxxxx; assign wn_im[1017] = 32'hxxxxxxxx; // 1017 0.999 0.043 +assign wn_re[1018] = 32'hxxxxxxxx; assign wn_im[1018] = 32'hxxxxxxxx; // 1018 0.999 0.037 +assign wn_re[1019] = 32'hxxxxxxxx; assign wn_im[1019] = 32'hxxxxxxxx; // 1019 1.000 0.031 +assign wn_re[1020] = 32'hxxxxxxxx; assign wn_im[1020] = 32'hxxxxxxxx; // 1020 1.000 0.025 +assign wn_re[1021] = 32'hxxxxxxxx; assign wn_im[1021] = 32'hxxxxxxxx; // 1021 1.000 0.018 +assign wn_re[1022] = 32'hxxxxxxxx; assign wn_im[1022] = 32'hxxxxxxxx; // 1022 1.000 0.012 +assign wn_re[1023] = 32'hxxxxxxxx; assign wn_im[1023] = 32'hxxxxxxxx; // 1023 1.000 0.006 + +endmodule diff --git a/rtl/ip/fft/axi_fft_wrapper.v b/rtl/ip/fft/axi_fft_wrapper.v new file mode 100644 index 0000000..d67f2f9 --- /dev/null +++ b/rtl/ip/fft/axi_fft_wrapper.v @@ -0,0 +1,383 @@ +`define FFT_CSR_ADDR 16'hf000 +`define FFT_IN_RE_BASE 16'h1000 +`define FFT_IN_IM_BASE 16'h2000 +`define FFT_OUT_RE_BASE 16'h3000 +`define FFT_OUT_IM_BASE 16'h4000 + +module fft_controller #( + parameter FFT_LEN = 1024, // FFT处理长度 + parameter BRAM_RD_LATENCY = 2 // 适配 BRAM 的读延迟 (通常 Block RAM 开启输出寄存器为 2) +)( + input aclk, + input aresetn, + + // AXI Lite / AXI4 Wrapper ports + input [4 :0] s_awid, + input [31:0] s_awaddr, + input [7 :0] s_awlen, + input [2 :0] s_awsize, + input [1 :0] s_awburst, + input s_awlock, + input [3 :0] s_awcache, + input [2 :0] s_awprot, + input s_awvalid, + output reg s_awready, + input [4 :0] s_wid, + input [31:0] s_wdata, + input [3 :0] s_wstrb, + input s_wlast, + input s_wvalid, + output reg s_wready, + output [4 :0] s_bid, + output [1 :0] s_bresp, + output reg s_bvalid, + input s_bready, + + input [4 :0] s_arid, + input [31:0] s_araddr, + input [7 :0] s_arlen, + input [2 :0] s_arsize, + input [1 :0] s_arburst, + input s_arlock, + input [3 :0] s_arcache, + input [2 :0] s_arprot, + input s_arvalid, + output reg s_arready, + output [4 :0] s_rid, + output reg [31:0] s_rdata, + output [1 :0] s_rresp, + output reg s_rlast, + output reg s_rvalid, + input s_rready, + + output fft_finish +); + + // AXI Burst 内部寄存器 + reg [31:0] aw_addr_reg; + reg [1 :0] aw_burst_reg; + reg [4 :0] aw_id_reg; + + reg [31:0] ar_addr_reg; + reg [7 :0] ar_len_reg; + reg [1 :0] ar_burst_reg; + reg [4 :0] ar_id_reg; + reg [7 :0] ar_cnt; + + // 写通道状态机 (AW, W, B) + localparam W_IDLE = 2'd0; + localparam W_DATA = 2'd1; + localparam W_RESP = 2'd2; + reg [1:0] w_state; + + always @(posedge aclk) begin + if (~aresetn) begin + w_state <= W_IDLE; + s_awready <= 1'b1; + s_wready <= 1'b0; + s_bvalid <= 1'b0; + aw_addr_reg <= 32'h0; + aw_burst_reg <= 2'h0; + aw_id_reg <= 5'h0; + end else begin + case (w_state) + W_IDLE: begin + s_awready <= 1'b1; + if (s_awvalid && s_awready) begin + s_awready <= 1'b0; + s_wready <= 1'b1; + aw_addr_reg <= s_awaddr; + aw_burst_reg <= s_awburst; + aw_id_reg <= s_awid; + w_state <= W_DATA; + end + end + W_DATA: begin + // 接收到有效写数据 + if (s_wvalid && s_wready) begin + // INCR 模式下地址递增 + if (aw_burst_reg == 2'b01) begin + aw_addr_reg <= aw_addr_reg + 4; + end + // 若是最后一拍，跳转到发送响应 + if (s_wlast) begin + s_wready <= 1'b0; + s_bvalid <= 1'b1; + w_state <= W_RESP; + end + end + end + W_RESP: begin + if (s_bvalid && s_bready) begin + s_bvalid <= 1'b0; + s_awready <= 1'b1; // 准备接收下一次写请求 + w_state <= W_IDLE; + end + end + default: w_state <= W_IDLE; + endcase + end + end + + // 产生有效的写动作脉冲，用于触发 BRAM 写使能 + wire w_active = (w_state == W_DATA) && s_wvalid && s_wready; + assign s_bid = aw_id_reg; + assign s_bresp = 2'b00; + + // 读通道状态机(AR, R) + localparam R_IDLE = 2'd0; + localparam R_WAIT = 2'd1; + localparam R_DATA = 2'd2; + reg [1:0] r_state; + reg [3:0] r_wait_cnt; + + always @(posedge aclk) begin + if (~aresetn) begin + r_state <= R_IDLE; + s_arready <= 1'b1; + s_rvalid <= 1'b0; + s_rlast <= 1'b0; + ar_addr_reg <= 32'h0; + ar_len_reg <= 8'h0; + ar_burst_reg <= 2'h0; + ar_id_reg <= 5'h0; + ar_cnt <= 8'h0; + r_wait_cnt <= 4'h0; + end else begin + case (r_state) + R_IDLE: begin + s_arready <= 1'b1; + if (s_arvalid && s_arready) begin + s_arready <= 1'b0; + ar_addr_reg <= s_araddr; + ar_len_reg <= s_arlen; + ar_burst_reg <= s_arburst; + ar_id_reg <= s_arid; + ar_cnt <= 8'h0; + r_wait_cnt <= BRAM_RD_LATENCY; + r_state <= R_WAIT; // 进入等待以拉取第一笔 BRAM 数据 + end + end + R_WAIT: begin + // 等待 BRAM 固定潜伏期结束 + if (r_wait_cnt <= 1) begin + s_rvalid <= 1'b1; + s_rlast <= (ar_cnt == ar_len_reg); + r_state <= R_DATA; + r_wait_cnt <= 4'h0; + end else begin + r_wait_cnt <= r_wait_cnt - 1; + end + end + R_DATA: begin + // 数据被总线成功读取 + if (s_rvalid && s_rready) begin + if (ar_cnt == ar_len_reg) begin + // Burst 结束 + s_rvalid <= 1'b0; + s_rlast <= 1'b0; + s_arready <= 1'b1; + r_state <= R_IDLE; + end else begin + // 准备读取下一拍数据 + ar_cnt <= ar_cnt + 1; + // INCR 模式下地址递增 + if (ar_burst_reg == 2'b01) begin + ar_addr_reg <= ar_addr_reg + 4; + end + s_rvalid <= 1'b0; + s_rlast <= 1'b0; + r_wait_cnt <= BRAM_RD_LATENCY; + r_state <= R_WAIT; // 再次进入等待状态 + end + end + end + default: r_state <= R_IDLE; + endcase + end + end + + assign s_rid = ar_id_reg; + assign s_rresp = 2'b00; + + // 地址译码 + wire hit_in_re = (aw_addr_reg[15:12] == 4'h1); + wire hit_in_im = (aw_addr_reg[15:12] == 4'h2); + wire hit_out_re = (ar_addr_reg[15:12] == 4'h3); + wire hit_out_im = (ar_addr_reg[15:12] == 4'h4); + + // 寄存器控制 + reg [3:0] fft_ctrl; + reg [3:0] fft_status; + + wire [31:0] fft_csr = {24'h0, fft_ctrl, fft_status}; + // 只有发生有效的写握手且地址对应 CSR 时，才写入控制寄存器 + wire write_fft_csr = w_active && (aw_addr_reg[15:0] == `FFT_CSR_ADDR); + + // 状态机 + localparam IDLE = 2'd0; + localparam LOAD = 2'd1; + localparam WAIT_OUT = 2'd2; + localparam DONE = 2'd3; + + reg [1:0] state, next_state; + reg [10:0] in_cnt; + reg [10:0] out_cnt; + + wire do_en; + wire [31:0] do_re; + wire [31:0] do_im; + + always @(posedge aclk) begin + if (~aresetn) state <= IDLE; + else state <= next_state; + end + + always @(*) begin + case (state) + IDLE: if (fft_ctrl[0]) next_state = LOAD; else next_state = IDLE; + LOAD: if (in_cnt == FFT_LEN - 1) next_state = WAIT_OUT; else next_state = LOAD; + WAIT_OUT: if (do_en && out_cnt == FFT_LEN - 1) next_state = DONE; else next_state = WAIT_OUT; + DONE: next_state = IDLE; + default: next_state = IDLE; + endcase + end + + always @(posedge aclk) begin + if (~aresetn) begin + in_cnt <= 0; + out_cnt <= 0; + end else if (state == IDLE) begin + in_cnt <= 0; + out_cnt <= 0; + end else begin + if (state == LOAD) in_cnt <= in_cnt + 1; + if (do_en) out_cnt <= out_cnt + 1; + end + end + + // 更新寄存器与状态 + always @(posedge aclk) begin + if (~aresetn) begin + fft_ctrl <= 4'h0; + fft_status <= 4'h0; + end else begin + if (write_fft_csr) begin + fft_ctrl <= s_wdata[7:4]; + end else if (state != IDLE) begin + fft_ctrl[0] <= 1'b0; + end + + fft_status[0] <= (state != IDLE && state != DONE); + + if (write_fft_csr && s_wdata[4]) begin + fft_status[1] <= 1'b0; + end else if (state == DONE) begin + fft_status[1] <= 1'b1; + end + end + end + + assign fft_finish = fft_status[1]; + + // BRAM 接口连线 + wire [31:0] in_re_dout; + wire [31:0] in_im_dout; + wire [31:0] out_re_dout; + wire [31:0] out_im_dout; + + my_bram0 u_in0( + .clka (aclk), + .ena (w_active && hit_in_re), // 由 burst写逻辑产生 + .wea (1'b1), + .addra (aw_addr_reg[11:2]), // 取当前递增的突发写地址 + .dina (s_wdata), + + .clkb (aclk), + .enb (state == LOAD), + .addrb (in_cnt[9:0]), + .doutb (in_re_dout) + ); + + my_bram0 u_in1( + .clka (aclk), + .ena (w_active && hit_in_im), + .wea (1'b1), + .addra (aw_addr_reg[11:2]), + .dina (s_wdata), + + .clkb (aclk), + .enb (state == LOAD), + .addrb (in_cnt[9:0]), + .doutb (in_im_dout) + ); + + // 对于输出 BRAM，采用原先的位反转（Bit-reverse）读取逻辑 + wire [9:0] b_rd_addr = ar_addr_reg[11:2]; + wire [9:0] bit_reversed_index = { + b_rd_addr[0], b_rd_addr[1], b_rd_addr[2], b_rd_addr[3], b_rd_addr[4], + b_rd_addr[5], b_rd_addr[6], b_rd_addr[7], b_rd_addr[8], b_rd_addr[9] + }; + + my_bram0 u_out0( + .clka (aclk), + .ena (do_en), + .wea (1'b1), + .addra (out_cnt[9:0]), + .dina (do_re), + + .clkb (aclk), + .enb (r_state != R_IDLE), // 当处于读突发事务时始终使能 BRAM + .addrb (bit_reversed_index), + .doutb (out_re_dout) + ); + + my_bram0 u_out1( + .clka (aclk), + .ena (do_en), + .wea (1'b1), + .addra (out_cnt[9:0]), + .dina (do_im), + + .clkb (aclk), + .enb (r_state != R_IDLE), + .addrb (bit_reversed_index), + .doutb (out_im_dout) + ); + + // 支持 1 到 N 拍的读延迟，让 di_en 严格对齐 BRAM 的吐出数据 + reg [3:0] di_en_shift; + always @(posedge aclk) begin + if (~aresetn) di_en_shift <= 0; + else di_en_shift <= {di_en_shift[2:0], (state == LOAD)}; + end + + wire di_en_r = (BRAM_RD_LATENCY == 1) ? di_en_shift[0] : + (BRAM_RD_LATENCY == 2) ? di_en_shift[1] : + (BRAM_RD_LATENCY == 3) ? di_en_shift[2] : di_en_shift[3]; + + FFT #( + .WIDTH(32) + ) u_FFT ( + .clock (aclk), + .reset (~aresetn), + .di_en (di_en_r), + .di_re (in_re_dout), + .di_im (in_im_dout), + .do_en (do_en), + .do_re (do_re), + .do_im (do_im) + ); + + // 读取返回数据选择 + wire [31:0] rdata_d = + (ar_addr_reg[15:0] == `FFT_CSR_ADDR) ? fft_csr : + hit_out_re ? out_re_dout : + hit_out_im ? out_im_dout : + 32'h0; + + always @(*) begin + s_rdata = rdata_d; + end + +endmodule \ No newline at end of file diff --git a/rtl/ip/matmul/matmul_axi_slave.v b/rtl/ip/matmul/matmul_axi_slave.v new file mode 100644 index 0000000..c8d5d02 --- /dev/null +++ b/rtl/ip/matmul/matmul_axi_slave.v @@ -0,0 +1,303 @@ +module matmul_axi_slave ( + input clk, + input resetn, + + input [4:0] s_axi_awid, + input [31:0] s_axi_awaddr, + input [7:0] s_axi_awlen, + input [2:0] s_axi_awsize, + input [1:0] s_axi_awburst, + input s_axi_awlock, + input [3:0] s_axi_awcache, + input [2:0] s_axi_awprot, + input s_axi_awvalid, + output s_axi_awready, + + input [4:0] s_axi_wid, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + input s_axi_wlast, + input s_axi_wvalid, + output s_axi_wready, + + output reg [4:0] s_axi_bid, + output [1:0] s_axi_bresp, + output reg s_axi_bvalid, + input s_axi_bready, + + input [4:0] s_axi_arid, + input [31:0] s_axi_araddr, + input [7:0] s_axi_arlen, + input [2:0] s_axi_arsize, + input [1:0] s_axi_arburst, + input s_axi_arlock, + input [3:0] s_axi_arcache, + input [2:0] s_axi_arprot, + input s_axi_arvalid, + output s_axi_arready, + + output reg [4:0] s_axi_rid, + output reg [31:0] s_axi_rdata, + output [1:0] s_axi_rresp, + output s_axi_rlast, + output reg s_axi_rvalid, + input s_axi_rready +); + +localparam ADDR_CTRL = 12'h000; +localparam ADDR_STATUS = 12'h004; +localparam ADDR_SRC_BASE = 12'h008; +localparam ADDR_DST_BASE = 12'h00c; +localparam ADDR_GROUP_NUM = 12'h010; +localparam ADDR_A_BASE = 12'h020; +localparam ADDR_B_BASE = 12'h060; +localparam ADDR_C_BASE = 12'h0a0; + +reg [31:0] src_base; +reg [31:0] dst_base; +reg [31:0] group_num; +reg [31:0] a_data [0:15]; +reg [31:0] b_data [0:15]; +reg [65:0] c_data [0:15]; + +reg [31:0] awaddr_hold; +reg [4:0] awid_hold; +reg aw_hold_valid; +reg [31:0] wdata_hold; +reg [3:0] wstrb_hold; +reg w_hold_valid; + +reg busy; +reg done; +reg error; +reg [3:0] calc_index; + +wire write_fire; +wire start_fire; +wire [11:0] write_offset = awaddr_hold[11:0]; +wire [11:0] read_offset = s_axi_araddr[11:0]; + +assign s_axi_awready = !aw_hold_valid; +assign s_axi_wready = !w_hold_valid; +assign s_axi_bresp = 2'b00; +assign s_axi_arready = !s_axi_rvalid; +assign s_axi_rresp = 2'b00; +assign s_axi_rlast = 1'b1; + +assign write_fire = aw_hold_valid && w_hold_valid && !s_axi_bvalid; +assign start_fire = write_fire && (write_offset == ADDR_CTRL) && wdata_hold[0] && !busy; + +function [31:0] apply_wstrb; + input [31:0] old_value; + input [31:0] new_value; + input [3:0] strobe; + begin + apply_wstrb = old_value; + if (strobe[0]) apply_wstrb[7:0] = new_value[7:0]; + if (strobe[1]) apply_wstrb[15:8] = new_value[15:8]; + if (strobe[2]) apply_wstrb[23:16] = new_value[23:16]; + if (strobe[3]) apply_wstrb[31:24] = new_value[31:24]; + end +endfunction + +function [63:0] mul_u32_shift_add; + input [31:0] lhs; + input [31:0] rhs; + integer bit_index; + begin + mul_u32_shift_add = 64'b0; + for (bit_index = 0; bit_index < 32; bit_index = bit_index + 1) begin + if (rhs[bit_index]) begin + mul_u32_shift_add = mul_u32_shift_add + ({32'b0, lhs} << bit_index); + end + end + end +endfunction + +function [65:0] calc_c_element; + input [3:0] index; + reg [1:0] row; + reg [1:0] col; + begin + row = index[3:2]; + col = index[1:0]; + calc_c_element = {2'b0, mul_u32_shift_add(a_data[{row, 2'd0}], b_data[{2'd0, col}])} + + {2'b0, mul_u32_shift_add(a_data[{row, 2'd1}], b_data[{2'd1, col}])} + + {2'b0, mul_u32_shift_add(a_data[{row, 2'd2}], b_data[{2'd2, col}])} + + {2'b0, mul_u32_shift_add(a_data[{row, 2'd3}], b_data[{2'd3, col}])}; + end +endfunction + +function [31:0] c_read_word; + input [5:0] word_index; + begin + case (word_index) + 6'd0: c_read_word = c_data[0][31:0]; + 6'd1: c_read_word = c_data[0][63:32]; + 6'd2: c_read_word = {30'b0, c_data[0][65:64]}; + 6'd3: c_read_word = c_data[1][31:0]; + 6'd4: c_read_word = c_data[1][63:32]; + 6'd5: c_read_word = {30'b0, c_data[1][65:64]}; + 6'd6: c_read_word = c_data[2][31:0]; + 6'd7: c_read_word = c_data[2][63:32]; + 6'd8: c_read_word = {30'b0, c_data[2][65:64]}; + 6'd9: c_read_word = c_data[3][31:0]; + 6'd10: c_read_word = c_data[3][63:32]; + 6'd11: c_read_word = {30'b0, c_data[3][65:64]}; + 6'd12: c_read_word = c_data[4][31:0]; + 6'd13: c_read_word = c_data[4][63:32]; + 6'd14: c_read_word = {30'b0, c_data[4][65:64]}; + 6'd15: c_read_word = c_data[5][31:0]; + 6'd16: c_read_word = c_data[5][63:32]; + 6'd17: c_read_word = {30'b0, c_data[5][65:64]}; + 6'd18: c_read_word = c_data[6][31:0]; + 6'd19: c_read_word = c_data[6][63:32]; + 6'd20: c_read_word = {30'b0, c_data[6][65:64]}; + 6'd21: c_read_word = c_data[7][31:0]; + 6'd22: c_read_word = c_data[7][63:32]; + 6'd23: c_read_word = {30'b0, c_data[7][65:64]}; + 6'd24: c_read_word = c_data[8][31:0]; + 6'd25: c_read_word = c_data[8][63:32]; + 6'd26: c_read_word = {30'b0, c_data[8][65:64]}; + 6'd27: c_read_word = c_data[9][31:0]; + 6'd28: c_read_word = c_data[9][63:32]; + 6'd29: c_read_word = {30'b0, c_data[9][65:64]}; + 6'd30: c_read_word = c_data[10][31:0]; + 6'd31: c_read_word = c_data[10][63:32]; + 6'd32: c_read_word = {30'b0, c_data[10][65:64]}; + 6'd33: c_read_word = c_data[11][31:0]; + 6'd34: c_read_word = c_data[11][63:32]; + 6'd35: c_read_word = {30'b0, c_data[11][65:64]}; + 6'd36: c_read_word = c_data[12][31:0]; + 6'd37: c_read_word = c_data[12][63:32]; + 6'd38: c_read_word = {30'b0, c_data[12][65:64]}; + 6'd39: c_read_word = c_data[13][31:0]; + 6'd40: c_read_word = c_data[13][63:32]; + 6'd41: c_read_word = {30'b0, c_data[13][65:64]}; + 6'd42: c_read_word = c_data[14][31:0]; + 6'd43: c_read_word = c_data[14][63:32]; + 6'd44: c_read_word = {30'b0, c_data[14][65:64]}; + 6'd45: c_read_word = c_data[15][31:0]; + 6'd46: c_read_word = c_data[15][63:32]; + 6'd47: c_read_word = {30'b0, c_data[15][65:64]}; + default: c_read_word = 32'b0; + endcase + end +endfunction + +integer i; +always @(posedge clk) begin + if (!resetn) begin + src_base <= 32'b0; + dst_base <= 32'b0; + group_num <= 32'd1; + awaddr_hold <= 32'b0; + awid_hold <= 5'b0; + aw_hold_valid <= 1'b0; + wdata_hold <= 32'b0; + wstrb_hold <= 4'b0; + w_hold_valid <= 1'b0; + s_axi_bid <= 5'b0; + s_axi_bvalid <= 1'b0; + s_axi_rid <= 5'b0; + s_axi_rdata <= 32'b0; + s_axi_rvalid <= 1'b0; + busy <= 1'b0; + done <= 1'b0; + error <= 1'b0; + calc_index <= 4'b0; + + for (i = 0; i < 16; i = i + 1) begin + a_data[i] <= 32'b0; + b_data[i] <= 32'b0; + c_data[i] <= 66'b0; + end + end else begin + if (s_axi_awvalid && s_axi_awready) begin + awaddr_hold <= s_axi_awaddr; + awid_hold <= s_axi_awid; + aw_hold_valid <= 1'b1; + end + + if (s_axi_wvalid && s_axi_wready) begin + wdata_hold <= s_axi_wdata; + wstrb_hold <= s_axi_wstrb; + w_hold_valid <= 1'b1; + end + + if (s_axi_bvalid && s_axi_bready) begin + s_axi_bvalid <= 1'b0; + end + + if (write_fire) begin + s_axi_bid <= awid_hold; + s_axi_bvalid <= 1'b1; + aw_hold_valid <= 1'b0; + w_hold_valid <= 1'b0; + + if (write_offset == ADDR_SRC_BASE) begin + src_base <= apply_wstrb(src_base, wdata_hold, wstrb_hold); + end else if (write_offset == ADDR_DST_BASE) begin + dst_base <= apply_wstrb(dst_base, wdata_hold, wstrb_hold); + end else if (write_offset == ADDR_GROUP_NUM) begin + group_num <= apply_wstrb(group_num, wdata_hold, wstrb_hold); + end else if ((write_offset >= ADDR_A_BASE) && (write_offset < ADDR_B_BASE)) begin + a_data[(write_offset - ADDR_A_BASE) >> 2] <= + apply_wstrb(a_data[(write_offset - ADDR_A_BASE) >> 2], wdata_hold, wstrb_hold); + end else if ((write_offset >= ADDR_B_BASE) && (write_offset < ADDR_C_BASE)) begin + b_data[(write_offset - ADDR_B_BASE) >> 2] <= + apply_wstrb(b_data[(write_offset - ADDR_B_BASE) >> 2], wdata_hold, wstrb_hold); + end else if (write_offset == ADDR_STATUS) begin + if (wdata_hold[1]) done <= 1'b0; + if (wdata_hold[2]) error <= 1'b0; + end else if ((write_offset != ADDR_CTRL) && (write_offset < ADDR_C_BASE)) begin + error <= 1'b1; + end + end + + if (s_axi_arvalid && s_axi_arready) begin + s_axi_rid <= s_axi_arid; + s_axi_rvalid <= 1'b1; + + if (read_offset == ADDR_CTRL) begin + s_axi_rdata <= 32'b0; + end else if (read_offset == ADDR_STATUS) begin + s_axi_rdata <= {29'b0, error, done, busy}; + end else if (read_offset == ADDR_SRC_BASE) begin + s_axi_rdata <= src_base; + end else if (read_offset == ADDR_DST_BASE) begin + s_axi_rdata <= dst_base; + end else if (read_offset == ADDR_GROUP_NUM) begin + s_axi_rdata <= group_num; + end else if ((read_offset >= ADDR_A_BASE) && (read_offset < ADDR_B_BASE)) begin + s_axi_rdata <= a_data[(read_offset - ADDR_A_BASE) >> 2]; + end else if ((read_offset >= ADDR_B_BASE) && (read_offset < ADDR_C_BASE)) begin + s_axi_rdata <= b_data[(read_offset - ADDR_B_BASE) >> 2]; + end else if ((read_offset >= ADDR_C_BASE) && (read_offset < (ADDR_C_BASE + 12'h0c0))) begin + s_axi_rdata <= c_read_word((read_offset - ADDR_C_BASE) >> 2); + end else begin + s_axi_rdata <= 32'b0; + end + end else if (s_axi_rvalid && s_axi_rready) begin + s_axi_rvalid <= 1'b0; + end + + if (start_fire) begin + busy <= 1'b1; + done <= 1'b0; + error <= 1'b0; + calc_index <= 4'd0; + end else if (busy) begin + c_data[calc_index] <= calc_c_element(calc_index); + if (calc_index == 4'd15) begin + busy <= 1'b0; + done <= 1'b1; + calc_index <= 4'd0; + end else begin + calc_index <= calc_index + 4'd1; + end + end + end +end + +endmodule \ No newline at end of file diff --git a/rtl/ip/open-la500/LICENSE b/rtl/ip/open-la500/LICENSE new file mode 100644 index 0000000..ee58399 --- /dev/null +++ b/rtl/ip/open-la500/LICENSE @@ -0,0 +1,127 @@ + 木兰宽松许可证, 第2版 + + 木兰宽松许可证， 第2版 + 2020年1月 http://license.coscl.org.cn/MulanPSL2 + + + 您对“软件”的复制、使用、修改及分发受木兰宽松许可证，第2版（“本许可证”）的如下条款的约束： + + 0. 定义 + + “软件”是指由“贡献”构成的许可在“本许可证”下的程序和相关文档的集合。 + + “贡献”是指由任一“贡献者”许可在“本许可证”下的受版权法保护的作品。 + + “贡献者”是指将受版权法保护的作品许可在“本许可证”下的自然人或“法人实体”。 + + “法人实体”是指提交贡献的机构及其“关联实体”。 + + “关联实体”是指，对“本许可证”下的行为方而言，控制、受控制或与其共同受控制的机构，此处的控制是指有受控方或共同受控方至少50%直接或间接的投票权、资金或其他有价证券。 + + 1. 授予版权许可 + + 每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的版权许可，您可以复制、使用、修改、分发其“贡献”，不论修改与否。 + + 2. 授予专利许可 + + 每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的（根据本条规定撤销除外）专利许可，供您制造、委托制造、使用、许诺销售、销售、进口其“贡献”或以其他方式转移其“贡献”。前述专利许可仅限于“贡献者”现在或将来拥有或控制的其“贡献”本身或其“贡献”与许可“贡献”时的“软件”结合而将必然会侵犯的专利权利要求，不包括对“贡献”的修改或包含“贡献”的其他结合。如果您或您的“关联实体”直接或间接地，就“软件”或其中的“贡献”对任何人发起专利侵权诉讼（包括反诉或交叉诉讼）或其他专利维权行动，指控其侵犯专利权，则“本许可证”授予您对“软件”的专利许可自您提起诉讼或发起维权行动之日终止。 + + 3. 无商标许可 + + “本许可证”不提供对“贡献者”的商品名称、商标、服务标志或产品名称的商标许可，但您为满足第4条规定的声明义务而必须使用除外。 + + 4. 分发限制 + + 您可以在任何媒介中将“软件”以源程序形式或可执行形式重新分发，不论修改与否，但您必须向接收者提供“本许可证”的副本，并保留“软件”中的版权、商标、专利及免责声明。 + + 5. 免责声明与责任限制 + + “软件”及其中的“贡献”在提供时不带任何明示或默示的担保。在任何情况下，“贡献者”或版权所有者不对任何人因使用“软件”或其中的“贡献”而引发的任何直接或间接损失承担责任，不论因何种原因导致或者基于何种法律理论，即使其曾被建议有此种损失的可能性。 + + 6. 语言 + “本许可证”以中英文双语表述，中英文版本具有同等法律效力。如果中英文版本存在任何冲突不一致，以中文版为准。 + + 条款结束 + + 如何将木兰宽松许可证，第2版，应用到您的软件 + + 如果您希望将木兰宽松许可证，第2版，应用到您的新软件，为了方便接收者查阅，建议您完成如下三步： + + 1， 请您补充如下声明中的空白，包括软件名、软件的首次发表年份以及您作为版权人的名字； + + 2， 请您在软件包的一级目录下创建以“LICENSE”为名的文件，将整个许可证文本放入该文件中； + + 3， 请将如下声明文本放入每个源文件的头部注释中。 + + Copyright (c) [Year] [name of copyright holder] + [Software Name] is licensed under Mulan PSL v2. + You can use this software according to the terms and conditions of the Mulan PSL v2. + You may obtain a copy of Mulan PSL v2 at: + http://license.coscl.org.cn/MulanPSL2 + THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + See the Mulan PSL v2 for more details. + + + Mulan Permissive Software License，Version 2 + + Mulan Permissive Software License，Version 2 (Mulan PSL v2) + January 2020 http://license.coscl.org.cn/MulanPSL2 + + Your reproduction, use, modification and distribution of the Software shall be subject to Mulan PSL v2 (this License) with the following terms and conditions: + + 0. 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IN THE CASE OF DIVERGENCE BETWEEN THE CHINESE AND ENGLISH VERSIONS, THE CHINESE VERSION SHALL PREVAIL. + + END OF THE TERMS AND CONDITIONS + + How to Apply the Mulan Permissive Software License，Version 2 (Mulan PSL v2) to Your Software + + To apply the Mulan PSL v2 to your work, for easy identification by recipients, you are suggested to complete following three steps: + + i Fill in the blanks in following statement, including insert your software name, the year of the first publication of your software, and your name identified as the copyright owner; + + ii Create a file named “LICENSE” which contains the whole context of this License in the first directory of your software package; + + iii Attach the statement to the appropriate annotated syntax at the beginning of each source file. + + + Copyright (c) [Year] [name of copyright holder] + [Software Name] is licensed under Mulan PSL v2. + You can use this software according to the terms and conditions of the Mulan PSL v2. + You may obtain a copy of Mulan PSL v2 at: + http://license.coscl.org.cn/MulanPSL2 + THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + See the Mulan PSL v2 for more details. diff --git a/rtl/ip/open-la500/README.md b/rtl/ip/open-la500/README.md new file mode 100644 index 0000000..beaa043 --- /dev/null +++ b/rtl/ip/open-la500/README.md @@ -0,0 +1,7 @@ +# openLA500 +## 前言 +openLA500是一款实现了龙芯架构32位精简版指令集（loongarch32r）的处理器核。其结构为单发射五级流水，分为取指、译码、执行、访存、写回五个流水级。并且含有两路组相连结构的指令和数据cache；32项tlb；以及简易的分支预测器。此外，处理器核对外为AXI接口，容易集成。 + +OpenLA500已经过流片验证，.13工艺下频率为100M，dhrystone，coremark分数分别为0.78 DMIPS/MHz(指令数有点高)，2.75 coremark/Mhz。软件方面，uboot、linux 5.14、ucore、rt-thread等常用工具及内核已完成对openLA500的适配。 + +详细设计报告见doc目录。 diff --git a/rtl/ip/open-la500/addr_trans.v b/rtl/ip/open-la500/addr_trans.v new file mode 100644 index 0000000..e03fafb --- /dev/null +++ b/rtl/ip/open-la500/addr_trans.v @@ -0,0 +1,250 @@ +`include "csr.h" + +module addr_trans +#( + parameter TLBNUM = 32 +) +( + input clk , + input [ 9:0] asid , + //trans mode + input inst_addr_trans_en , + input data_addr_trans_en , + //inst addr trans + input inst_fetch , + input [31:0] inst_vaddr , + input inst_dmw0_en , + input inst_dmw1_en , + output [ 7:0] inst_index , + output [19:0] inst_tag , + output [ 3:0] inst_offset , + output inst_tlb_found , + output inst_tlb_v , + output inst_tlb_d , + output [ 1:0] inst_tlb_mat , + output [ 1:0] inst_tlb_plv , + //data addr trans + input data_fetch , + input [31:0] data_vaddr , + input data_dmw0_en , + input data_dmw1_en , + input cacop_op_mode_di , + output [ 7:0] data_index , + output [19:0] data_tag , + output [ 3:0] data_offset , + output data_tlb_found , + output [ 4:0] data_tlb_index , + output data_tlb_v , + output data_tlb_d , + output [ 1:0] data_tlb_mat , + output [ 1:0] data_tlb_plv , + //tlbwi tlbwr tlb write + input tlbfill_en , + input tlbwr_en , + input [ 4:0] rand_index , + input [31:0] tlbehi_in , + input [31:0] tlbelo0_in , + input [31:0] tlbelo1_in , + input [31:0] tlbidx_in , + input [ 5:0] ecode_in , + //tlbr tlb read + output [31:0] tlbehi_out , + output [31:0] tlbelo0_out , + output [31:0] tlbelo1_out , + output [31:0] tlbidx_out , + output [ 9:0] asid_out , + //invtlb + input invtlb_en , + input [ 9:0] invtlb_asid , + input [18:0] invtlb_vpn , + input [ 4:0] invtlb_op , + //from csr + input [31:0] csr_dmw0 , + input [31:0] csr_dmw1 , + input csr_da , + input csr_pg +); + +wire [18:0] s0_vppn ; +wire s0_odd_page ; +wire [ 5:0] s0_ps ; +wire [19:0] s0_ppn ; + +wire [18:0] s1_vppn ; +wire s1_odd_page ; +wire [ 5:0] s1_ps ; +wire [19:0] s1_ppn ; + +wire we ; +wire [ 4:0] w_index ; +wire [18:0] w_vppn ; +wire w_g ; +wire [ 5:0] w_ps ; +wire w_e ; +wire w_v0 ; +wire w_d0 ; +wire [ 1:0] w_mat0 ; +wire [ 1:0] w_plv0 ; +wire [19:0] w_ppn0 ; +wire w_v1 ; +wire w_d1 ; +wire [ 1:0] w_mat1 ; +wire [ 1:0] w_plv1 ; +wire [19:0] w_ppn1 ; + +wire [ 4:0] r_index ; +wire [18:0] r_vppn ; +wire [ 9:0] r_asid ; +wire r_g ; +wire [ 5:0] r_ps ; +wire r_e ; +wire r_v0 ; +wire r_d0 ; +wire [ 1:0] r_mat0 ; +wire [ 1:0] r_plv0 ; +wire [19:0] r_ppn0 ; +wire r_v1 ; +wire r_d1 ; +wire [ 1:0] r_mat1 ; +wire [ 1:0] r_plv1 ; +wire [19:0] r_ppn1 ; + +reg [31:0] inst_vaddr_buffer ; +reg [31:0] data_vaddr_buffer ; +wire [31:0] inst_paddr; +wire [31:0] data_paddr; + +wire pg_mode; +wire da_mode; + +always @(posedge clk) begin + if (inst_fetch) begin + inst_vaddr_buffer <= inst_vaddr; + end + + if (data_fetch) begin + data_vaddr_buffer <= data_vaddr; + end +end + +//trans search port sig +assign s0_vppn = inst_vaddr[31:13]; +assign s0_odd_page = inst_vaddr[12]; + +assign s1_vppn = data_vaddr[31:13]; +assign s1_odd_page = data_vaddr[12]; + +//trans write port sig +assign we = tlbfill_en || tlbwr_en; +assign w_index = ({5{tlbfill_en}} & rand_index) | ({5{tlbwr_en}} & tlbidx_in[`INDEX]); +assign w_vppn = tlbehi_in[`VPPN]; +assign w_g = tlbelo0_in[`TLB_G] && tlbelo1_in[`TLB_G]; +assign w_ps = tlbidx_in[`PS]; +assign w_e = (ecode_in == 6'h3f) ? 1'b1 : !tlbidx_in[`NE]; +assign w_v0 = tlbelo0_in[`TLB_V]; +assign w_d0 = tlbelo0_in[`TLB_D]; +assign w_plv0 = tlbelo0_in[`TLB_PLV]; +assign w_mat0 = tlbelo0_in[`TLB_MAT]; +assign w_ppn0 = tlbelo0_in[`TLB_PPN_EN]; +assign w_v1 = tlbelo1_in[`TLB_V]; +assign w_d1 = tlbelo1_in[`TLB_D]; +assign w_plv1 = tlbelo1_in[`TLB_PLV]; +assign w_mat1 = tlbelo1_in[`TLB_MAT]; +assign w_ppn1 = tlbelo1_in[`TLB_PPN_EN]; + +//trans read port sig +assign r_index = tlbidx_in[`INDEX]; +assign tlbehi_out = {r_vppn, 13'b0}; +assign tlbelo0_out = {4'b0, r_ppn0, 1'b0, r_g, r_mat0, r_plv0, r_d0, r_v0}; +assign tlbelo1_out = {4'b0, r_ppn1, 1'b0, r_g, r_mat1, r_plv1, r_d1, r_v1}; +assign tlbidx_out = {!r_e, 1'b0, r_ps, 24'b0}; //note do not write index +assign asid_out = r_asid; + +tlb_entry tlb_entry( + .clk (clk ), + // search port 0 + .s0_fetch (inst_fetch ), + .s0_vppn (s0_vppn ), + .s0_odd_page (s0_odd_page ), + .s0_asid (asid ), + .s0_found (inst_tlb_found ), + .s0_index (), + .s0_ps (s0_ps ), + .s0_ppn (s0_ppn ), + .s0_v (inst_tlb_v ), + .s0_d (inst_tlb_d ), + .s0_mat (inst_tlb_mat ), + .s0_plv (inst_tlb_plv ), + // search port 1 + .s1_fetch (data_fetch ), + .s1_vppn (s1_vppn ), + .s1_odd_page (s1_odd_page ), + .s1_asid (asid ), + .s1_found (data_tlb_found ), + .s1_index (data_tlb_index ), + .s1_ps (s1_ps ), + .s1_ppn (s1_ppn ), + .s1_v (data_tlb_v ), + .s1_d (data_tlb_d ), + .s1_mat (data_tlb_mat ), + .s1_plv (data_tlb_plv ), + // write port + .we (we ), + .w_index (w_index ), + .w_vppn (w_vppn ), + .w_asid (asid ), + .w_g (w_g ), + .w_ps (w_ps ), + .w_e (w_e ), + .w_v0 (w_v0 ), + .w_d0 (w_d0 ), + .w_plv0 (w_plv0 ), + .w_mat0 (w_mat0 ), + .w_ppn0 (w_ppn0 ), + .w_v1 (w_v1 ), + .w_d1 (w_d1 ), + .w_plv1 (w_plv1 ), + .w_mat1 (w_mat1 ), + .w_ppn1 (w_ppn1 ), + //read port + .r_index (r_index ), + .r_vppn (r_vppn ), + .r_asid (r_asid ), + .r_g (r_g ), + .r_ps (r_ps ), + .r_e (r_e ), + .r_v0 (r_v0 ), + .r_d0 (r_d0 ), + .r_mat0 (r_mat0 ), + .r_plv0 (r_plv0 ), + .r_ppn0 (r_ppn0 ), + .r_v1 (r_v1 ), + .r_d1 (r_d1 ), + .r_mat1 (r_mat1 ), + .r_plv1 (r_plv1 ), + .r_ppn1 (r_ppn1 ), + //invalid port + .inv_en (invtlb_en ), + .inv_op (invtlb_op ), + .inv_asid (invtlb_asid ), + .inv_vpn (invtlb_vpn ) +); + +assign pg_mode = !csr_da && csr_pg; +assign da_mode = csr_da && !csr_pg; + +assign inst_paddr = (pg_mode && inst_dmw0_en) ? {csr_dmw0[`PSEG], inst_vaddr_buffer[28:0]} : + (pg_mode && inst_dmw1_en) ? {csr_dmw1[`PSEG], inst_vaddr_buffer[28:0]} : inst_vaddr_buffer; + +assign inst_offset = inst_vaddr[3:0]; +assign inst_index = inst_vaddr[11:4]; +assign inst_tag = inst_addr_trans_en ? ((s0_ps == 6'd12) ? s0_ppn : {s0_ppn[19:10], inst_paddr[21:12]}) : inst_paddr[31:12]; + +assign data_paddr = (pg_mode && data_dmw0_en && !cacop_op_mode_di) ? {csr_dmw0[`PSEG], data_vaddr_buffer[28:0]} : + (pg_mode && data_dmw1_en && !cacop_op_mode_di) ? {csr_dmw1[`PSEG], data_vaddr_buffer[28:0]} : data_vaddr_buffer; + +assign data_offset = data_vaddr[3:0]; +assign data_index = data_vaddr[11:4]; +assign data_tag = data_addr_trans_en ? ((s1_ps == 6'd12) ? s1_ppn : {s1_ppn[19:10], data_paddr[21:12]}) : data_paddr[31:12]; + +endmodule diff --git a/rtl/ip/open-la500/alu.v b/rtl/ip/open-la500/alu.v new file mode 100644 index 0000000..8569fe9 --- /dev/null +++ b/rtl/ip/open-la500/alu.v @@ -0,0 +1,109 @@ +module alu( + input [13:0] alu_op, + input [31:0] alu_src1, + input [31:0] alu_src2, + output [31:0] alu_result +); + +wire op_add; +wire op_sub; +wire op_slt; +wire op_sltu; +wire op_and; +wire op_nor; +wire op_or; +wire op_xor; +wire op_sll; +wire op_srl; +wire op_sra; +wire op_lui; +wire op_andn; +wire op_orn; + +// control code decomposition +assign op_add = alu_op[ 0]; +assign op_sub = alu_op[ 1]; +assign op_slt = alu_op[ 2]; +assign op_sltu = alu_op[ 3]; +assign op_and = alu_op[ 4]; +assign op_nor = alu_op[ 5]; +assign op_or = alu_op[ 6]; +assign op_xor = alu_op[ 7]; +assign op_sll = alu_op[ 8]; +assign op_srl = alu_op[ 9]; +assign op_sra = alu_op[10]; +assign op_lui = alu_op[11]; +assign op_andn = alu_op[12]; +assign op_orn = alu_op[13]; + +wire [31:0] add_sub_result; +wire [31:0] slt_result; +wire [31:0] sltu_result; +wire [31:0] and_result; +wire [31:0] nor_result; +wire [31:0] or_result; +wire [31:0] xor_result; +wire [31:0] lui_result; +wire [31:0] sll_result; +wire [63:0] sr64_result; +wire [31:0] sr_result; +wire [31:0] andn_result; +wire [31:0] orn_result; + + +// 32-bit adder +wire [31:0] adder_a; +wire [31:0] adder_b; +wire adder_cin; +wire [31:0] adder_result; +wire adder_cout; + +assign adder_a = alu_src1; +assign adder_b = (op_sub | op_slt | op_sltu) ? ~alu_src2 : alu_src2; //src1 - src2 rj-rk +assign adder_cin = (op_sub | op_slt | op_sltu) ? 1'b1 : 1'b0; +assign {adder_cout, adder_result} = adder_a + adder_b + adder_cin; + +// ADD, SUB result +assign add_sub_result = adder_result; + +// SLT result +assign slt_result[31:1] = 31'b0; //rj < rk 1 +assign slt_result[0] = (alu_src1[31] & ~alu_src2[31]) + | ((alu_src1[31] ~^ alu_src2[31]) & adder_result[31]); + +// SLTU result +assign sltu_result[31:1] = 31'b0; +assign sltu_result[0] = ~adder_cout; + +// bitwise operation +assign and_result = alu_src1 & alu_src2; +assign andn_result= alu_src1 & ~alu_src2; +assign or_result = alu_src1 | alu_src2; //bug6 cycle +assign orn_result = alu_src1 | ~alu_src2; +assign nor_result = ~or_result; +assign xor_result = alu_src1 ^ alu_src2; +assign lui_result = alu_src2; + +// SLL result +assign sll_result = alu_src1 << alu_src2[4:0]; //rj << i5 + +// SRL, SRA result +assign sr64_result = {{32{op_sra & alu_src1[31]}}, alu_src1[31:0]} >> alu_src2[4:0]; //rj >> i5 + +assign sr_result = sr64_result[31:0]; + +// final result mux +assign alu_result = ({32{op_add|op_sub}} & add_sub_result) + | ({32{op_slt }} & slt_result) + | ({32{op_sltu }} & sltu_result) + | ({32{op_and }} & and_result) + | ({32{op_andn }} & andn_result) + | ({32{op_nor }} & nor_result) + | ({32{op_or }} & or_result) + | ({32{op_orn }} & orn_result) + | ({32{op_xor }} & xor_result) + | ({32{op_lui }} & lui_result) + | ({32{op_sll }} & sll_result) + | ({32{op_srl|op_sra}} & sr_result); //bug7 srl and sra sign + +endmodule diff --git a/rtl/ip/open-la500/axi_bridge.v b/rtl/ip/open-la500/axi_bridge.v new file mode 100644 index 0000000..4219790 --- /dev/null +++ b/rtl/ip/open-la500/axi_bridge.v @@ -0,0 +1,317 @@ +module axi_bridge( + input clk, + input reset, + + output reg[ 3:0] arid, + output reg[31:0] araddr, + output reg[ 7:0] arlen, + output reg[ 2:0] arsize, + output [ 1:0] arburst, + output [ 1:0] arlock, + output [ 3:0] arcache, + output [ 2:0] arprot, + output reg arvalid, + input arready, + + input [ 3:0] rid, + input [31:0] rdata, + input [ 1:0] rresp, + input rlast, + input rvalid, + output reg rready, + + output [ 3:0] awid, + output reg[31:0] awaddr, + output reg[ 7:0] awlen, + output reg[ 2:0] awsize, + output [ 1:0] awburst, + output [ 1:0] awlock, + output [ 3:0] awcache, + output [ 2:0] awprot, + output reg awvalid, + input awready, + + output [ 3:0] wid, + output reg[31:0] wdata, + output reg[ 3:0] wstrb, + output reg wlast, + output reg wvalid, + input wready, + + input [ 3:0] bid, + input [ 1:0] bresp, + input bvalid, + output reg bready, + //cache sign + input inst_rd_req , + input [ 2:0] inst_rd_type , + input [31:0] inst_rd_addr , + output inst_rd_rdy , + output inst_ret_valid , + output inst_ret_last , + output [31:0] inst_ret_data , + input inst_wr_req , + input [ 2:0] inst_wr_type , + input [31:0] inst_wr_addr , + input [ 3:0] inst_wr_wstrb , + input [127:0] inst_wr_data , + output inst_wr_rdy , + + input data_rd_req , + input [ 2:0] data_rd_type , + input [31:0] data_rd_addr , + output data_rd_rdy , + output data_ret_valid , + output data_ret_last , + output [31:0] data_ret_data , + input data_wr_req , + input [ 2:0] data_wr_type , + input [31:0] data_wr_addr , + input [ 3:0] data_wr_wstrb , + input [127:0] data_wr_data , + output data_wr_rdy , + output write_buffer_empty +); + +//fixed signal +assign arburst = 2'b1; +assign arlock = 2'b0; +assign arcache = 4'b0; +assign arprot = 3'b0; +assign awid = 4'b1; +assign awburst = 2'b1; +assign awlock = 2'b0; +assign awcache = 4'b0; +assign awprot = 3'b0; +assign wid = 4'b1; + +assign inst_wr_rdy = 1'b1; + +localparam read_requst_empty = 1'b0; +localparam read_requst_ready = 1'b1; +localparam read_respond_empty = 1'b0; +localparam read_respond_transfer = 1'b1; +localparam write_request_empty = 3'b000; +localparam write_addr_ready = 3'b001; +localparam write_data_ready = 3'b010; +localparam write_all_ready = 3'b011; +localparam write_data_transform = 3'b100; +localparam write_data_wait = 3'b101; +localparam write_wait_b = 3'b110; + +reg read_requst_state; +reg read_respond_state; +reg [2:0] write_requst_state; + +wire write_wait_enable; + +wire rd_requst_state_is_empty; +wire rd_requst_can_receive; + +assign rd_requst_state_is_empty = read_requst_state == read_requst_empty; + +wire data_rd_cache_line; +wire inst_rd_cache_line; +wire [ 2:0] data_real_rd_size; +wire [ 7:0] data_real_rd_len ; +wire [ 2:0] inst_real_rd_size; +wire [ 7:0] inst_real_rd_len ; +wire data_wr_cache_line; +wire [ 2:0] data_real_wr_size; +wire [ 7:0] data_real_wr_len ; + +reg [127:0] write_buffer_data; +reg [ 2:0] write_buffer_num; + +wire write_buffer_last; + +assign write_buffer_empty = (write_buffer_num == 3'b0) && !write_wait_enable; + +assign rd_requst_can_receive = rd_requst_state_is_empty && !(write_wait_enable && !(bvalid && bready)); + +assign data_rd_rdy = rd_requst_can_receive; +assign inst_rd_rdy = !data_rd_req && rd_requst_can_receive; + +//read type must be cache line +assign data_rd_cache_line = data_rd_type == 3'b100 ; +assign data_real_rd_size = data_rd_cache_line ? 3'b10 : data_rd_type; +assign data_real_rd_len = data_rd_cache_line ? 8'b11 : 8'b0 ; + +assign inst_rd_cache_line = inst_rd_type == 3'b100 ; +assign inst_real_rd_size = inst_rd_cache_line ? 3'b10 : inst_rd_type; +assign inst_real_rd_len = inst_rd_cache_line ? 8'b11 : 8'b0 ; + +//write size can be special +assign data_wr_cache_line = data_wr_type == 3'b100; +assign data_real_wr_size = data_wr_cache_line ? 3'b10 : data_wr_type; +assign data_real_wr_len = data_wr_cache_line ? 8'b11 : 8'b0 ; + +assign inst_ret_valid = !rid[0] && rvalid; +assign inst_ret_last = !rid[0] && rlast; +assign inst_ret_data = rdata; //this signal needed buffer??? +assign data_ret_valid = rid[0] && rvalid; +assign data_ret_last = rid[0] && rlast; +assign data_ret_data = rdata; + +assign data_wr_rdy = (write_requst_state == write_request_empty); + +assign write_buffer_last = write_buffer_num == 3'b1; + +always @(posedge clk) begin + if (reset) begin + read_requst_state <= read_requst_empty; + arvalid <= 1'b0; + end + else case (read_requst_state) + read_requst_empty: begin + if (data_rd_req) begin + if (write_wait_enable) begin + if (bvalid && bready) begin //when wait write back, stop send read request. easiest way. + read_requst_state <= read_requst_ready; + arid <= 4'b1; + araddr <= data_rd_addr; + arsize <= data_real_rd_size; + arlen <= data_real_rd_len; + arvalid <= 1'b1; + end + end + else begin + read_requst_state <= read_requst_ready; + arid <= 4'b1; + araddr <= data_rd_addr; + arsize <= data_real_rd_size; + arlen <= data_real_rd_len; + arvalid <= 1'b1; + end + end + else if (inst_rd_req) begin + if (write_wait_enable) begin + if (bvalid && bready) begin + read_requst_state <= read_requst_ready; + arid <= 4'b0; + araddr <= inst_rd_addr; + arsize <= inst_real_rd_size; + arlen <= inst_real_rd_len; + arvalid <= 1'b1; + end + end + else begin + read_requst_state <= read_requst_ready; + arid <= 4'b0; + araddr <= inst_rd_addr; + arsize <= inst_real_rd_size; + arlen <= inst_real_rd_len; + arvalid <= 1'b1; + end + end + end + read_requst_ready: begin + if (arready && arid[0]) begin + read_requst_state <= read_requst_empty; + arvalid <= 1'b0; + end + else if (arready && !arid[0]) begin + read_requst_state <= read_requst_empty; + arvalid <= 1'b0; + end + end + endcase +end + +always @(posedge clk) begin + if (reset) begin + read_respond_state <= read_respond_empty; + rready <= 1'b1; + end + else case (read_respond_state) + read_respond_empty: begin + if (rvalid && rready) begin + read_respond_state <= read_respond_transfer; + end + end + read_respond_transfer: begin + if (rlast && rvalid) begin + read_respond_state <= read_respond_empty; + end + end + endcase +end + +always @(posedge clk) begin + if (reset) begin + write_requst_state <= write_request_empty; + awvalid <= 1'b0; + wvalid <= 1'b0; + wlast <= 1'b0; + bready <= 1'b0; + + write_buffer_num <= 3'b0; + write_buffer_data <= 128'b0; + end + else case (write_requst_state) + write_request_empty: begin + if (data_wr_req) begin + write_requst_state <= write_data_wait; + //end + awaddr <= data_wr_addr; + awsize <= data_real_wr_size; + awlen <= data_real_wr_len; + awvalid <= 1'b1; + wdata <= data_wr_data[31:0]; //from write 128 bit buffer + wstrb <= data_wr_wstrb; + + write_buffer_data <= {32'b0, data_wr_data[127:32]}; + + if (data_wr_type == 3'b100) begin + write_buffer_num <= 3'b011; + end + else begin + write_buffer_num <= 3'b0; + wlast <= 1'b1; + end + end + end + write_data_wait: begin + if (awready) begin + write_requst_state <= write_data_transform; + awvalid <= 1'b0; + wvalid <= 1'b1; + end + end + write_data_transform: begin + if (wready) begin + if (wlast) begin + write_requst_state <= write_wait_b; + wvalid <= 1'b0; + wlast <= 1'b0; + bready <= 1'b1; + end + else begin + if (write_buffer_last) begin + wlast <= 1'b1; + end + + write_requst_state <= write_data_transform; + + wdata <= write_buffer_data[31:0]; + wvalid <= 1'b1; + write_buffer_data <= {32'b0, write_buffer_data[127:32]}; + write_buffer_num <= write_buffer_num - 3'b1; + end + end + end + write_wait_b: begin + if (bvalid && bready) begin + write_requst_state <= write_request_empty; + bready <= 1'b0; + end + end + default: begin + write_requst_state <= write_request_empty; + end + endcase +end + +assign write_wait_enable = ~(write_requst_state == write_request_empty); + +endmodule diff --git a/rtl/ip/open-la500/btb.v b/rtl/ip/open-la500/btb.v new file mode 100644 index 0000000..e2f6e34 --- /dev/null +++ b/rtl/ip/open-la500/btb.v @@ -0,0 +1,238 @@ +module btb +#( + parameter BTBNUM = 32, + parameter RASNUM = 16 +) +( + input clk , + input reset , + //from/to if + input [31:0] fetch_pc , + input fetch_en , + output [31:0] ret_pc , + output taken , + output ret_en , + output [ 4:0] ret_index , + //from id + input operate_en , + input [31:0] operate_pc , + input [ 4:0] operate_index , + input pop_ras , + input push_ras , + input add_entry , + input delete_entry , + input pre_error , + input pre_right , + input target_error , + input right_orien , + input [31:0] right_target +); + +/* +* btb_pc record all branch inst pc except jirl +* ras_pc only record jirl pc +*/ +reg [29:0] btb_pc [BTBNUM-1:0]; +reg [29:0] btb_target [BTBNUM-1:0]; +reg [ 1:0] btb_counter [BTBNUM-1:0]; + +reg [BTBNUM-1:0] btb_valid; + +reg [29:0] ras_pc [RASNUM-1:0]; + +reg [RASNUM-1:0] ras_valid; + +reg [31:0] fetch_pc_r; +reg fetch_en_r; + +//reg [BTBNUM-1:0] jirl_flag; + +reg [29:0] ras [7:0]; +reg [ 3:0] ras_ptr; + +wire [29:0] ras_top; + +wire ras_full; +wire ras_empty; + +wire [31:0] btb_match_rd; +wire [15:0] ras_match_rd; + +wire btb_match; +wire ras_match; + +wire [29:0] btb_match_target; +wire [ 1:0] btb_match_counter; +wire [ 4:0] btb_match_index; +wire [ 4:0] btb_random_index; + +wire [ 3:0] ras_match_index; +wire [ 3:0] ras_random_index; + +wire btb_all_entry_valid; +wire [4:0] btb_select_one_invalid_entry; +wire [4:0] btb_add_entry_index; +reg [4:0] btb_add_entry_index_r; +wire [31:0] btb_add_entry_dec; + +wire ras_all_entry_valid; +wire [3:0] ras_select_one_invalid_entry; +wire [3:0] ras_add_entry_index; + +wire [31:0] btb_untaken_entry; +reg [31:0] btb_untaken_entry_r; +wire [31:0] btb_untaken_entry_t; +reg btb_add_entry_r; +wire [4:0] btb_sel_one_untaken_entry; +wire btb_has_one_untaken_entry; + +reg [5:0] fcsr; + +always @(posedge clk) begin + if (reset) + fetch_en_r <= 1'b0; + else + fetch_en_r <= fetch_en; + + if (fetch_en) + fetch_pc_r <= fetch_pc; +end + +always @(posedge clk) begin + btb_untaken_entry_r <= btb_untaken_entry; + btb_add_entry_r <= operate_en && !pop_ras && add_entry; + btb_add_entry_index_r <= btb_add_entry_index; +end + +//untaken entry list cal at previous clock +assign btb_untaken_entry_t = btb_untaken_entry_r & ({32{!btb_add_entry_r}} | ~btb_add_entry_dec); +assign btb_has_one_untaken_entry = |btb_untaken_entry_t; + +decoder_5_32 dec_btb_add_entry (.in(btb_add_entry_index_r), .out(btb_add_entry_dec)); +one_valid_32 sel_one_untaken_entry (.in(btb_untaken_entry_t), .out_en(btb_sel_one_untaken_entry)); + +//assign btb_random_index = (btb_match && (fcsr[4:0] == btb_match_index)) ? (fcsr[4:0]+1'b1) : fcsr[4:0]; +//untaken entry can exit first, make no difference, except lose history infor. +assign btb_add_entry_index = !btb_all_entry_valid ? btb_select_one_invalid_entry : + btb_has_one_untaken_entry ? btb_sel_one_untaken_entry : + fcsr[4:0] ; + +assign btb_all_entry_valid = &btb_valid; +one_valid_32 sel_one_btb_entry (.in(~btb_valid), .out_en(btb_select_one_invalid_entry)); + +//assign ras_random_index = (ras_match && (fcsr[3:0] == ras_match_index)) ? (fcsr[3:0]+1'b1) : fcsr[3:0]; +assign ras_add_entry_index = ras_all_entry_valid ? fcsr[3:0] : ras_select_one_invalid_entry; +assign ras_all_entry_valid = &ras_valid; +one_valid_16 sel_one_ras_entry (.in(~ras_valid), .out_en(ras_select_one_invalid_entry)); + +always @(posedge clk) begin + if (reset) begin + btb_valid <= 32'b0; + ras_valid <= 16'b0; + end + else if (operate_en && !pop_ras) begin + if (add_entry) begin + btb_valid[btb_add_entry_index] <= 1'b1; + btb_pc[btb_add_entry_index] <= operate_pc[31:2]; + btb_target[btb_add_entry_index] <= right_target[31:2]; + btb_counter[btb_add_entry_index] <= 2'b10; + end + else if (target_error) begin + btb_target[operate_index] <= right_target[31:2]; + btb_counter[operate_index] <= 2'b10; + end + else if (pre_error || pre_right) begin + if (right_orien) begin + if (btb_counter[operate_index] != 2'b11) begin + btb_counter[operate_index] <= btb_counter[operate_index] + 2'b1; + end + end + else begin + if (btb_counter[operate_index] != 2'b00) begin + btb_counter[operate_index] <= btb_counter[operate_index] - 2'b1; + end + end + end + end + else if (operate_en && pop_ras) begin + if (add_entry) begin + ras_valid[ras_add_entry_index] <= 1'b1; + ras_pc[ras_add_entry_index] <= operate_pc[31:2]; + end + end + +end + +genvar i; +generate + for (i = 0; i < BTBNUM; i = i + 1) + begin: btb_match_com + assign btb_match_rd[i] = fetch_en_r && ((fetch_pc_r[31:2] == btb_pc[i]) && btb_valid[i]); + end +endgenerate + +generate + for (i = 0; i < RASNUM; i = i + 1) + begin: ras_match_com + assign ras_match_rd[i] = fetch_en_r && ((fetch_pc_r[31:2] == ras_pc[i]) && ras_valid[i]); + end +endgenerate + +generate + for (i = 0; i < BTBNUM; i = i + 1) + begin: sel_untaken_entry + assign btb_untaken_entry[i] = btb_valid[i] && ~|btb_counter[i]; + end +endgenerate + +assign btb_match = |btb_match_rd; +assign ras_match = |ras_match_rd && !ras_empty; + +assign ras_top = ras[ras_ptr - 4'b1]; //ras modify may before inst fetch + +encoder_32_5 encode_btb_match (.in(btb_match_rd), .out(btb_match_index)); +encoder_16_4 encode_ras_match (.in(ras_match_rd), .out(ras_match_index)); + +assign btb_match_target = btb_target[btb_match_index]; +assign btb_match_counter = btb_counter[btb_match_index]; + +assign ret_pc = {32{ras_match}} & {ras_top, 2'b0} | + {32{btb_match}} & {btb_match_target, 2'b0}; +assign ret_en = btb_match || ras_match; +assign taken = btb_match && btb_match_counter[1] || ras_match; +assign ret_index = {5{btb_match}} & {btb_match_index} | + {5{ras_match}} & {1'b0,ras_match_index}; + +assign ras_full = ras_ptr[3]; +assign ras_empty = (ras_ptr == 4'd0); + +always @(posedge clk) begin + if (reset) begin + ras_ptr <= 4'b0; + end + else if (operate_en) begin + if (push_ras && !ras_full) begin + ras[ras_ptr] <= operate_pc[31:2] + 30'b1; + ras_ptr <= ras_ptr + 4'b1; + end + else if (pop_ras && !ras_empty) begin + ras_ptr <= ras_ptr - 4'b1; + end + end +end + +always @(posedge clk) begin + if (reset) begin + fcsr <= 6'b100010; + end + else begin + fcsr[0] <= fcsr[5]; + fcsr[1] <= fcsr[0]; + fcsr[2] <= fcsr[1]; + fcsr[3] <= fcsr[2] ^ fcsr[5]; + fcsr[4] <= fcsr[3] ^ fcsr[5]; + fcsr[5] <= fcsr[4]; + end +end + +endmodule diff --git a/rtl/ip/open-la500/csr.h b/rtl/ip/open-la500/csr.h new file mode 100644 index 0000000..a1d8a43 --- /dev/null +++ b/rtl/ip/open-la500/csr.h @@ -0,0 +1,73 @@ +//CRMD +`define PLV 1:0 +`define IE 2 +`define DA 3 +`define PG 4 +`define DATF 6:5 +`define DATM 8:7 +//PRMD +`define PPLV 1:0 +`define PIE 2 +//ECTL +`define LIE 12:0 +`define LIE_1 9:0 +`define LIE_2 12:11 +//ESTAT +`define IS 12:0 +`define ECODE 21:16 +`define ESUBCODE 30:22 +//TLBIDX +`define INDEX 4:0 +`define PS 29:24 +`define NE 31 +//TLBEHI +`define VPPN 31:13 +//TLBELO +`define TLB_V 0 +`define TLB_D 1 +`define TLB_PLV 3:2 +`define TLB_MAT 5:4 +`define TLB_G 6 +`define TLB_PPN 31:8 +`define TLB_PPN_EN 27:8 //todo +//ASID +`define TLB_ASID 9:0 +//CPUID +`define COREID 8:0 +//LLBCTL +`define ROLLB 0 +`define WCLLB 1 +`define KLO 2 +//TCFG +`define EN 0 +`define PERIODIC 1 +`define INITVAL 31:2 +//TICLR +`define CLR 0 +//TLBRENTRY +`define TLBRENTRY_PA 31:6 +//DMW +`define PLV0 0 +`define PLV3 3 +`define DMW_MAT 5:4 +`define PSEG 27:25 +`define VSEG 31:29 +//PGDL PGDH PGD +`define BASE 31:12 + +`define ECODE_INT 6'h0 +`define ECODE_PIL 6'h1 +`define ECODE_PIS 6'h2 +`define ECODE_PIF 6'h3 +`define ECODE_PME 6'h4 +`define ECODE_PPI 6'h7 +`define ECODE_ADEF 6'h8 +`define ECODE_ALE 6'h9 +`define ECODE_SYS 6'hb +`define ECODE_BRK 6'hc +`define ECODE_INE 6'hd +`define ECODE_IPE 6'he +`define ECODE_FPD 6'hf +`define ECODE_TLBR 6'h3f + +`define ESUBCODE_ADEF 9'h0 diff --git a/rtl/ip/open-la500/csr.v b/rtl/ip/open-la500/csr.v new file mode 100644 index 0000000..b43d83d --- /dev/null +++ b/rtl/ip/open-la500/csr.v @@ -0,0 +1,856 @@ +`include "mycpu.h" +`include "csr.h" + +module csr +#( + parameter TLBNUM = 32 +) +( + input clk , + input reset , + //from to ds + input [13:0] rd_addr , + output [31:0] rd_data , + //timer 64 + output [63:0] timer_64_out , + output [31:0] tid_out , + //from ws + input csr_wr_en , + input [13:0] wr_addr , + input [31:0] wr_data , + //interrupt + input [ 7:0] interrupt , + output has_int , + //from ws + input excp_flush , + input ertn_flush , + input [31:0] era_in , + input [ 8:0] esubcode_in , + input [ 5:0] ecode_in , + input va_error_in , + input [31:0] bad_va_in , + input tlbsrch_en , + input tlbsrch_found , + input [ 4:0] tlbsrch_index , + input excp_tlbrefill, + input excp_tlb , + input [18:0] excp_tlb_vppn, + //from ws llbit + input llbit_in , + input llbit_set_in , + input [27:0] lladdr_in , + input lladdr_set_in, + //to es + output llbit_out , + output [18:0] vppn_out , + //to ms + output [27:0] lladdr_out , + //to fs + output [31:0] eentry_out , + output [31:0] era_out , + output [31:0] tlbrentry_out, + output disable_cache_out, + //to addr trans + output [ 9:0] asid_out , + output [ 4:0] rand_index , + output [31:0] tlbehi_out , + output [31:0] tlbelo0_out , + output [31:0] tlbelo1_out , + output [31:0] tlbidx_out , + output pg_out , + output da_out , + output [31:0] dmw0_out , + output [31:0] dmw1_out , + output [ 1:0] datf_out , + output [ 1:0] datm_out , + output [ 5:0] ecode_out , + //from addr trans + input tlbrd_en , + input [31:0] tlbehi_in , + input [31:0] tlbelo0_in , + input [31:0] tlbelo1_in , + input [31:0] tlbidx_in , + input [ 9:0] asid_in , + //general use + output [ 1:0] plv_out + // csr regs for diff +`ifdef DIFFTEST_EN + , + output [31:0] csr_crmd_diff, + output [31:0] csr_prmd_diff, + output [31:0] csr_ectl_diff, + output [31:0] csr_estat_diff, + output [31:0] csr_era_diff, + output [31:0] csr_badv_diff, + output [31:0] csr_eentry_diff, + output [31:0] csr_tlbidx_diff, + output [31:0] csr_tlbehi_diff, + output [31:0] csr_tlbelo0_diff, + output [31:0] csr_tlbelo1_diff, + output [31:0] csr_asid_diff, + output [31:0] csr_save0_diff, + output [31:0] csr_save1_diff, + output [31:0] csr_save2_diff, + output [31:0] csr_save3_diff, + output [31:0] csr_tid_diff, + output [31:0] csr_tcfg_diff, + output [31:0] csr_tval_diff, + output [31:0] csr_ticlr_diff, + output [31:0] csr_llbctl_diff, + output [31:0] csr_tlbrentry_diff, + output [31:0] csr_dmw0_diff, + output [31:0] csr_dmw1_diff, + output [31:0] csr_pgdl_diff, + output [31:0] csr_pgdh_diff +`endif +); + +localparam CRMD = 14'h0; +localparam PRMD = 14'h1; +localparam ECTL = 14'h4; +localparam ESTAT = 14'h5; +localparam ERA = 14'h6; +localparam BADV = 14'h7; +localparam EENTRY = 14'hc; +localparam TLBIDX= 14'h10; +localparam TLBEHI= 14'h11; +localparam TLBELO0=14'h12; +localparam TLBELO1=14'h13; +localparam ASID = 14'h18; +localparam PGDL = 14'h19; +localparam PGDH = 14'h1a; +localparam PGD = 14'h1b; +localparam CPUID = 14'h20; +localparam SAVE0 = 14'h30; +localparam SAVE1 = 14'h31; +localparam SAVE2 = 14'h32; +localparam SAVE3 = 14'h33; +localparam TID = 14'h40; +localparam TCFG = 14'h41; +localparam TVAL = 14'h42; +localparam CNTC = 14'h43; +localparam TICLR = 14'h44; +localparam LLBCTL= 14'h60; +localparam TLBRENTRY = 14'h88; +localparam DMW0 = 14'h180; +localparam DMW1 = 14'h181; +localparam BRK = 14'h100; +localparam DISABLE_CACHE = 14'h101; +localparam CPUCFG_1 = 14'hb1; +localparam CPUCFG_2 = 14'hb2; +localparam CPUCFG_10 = 14'hc0; +localparam CPUCFG_11 = 14'hc1; +localparam CPUCFG_12 = 14'hc2; +localparam CPUCFG_13 = 14'hc3; + +wire crmd_wen = csr_wr_en & (wr_addr == CRMD); +wire prmd_wen = csr_wr_en & (wr_addr == PRMD); +wire ectl_wen = csr_wr_en & (wr_addr == ECTL); +wire estat_wen = csr_wr_en & (wr_addr == ESTAT); +wire era_wen = csr_wr_en & (wr_addr == ERA); +wire badv_wen = csr_wr_en & (wr_addr == BADV); +wire eentry_wen = csr_wr_en & (wr_addr == EENTRY); +wire tlbidx_wen = csr_wr_en & (wr_addr == TLBIDX); +wire tlbehi_wen = csr_wr_en & (wr_addr == TLBEHI); +wire tlbelo0_wen= csr_wr_en & (wr_addr == TLBELO0); +wire tlbelo1_wen= csr_wr_en & (wr_addr == TLBELO1); +wire asid_wen = csr_wr_en & (wr_addr == ASID); +wire pgdl_wen = csr_wr_en & (wr_addr == PGDL); +wire pgdh_wen = csr_wr_en & (wr_addr == PGDH); +wire pgd_wen = csr_wr_en & (wr_addr == PGD); +wire cpuid_wen = csr_wr_en & (wr_addr == CPUID); +wire save0_wen = csr_wr_en & (wr_addr == SAVE0); +wire save1_wen = csr_wr_en & (wr_addr == SAVE1); +wire save2_wen = csr_wr_en & (wr_addr == SAVE2); +wire save3_wen = csr_wr_en & (wr_addr == SAVE3); +wire tid_wen = csr_wr_en & (wr_addr == TID); +wire tcfg_wen = csr_wr_en & (wr_addr == TCFG); +wire tval_wen = csr_wr_en & (wr_addr == TVAL); +wire cntc_wen = csr_wr_en & (wr_addr == CNTC); +wire ticlr_wen = csr_wr_en & (wr_addr == TICLR); +wire llbctl_wen = csr_wr_en & (wr_addr == LLBCTL); +wire tlbrentry_wen = csr_wr_en & (wr_addr == TLBRENTRY); +wire DMW0_wen = csr_wr_en & (wr_addr == DMW0); +wire DMW1_wen = csr_wr_en & (wr_addr == DMW1); +wire BRK_wen = csr_wr_en & (wr_addr == BRK); +wire disable_cache_wen = csr_wr_en & (wr_addr == DISABLE_CACHE); + +reg [31:0] csr_crmd; +reg [31:0] csr_prmd; +reg [31:0] csr_ectl; +reg [31:0] csr_estat; +reg [31:0] csr_era; +reg [31:0] csr_badv; +reg [31:0] csr_eentry; +reg [31:0] csr_tlbidx; +reg [31:0] csr_tlbehi; +reg [31:0] csr_tlbelo0; +reg [31:0] csr_tlbelo1; +reg [31:0] csr_asid; +reg [31:0] csr_cpuid; +reg [31:0] csr_save0; +reg [31:0] csr_save1; +reg [31:0] csr_save2; +reg [31:0] csr_save3; +reg [31:0] csr_tid; +reg [31:0] csr_tcfg; +reg [31:0] csr_tval; +reg [31:0] csr_cntc; +reg [31:0] csr_ticlr; +reg [31:0] csr_llbctl; +reg [31:0] csr_tlbrentry; +reg [31:0] csr_dmw0; +reg [31:0] csr_dmw1; +reg [31:0] csr_pgdl; +reg [31:0] csr_pgdh; +reg [31:0] csr_brk; +reg [31:0] csr_disable_cache; +reg [31:0] csr_cpucfg1; +reg [31:0] csr_cpucfg2; +reg [31:0] csr_cpucfg10; +reg [31:0] csr_cpucfg11; +reg [31:0] csr_cpucfg12; +reg [31:0] csr_cpucfg13; + + +wire [31:0] csr_pgd; + +reg timer_en; +reg [63:0] timer_64; + +reg llbit; +reg [27:0] lladdr; + +wire tlbrd_valid_wr_en; +wire tlbrd_invalid_wr_en; + +wire eret_tlbrefill_excp; + +wire no_forward; + +assign csr_pgd = csr_badv[31] ? csr_pgdh : csr_pgdl; + +assign eret_tlbrefill_excp = csr_estat[`ECODE] == 6'h3f; + +assign tlbrd_valid_wr_en = tlbrd_en && !tlbidx_in[`NE]; +assign tlbrd_invalid_wr_en = tlbrd_en && tlbidx_in[`NE]; + +assign has_int = ((csr_ectl[`LIE] & csr_estat[`IS]) != 13'b0) & csr_crmd[`IE]; + +assign eentry_out = csr_eentry; +assign era_out = csr_era; +assign timer_64_out = timer_64 + {{32{csr_cntc[31]}}, csr_cntc}; +assign tid_out = csr_tid; +assign llbit_out = llbit; +assign lladdr_out = lladdr; +assign asid_out = csr_asid[`TLB_ASID]; +assign vppn_out = (csr_wr_en && wr_addr == TLBEHI) ? wr_data[`VPPN] : csr_tlbehi[`VPPN]; +assign tlbehi_out = csr_tlbehi; +assign tlbelo0_out = csr_tlbelo0; +assign tlbelo1_out = csr_tlbelo1; +assign tlbidx_out = csr_tlbidx; +assign rand_index = timer_64[4:0]; +assign disable_cache_out = csr_disable_cache[0]; + +//forward to if stage +assign no_forward = !excp_tlbrefill && !(eret_tlbrefill_excp && ertn_flush) && !crmd_wen; + +assign pg_out = excp_tlbrefill & 1'b0 | + (eret_tlbrefill_excp && ertn_flush) & 1'b1 | + crmd_wen & wr_data[`PG] | + no_forward & csr_crmd[`PG]; + +assign da_out = excp_tlbrefill & 1'b1 | + (eret_tlbrefill_excp && ertn_flush) & 1'b0 | + crmd_wen & wr_data[`DA] | + no_forward & csr_crmd[`DA]; + +assign dmw0_out = DMW0_wen ? wr_data : csr_dmw0; +assign dmw1_out = DMW1_wen ? wr_data : csr_dmw1; + +assign plv_out = {2{excp_flush}} & 2'b0 | + {2{ertn_flush}} & csr_prmd[`PPLV] | + {2{crmd_wen }} & wr_data[`PLV] | + {2{!excp_flush && !ertn_flush && !crmd_wen}} & csr_crmd[`PLV]; + +assign tlbrentry_out= csr_tlbrentry; +assign datf_out = csr_crmd[`DATF]; +assign datm_out = csr_crmd[`DATM]; + +assign ecode_out = csr_estat[`ECODE]; + +assign rd_data = {32{rd_addr == CRMD }} & csr_crmd | + {32{rd_addr == PRMD }} & csr_prmd | + {32{rd_addr == ECTL }} & csr_ectl | + {32{rd_addr == ESTAT }} & csr_estat | + {32{rd_addr == ERA }} & csr_era | + {32{rd_addr == BADV }} & csr_badv | + {32{rd_addr == EENTRY}} & csr_eentry | + {32{rd_addr == TLBIDX}} & csr_tlbidx | + {32{rd_addr == TLBEHI}} & csr_tlbehi | + {32{rd_addr == TLBELO0}} & csr_tlbelo0 | + {32{rd_addr == TLBELO1}} & csr_tlbelo1 | + {32{rd_addr == ASID }} & csr_asid | + {32{rd_addr == PGDL }} & csr_pgdl | + {32{rd_addr == PGDH }} & csr_pgdh | + {32{rd_addr == PGD }} & csr_pgd | + {32{rd_addr == CPUID }} & csr_cpuid | + {32{rd_addr == SAVE0 }} & csr_save0 | + {32{rd_addr == SAVE1 }} & csr_save1 | + {32{rd_addr == SAVE2 }} & csr_save2 | + {32{rd_addr == SAVE3 }} & csr_save3 | + {32{rd_addr == TID }} & csr_tid | + {32{rd_addr == TCFG }} & csr_tcfg | + {32{rd_addr == CNTC }} & csr_cntc | + {32{rd_addr == TICLR }} & csr_ticlr | + {32{rd_addr == LLBCTL}} & {csr_llbctl[31:1], llbit} | + {32{rd_addr == TVAL }} & csr_tval | + {32{rd_addr == TLBRENTRY}} & csr_tlbrentry | + {32{rd_addr == DMW0}} & csr_dmw0 | + {32{rd_addr == DMW1}} & csr_dmw1 | + {32{rd_addr == CPUCFG_1 }} & csr_cpucfg1 | + {32{rd_addr == CPUCFG_2 }} & csr_cpucfg2 | + {32{rd_addr == CPUCFG_10 }} & csr_cpucfg10 | + {32{rd_addr == CPUCFG_11 }} & csr_cpucfg11 | + {32{rd_addr == CPUCFG_12 }} & csr_cpucfg12 | + {32{rd_addr == CPUCFG_13 }} & csr_cpucfg13 ; + +//crmd +always @(posedge clk) begin + if (reset) begin + csr_crmd[ `PLV] <= 2'b0; + csr_crmd[ `IE] <= 1'b0; + csr_crmd[ `DA] <= 1'b1; + csr_crmd[ `PG] <= 1'b0; + csr_crmd[`DATF] <= 2'b0; + csr_crmd[`DATM] <= 2'b0; + csr_crmd[31: 9] <= 23'b0; + end + else if (excp_flush) begin + csr_crmd[ `PLV] <= 2'b0; + csr_crmd[ `IE] <= 1'b0; + if (excp_tlbrefill) begin + csr_crmd [`DA] <= 1'b1; + csr_crmd [`PG] <= 1'b0; + end + end + else if (ertn_flush) begin + csr_crmd[ `PLV] <= csr_prmd[`PPLV]; + csr_crmd[ `IE] <= csr_prmd[`PIE ]; + if (eret_tlbrefill_excp) begin + csr_crmd[`DA] <= 1'b0; + csr_crmd[`PG] <= 1'b1; + end + end + else if (crmd_wen) begin + csr_crmd[ `PLV] <= wr_data[ `PLV]; + csr_crmd[ `IE] <= wr_data[ `IE]; + csr_crmd[ `DA] <= wr_data[ `DA]; + csr_crmd[ `PG] <= wr_data[ `PG]; + csr_crmd[`DATF] <= wr_data[`DATF]; + csr_crmd[`DATM] <= wr_data[`DATM]; + end +end + +//prmd +always @(posedge clk) begin + if (reset) begin + csr_prmd[31:3] <= 29'b0; + end + else if (excp_flush) begin + csr_prmd[`PPLV] <= csr_crmd[`PLV]; + csr_prmd[ `PIE] <= csr_crmd[`IE ]; + end + else if (prmd_wen) begin + csr_prmd[`PPLV] <= wr_data[`PPLV]; + csr_prmd[ `PIE] <= wr_data[ `PIE]; + end +end + +//ectl +always @(posedge clk) begin + if (reset) begin + csr_ectl <= 32'b0; + end + else if (ectl_wen) begin + csr_ectl[ `LIE_1] <= wr_data[ `LIE_1]; + csr_ectl[ `LIE_2] <= wr_data[ `LIE_2]; + end +end + +//estat +always @(posedge clk) begin + if (reset) begin + csr_estat[ 1: 0] <= 2'b0; + csr_estat[10] <= 1'b0; + csr_estat[12] <= 1'b0; + csr_estat[15:13] <= 3'b0; + csr_estat[31] <= 1'b0; + csr_estat[21:16] <= 6'b0; + + timer_en <= 1'b0; + end + else begin + if (ticlr_wen && wr_data[`CLR]) begin + csr_estat[11] <= 1'b0; + end + else if (tcfg_wen) begin + timer_en <= wr_data[`EN]; + end + else if (timer_en && (csr_tval == 32'b0)) begin + csr_estat[11] <= 1'b1; + timer_en <= csr_tcfg[`PERIODIC]; + end + csr_estat[9:2] <= interrupt; + if (excp_flush) begin + csr_estat[ `ECODE] <= ecode_in; + csr_estat[`ESUBCODE] <= esubcode_in; + end + else if (estat_wen) begin + csr_estat[ 1:0] <= wr_data[ 1:0]; + end + end +end + +//era +always @(posedge clk) begin + if (excp_flush) begin + csr_era <= era_in; + end + else if (era_wen) begin + csr_era <= wr_data; + end +end + +//badv +always @(posedge clk) begin + if (badv_wen) begin + csr_badv <= wr_data; + end + else if (va_error_in) begin + csr_badv <= bad_va_in; + end +end + +//eentry +always @(posedge clk) begin + if (reset) begin + csr_eentry[5:0] <= 6'b0; + end + else if (eentry_wen) begin + csr_eentry[31:6] <= wr_data[31:6]; + end +end + +//tlbidx +always @(posedge clk) begin + if (reset) begin + csr_tlbidx[23: 5] <= 19'b0; + csr_tlbidx[30] <= 1'b0; + csr_tlbidx[`INDEX]<= 5'b0; + end + else if (tlbidx_wen) begin + csr_tlbidx[$clog2(TLBNUM)-1:0] <= wr_data[$clog2(TLBNUM)-1:0]; + csr_tlbidx[`PS] <= wr_data[`PS]; + csr_tlbidx[`NE] <= wr_data[`NE]; + end + else if (tlbsrch_en) begin + if (tlbsrch_found) begin + csr_tlbidx[`INDEX] <= tlbsrch_index; + csr_tlbidx[`NE] <= 1'b0; + end + else begin + csr_tlbidx[`NE] <= 1'b1; + end + end + else if (tlbrd_valid_wr_en) begin + csr_tlbidx[`PS] <= tlbidx_in[`PS]; + csr_tlbidx[`NE] <= tlbidx_in[`NE]; + end + else if (tlbrd_invalid_wr_en) begin + csr_tlbidx[`PS] <= 6'b0; + csr_tlbidx[`NE] <= tlbidx_in[`NE]; + end +end + +//tlbehi +always @(posedge clk) begin + if (reset) begin + csr_tlbehi[12:0] <= 13'b0; + end + else if (tlbehi_wen) begin + csr_tlbehi[`VPPN] <= wr_data[`VPPN]; + end + else if (tlbrd_valid_wr_en) begin + csr_tlbehi[`VPPN] <= tlbehi_in[`VPPN]; + end + else if (tlbrd_invalid_wr_en) begin + csr_tlbehi[`VPPN] <= 19'b0; + end + else if (excp_tlb) begin + csr_tlbehi[`VPPN] <= excp_tlb_vppn; + end +end + +//tlbelo0 +always @(posedge clk) begin + if (reset) begin + csr_tlbelo0[7] <= 1'b0; + end + else if (tlbelo0_wen) begin + csr_tlbelo0[`TLB_V] <= wr_data[`TLB_V]; + csr_tlbelo0[`TLB_D] <= wr_data[`TLB_D]; + csr_tlbelo0[`TLB_PLV] <= wr_data[`TLB_PLV]; + csr_tlbelo0[`TLB_MAT] <= wr_data[`TLB_MAT]; + csr_tlbelo0[`TLB_G] <= wr_data[`TLB_G]; + csr_tlbelo0[`TLB_PPN_EN] <= wr_data[`TLB_PPN_EN]; + end + else if (tlbrd_valid_wr_en) begin + csr_tlbelo0[`TLB_V] <= tlbelo0_in[`TLB_V]; + csr_tlbelo0[`TLB_D] <= tlbelo0_in[`TLB_D]; + csr_tlbelo0[`TLB_PLV] <= tlbelo0_in[`TLB_PLV]; + csr_tlbelo0[`TLB_MAT] <= tlbelo0_in[`TLB_MAT]; + csr_tlbelo0[`TLB_G] <= tlbelo0_in[`TLB_G]; + csr_tlbelo0[`TLB_PPN_EN] <= tlbelo0_in[`TLB_PPN_EN]; + end + else if (tlbrd_invalid_wr_en) begin + csr_tlbelo0[`TLB_V] <= 1'b0; + csr_tlbelo0[`TLB_D] <= 1'b0; + csr_tlbelo0[`TLB_PLV] <= 2'b0; + csr_tlbelo0[`TLB_MAT] <= 2'b0; + csr_tlbelo0[`TLB_G] <= 1'b0; + csr_tlbelo0[`TLB_PPN_EN] <= 20'b0; + end +end + +//tlbelo1 +always @(posedge clk) begin + if (reset) begin + csr_tlbelo1[7] <= 1'b0; + end + else if (tlbelo1_wen) begin + csr_tlbelo1[`TLB_V] <= wr_data[`TLB_V]; + csr_tlbelo1[`TLB_D] <= wr_data[`TLB_D]; + csr_tlbelo1[`TLB_PLV] <= wr_data[`TLB_PLV]; + csr_tlbelo1[`TLB_MAT] <= wr_data[`TLB_MAT]; + csr_tlbelo1[`TLB_G] <= wr_data[`TLB_G]; + csr_tlbelo1[`TLB_PPN_EN] <= wr_data[`TLB_PPN_EN]; + end + else if (tlbrd_valid_wr_en) begin + csr_tlbelo1[`TLB_V] <= tlbelo1_in[`TLB_V]; + csr_tlbelo1[`TLB_D] <= tlbelo1_in[`TLB_D]; + csr_tlbelo1[`TLB_PLV] <= tlbelo1_in[`TLB_PLV]; + csr_tlbelo1[`TLB_MAT] <= tlbelo1_in[`TLB_MAT]; + csr_tlbelo1[`TLB_G] <= tlbelo1_in[`TLB_G]; + csr_tlbelo1[`TLB_PPN_EN] <= tlbelo1_in[`TLB_PPN_EN]; + end + else if (tlbrd_invalid_wr_en) begin + csr_tlbelo1[`TLB_V] <= 1'b0; + csr_tlbelo1[`TLB_D] <= 1'b0; + csr_tlbelo1[`TLB_PLV] <= 2'b0; + csr_tlbelo1[`TLB_MAT] <= 2'b0; + csr_tlbelo1[`TLB_G] <= 1'b0; + csr_tlbelo1[`TLB_PPN_EN] <= 20'b0; + end +end + +//asid +always @(posedge clk) begin + if (reset) begin + csr_asid[31:10] <= 22'h280; //ASIDBITS = 10 + end + else if (asid_wen) begin + csr_asid[`TLB_ASID] <= wr_data[`TLB_ASID]; + end + else if (tlbrd_valid_wr_en) begin + csr_asid[`TLB_ASID] <= asid_in; + end + else if (tlbrd_invalid_wr_en) begin + csr_asid[`TLB_ASID] <= 10'b0; + end +end + +//TLBRENTRY +always @(posedge clk) begin + if (reset) begin + csr_tlbrentry[5:0] <= 6'b0; + end + else if (tlbrentry_wen) begin + csr_tlbrentry[`TLBRENTRY_PA] <= wr_data[`TLBRENTRY_PA]; + end +end + +//dmw0 +always @(posedge clk) begin + if (reset) begin + csr_dmw0[ 2:1] <= 2'b0; + csr_dmw0[24:6] <= 19'b0; + csr_dmw0[28] <= 1'b0; + end + else if (DMW0_wen) begin + csr_dmw0[`PLV0] <= wr_data[`PLV0]; + csr_dmw0[`PLV3] <= wr_data[`PLV3]; + csr_dmw0[`DMW_MAT] <= wr_data[`DMW_MAT]; + csr_dmw0[`PSEG] <= wr_data[`PSEG]; + csr_dmw0[`VSEG] <= wr_data[`VSEG]; + end +end + +//dmw1 +always @(posedge clk) begin + if (reset) begin + csr_dmw1[ 2:1] <= 2'b0; + csr_dmw1[24:6] <= 19'b0; + csr_dmw1[28] <= 1'b0; + end + else if (DMW1_wen) begin + csr_dmw1[`PLV0] <= wr_data[`PLV0]; + csr_dmw1[`PLV3] <= wr_data[`PLV3]; + csr_dmw1[`DMW_MAT] <= wr_data[`DMW_MAT]; + csr_dmw1[`PSEG] <= wr_data[`PSEG]; + csr_dmw1[`VSEG] <= wr_data[`VSEG]; + end +end + +//cpuid +always @(posedge clk) begin + if (reset) begin + csr_cpuid <= 32'b0; + end +end + +//save0 +always @(posedge clk) begin + if (save0_wen) begin + csr_save0 <= wr_data; + end +end + +//save1 +always @(posedge clk) begin + if (save1_wen) begin + csr_save1 <= wr_data; + end +end + +//save2 +always @(posedge clk) begin + if (save2_wen) begin + csr_save2 <= wr_data; + end +end + +//save3 +always @(posedge clk) begin + if (save3_wen) begin + csr_save3 <= wr_data; + end +end + +//tid +always @(posedge clk) begin + if (reset) begin + csr_tid <= 32'b0; + end + else if (tid_wen) begin + csr_tid <= wr_data; + end +end + +//tcfg +always @(posedge clk) begin + if (reset) begin + csr_tcfg[`EN] <= 1'b0; + end + else if (tcfg_wen) begin + csr_tcfg[ `EN] <= wr_data[ `EN]; + csr_tcfg[`PERIODIC] <= wr_data[`PERIODIC]; + csr_tcfg[ `INITVAL] <= wr_data[ `INITVAL]; + end +end + +//cntc +always @(posedge clk) begin + if (reset) begin + csr_cntc <= 32'b0; + end + else if (cntc_wen) begin + csr_cntc <= wr_data; + end +end + +//tval +always @(posedge clk) begin + if (tcfg_wen) begin + csr_tval <= {wr_data[ `INITVAL], 2'b0}; + end + else if (timer_en) begin + if (csr_tval != 32'b0) begin + csr_tval <= csr_tval - 32'b1; + end + else if (csr_tval == 32'b0) begin + csr_tval <= csr_tcfg[`PERIODIC] ? {csr_tcfg[`INITVAL], 2'b0} : 32'hffffffff; + end + end +end + +//ticlr +always @(posedge clk) begin + if (reset) begin + csr_ticlr <= 32'b0; + end +end + +//llbctl +always @(posedge clk) begin + if (reset) begin + csr_llbctl[`KLO] <= 1'b0; + csr_llbctl[31:3] <= 29'b0; + csr_llbctl[`WCLLB] <= 1'b0; + llbit <= 1'b0; + end + else if (ertn_flush) begin + if (csr_llbctl[`KLO]) begin + csr_llbctl[`KLO] <= 1'b0; + end + else begin + llbit <= 1'b0; + end + end + else if (llbctl_wen) begin + csr_llbctl[ `KLO] <= wr_data[ `KLO]; + if (wr_data[`WCLLB] == 1'b1) begin + llbit <= 1'b0; + end + end + else if (llbit_set_in) begin + llbit <= llbit_in; + end +end + +always @(posedge clk) begin + if (reset) begin + lladdr <= 28'b0; + end + else if (lladdr_set_in) begin + lladdr <= lladdr_in; + end +end + +//timer_64 +always @(posedge clk) begin + if (reset) begin + timer_64 <= 64'b0; + end + else begin + timer_64 <= timer_64 + 1'b1; + end +end + +//pgdl +always @(posedge clk) begin + if (pgdl_wen) begin + csr_pgdl[`BASE] <= wr_data[`BASE]; + end +end + +//pgdh +always @(posedge clk) begin + if (pgdh_wen) begin + csr_pgdh[`BASE] <= wr_data[`BASE]; + end +end + +//use for break in chipscope in software +always @(posedge clk) begin + if (reset) begin + csr_brk <= 32'b0; + end + if (BRK_wen) begin + csr_brk <= wr_data; + end +end + +//use for disable cache or enable cache +always @(posedge clk) begin + if (reset) begin + csr_disable_cache <= 32'b0; + end + if (disable_cache_wen) begin + csr_disable_cache <= wr_data; + end +end + +//cpucfg1 +always @(posedge clk) begin + if (reset) begin + csr_cpucfg1 <= 32'h1f1f4; + end +end + +//cpucfg2 +always @(posedge clk) begin + if (reset) begin + csr_cpucfg2 <= 32'h0; + end +end + +//cpucfg10 +always @(posedge clk) begin + if (reset) begin + csr_cpucfg10 <= 32'h5; + end +end + +//cpucfg11 +always @(posedge clk) begin + if (reset) begin + csr_cpucfg11 <= 32'h04080001; + end +end + +//cpucfg12 +always @(posedge clk) begin + if (reset) begin + csr_cpucfg12 <= 32'h04080001; + end +end + +//cpucfg13 +always @(posedge clk) begin + if (reset) begin + csr_cpucfg13 <= 32'h0; + end +end + +// difftest +`ifdef DIFFTEST_EN +assign csr_crmd_diff = csr_crmd; +assign csr_prmd_diff = csr_prmd; +assign csr_ectl_diff = csr_ectl; +assign csr_estat_diff = csr_estat; +assign csr_era_diff = csr_era; +assign csr_badv_diff = csr_badv; +assign csr_eentry_diff = csr_eentry; +assign csr_tlbidx_diff = csr_tlbidx; +assign csr_tlbehi_diff = csr_tlbehi; +assign csr_tlbelo0_diff = csr_tlbelo0; +assign csr_tlbelo1_diff = csr_tlbelo1; +assign csr_asid_diff = csr_asid; +assign csr_save0_diff = csr_save0; +assign csr_save1_diff = csr_save1; +assign csr_save2_diff = csr_save2; +assign csr_save3_diff = csr_save3; +assign csr_tid_diff = csr_tid; +assign csr_tcfg_diff = csr_tcfg; +assign csr_tval_diff = csr_tval; +assign csr_ticlr_diff = csr_ticlr; +assign csr_llbctl_diff = {csr_llbctl[31:1], llbit}; +assign csr_tlbrentry_diff = csr_tlbrentry; +assign csr_dmw0_diff = csr_dmw0; +assign csr_dmw1_diff = csr_dmw1; +assign csr_pgdl_diff = csr_pgdl; +assign csr_pgdh_diff = csr_pgdh; +`endif + +endmodule diff --git a/rtl/ip/open-la500/dcache.v b/rtl/ip/open-la500/dcache.v new file mode 100644 index 0000000..d9c2045 --- /dev/null +++ b/rtl/ip/open-la500/dcache.v @@ -0,0 +1,651 @@ +module dcache +( + input clk , + input reset , + //to from cpu + input valid , + input op , //cache inst treat as load, op is zero + input [ 2:0] size , + input [ 7:0] index , + input [19:0] tag , + input [ 3:0] offset , + input [ 3:0] wstrb , + input [31:0] wdata , + output addr_ok , + output data_ok , + output [31:0] rdata , + input uncache_en , + input dcacop_op_en , + input [ 1:0] cacop_op_mode, + input [ 4:0] preld_hint , + input preld_en , + input tlb_excp_cancel_req, + input sc_cancel_req, + output dcache_empty , + //to from axi + output rd_req , + output [ 2:0] rd_type , + output [31:0] rd_addr , + input rd_rdy , + input ret_valid , + input ret_last , + input [31:0] ret_data , + output reg wr_req , + output [ 2:0] wr_type , + output [31:0] wr_addr , + output [ 3:0] wr_wstrb , + output [127:0] wr_data , + input wr_rdy , + //to perf_counter + output cache_miss +); + +reg [1:0] way_d_reg [255:0]; + +wire request_uncache_en ; +reg request_buffer_op ; +reg request_buffer_preld ; +reg [ 2:0] request_buffer_size ; +reg [ 7:0] request_buffer_index ; +reg [19:0] request_buffer_tag ; +reg [ 3:0] request_buffer_offset ; +reg [ 3:0] request_buffer_wstrb ; +reg [31:0] request_buffer_wdata ; +reg request_buffer_uncache_en ; +reg request_buffer_dcacop ; +reg [ 1:0] request_buffer_cacop_op_mode; + +reg [ 1:0] miss_buffer_replace_way ; +reg [ 1:0] miss_buffer_ret_num ; +wire [ 1:0] ret_num_add_one ; + +reg [ 7:0] write_buffer_index ; +reg [ 3:0] write_buffer_wstrb ; +reg [31:0] write_buffer_wdata ; +reg [ 1:0] write_buffer_way ; +reg [ 3:0] write_buffer_offset ; + +wire [ 7:0] way_bank_addra [1:0][3:0]; +wire [31:0] way_bank_dina [1:0][3:0]; +wire [31:0] way_bank_douta [1:0][3:0]; +wire way_bank_ena [1:0][3:0]; +wire [ 3:0] way_bank_wea [1:0][3:0]; + +wire [ 7:0] way_tagv_addra [1:0]; +wire [20:0] way_tagv_dina [1:0]; +wire [20:0] way_tagv_douta [1:0]; +wire way_tagv_ena [1:0]; +wire way_tagv_wea [1:0]; + +wire wr_match_way_bank[1:0][3:0]; + +wire [ 1:0] way_d ; + +wire [ 1:0] way_hit ; +wire cache_hit ; + +wire [31:0] way_load_word [1:0]; +wire [127:0] way_data [1:0]; +wire [31:0] load_res ; + +wire [127:0] replace_data ; +wire replace_d ; +wire replace_v ; +wire [19:0] replace_tag ; +wire [ 1:0] random_val ; +wire [ 3:0] chosen_way ; +wire [ 1:0] replace_way ; +wire [ 1:0] invalid_way ; +wire has_invalid_way ; +wire [ 1:0] rand_repl_way ; +wire [ 3:0] cacop_chose_way ; + +wire main_idle2lookup ; +wire main_lookup2lookup; + +wire main_state_is_idle ; +wire main_state_is_lookup ; +wire main_state_is_miss ; +wire main_state_is_replace; +wire main_state_is_refill ; + +wire write_state_is_idle; +wire write_state_is_full; + +wire uncache_wr ; +reg uncache_wr_buffer; +wire [ 2:0] uncache_wr_type; + +wire [ 1:0] way_wr_en; + +wire [31:0] refill_data; +wire [31:0] write_in; + +wire cacop_op_mode0; +wire cacop_op_mode1; +wire cacop_op_mode2; + +wire cacop_op_mode2_hit_wr; +reg cacop_op_mode2_hit_wr_buffer; + +wire preld_st_en; +wire preld_ld_en; +wire preld_ld_st_en; + +wire req_or_inst_valid; + +reg [1:0] lookup_way_hit_buffer; + +localparam main_idle = 5'b00001; +localparam main_lookup = 5'b00010; +localparam main_miss = 5'b00100; +localparam main_replace = 5'b01000; +localparam main_refill = 5'b10000; +localparam write_buffer_idle = 1'b0; +localparam write_buffer_write = 1'b1; + +genvar i,j; + +reg [4:0] main_state; +reg write_buffer_state; + +reg rd_req_buffer; + +// wire invalid_way; + +wire cancel_req = tlb_excp_cancel_req || sc_cancel_req; + +//state machine +//main loop +always @(posedge clk) begin + if (reset) begin + main_state <= main_idle; + + request_buffer_op <= 1'b0; + request_buffer_preld <= 1'b0; + request_buffer_size <= 3'b0; + request_buffer_index <= 8'b0; + request_buffer_tag <= 20'b0; + request_buffer_offset <= 4'b0; + request_buffer_wstrb <= 4'b0; + request_buffer_wdata <= 32'b0; + request_buffer_uncache_en <= 1'b0; + + request_buffer_cacop_op_mode <= 2'b0; + request_buffer_dcacop <= 1'b0; + + miss_buffer_replace_way <= 2'b0; + + wr_req <= 1'b0; + end + else case (main_state) + main_idle: begin + if (req_or_inst_valid && main_idle2lookup) begin + main_state <= main_lookup; + + request_buffer_op <= op ; + request_buffer_preld <= preld_en ; + request_buffer_size <= size ; + request_buffer_index <= index ; + request_buffer_offset <= offset ; + request_buffer_wstrb <= wstrb ; + request_buffer_wdata <= wdata ; + + request_buffer_cacop_op_mode <= cacop_op_mode ; + request_buffer_dcacop <= dcacop_op_en ; + end + end + main_lookup: begin + if (req_or_inst_valid && main_lookup2lookup) begin + main_state <= main_lookup; + + request_buffer_op <= op ; + request_buffer_preld <= preld_en ; + request_buffer_size <= size ; + request_buffer_index <= index ; + request_buffer_offset <= offset ; + request_buffer_wstrb <= wstrb ; + request_buffer_wdata <= wdata ; + + request_buffer_cacop_op_mode <= cacop_op_mode ; + request_buffer_dcacop <= dcacop_op_en ; + end + else if (cancel_req) begin + main_state <= main_idle; + end + else if (!cache_hit) begin + //uncache wr --> wr_req 1 + //uncache rd, cacop(code==0) --> wr_req 0 + //cacop(code==1, 2), cache st, cache ld --> wr_req (dirty && valid) + if (uncache_wr || ((replace_d && replace_v) && (!request_uncache_en || cacop_op_mode2_hit_wr) && !cacop_op_mode0)) + main_state <= main_miss; + else + main_state <= main_replace; + + request_buffer_tag <= tag; + request_buffer_uncache_en <= request_uncache_en; + uncache_wr_buffer <= uncache_wr; + miss_buffer_replace_way <= replace_way; + cacop_op_mode2_hit_wr_buffer <= cacop_op_mode2_hit_wr; + end + else begin + main_state <= main_idle; + end + end + main_miss: begin + if (wr_rdy) begin + main_state <= main_replace; + wr_req <= 1'b1; + end + end + main_replace: begin + if (rd_rdy) begin + main_state <= main_refill; + miss_buffer_ret_num <= 2'b0; //when get ret data, it will be sent to cpu directly. + end + wr_req <= 1'b0; + end + main_refill: begin + if ((ret_valid && ret_last) || !rd_req_buffer) begin //when rd_req is not set, go to next state directly + main_state <= main_idle; + end + else begin + if (ret_valid) begin + miss_buffer_ret_num <= ret_num_add_one; + end + end + end + default: begin + main_state <= main_idle; + end + endcase +end + +//hit write state +always @(posedge clk) begin + if (reset) begin + write_buffer_state <= write_buffer_idle; + + write_buffer_index <= 8'b0; + write_buffer_wstrb <= 4'b0; + write_buffer_wdata <= 32'b0; + write_buffer_offset <= 4'b0; + write_buffer_way <= 2'b0; + end + else case (write_buffer_state) + write_buffer_idle: begin + if (main_state_is_lookup && cache_hit && request_buffer_op && !cancel_req) begin + write_buffer_state <= write_buffer_write; + + write_buffer_index <= request_buffer_index; + write_buffer_wstrb <= request_buffer_wstrb; + write_buffer_wdata <= request_buffer_wdata; + write_buffer_offset <= request_buffer_offset; + write_buffer_way <= way_hit; + end + end + write_buffer_write: begin + if (main_state_is_lookup && cache_hit && request_buffer_op && !cancel_req) begin + write_buffer_state <= write_buffer_write; + + write_buffer_index <= request_buffer_index; + write_buffer_wstrb <= request_buffer_wstrb; + write_buffer_wdata <= request_buffer_wdata; + write_buffer_offset <= request_buffer_offset; + write_buffer_way <= way_hit; + end + else begin + write_buffer_state <= write_buffer_idle; + end + end + endcase +end + +/*====================================main state idle=======================================*/ + +assign req_or_inst_valid = valid || dcacop_op_en || preld_en; + +//state change condition, write hit cache block write do not conflict with lookup read and cacop +assign main_idle2lookup = !(write_state_is_full && ((write_buffer_offset[3:2] == offset[3:2]) || dcacop_op_en)); + +assign dcache_empty = main_state_is_idle; +//addr_ok logic + +/*===================================main state lookup======================================*/ + +//tag compare +generate for(i=0;i<2;i=i+1) begin:gen_way_hit + assign way_hit[i] = way_tagv_douta[i][0] && (tag == way_tagv_douta[i][20:1]); //this signal will not maintain +end endgenerate + +assign cache_hit = |way_hit && !(uncache_en || cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2); //uncache road reuse +//when cache inst op mode2 no hit, main state machine will still go a round. implement easy. + +assign main_lookup2lookup = !(write_state_is_full && ((write_buffer_offset[3:2] == offset[3:2]) || dcacop_op_en)) && + !(request_buffer_op && !op && ((request_buffer_offset[3:2] == offset[3:2]) || dcacop_op_en)) && + cache_hit; + +assign addr_ok = (main_state_is_idle && main_idle2lookup) || (main_state_is_lookup && main_lookup2lookup); //request can be get + +//data select +generate for(i=0;i<2;i=i+1) begin:gen_way_data + assign way_data[i] = {way_bank_douta[i][3],way_bank_douta[i][2],way_bank_douta[i][1],way_bank_douta[i][0]}; + + assign way_load_word[i] = way_data[i][request_buffer_offset[3:2]*32 +: 32]; +end endgenerate + +assign load_res = {32{way_hit[0]}} & way_load_word[0] | + {32{way_hit[1]}} & way_load_word[1] ; + +assign request_uncache_en = (uncache_en && !request_buffer_dcacop); + +assign uncache_wr = request_uncache_en && request_buffer_op && !cacop_op_mode1 && !cacop_op_mode2_hit_wr; +//data_ok logic + +decoder_2_4 dec_rand_way (.in({1'b0,random_val[0]}),.out(chosen_way)); + +one_valid_n #(2) sel_one_invalid (.in(~{way_tagv_douta[1][0],way_tagv_douta[0][0]}),.out(invalid_way),.nozero(has_invalid_way)); + +assign rand_repl_way = has_invalid_way ? invalid_way : chosen_way[1:0]; //chose invalid way first. + +decoder_2_4 dec_cacop_way (.in({1'b0,request_buffer_offset[0]}),.out(cacop_chose_way)); + +assign replace_way = {2{cacop_op_mode0 || cacop_op_mode1}} & cacop_chose_way[1:0] | + {2{cacop_op_mode2}} & way_hit | + {2{!request_buffer_dcacop}} & rand_repl_way; + +assign way_d = way_d_reg[request_buffer_index] | + {2{(write_buffer_index==request_buffer_index)&&write_state_is_full}}&write_buffer_way; + +assign replace_d = |(replace_way & way_d); +assign replace_v = |(replace_way & {way_tagv_douta[1][0],way_tagv_douta[0][0]}); + +/*====================================main state miss=======================================*/ + +assign replace_tag = {20{miss_buffer_replace_way[0]}} & way_tagv_douta[0][20:1] | + {20{miss_buffer_replace_way[1]}} & way_tagv_douta[1][20:1] ; + +assign replace_data = {128{miss_buffer_replace_way[0]}} & way_data[0] | + {128{miss_buffer_replace_way[1]}} & way_data[1] ; + +assign wr_type = uncache_wr_buffer ? uncache_wr_type : 3'b100; //replace cache line +assign wr_addr = uncache_wr_buffer ? {request_buffer_tag, request_buffer_index, request_buffer_offset} : + {replace_tag, request_buffer_index, 4'b0}; +assign wr_data = uncache_wr_buffer ? {96'b0, request_buffer_wdata} : replace_data; +assign wr_wstrb = uncache_wr_buffer ? request_buffer_wstrb : 4'hf; + +//assign wr_req = main_state_is_miss; + +/*==================================main state replace======================================*/ + +assign uncache_wr_type = request_buffer_size; + +assign rd_req = main_state_is_replace && !(uncache_wr_buffer || cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2); + +assign rd_type = request_buffer_uncache_en ? request_buffer_size : 3'b100; +assign rd_addr = request_buffer_uncache_en ? {request_buffer_tag, request_buffer_index, request_buffer_offset} : {request_buffer_tag, request_buffer_index, 4'b0}; +/*===================================main state refill======================================*/ + +//write process will not block pipeline +//preld ins will not block pipeline ps:preld is not real mem inst, this operation is controled in pipeline +assign data_ok = ((main_state_is_lookup && (cache_hit || request_buffer_op || cancel_req)) || + (main_state_is_refill && (!request_buffer_op && (ret_valid && ((miss_buffer_ret_num == request_buffer_offset[3:2]) || request_buffer_uncache_en))))) && + !(request_buffer_preld || request_buffer_dcacop); //when rd_req is not set, set data_ok directly. +//rdate connect with ret_data dirctly. maintain one clock only + +assign write_in = {(request_buffer_wstrb[3] ? request_buffer_wdata[31:24] : ret_data[31:24]), + (request_buffer_wstrb[2] ? request_buffer_wdata[23:16] : ret_data[23:16]), + (request_buffer_wstrb[1] ? request_buffer_wdata[15: 8] : ret_data[15: 8]), + (request_buffer_wstrb[0] ? request_buffer_wdata[ 7: 0] : ret_data[ 7: 0])}; + +assign refill_data = (request_buffer_op && (request_buffer_offset[3:2] == miss_buffer_ret_num)) ? write_in : ret_data; + +assign way_wr_en = miss_buffer_replace_way & {2{ret_valid}}; //when rd_req is not set, ret_valid and ret_last will not be set. block will not be wr also. + +assign cache_miss = main_state_is_refill && ret_last && !(request_buffer_uncache_en || request_buffer_dcacop || request_buffer_preld); + +//add one +assign ret_num_add_one[0] = miss_buffer_ret_num[0] ^ 1'b1; +assign ret_num_add_one[1] = miss_buffer_ret_num[1] ^ miss_buffer_ret_num[0]; + +always @(posedge clk) begin + if (reset) begin + rd_req_buffer <= 1'b0; + end + else if (rd_req) begin + rd_req_buffer <= 1'b1; + end + else if (main_state_is_refill && (ret_valid && ret_last)) begin + rd_req_buffer <= 1'b0; + end +end + +/*==========================================================================================*/ + +//refill or write state update dirty reg +always @(posedge clk) begin + if (main_state_is_refill && ((ret_valid && ret_last) || !rd_req_buffer) && (!(request_buffer_uncache_en || cacop_op_mode0))) begin + way_d_reg[request_buffer_index][0] <= miss_buffer_replace_way[0] ? request_buffer_op : way_d_reg[request_buffer_index][0]; + way_d_reg[request_buffer_index][1] <= miss_buffer_replace_way[1] ? request_buffer_op : way_d_reg[request_buffer_index][1]; + end + else if (write_state_is_full) begin + way_d_reg[write_buffer_index] <= way_d_reg[write_buffer_index] | write_buffer_way; + end +end + +//cache ins control signal +assign cacop_op_mode0 = request_buffer_dcacop && (request_buffer_cacop_op_mode == 2'b00); +assign cacop_op_mode1 = request_buffer_dcacop && ((request_buffer_cacop_op_mode == 2'b01) || (request_buffer_cacop_op_mode == 2'b11)); +assign cacop_op_mode2 = request_buffer_dcacop && (request_buffer_cacop_op_mode == 2'b10); + +assign cacop_op_mode2_hit_wr = cacop_op_mode2 && |way_hit; + +//output +assign rdata = {32{main_state_is_lookup}} & load_res | + {32{main_state_is_refill}} & ret_data ; + +generate +for(i=0;i<2;i=i+1) begin:gen_data_way + for(j=0;j<4;j=j+1) begin:gen_data_bank +/*===============================bank addra logic==============================*/ + + assign wr_match_way_bank[i][j] = write_state_is_full && (write_buffer_way[i] && (write_buffer_offset[3:2] == j[1:0])); + + assign way_bank_addra[i][j] = wr_match_way_bank[i][j] ? write_buffer_index : ({8{addr_ok}} & index | /*lookup*/ + {8{!addr_ok}} & request_buffer_index); + +/*===============================bank we logic=================================*/ + + assign way_bank_wea[i][j] = {4{wr_match_way_bank[i][j]}} & write_buffer_wstrb | + {4{main_state_is_refill && (way_wr_en[i] && (miss_buffer_ret_num == j[1:0]))}} & 4'hf; + +/*===============================bank dina logic=================================*/ + + assign way_bank_dina[i][j] = {32{write_state_is_full}} & write_buffer_wdata | + {32{main_state_is_refill}} & refill_data ; + +/*===============================bank ena logic=================================*/ + + assign way_bank_ena[i][j] = (!(request_buffer_uncache_en || cacop_op_mode0)) || main_state_is_idle || main_state_is_lookup; + end +end +endgenerate + +generate +for(i=0;i<2;i=i+1) begin:gen_tagv_way +/*===============================tagv addra logic=================================*/ + +assign way_tagv_addra[i] = {8{addr_ok }} & index | + {8{!addr_ok}} & request_buffer_index ; + +/*===============================tagv ena logic=================================*/ + +assign way_tagv_ena[i] = (!request_buffer_uncache_en) || main_state_is_idle || main_state_is_lookup; + +/*===============================tagv wea logic=================================*/ + +assign way_tagv_wea[i] = miss_buffer_replace_way[i] && main_state_is_refill && + ((ret_valid && ret_last) || cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2_hit_wr_buffer); //write at least 4B + +/*===============================tagv dina logic=================================*/ + +assign way_tagv_dina[i] = (cacop_op_mode0 || cacop_op_mode1 || cacop_op_mode2_hit_wr_buffer) ? 21'b0 : {request_buffer_tag, 1'b1}; +end +endgenerate +/*==============================================================================*/ + +generate +for(i=0;i<2;i=i+1) begin:data_ram_way + for(j=0;j<4;j=j+1) begin:data_ram_bank + data_bank_sram u( + .addra (way_bank_addra[i][j]), + .clka (clk ), + .dina (way_bank_dina[i][j] ), + .douta (way_bank_douta[i][j]), + .ena (way_bank_ena[i][j] ), + .wea (way_bank_wea[i][j] ) + ); + end +end +endgenerate + +generate +for(i=0;i<2;i=i+1) begin:tagv_ram_way + //[20:1] tag [0:0] v + tagv_sram u( + .addra (way_tagv_addra[i]), + .clka (clk ), + .dina (way_tagv_dina[i] ), + .douta (way_tagv_douta[i]), + .ena (way_tagv_ena[i] ), + .wea (way_tagv_wea[i] ) + ); +end +endgenerate + +lfsr lfsr( + .clk (clk ), + .reset (reset ), + .random_val (random_val ) +); + +assign main_state_is_idle = main_state == main_idle ; +assign main_state_is_lookup = main_state == main_lookup ; +assign main_state_is_miss = main_state == main_miss ; +assign main_state_is_replace = main_state == main_replace; +assign main_state_is_refill = main_state == main_refill ; + +assign write_state_is_idle = (write_buffer_state == write_buffer_idle) ; +assign write_state_is_full = (write_buffer_state == write_buffer_write); + +endmodule + +`ifdef SIMU +module data_bank_sram +#( + parameter WIDTH = 32 , + parameter DEPTH = 256 +) +( + input [ 7:0] addra , + input clka , + input [31:0] dina , + output [31:0] douta , + input ena , + input [ 3:0] wea +); + +reg [31:0] mem_reg [255:0]; +reg [31:0] output_buffer; + +always @(posedge clka) begin + if (ena) begin + if (wea) begin + if (wea[0]) begin + mem_reg[addra][ 7: 0] <= dina[ 7: 0]; + end + + if (wea[1]) begin + mem_reg[addra][15: 8] <= dina[15: 8]; + end + + if (wea[2]) begin + mem_reg[addra][23:16] <= dina[23:16]; + end + + if (wea[3]) begin + mem_reg[addra][31:24] <= dina[31:24]; + end + end + else begin + output_buffer <= mem_reg[addra]; + end + end +end + +assign douta = output_buffer; + +endmodule + +module tagv_sram +#( + parameter WIDTH = 21 , + parameter DEPTH = 256 +) +( + input [ 7:0] addra , + input clka , + input [20:0] dina , + output [20:0] douta , + input ena , + input wea +); + +reg [20:0] mem_reg [255:0]; +reg [20:0] output_buffer; + +always @(posedge clka) begin + if (ena) begin + if (wea) begin + mem_reg[addra] <= dina; + end + else begin + output_buffer <= mem_reg[addra]; + end + end +end + +assign douta = output_buffer; + +endmodule +`endif + +module lfsr +( + input clk , + input reset , + + output [1:0] random_val +); + +reg [7:0] r_lfsr; + +always @(posedge clk) begin + if (reset) begin + r_lfsr <= 8'b1; + end + else begin + r_lfsr[0] <= r_lfsr[7]; + r_lfsr[1] <= r_lfsr[0]; + r_lfsr[2] <= r_lfsr[1]; + r_lfsr[3] <= r_lfsr[2]; + r_lfsr[4] <= r_lfsr[3] ^ r_lfsr[7]; + r_lfsr[5] <= r_lfsr[4] ^ r_lfsr[7]; + r_lfsr[6] <= r_lfsr[5] ^ r_lfsr[7]; + r_lfsr[7] <= r_lfsr[6]; + end +end + +assign random_val = r_lfsr[7:6]; + +endmodule diff --git a/rtl/ip/open-la500/div.v b/rtl/ip/open-la500/div.v new file mode 100644 index 0000000..225827c --- /dev/null +++ b/rtl/ip/open-la500/div.v @@ -0,0 +1,99 @@ +//x/y //执行需要34个周期 +module div( + input div_clk, reset, + input div, + input div_signed, + input [31:0] x, y, + output [31:0] s, r, + output complete + ); + +reg [32:0] UnsignS; +reg [32:0] UnsignR; +reg [32:0] tmp_r; +reg [7:0] count; +wire [32:0] tmp_d; +wire [32:0] result_r; +wire [32:0] UnsignX, UnsignY; + +reg div_signed_buffer; +reg x_31_buffer; +reg y_31_buffer; +wire real_div_signed; +wire real_x_31; +wire real_y_31; +wire complete_delay; +wire real_complete; + +assign complete_delay = (count == 8'hf0); +assign real_complete = complete_delay || complete; + +always @(posedge div_clk) begin + if (reset) begin + div_signed_buffer <= 1'b0; + x_31_buffer <= 1'b0; + y_31_buffer <= 1'b0; + end + else if (div) begin + div_signed_buffer <= div_signed; //when div inst go to ms, div_signed will be changed. so buffer it. + x_31_buffer <= x[31]; + y_31_buffer <= y[31]; + end +end + +assign real_div_signed = real_complete ? div_signed_buffer : div_signed; +assign real_x_31 = real_complete ? x_31_buffer : x[31]; +assign real_y_31 = real_complete ? y_31_buffer : y[31]; + +assign UnsignX = {1'b0, (real_div_signed ? (x[31] ? (~x + 32'b1) : x) : x)}; //取绝对值并扩展至33位 +assign UnsignY = {1'b0, (real_div_signed ? (y[31] ? (~y + 32'b1) : y) : y)}; + +always @(posedge div_clk) begin //33位除法计算 + if (reset) begin + count <= 8'd32; + tmp_r <= 33'b0; + UnsignS <= 33'b0; + UnsignR <= 33'b0; + end + else if (~div || complete_delay) begin + count <= 8'd32; //计算33次 + tmp_r <= 33'b0; + end + else if (~(count[7])) begin + if (tmp_d[32]) begin //tmp_d为负数 + UnsignS <= {UnsignS[31:0], 1'b0}; + tmp_r <= result_r; + end + else begin + UnsignS <= {UnsignS[31:0], 1'b1}; + tmp_r <= tmp_d; + end + count <= count - 8'd1; + end + else begin + UnsignR <= tmp_r; + count <= 8'hf0; //complete signal only maintain one clock + end + +end + +assign complete = (count == 8'hff);//chenji + +assign result_r = {tmp_r[31:0], UnsignX[count]}; +assign tmp_d = result_r - UnsignY; + +wire [32:0] TmpS, TmpR; +assign TmpS = (real_div_signed ? ((real_x_31 == real_y_31) ? UnsignS : ~(UnsignS - 1)) : UnsignS); //去绝对值并截位 +assign TmpR = (real_div_signed ? (real_x_31 ? ~(UnsignR - 1) : UnsignR) : UnsignR); + +assign s = TmpS[31:0]; +assign r = TmpR[31:0]; + +endmodule + +//表达式的符号关系 +//x[31] y[31] s[31] r[31] +// 0 0 0 0 +// 0 1 1 0 +// 1 0 1 1 +// 1 1 0 1 diff --git a/rtl/ip/open-la500/doc/lacc接口.md b/rtl/ip/open-la500/doc/lacc接口.md new file mode 100644 index 0000000..81e9cab --- /dev/null +++ b/rtl/ip/open-la500/doc/lacc接口.md @@ -0,0 +1,135 @@ +# LaCC 接口 + +LaCC(Loongarch32R Custom Coprocessor Interface) 接口是 Open-LA500 用于扩展自定义指令的接口。 + +# 指令格式 + +![](./picture/lacc_inst.png) + +| 域 | 描述 | +| ------ | --------------------------------------------------- | +| opcode | 固定为1100,用于确定当前指令 | +| command| 用于编码多个自定义指令，将发送至lacc接口 | +| imm | 额外的立即数 | +| rj | 第一个寄存器的编码 | +| rk | 第二个寄存器的编码 | +| rd | 目的寄存器编码，当目的寄存器不为0时会写回寄存器堆中 | + +# 接口定义 + +> 方向为协处理器视角 + +| 通道 | 方向 | 宽度 | 信号名 | 描述 | +| -------- | ------ | ------------- | --------------- | ------------------------------------------------------------ | +| 全局 | input | 1 | lacc_flush | 当处理器触发异常或分支预测失败时将该信号置位 | +| 请求 | input | 1 | lacc_req_valid | 处理器核发送请求 | +| 请求 | input | LACC_OP_WIDTH | lacc_req_command| 指令中的command域 | +| 请求 | input | 7 | lacc_req_imm | 指令中的imm域 | +| 请求 | input | 32 | lacc_req_rj | 第一个寄存器的值 | +| 请求 | input | 32 | lacc_req_rk | 第二个寄存器的值 | +| 回复 | output | 1 | lacc_rsp_valid | 指令完成信号，处理器将继续执行 | +| 回复 | output | 32 | lacc_rsp_rdat | 写回寄存器的数据 | +| 访存请求 | output | 1 | lacc_data_valid | 向dcache发送的访存请求信号 | +| 访存请求 | input | 1 | lacc_data_ready | dcache当前是否可以接受请求 | +| 访存请求 | output | 32 | lacc_data_addr | 访存地址 | +| 访存请求 | output | 1 | lacc_data_read | 是否为读请求 | +| 访存请求 | output | 32 | lacc_data_wdata | 写入数据 | +| 访存请求 | output | 2 | lacc_data_size | 访存数据大小
    2'b00: byte
    2'b01: half
    2'b10: word | +| 访存回复 | input | 1 | lacc_drsp_valid | dcache发送的回复信号
    写请求将会在第二周期接收到该回复
    读请求将会在dcache成功后接收 | +| 访存回复 | input | 32 | lacc_drsp_data | 访存得到的数据 | + +# 运行流程 + +1. 在解码阶段解析 lacc 指令，并将 op 和 imm 发送给执行阶段 +2. 在执行阶段`lacc_req_valid`为1，lacc接口将接受 lacc 指令并暂停，直到`lacc_rsp_valid`为高才会将指令发送给下一级 +3. 如果需要访存，可以将 `lacc_data_valid` 置高并设置访存地址及大小等信息。当`lacc_data_valid`和`lacc_data_ready`同时为高则当前请求成功发送至dcache。 +4. 当指令执行完成之后将`lacc_rsp_valid`置高，指令将从 exe 级继续执行 + + + +lacc读请求时序,读取地址为0x1C0FFF38，读取数据为0x00000000 + +![](./picture/lacc_read.png) + +lacc写请求时序，写入地址为0x1C0FFEE8,写入数据为0x70A3A52B + +![](./picture/lacc_write.png) + +# 自定义指令 + +添加自定义指令只需两步： + +1. 修改`mycpu.h`中的`LACC_OP_SIZE`为自定义指令数量（若`LACC_OP_SIZE`为1需要修改`LACC_OP_WIDTH`为1），并且取消`HAS_LACC`的注释 +2. 在`lacc_core.v`中删除示例`lacc_demo`，写入自定指令代码 + +# demo + +demo实现了从两个地址载入向量，点乘之后再存入缓存中的功能，代码位于`lacc_demo.v`中。 + +## 指令 + +| 指令 | op | rj | rk | 描述 | +| -------- | ---- | ----- | ----- | ----------------------------------------------- | +| op_cfg | 1 | size | waddr | 设置写回地址及向量长度 | +| op_lmadd | 0 | addr1 | addr2 | 设置需要计算的两个内存地址，对位相加再存入waddr | + +## 状态机 + +| 状态 | 说明 | 转换条件 | 下一状态 | +| --------- | --------------- | ----------------------------------------- | --------- | +| IDLE | | lacc_req_valid & op_lmadd | REQ_ADDR1 | +| REQ_ADDR1 | 访问addr1的数据 | data_hsk(访问addr1数据) | REQ_ADDR2 | +| REQ_ADDR2 | 访问addr2的数据 | data_hsk(访问addr2数据) | FINAL | +| FINAL | 计算结果并写回 | data_hsk & req_size_nz(写入数据且size!=0) | REQ_ADDR1 | +| FINAL | | data_hsk & ~req_size_nz | IDLE | + +data_hsk即`lacc_data_valid & lacc_data_ready`，表明当前访存请求发送成功。 + +**数据控制** + +使用buffer_valid信号表示第一个地址的数据是否被接收。wdata_valid表示写回数据准备完成 + +当`buffer_valid & lacc_drsp_valid`为高时说明第二个地址的数据已经返回，在该周期计算`buffer_data+lacc_drsp_rdata`并写入wdata + +# 修改编译器 + +我们可以使用".word xxxxxxx"的格式在汇编中添加自定义指令。但是这种方式阅读不够友好，并且不利于操作数读写，例如 + +```c + asm volatile ( + "move $r5, %[addr]\n\t" + "move $r6, %[para]\n\t" + ".word 0xc00018a0\n\t" + ::[addr]"r"(addr),[para]"r"(para) + :"$r5", "$r6" + ); +``` + +**修改编译器** + +我们可以修改binutils使得编译器可以识别自定义指令。 + +- 下载loongarch toolchain: https://gitee.com/loongson-edu/la32r-toolchains/tree/master +- 进入src/la32r_binutils/opcodes,打开loongarch-opc.c,在`loongarch_fix_opcodes`结构体中添加 +```c +{0xc0000000, 0xf0000000, "lacc", "u22:6,r0:5,r5:5,r10:5,u15:7", 0, 0, 0, 0} +``` +- 根据toolchina的README编译，并将bin目录添加到path中 + + + +自定义指令的格式为: + +``` +lacc command, rd, rj, rk, imm +``` + +上例可以修改为： + +```c + asm volatile ( + "lacc 0x0, $r0, %[addr], %[para], 0x0\n\t" + ::[addr]"r"(addr), [para]"r"(para) + ); +``` + diff --git a/rtl/ip/open-la500/doc/picture/lacc_inst.png b/rtl/ip/open-la500/doc/picture/lacc_inst.png new file mode 100644 index 0000000000000000000000000000000000000000..2a95ed04083847b2a4723fb244134957f6755d72 GIT binary patch literal 2925 zcmd6pdo&a78^DJ$Hn+?WGe%KFE@_*PTw0|NHOkzJNW(-FxkQpk7gQ!vxz-SkxlV4& z_3O^&KCN8lmP^g7AD#0%=lAdTzu!O4`#kS?Zs)wu`MgiOjTJ@|BnJWj0HUW)ncD&Y ze1vUXUr2CU;>29Nw-3HRTZ}1y)Crpb0KjUe%}-niab`OmzXr9I7%R(ml?V4S9AYA4 zPnv7)65X{6YF_W)U3}Wjr0k!Q39gV6jZ$ZnKv9u`ANK8YcvoT@^IZMfTcwjdwTh)& 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