Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
This commit is contained in:
396
sim/matmul_flow_tb.v
Normal file
396
sim/matmul_flow_tb.v
Normal file
@@ -0,0 +1,396 @@
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`timescale 1ns / 1ps
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`include "config.h"
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`define UART_PSEL u_soc_top.u_axi_uart_controller.uart0.PSEL
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`define UART_PENABLE u_soc_top.u_axi_uart_controller.uart0.PENABLE
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`define UART_PWRITE u_soc_top.u_axi_uart_controller.uart0.PWRITE
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`define UART_WADDR u_soc_top.u_axi_uart_controller.uart0.PADDR[7:0]
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`define UART_WDATA u_soc_top.u_axi_uart_controller.uart0.PWDATA[7:0]
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module tb_matmul_flow;
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localparam EXTRAM_WORDS = 1048576;
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localparam DONE_LEN = 11;
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localparam PC_CALL_MAIN = 32'h1c0001bc;
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localparam PC_MAIN_ENTRY = 32'h1c000240;
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localparam PC_MATMUL_INIT = 32'h1c000274;
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localparam PC_MATMUL_LOAD_LOOP = 32'h1c0002f0;
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localparam PC_MATMUL_WAIT = 32'h1c00045c;
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localparam PC_MATMUL_STORE = 32'h1c000480;
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localparam PC_DONE_PRINTF = 32'h1c0004a8;
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reg reset;
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reg clk;
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reg [3:0] touch_btn;
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reg [31:0] dip_sw;
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wire UART_RX;
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wire UART_TX;
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wire [2:0] video_red;
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wire [2:0] video_green;
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wire [1:0] video_blue;
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wire video_hsync;
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wire video_vsync;
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wire video_clk;
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wire video_de;
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wire [15:0] leds;
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wire [7:0] dpy0;
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wire [7:0] dpy1;
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wire [19:0] base_ram_addr;
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wire [3:0] base_ram_be_n;
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wire base_ram_ce_n;
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wire base_ram_oe_n;
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wire base_ram_we_n;
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wire [19:0] ext_ram_addr;
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wire [3:0] ext_ram_be_n;
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wire ext_ram_ce_n;
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wire ext_ram_oe_n;
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wire ext_ram_we_n;
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wire [31:0] base_ram_data;
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wire [31:0] ext_ram_data;
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reg [31:0] expected_mem [0:EXTRAM_WORDS-1];
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reg [8*256-1:0] input_hex;
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reg [8*256-1:0] expected_hex;
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reg [31:0] group_num;
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reg [31:0] timeout_cycles;
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reg [31:0] progress_cycles;
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reg [31:0] uart_shift [0:DONE_LEN-1];
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reg done_seen;
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integer i;
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integer err_count;
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integer check_words;
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integer timeout_count;
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integer uart_count;
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integer matmul_write_rsp_count;
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integer matmul_read_rsp_count;
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integer ram_read_rsp_count;
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integer cpu_read_req_count;
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integer cpu_write_rsp_count;
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reg [31:0] last_debug_pc;
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reg [31:0] same_pc_cycles;
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reg main_seen;
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reg matmul_access_seen;
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reg done_printf_seen;
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reg [8*32-1:0] phase_text;
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initial begin
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clk = 1'b0;
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forever #10 clk = ~clk;
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end
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initial begin
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input_hex = "../../../../../../tools/matmul_testdata/extram_input_4mb.hex";
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expected_hex = "../../../../../../tools/matmul_testdata/extram_expected_4mb.hex";
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group_num = 32'd10;
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timeout_cycles = 32'd5000000;
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progress_cycles = 32'd500000;
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if (!$value$plusargs("INPUT_HEX=%s", input_hex)) begin
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end
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if (!$value$plusargs("EXPECTED_HEX=%s", expected_hex)) begin
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end
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if (!$value$plusargs("GROUPS=%d", group_num)) begin
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end
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if (!$value$plusargs("TIMEOUT_CYCLES=%d", timeout_cycles)) begin
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end
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if (!$value$plusargs("PROGRESS_CYCLES=%d", progress_cycles)) begin
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end
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reset = 1'b1;
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touch_btn = 4'h0;
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dip_sw = 32'h0000_abcd;
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done_seen = 1'b0;
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timeout_count = 0;
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uart_count = 0;
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matmul_write_rsp_count = 0;
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matmul_read_rsp_count = 0;
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ram_read_rsp_count = 0;
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cpu_read_req_count = 0;
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cpu_write_rsp_count = 0;
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last_debug_pc = 32'b0;
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same_pc_cycles = 32'b0;
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main_seen = 1'b0;
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matmul_access_seen = 1'b0;
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done_printf_seen = 1'b0;
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for (i = 0; i < DONE_LEN; i = i + 1) begin
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uart_shift[i] = 32'b0;
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end
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$display("[MATMUL_TB] load ExtRAM input: %0s", input_hex);
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$display("[MATMUL_TB] load expected image: %0s", expected_hex);
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$display("[MATMUL_TB] groups: %0d", group_num);
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$readmemh(input_hex, ext_sram_sp.BRAM);
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$readmemh(expected_hex, expected_mem);
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#2000;
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$display("[MATMUL_TB] release reset and start timing");
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reset = 1'b0;
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end
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always @(posedge clk) begin
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if (!reset && !done_seen) begin
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timeout_count <= timeout_count + 1;
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if (u_soc_top.debug_wb_pc == last_debug_pc) begin
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same_pc_cycles <= same_pc_cycles + 1;
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end else begin
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last_debug_pc <= u_soc_top.debug_wb_pc;
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same_pc_cycles <= 32'b0;
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end
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if (u_soc_top.cpu_arvalid && u_soc_top.cpu_arready) begin
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cpu_read_req_count <= cpu_read_req_count + 1;
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end
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if (u_soc_top.cpu_bvalid && u_soc_top.cpu_bready) begin
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cpu_write_rsp_count <= cpu_write_rsp_count + 1;
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end
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if (u_soc_top.ram_rvalid && u_soc_top.ram_rready) begin
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ram_read_rsp_count <= ram_read_rsp_count + 1;
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end
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if (u_soc_top.axiOut_7_bvalid && u_soc_top.axiOut_7_bready) begin
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matmul_write_rsp_count <= matmul_write_rsp_count + 1;
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matmul_access_seen <= 1'b1;
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end
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if (u_soc_top.axiOut_7_rvalid && u_soc_top.axiOut_7_rready) begin
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matmul_read_rsp_count <= matmul_read_rsp_count + 1;
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matmul_access_seen <= 1'b1;
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end
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if (!main_seen && (u_soc_top.debug_wb_pc >= PC_MAIN_ENTRY)) begin
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main_seen <= 1'b1;
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$display("[MATMUL_TB] stage: entered main at cycles=%0d pc=%08x inst=%08x",
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timeout_count, u_soc_top.debug_wb_pc, u_soc_top.debug_wb_inst);
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end
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if (!done_printf_seen && (u_soc_top.debug_wb_pc >= PC_DONE_PRINTF) &&
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(u_soc_top.debug_wb_pc < 32'h1c000780)) begin
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done_printf_seen <= 1'b1;
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$display("[MATMUL_TB] stage: software reached MATMUL_DONE printf path at cycles=%0d pc=%08x",
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timeout_count, u_soc_top.debug_wb_pc);
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end
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if ((progress_cycles != 0) && (timeout_count != 0) &&
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((timeout_count % progress_cycles) == 0)) begin
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print_progress;
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end
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if (timeout_count >= timeout_cycles) begin
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$display("");
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$display("[MATMUL_TB] TIMEOUT: MATMUL_DONE was not printed");
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$display("[MATMUL_TB] debug_wb_pc = %08x", u_soc_top.debug_wb_pc);
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print_progress;
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$display("[MATMUL_TB] matmul busy=%0d done=%0d error=%0d",
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u_soc_top.u_matmul_axi_slave.busy,
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u_soc_top.u_matmul_axi_slave.done,
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u_soc_top.u_matmul_axi_slave.error);
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$finish;
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end
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end
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end
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soc_top #(.SIMULATION(1'b1)) u_soc_top (
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.clk (clk),
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.reset (reset),
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.touch_btn (touch_btn),
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.dip_sw (dip_sw),
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.video_red (video_red),
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.video_green (video_green),
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.video_blue (video_blue),
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.video_hsync (video_hsync),
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.video_vsync (video_vsync),
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.video_clk (video_clk),
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.video_de (video_de),
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.leds (leds),
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.dpy0 (dpy0),
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.dpy1 (dpy1),
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.base_ram_addr (base_ram_addr),
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.base_ram_be_n (base_ram_be_n),
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.base_ram_ce_n (base_ram_ce_n),
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.base_ram_oe_n (base_ram_oe_n),
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.base_ram_we_n (base_ram_we_n),
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.ext_ram_addr (ext_ram_addr),
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.ext_ram_be_n (ext_ram_be_n),
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.ext_ram_ce_n (ext_ram_ce_n),
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.ext_ram_oe_n (ext_ram_oe_n),
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.ext_ram_we_n (ext_ram_we_n),
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.base_ram_data (base_ram_data),
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.ext_ram_data (ext_ram_data),
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.UART_RX (UART_RX),
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.UART_TX (UART_TX)
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);
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sram_sp #(
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.AW(20),
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.Init_File(`SRAM_Init_File)
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) base_sram_sp (
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.ram_addr (base_ram_addr),
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.ram_be_n (base_ram_be_n),
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.ram_ce_n (base_ram_ce_n),
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.ram_oe_n (base_ram_oe_n),
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.ram_we_n (base_ram_we_n),
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.ram_data (base_ram_data)
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);
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sram_sp #(
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.AW(20),
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.Init_File("none")
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) ext_sram_sp (
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.ram_addr (ext_ram_addr),
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.ram_be_n (ext_ram_be_n),
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.ram_ce_n (ext_ram_ce_n),
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.ram_oe_n (ext_ram_oe_n),
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.ram_we_n (ext_ram_we_n),
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.ram_data (ext_ram_data)
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);
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wire uart_wen;
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wire uart_display;
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wire [7:0] uart_data;
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assign uart_wen = (`UART_PSEL == 1'b1) && (`UART_PENABLE == 1'b1) && (`UART_PWRITE == 1'b1);
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assign uart_display = uart_wen && (`UART_WADDR == 8'h0);
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assign uart_data = `UART_WDATA;
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always @(posedge clk) begin
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if (uart_display) begin
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uart_count <= uart_count + 1;
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$write("%c", uart_data);
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for (i = 0; i < DONE_LEN-1; i = i + 1) begin
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uart_shift[i] <= uart_shift[i+1];
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end
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uart_shift[DONE_LEN-1] <= {24'b0, uart_data};
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if ((uart_shift[1][7:0] == "M") &&
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(uart_shift[2][7:0] == "A") &&
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(uart_shift[3][7:0] == "T") &&
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(uart_shift[4][7:0] == "M") &&
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(uart_shift[5][7:0] == "U") &&
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(uart_shift[6][7:0] == "L") &&
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(uart_shift[7][7:0] == "_") &&
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(uart_shift[8][7:0] == "D") &&
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(uart_shift[9][7:0] == "O") &&
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(uart_shift[10][7:0] == "N") &&
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(uart_data == "E")) begin
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done_seen <= 1'b1;
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check_result;
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end
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end
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end
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task update_phase_text;
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begin
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if (u_soc_top.debug_wb_pc == PC_CALL_MAIN) begin
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if (same_pc_cycles >= progress_cycles) begin
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phase_text = "STUCK_AT_CALL_MAIN";
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end else begin
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phase_text = "BOOT_CALL_MAIN";
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end
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end else if (u_soc_top.debug_wb_pc < PC_MAIN_ENTRY) begin
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phase_text = "BOOT";
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end else if (u_soc_top.debug_wb_pc < PC_MATMUL_INIT) begin
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phase_text = "MAIN_PROLOGUE";
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end else if (u_soc_top.debug_wb_pc < PC_MATMUL_LOAD_LOOP) begin
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phase_text = "MATMUL_REG_INIT";
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end else if (u_soc_top.debug_wb_pc < PC_MATMUL_WAIT) begin
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phase_text = "LOAD_A_B_START_HW";
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end else if (u_soc_top.debug_wb_pc < PC_MATMUL_STORE) begin
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phase_text = "POLL_MATMUL_DONE";
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end else if (u_soc_top.debug_wb_pc < PC_DONE_PRINTF) begin
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phase_text = "STORE_RESULTS";
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end else if (u_soc_top.debug_wb_pc < 32'h1c000780) begin
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phase_text = "PRINT_DONE";
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end else begin
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phase_text = "LIB_OR_TRAP";
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end
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end
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endtask
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task print_progress;
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begin
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update_phase_text;
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$display("[MATMUL_TB] progress cycles=%0d phase=%0s pc=%08x inst=%08x same_pc_cycles=%0d uart_bytes=%0d",
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timeout_count, phase_text, u_soc_top.debug_wb_pc,
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u_soc_top.debug_wb_inst, same_pc_cycles, uart_count);
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$display("[MATMUL_TB] bus cpu_ar=%0d/%0d addr=%08x cpu_aw=%0d/%0d addr=%08x cpu_w=%0d/%0d cpu_b=%0d/%0d cpu_reads=%0d cpu_write_rsps=%0d ram_r_rsps=%0d",
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u_soc_top.cpu_arvalid, u_soc_top.cpu_arready, u_soc_top.cpu_araddr,
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u_soc_top.cpu_awvalid, u_soc_top.cpu_awready, u_soc_top.cpu_awaddr,
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u_soc_top.cpu_wvalid, u_soc_top.cpu_wready,
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u_soc_top.cpu_bvalid, u_soc_top.cpu_bready,
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cpu_read_req_count, cpu_write_rsp_count, ram_read_rsp_count);
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$display("[MATMUL_TB] cpu_bridge ws_valid=%0d inst_req=%0d/%0d inst_addr=%08x inst_ret=%0d data_wr=%0d/%0d data_wr_addr=%08x write_state=%0d write_wait=%0d read_state=%0d b=%0d/%0d",
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u_soc_top.u_cpu.ws_valid,
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u_soc_top.u_cpu.inst_rd_req,
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u_soc_top.u_cpu.inst_rd_rdy,
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u_soc_top.u_cpu.inst_rd_addr,
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u_soc_top.u_cpu.inst_ret_valid,
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u_soc_top.u_cpu.data_wr_req,
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u_soc_top.u_cpu.data_wr_rdy,
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u_soc_top.u_cpu.data_wr_addr,
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u_soc_top.u_cpu.axi_bridge.write_requst_state,
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u_soc_top.u_cpu.axi_bridge.write_wait_enable,
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u_soc_top.u_cpu.axi_bridge.read_requst_state,
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u_soc_top.u_cpu.bvalid,
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u_soc_top.u_cpu.bready);
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$display("[MATMUL_TB] uart_axi aw=%0d/%0d addr=%08x w=%0d/%0d strb=%x data=%08x b=%0d/%0d sel_wr=%0d apb_psel=%0d penable=%0d pwrite=%0d paddr=%02x",
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u_soc_top.u_axi_uart_controller.axi_s_awvalid,
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u_soc_top.u_axi_uart_controller.axi_s_awready,
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u_soc_top.u_axi_uart_controller.axi_s_awaddr,
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u_soc_top.u_axi_uart_controller.axi_s_wvalid,
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u_soc_top.u_axi_uart_controller.axi_s_wready,
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u_soc_top.u_axi_uart_controller.axi_s_wstrb,
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u_soc_top.u_axi_uart_controller.axi_s_wdata,
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u_soc_top.u_axi_uart_controller.axi_s_bvalid,
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u_soc_top.u_axi_uart_controller.axi_s_bready,
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u_soc_top.u_axi_uart_controller.AA_axi2apb_bridge_cpu.axi_s_sel_wr,
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u_soc_top.u_axi_uart_controller.uart0.PSEL,
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u_soc_top.u_axi_uart_controller.uart0.PENABLE,
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u_soc_top.u_axi_uart_controller.uart0.PWRITE,
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u_soc_top.u_axi_uart_controller.uart0.PADDR);
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$display("[MATMUL_TB] matmul busy=%0d done=%0d error=%0d access_seen=%0d write_rsps=%0d read_rsps=%0d axi7_aw=%0d/%0d addr=%08x axi7_w=%0d/%0d axi7_b=%0d/%0d axi7_ar=%0d/%0d addr=%08x axi7_r=%0d/%0d",
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||||
u_soc_top.u_matmul_axi_slave.busy,
|
||||
u_soc_top.u_matmul_axi_slave.done,
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u_soc_top.u_matmul_axi_slave.error,
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matmul_access_seen,
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||||
matmul_write_rsp_count,
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||||
matmul_read_rsp_count,
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u_soc_top.axiOut_7_awvalid,
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||||
u_soc_top.axiOut_7_awready,
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u_soc_top.axiOut_7_awaddr,
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u_soc_top.axiOut_7_wvalid,
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||||
u_soc_top.axiOut_7_wready,
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||||
u_soc_top.axiOut_7_bvalid,
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||||
u_soc_top.axiOut_7_bready,
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||||
u_soc_top.axiOut_7_arvalid,
|
||||
u_soc_top.axiOut_7_arready,
|
||||
u_soc_top.axiOut_7_araddr,
|
||||
u_soc_top.axiOut_7_rvalid,
|
||||
u_soc_top.axiOut_7_rready);
|
||||
end
|
||||
endtask
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||||
|
||||
task check_result;
|
||||
begin
|
||||
$display("");
|
||||
$display("[MATMUL_TB] MATMUL_DONE captured after %0d clk cycles", timeout_count);
|
||||
|
||||
err_count = 0;
|
||||
check_words = group_num * 80;
|
||||
for (i = 0; i < check_words; i = i + 1) begin
|
||||
if (ext_sram_sp.BRAM[i] !== expected_mem[i]) begin
|
||||
if (err_count < 16) begin
|
||||
$display("[MATMUL_TB] mismatch word[%0d]: got=%08x expected=%08x",
|
||||
i, ext_sram_sp.BRAM[i], expected_mem[i]);
|
||||
end
|
||||
err_count = err_count + 1;
|
||||
end
|
||||
end
|
||||
|
||||
if (err_count == 0) begin
|
||||
$display("[MATMUL_TB] PASS: source and result regions match expected image");
|
||||
end else begin
|
||||
$display("[MATMUL_TB] FAIL: %0d mismatched words", err_count);
|
||||
end
|
||||
$finish;
|
||||
end
|
||||
endtask
|
||||
|
||||
endmodule
|
||||
230
sim/mycpu_tb.v
Normal file
230
sim/mycpu_tb.v
Normal file
@@ -0,0 +1,230 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
`timescale 1ns / 1ps
|
||||
`include "config.h"
|
||||
// `define FFT_OUTPUT_TXT
|
||||
|
||||
`define UART_PSEL u_soc_top.u_axi_uart_controller.uart0.PSEL
|
||||
`define UART_PENBLE u_soc_top.u_axi_uart_controller.uart0.PENABLE
|
||||
`define UART_PWRITE u_soc_top.u_axi_uart_controller.uart0.PWRITE
|
||||
`define UART_WADDR u_soc_top.u_axi_uart_controller.uart0.PADDR[7:0]
|
||||
`define UART_WDATA u_soc_top.u_axi_uart_controller.uart0.PWDATA[7:0]
|
||||
`define END_PC 32'h1c000200
|
||||
|
||||
module tb_top( );
|
||||
reg reset;
|
||||
reg clk;
|
||||
reg [3:0] touch_btn;
|
||||
reg [31:0] dip_sw;
|
||||
|
||||
wire UART_RX;
|
||||
wire UART_TX;
|
||||
wire [2:0] video_red;
|
||||
wire [2:0] video_green;
|
||||
wire [1:0] video_blue;
|
||||
wire video_hsync;
|
||||
wire video_vsync;
|
||||
wire video_clk;
|
||||
wire video_de;
|
||||
wire [15:0] leds;
|
||||
wire [7:0] dpy0;
|
||||
wire [7:0] dpy1;
|
||||
wire [19:0] base_ram_addr;
|
||||
wire [ 3:0] base_ram_be_n;
|
||||
wire base_ram_ce_n;
|
||||
wire base_ram_oe_n;
|
||||
wire base_ram_we_n;
|
||||
wire [19:0] ext_ram_addr;
|
||||
wire [ 3:0] ext_ram_be_n;
|
||||
wire ext_ram_ce_n;
|
||||
wire ext_ram_oe_n;
|
||||
wire ext_ram_we_n;
|
||||
wire [31:0] base_ram_data;
|
||||
wire [31:0] ext_ram_data;
|
||||
|
||||
//产生时钟与复位信号
|
||||
initial begin
|
||||
clk = 1'b0;
|
||||
reset = 1'b1;
|
||||
dip_sw = 32'h0;
|
||||
#2000;
|
||||
reset = 1'b0;
|
||||
end
|
||||
always #10 clk=~clk;
|
||||
|
||||
//产生按键信号
|
||||
initial begin
|
||||
touch_btn = 4'h0;
|
||||
dip_sw = 32'h0000_abcd;
|
||||
|
||||
#3000000;
|
||||
|
||||
#100000
|
||||
touch_btn = 4'b0001;
|
||||
#50
|
||||
touch_btn = 4'b0000;
|
||||
|
||||
#100000
|
||||
touch_btn = 4'b0010;
|
||||
#50
|
||||
touch_btn = 4'b0000;
|
||||
|
||||
#100000
|
||||
touch_btn = 4'b0100;
|
||||
#50
|
||||
touch_btn = 4'b0000;
|
||||
|
||||
#100000
|
||||
touch_btn = 4'b1000;
|
||||
#50
|
||||
touch_btn = 4'b0000;
|
||||
|
||||
end
|
||||
|
||||
soc_top #(.SIMULATION(1'b1)) u_soc_top (
|
||||
.clk ( clk ),
|
||||
.reset ( reset ),
|
||||
.touch_btn ( touch_btn ),
|
||||
.dip_sw ( dip_sw ),
|
||||
|
||||
.video_red ( video_red ),
|
||||
.video_green ( video_green ),
|
||||
.video_blue ( video_blue ),
|
||||
.video_hsync ( video_hsync ),
|
||||
.video_vsync ( video_vsync ),
|
||||
.video_clk ( video_clk ),
|
||||
.video_de ( video_de ),
|
||||
.leds ( leds ),
|
||||
.dpy0 ( dpy0 ),
|
||||
.dpy1 ( dpy1 ),
|
||||
|
||||
.base_ram_addr ( base_ram_addr ),
|
||||
.base_ram_be_n ( base_ram_be_n ),
|
||||
.base_ram_ce_n ( base_ram_ce_n ),
|
||||
.base_ram_oe_n ( base_ram_oe_n ),
|
||||
.base_ram_we_n ( base_ram_we_n ),
|
||||
.ext_ram_addr ( ext_ram_addr ),
|
||||
.ext_ram_be_n ( ext_ram_be_n ),
|
||||
.ext_ram_ce_n ( ext_ram_ce_n ),
|
||||
.ext_ram_oe_n ( ext_ram_oe_n ),
|
||||
.ext_ram_we_n ( ext_ram_we_n ),
|
||||
|
||||
.base_ram_data ( base_ram_data ),
|
||||
.ext_ram_data ( ext_ram_data ),
|
||||
|
||||
.UART_RX ( UART_RX ),
|
||||
.UART_TX ( UART_TX )
|
||||
);
|
||||
|
||||
sram_sp #(
|
||||
.AW ( 18 ),
|
||||
.Init_File(`SRAM_Init_File))
|
||||
base_sram_sp (
|
||||
.ram_addr ( base_ram_addr ),
|
||||
.ram_be_n ( base_ram_be_n ),
|
||||
.ram_ce_n ( base_ram_ce_n ),
|
||||
.ram_oe_n ( base_ram_oe_n ),
|
||||
.ram_we_n ( base_ram_we_n ),
|
||||
|
||||
.ram_data ( base_ram_data )
|
||||
);
|
||||
|
||||
sram_sp #(
|
||||
.AW ( 18 ),
|
||||
.Init_File(`SRAM_Init_File))
|
||||
ext_sram_sp (
|
||||
.ram_addr ( ext_ram_addr ),
|
||||
.ram_be_n ( ext_ram_be_n ),
|
||||
.ram_ce_n ( ext_ram_ce_n ),
|
||||
.ram_oe_n ( ext_ram_oe_n ),
|
||||
.ram_we_n ( ext_ram_we_n ),
|
||||
|
||||
.ram_data ( ext_ram_data )
|
||||
);
|
||||
|
||||
//模拟串口打印
|
||||
wire uart_display;
|
||||
wire [7:0] uart_data;
|
||||
wire uart_wen;
|
||||
assign uart_wen = (`UART_PSEL == 1'b1) && (`UART_PENBLE == 1'b1) && (`UART_PWRITE == 1'b1);
|
||||
assign uart_display = (uart_wen == 1'b1) && (`UART_WADDR == 8'h0);
|
||||
assign uart_data = `UART_WDATA;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(uart_display)
|
||||
begin
|
||||
if(uart_data==8'hff)
|
||||
begin
|
||||
;//$finish;
|
||||
end
|
||||
else
|
||||
begin
|
||||
$write("%c",uart_data);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//仿真结束
|
||||
wire [31:0] debug_wb_pc;
|
||||
assign debug_wb_pc = u_soc_top.debug_wb_pc;
|
||||
wire test_end = debug_wb_pc==`END_PC;
|
||||
always @(posedge u_soc_top.cpu_clk)
|
||||
begin
|
||||
if (!u_soc_top.cpu_resetn) begin
|
||||
end
|
||||
else if(test_end) begin
|
||||
$display("==============================================================");
|
||||
$display("Test end!");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
//FFT测试结果输出
|
||||
`ifdef FFT_OUTPUT_TXT
|
||||
integer fft_output_re;
|
||||
integer fft_output_im;
|
||||
initial begin
|
||||
fft_output_re = $fopen("../../../../../../python/fft512_output_re.txt", "w");
|
||||
fft_output_im = $fopen("../../../../../../python/fft512_output_im.txt", "w");
|
||||
forever begin
|
||||
@(posedge u_soc_top.u_axi_fft_top.u_axi_fft_wrap.aclk);
|
||||
if(u_soc_top.u_axi_fft_top.u_axi_fft_wrap.valid_out) begin
|
||||
$fwrite(fft_output_re, "%04h\n", u_soc_top.u_axi_fft_top.u_axi_fft_wrap.y_re);
|
||||
$fwrite(fft_output_im, "%04h\n", u_soc_top.u_axi_fft_top.u_axi_fft_wrap.y_im);
|
||||
end
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
52
sim/sram.v
Normal file
52
sim/sram.v
Normal file
@@ -0,0 +1,52 @@
|
||||
`timescale 1ns/100ps
|
||||
module sram_sp #(
|
||||
parameter AW = 16,
|
||||
parameter Init_File = "none"
|
||||
)
|
||||
(
|
||||
inout [31:0] ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享
|
||||
input [19:0] ram_addr, //BaseRAM地址
|
||||
input [ 3:0] ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0
|
||||
input ram_ce_n, //BaseRAM片选，低有效
|
||||
input ram_oe_n, //BaseRAM读使能，低有效
|
||||
input ram_we_n //BaseRAM写使能，低有效
|
||||
|
||||
);
|
||||
localparam AWT = ((1<<(AW-0))-1);
|
||||
|
||||
reg [31:0] BRAM [AWT:0];
|
||||
|
||||
initial begin
|
||||
if(Init_File != "none") begin
|
||||
$readmemb(Init_File,BRAM);
|
||||
end
|
||||
end
|
||||
|
||||
reg [AW-1:0] addr_q1;
|
||||
wire [3:0] write_enable;
|
||||
|
||||
assign write_enable[3:0] = (~ram_be_n) & {4{(~ram_ce_n) & (~ram_we_n)}};
|
||||
|
||||
|
||||
always@(posedge write_enable[0]) begin
|
||||
#10;
|
||||
if(~ram_be_n[0]) BRAM[ram_addr][7:0] <= ram_data[7:0];
|
||||
end
|
||||
always@(posedge write_enable[1]) begin
|
||||
#10;
|
||||
if(~ram_be_n[1]) BRAM[ram_addr][15:8] <= ram_data[15:8];
|
||||
end
|
||||
always@(posedge write_enable[2]) begin
|
||||
#10;
|
||||
if(~ram_be_n[2]) BRAM[ram_addr][23:16] <= ram_data[23:16];
|
||||
end
|
||||
always@(posedge write_enable[3]) begin
|
||||
#10;
|
||||
if(~ram_be_n[3]) BRAM[ram_addr][31:24] <= ram_data[31:24];
|
||||
end
|
||||
|
||||
wire [31:0] RDATA = BRAM[ram_addr];
|
||||
|
||||
assign ram_data = ((~ram_ce_n) & (~ram_oe_n)) ? RDATA : 32'hzzzzzzzz;
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user