Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

sdk/software/examples/.gitignore

@@ -0,0 +1,56 @@
+# ========================================
+# Build outputs (per-project obj/ directories)
+# ========================================
+obj/
+*.o
+
+# ========================================
+# Editor / IDE
+# ========================================
+.vscode/
+.idea/
+*.swp
+*.swo
+*~
+\#*\#
+.\#*
+
+# ========================================
+# OS generated files
+# ========================================
+.DS_Store
+Thumbs.db
+desktop.ini
+
+# ========================================
+# FPGA / Vivado project files (if any leak in)
+# ========================================
+*.bit
+*.dcp
+*.jou
+*.xpr
+*.xrf
+*.bd
+*.xci
+*.xdc
+*.vcd
+*.wcfg
+*.wdb
+*.edif
+.svn/
+.Xil/
+.hw/
+.runs/
+.sim/
+.ip_user_files/
+vivado_*.log
+vivado_*.backup.jou
+Nexys4DDR/
+*.cache/
+*.gen/
+
+# ========================================
+# Misc
+# ========================================
+*.tmp
+*.log