Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
This commit is contained in:
570
rtl/ip/axi_axil_adapter/axi_axil_adapter_wr.v
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570
rtl/ip/axi_axil_adapter/axi_axil_adapter_wr.v
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/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 to AXI4-Lite adapter (write)
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*/
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module axi_axil_adapter_wr #
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(
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// Width of address bus in bits
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parameter ADDR_WIDTH = 32,
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// Width of input (slave) AXI interface data bus in bits
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parameter AXI_DATA_WIDTH = 32,
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// Width of input (slave) AXI interface wstrb (width of data bus in words)
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parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
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// Width of AXI ID signal
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parameter AXI_ID_WIDTH = 8,
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// Width of output (master) AXI lite interface data bus in bits
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parameter AXIL_DATA_WIDTH = 32,
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// Width of output (master) AXI lite interface wstrb (width of data bus in words)
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parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
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// When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
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parameter CONVERT_BURST = 1,
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// When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
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parameter CONVERT_NARROW_BURST = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI slave interface
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*/
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input wire [AXI_ID_WIDTH-1:0] s_axi_awid,
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input wire [ADDR_WIDTH-1:0] s_axi_awaddr,
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input wire [7:0] s_axi_awlen,
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input wire [2:0] s_axi_awsize,
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input wire [1:0] s_axi_awburst,
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input wire s_axi_awlock,
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input wire [3:0] s_axi_awcache,
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input wire [2:0] s_axi_awprot,
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input wire s_axi_awvalid,
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output wire s_axi_awready,
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input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata,
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input wire [AXI_STRB_WIDTH-1:0] s_axi_wstrb,
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input wire s_axi_wlast,
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input wire s_axi_wvalid,
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output wire s_axi_wready,
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output wire [AXI_ID_WIDTH-1:0] s_axi_bid,
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output wire [1:0] s_axi_bresp,
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output wire s_axi_bvalid,
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input wire s_axi_bready,
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/*
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* AXI lite master interface
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*/
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output wire [ADDR_WIDTH-1:0] m_axil_awaddr,
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output wire [2:0] m_axil_awprot,
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output wire m_axil_awvalid,
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input wire m_axil_awready,
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output wire [AXIL_DATA_WIDTH-1:0] m_axil_wdata,
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output wire [AXIL_STRB_WIDTH-1:0] m_axil_wstrb,
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output wire m_axil_wvalid,
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input wire m_axil_wready,
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input wire [1:0] m_axil_bresp,
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input wire m_axil_bvalid,
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output wire m_axil_bready
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);
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parameter AXI_ADDR_BIT_OFFSET = $clog2(AXI_STRB_WIDTH);
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parameter AXIL_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_WIDTH);
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parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
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parameter AXIL_WORD_WIDTH = AXIL_STRB_WIDTH;
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parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
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parameter AXIL_WORD_SIZE = AXIL_DATA_WIDTH/AXIL_WORD_WIDTH;
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parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
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parameter AXIL_BURST_SIZE = $clog2(AXIL_STRB_WIDTH);
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// output bus is wider
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parameter EXPAND = AXIL_STRB_WIDTH > AXI_STRB_WIDTH;
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parameter DATA_WIDTH = EXPAND ? AXIL_DATA_WIDTH : AXI_DATA_WIDTH;
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parameter STRB_WIDTH = EXPAND ? AXIL_STRB_WIDTH : AXI_STRB_WIDTH;
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// required number of segments in wider bus
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parameter SEGMENT_COUNT = EXPAND ? (AXIL_STRB_WIDTH / AXI_STRB_WIDTH) : (AXI_STRB_WIDTH / AXIL_STRB_WIDTH);
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// data width and keep width per segment
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parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT;
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parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
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// bus width assertions
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initial begin
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if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin
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$error("Error: AXI slave interface data width not evenly divisble (instance %m)");
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$finish;
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end
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if (AXIL_WORD_SIZE * AXIL_STRB_WIDTH != AXIL_DATA_WIDTH) begin
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$error("Error: AXI lite master interface data width not evenly divisble (instance %m)");
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$finish;
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end
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if (AXI_WORD_SIZE != AXIL_WORD_SIZE) begin
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$error("Error: word size mismatch (instance %m)");
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$finish;
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end
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if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin
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$error("Error: AXI slave interface word width must be even power of two (instance %m)");
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$finish;
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end
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if (2**$clog2(AXIL_WORD_WIDTH) != AXIL_WORD_WIDTH) begin
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$error("Error: AXI lite master interface word width must be even power of two (instance %m)");
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$finish;
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end
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end
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_DATA = 2'd1,
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STATE_DATA_2 = 2'd2,
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STATE_RESP = 2'd3;
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// 添加安全的位选边界，防止 ModelSim 报 Range Reversed 错误
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localparam SAFE_EXP_MSB = (AXIL_ADDR_BIT_OFFSET > AXI_ADDR_BIT_OFFSET) ? AXIL_ADDR_BIT_OFFSET - 1 : AXI_ADDR_BIT_OFFSET;
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localparam SAFE_EXP_LSB = AXI_ADDR_BIT_OFFSET;
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localparam SAFE_NAR_MSB = (AXI_ADDR_BIT_OFFSET > AXIL_ADDR_BIT_OFFSET) ? AXI_ADDR_BIT_OFFSET - 1 : AXIL_ADDR_BIT_OFFSET;
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localparam SAFE_NAR_LSB = AXIL_ADDR_BIT_OFFSET;
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reg [1:0] state_reg = STATE_IDLE, state_next;
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reg [AXI_ID_WIDTH-1:0] id_reg = {AXI_ID_WIDTH{1'b0}}, id_next;
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reg [ADDR_WIDTH-1:0] addr_reg = {ADDR_WIDTH{1'b0}}, addr_next;
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reg [DATA_WIDTH-1:0] data_reg = {DATA_WIDTH{1'b0}}, data_next;
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reg [STRB_WIDTH-1:0] strb_reg = {STRB_WIDTH{1'b0}}, strb_next;
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reg [7:0] burst_reg = 8'd0, burst_next;
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reg [2:0] burst_size_reg = 3'd0, burst_size_next;
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reg [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
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reg burst_active_reg = 1'b0, burst_active_next;
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reg convert_burst_reg = 1'b0, convert_burst_next;
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reg first_transfer_reg = 1'b0, first_transfer_next;
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reg last_segment_reg = 1'b0, last_segment_next;
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reg s_axi_awready_reg = 1'b0, s_axi_awready_next;
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reg s_axi_wready_reg = 1'b0, s_axi_wready_next;
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reg [AXI_ID_WIDTH-1:0] s_axi_bid_reg = {AXI_ID_WIDTH{1'b0}}, s_axi_bid_next;
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reg [1:0] s_axi_bresp_reg = 2'd0, s_axi_bresp_next;
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reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
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reg [ADDR_WIDTH-1:0] m_axil_awaddr_reg = {ADDR_WIDTH{1'b0}}, m_axil_awaddr_next;
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reg [2:0] m_axil_awprot_reg = 3'd0, m_axil_awprot_next;
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reg m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
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reg [AXIL_DATA_WIDTH-1:0] m_axil_wdata_reg = {AXIL_DATA_WIDTH{1'b0}}, m_axil_wdata_next;
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reg [AXIL_STRB_WIDTH-1:0] m_axil_wstrb_reg = {AXIL_STRB_WIDTH{1'b0}}, m_axil_wstrb_next;
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reg m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
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reg m_axil_bready_reg = 1'b0, m_axil_bready_next;
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assign s_axi_awready = s_axi_awready_reg;
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assign s_axi_wready = s_axi_wready_reg;
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assign s_axi_bid = s_axi_bid_reg;
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assign s_axi_bresp = s_axi_bresp_reg;
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assign s_axi_bvalid = s_axi_bvalid_reg;
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assign m_axil_awaddr = m_axil_awaddr_reg;
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//assign m_axil_awlen = m_axil_awlen_reg;
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//assign m_axil_awsize = m_axil_awsize_reg;
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//assign m_axil_awburst = m_axil_awburst_reg;
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assign m_axil_awprot = m_axil_awprot_reg;
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assign m_axil_awvalid = m_axil_awvalid_reg;
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assign m_axil_wdata = m_axil_wdata_reg;
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assign m_axil_wstrb = m_axil_wstrb_reg;
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assign m_axil_wvalid = m_axil_wvalid_reg;
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assign m_axil_bready = m_axil_bready_reg;
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integer i;
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always @* begin
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state_next = STATE_IDLE;
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id_next = id_reg;
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addr_next = addr_reg;
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data_next = data_reg;
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strb_next = strb_reg;
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burst_next = burst_reg;
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burst_size_next = burst_size_reg;
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master_burst_size_next = master_burst_size_reg;
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burst_active_next = burst_active_reg;
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convert_burst_next = convert_burst_reg;
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first_transfer_next = first_transfer_reg;
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last_segment_next = last_segment_reg;
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s_axi_awready_next = 1'b0;
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s_axi_wready_next = 1'b0;
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s_axi_bid_next = s_axi_bid_reg;
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s_axi_bresp_next = s_axi_bresp_reg;
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s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_bready;
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m_axil_awaddr_next = m_axil_awaddr_reg;
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m_axil_awprot_next = m_axil_awprot_reg;
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m_axil_awvalid_next = m_axil_awvalid_reg && !m_axil_awready;
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m_axil_wdata_next = m_axil_wdata_reg;
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m_axil_wstrb_next = m_axil_wstrb_reg;
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m_axil_wvalid_next = m_axil_wvalid_reg && !m_axil_wready;
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m_axil_bready_next = 1'b0;
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if (SEGMENT_COUNT == 1) begin
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// master output is same width; direct transfer with no splitting/merging
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case (state_reg)
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STATE_IDLE: begin
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// idle state; wait for new burst
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s_axi_awready_next = !m_axil_awvalid;
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first_transfer_next = 1'b1;
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if (s_axi_awready && s_axi_awvalid) begin
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s_axi_awready_next = 1'b0;
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id_next = s_axi_awid;
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m_axil_awaddr_next = s_axi_awaddr;
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addr_next = s_axi_awaddr;
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burst_next = s_axi_awlen;
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burst_size_next = s_axi_awsize;
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burst_active_next = 1'b1;
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m_axil_awprot_next = s_axi_awprot;
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m_axil_awvalid_next = 1'b1;
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s_axi_wready_next = !m_axil_wvalid;
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state_next = STATE_DATA;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_DATA: begin
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// data state; transfer write data
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s_axi_wready_next = !m_axil_wvalid;
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if (s_axi_wready && s_axi_wvalid) begin
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m_axil_wdata_next = s_axi_wdata;
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m_axil_wstrb_next = s_axi_wstrb;
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m_axil_wvalid_next = 1'b1;
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burst_next = burst_reg - 1;
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burst_active_next = burst_reg != 0;
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addr_next = addr_reg + (1 << burst_size_reg);
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s_axi_wready_next = 1'b0;
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m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
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state_next = STATE_RESP;
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end else begin
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state_next = STATE_DATA;
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end
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end
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STATE_RESP: begin
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// resp state; transfer write response
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m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
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if (m_axil_bready && m_axil_bvalid) begin
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m_axil_bready_next = 1'b0;
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s_axi_bid_next = id_reg;
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first_transfer_next = 1'b0;
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if (first_transfer_reg || m_axil_bresp != 0) begin
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s_axi_bresp_next = m_axil_bresp;
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end
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if (burst_active_reg) begin
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// burst on slave interface still active; start new AXI lite write
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m_axil_awaddr_next = addr_reg;
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m_axil_awvalid_next = 1'b1;
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s_axi_wready_next = !m_axil_wvalid;
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state_next = STATE_DATA;
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end else begin
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// burst on slave interface finished; return to idle
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s_axi_bvalid_next = 1'b1;
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s_axi_awready_next = !m_axil_awvalid;
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state_next = STATE_IDLE;
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end
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end else begin
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state_next = STATE_RESP;
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end
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end
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endcase
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end else if (EXPAND) begin
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// master output is wider; merge writes
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case (state_reg)
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STATE_IDLE: begin
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// idle state; wait for new burst
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s_axi_awready_next = !m_axil_awvalid;
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first_transfer_next = 1'b1;
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data_next = {DATA_WIDTH{1'b0}};
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strb_next = {STRB_WIDTH{1'b0}};
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if (s_axi_awready && s_axi_awvalid) begin
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s_axi_awready_next = 1'b0;
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id_next = s_axi_awid;
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m_axil_awaddr_next = s_axi_awaddr;
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addr_next = s_axi_awaddr;
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burst_next = s_axi_awlen;
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burst_size_next = s_axi_awsize;
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if (CONVERT_BURST && s_axi_awcache[1] && (CONVERT_NARROW_BURST || s_axi_awsize == AXI_BURST_SIZE)) begin
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// merge writes
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// require CONVERT_BURST and awcache[1] set
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convert_burst_next = 1'b1;
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master_burst_size_next = AXIL_BURST_SIZE;
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state_next = STATE_DATA_2;
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end else begin
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// output narrow burst
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convert_burst_next = 1'b0;
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master_burst_size_next = s_axi_awsize;
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state_next = STATE_DATA;
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end
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m_axil_awprot_next = s_axi_awprot;
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m_axil_awvalid_next = 1'b1;
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s_axi_wready_next = !m_axil_wvalid;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_DATA: begin
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// data state; transfer write data
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s_axi_wready_next = !m_axil_wvalid || m_axil_wready;
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if (s_axi_wready && s_axi_wvalid) begin
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m_axil_wdata_next = {(AXIL_WORD_WIDTH/AXI_WORD_WIDTH){s_axi_wdata}};
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m_axil_wstrb_next = s_axi_wstrb << (addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB] * AXI_STRB_WIDTH);
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m_axil_wvalid_next = 1'b1;
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burst_next = burst_reg - 1;
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burst_active_next = burst_reg != 0;
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addr_next = addr_reg + (1 << burst_size_reg);
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s_axi_wready_next = 1'b0;
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m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
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state_next = STATE_RESP;
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end else begin
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state_next = STATE_DATA;
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end
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end
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STATE_DATA_2: begin
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s_axi_wready_next = !m_axil_wvalid;
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if (s_axi_wready && s_axi_wvalid) begin
|
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if (CONVERT_NARROW_BURST) begin
|
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for (i = 0; i < AXI_WORD_WIDTH; i = i + 1) begin
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if (s_axi_wstrb[i]) begin
|
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data_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_DATA_WIDTH+i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE] = s_axi_wdata[i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE];
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strb_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_STRB_WIDTH+i] = 1'b1;
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end
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end
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end else begin
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||||
data_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = s_axi_wdata;
|
||||
strb_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_STRB_WIDTH +: SEGMENT_STRB_WIDTH] = s_axi_wstrb;
|
||||
end
|
||||
m_axil_wdata_next = data_next;
|
||||
m_axil_wstrb_next = strb_next;
|
||||
burst_next = burst_reg - 1;
|
||||
burst_active_next = burst_reg != 0;
|
||||
addr_next = addr_reg + (1 << burst_size_reg);
|
||||
if (burst_reg == 0 || addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
|
||||
data_next = {DATA_WIDTH{1'b0}};
|
||||
strb_next = {STRB_WIDTH{1'b0}};
|
||||
m_axil_wvalid_next = 1'b1;
|
||||
s_axi_wready_next = 1'b0;
|
||||
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
|
||||
state_next = STATE_RESP;
|
||||
end else begin
|
||||
state_next = STATE_DATA_2;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_DATA_2;
|
||||
end
|
||||
end
|
||||
STATE_RESP: begin
|
||||
// resp state; transfer write response
|
||||
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
|
||||
|
||||
if (m_axil_bready && m_axil_bvalid) begin
|
||||
m_axil_bready_next = 1'b0;
|
||||
s_axi_bid_next = id_reg;
|
||||
first_transfer_next = 1'b0;
|
||||
if (first_transfer_reg || m_axil_bresp != 0) begin
|
||||
s_axi_bresp_next = m_axil_bresp;
|
||||
end
|
||||
if (burst_active_reg) begin
|
||||
// burst on slave interface still active; start new AXI lite write
|
||||
m_axil_awaddr_next = addr_reg;
|
||||
m_axil_awvalid_next = 1'b1;
|
||||
s_axi_wready_next = !m_axil_wvalid || m_axil_wready;
|
||||
if (convert_burst_reg) begin
|
||||
state_next = STATE_DATA_2;
|
||||
end else begin
|
||||
state_next = STATE_DATA;
|
||||
end
|
||||
end else begin
|
||||
// burst on slave interface finished; return to idle
|
||||
s_axi_bvalid_next = 1'b1;
|
||||
s_axi_awready_next = !m_axil_awvalid;
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_RESP;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
// master output is narrower; split writes, and possibly split burst
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
// idle state; wait for new burst
|
||||
s_axi_awready_next = !m_axil_awvalid;
|
||||
|
||||
first_transfer_next = 1'b1;
|
||||
|
||||
if (s_axi_awready && s_axi_awvalid) begin
|
||||
s_axi_awready_next = 1'b0;
|
||||
id_next = s_axi_awid;
|
||||
m_axil_awaddr_next = s_axi_awaddr;
|
||||
addr_next = s_axi_awaddr;
|
||||
burst_next = s_axi_awlen;
|
||||
burst_size_next = s_axi_awsize;
|
||||
burst_active_next = 1'b1;
|
||||
if (s_axi_awsize > AXIL_BURST_SIZE) begin
|
||||
// need to adjust burst size
|
||||
master_burst_size_next = AXIL_BURST_SIZE;
|
||||
end else begin
|
||||
// pass through narrow (enough) burst
|
||||
master_burst_size_next = s_axi_awsize;
|
||||
end
|
||||
m_axil_awprot_next = s_axi_awprot;
|
||||
m_axil_awvalid_next = 1'b1;
|
||||
s_axi_wready_next = !m_axil_wvalid;
|
||||
state_next = STATE_DATA;
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
STATE_DATA: begin
|
||||
s_axi_wready_next = !m_axil_wvalid;
|
||||
|
||||
if (s_axi_wready && s_axi_wvalid) begin
|
||||
data_next = s_axi_wdata;
|
||||
strb_next = s_axi_wstrb;
|
||||
m_axil_wdata_next = s_axi_wdata >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_DATA_WIDTH);
|
||||
m_axil_wstrb_next = s_axi_wstrb >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_STRB_WIDTH);
|
||||
m_axil_wvalid_next = 1'b1;
|
||||
burst_next = burst_reg - 1;
|
||||
burst_active_next = burst_reg != 0;
|
||||
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
|
||||
last_segment_next = addr_next[burst_size_reg] != addr_reg[burst_size_reg];
|
||||
s_axi_wready_next = 1'b0;
|
||||
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
|
||||
state_next = STATE_RESP;
|
||||
end else begin
|
||||
state_next = STATE_DATA;
|
||||
end
|
||||
end
|
||||
STATE_DATA_2: begin
|
||||
s_axi_wready_next = 1'b0;
|
||||
|
||||
if (!m_axil_wvalid || m_axil_wready) begin
|
||||
m_axil_wdata_next = data_reg >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_DATA_WIDTH);
|
||||
m_axil_wstrb_next = strb_reg >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_STRB_WIDTH);
|
||||
m_axil_wvalid_next = 1'b1;
|
||||
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
|
||||
last_segment_next = addr_next[burst_size_reg] != addr_reg[burst_size_reg];
|
||||
s_axi_wready_next = 1'b0;
|
||||
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
|
||||
state_next = STATE_RESP;
|
||||
end else begin
|
||||
state_next = STATE_DATA_2;
|
||||
end
|
||||
end
|
||||
STATE_RESP: begin
|
||||
// resp state; transfer write response
|
||||
m_axil_bready_next = !s_axi_bvalid && !m_axil_awvalid;
|
||||
|
||||
if (m_axil_bready && m_axil_bvalid) begin
|
||||
first_transfer_next = 1'b0;
|
||||
m_axil_awaddr_next = addr_reg;
|
||||
m_axil_bready_next = 1'b0;
|
||||
s_axi_bid_next = id_reg;
|
||||
if (first_transfer_reg || m_axil_bresp != 0) begin
|
||||
s_axi_bresp_next = m_axil_bresp;
|
||||
end
|
||||
if (burst_active_reg || !last_segment_reg) begin
|
||||
// burst on slave interface still active; start new burst
|
||||
m_axil_awvalid_next = 1'b1;
|
||||
if (last_segment_reg) begin
|
||||
s_axi_wready_next = !m_axil_wvalid;
|
||||
state_next = STATE_DATA;
|
||||
end else begin
|
||||
s_axi_wready_next = 1'b0;
|
||||
state_next = STATE_DATA_2;
|
||||
end
|
||||
end else begin
|
||||
// burst on slave interface finished; return to idle
|
||||
s_axi_bvalid_next = 1'b1;
|
||||
s_axi_awready_next = !m_axil_awvalid;
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_RESP;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
state_reg <= state_next;
|
||||
|
||||
id_reg <= id_next;
|
||||
addr_reg <= addr_next;
|
||||
data_reg <= data_next;
|
||||
strb_reg <= strb_next;
|
||||
burst_reg <= burst_next;
|
||||
burst_size_reg <= burst_size_next;
|
||||
master_burst_size_reg <= master_burst_size_next;
|
||||
burst_active_reg <= burst_active_next;
|
||||
convert_burst_reg <= convert_burst_next;
|
||||
first_transfer_reg <= first_transfer_next;
|
||||
last_segment_reg <= last_segment_next;
|
||||
|
||||
s_axi_awready_reg <= s_axi_awready_next;
|
||||
s_axi_wready_reg <= s_axi_wready_next;
|
||||
s_axi_bid_reg <= s_axi_bid_next;
|
||||
s_axi_bresp_reg <= s_axi_bresp_next;
|
||||
s_axi_bvalid_reg <= s_axi_bvalid_next;
|
||||
|
||||
m_axil_awaddr_reg <= m_axil_awaddr_next;
|
||||
m_axil_awprot_reg <= m_axil_awprot_next;
|
||||
m_axil_awvalid_reg <= m_axil_awvalid_next;
|
||||
m_axil_wdata_reg <= m_axil_wdata_next;
|
||||
m_axil_wstrb_reg <= m_axil_wstrb_next;
|
||||
m_axil_wvalid_reg <= m_axil_wvalid_next;
|
||||
m_axil_bready_reg <= m_axil_bready_next;
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
|
||||
s_axi_awready_reg <= 1'b0;
|
||||
s_axi_wready_reg <= 1'b0;
|
||||
s_axi_bvalid_reg <= 1'b0;
|
||||
|
||||
m_axil_awvalid_reg <= 1'b0;
|
||||
m_axil_wvalid_reg <= 1'b0;
|
||||
m_axil_bready_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user