Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

.gitignore

@@ -0,0 +1,53 @@
+# ========================================
+# Vivado project & IP files (not tracked)
+# ========================================
+fpga/.Xil/
+fpga/project/
+*.xpr
+*.xci
+*.xcix
+*.xdc
+*.bd
+*.dcp
+*.jou
+*.log
+*.backup.jou
+*.backup.log
+webtalk*.log
+webtalk*.jou
+*.wdb
+*.pb
+*.str
+vivado_pid*.txt
+*.bit
+
+# ========================================
+# OS generated files
+# ========================================
+.DS_Store
+.DS_Store?
+._*
+.Spotlight-V100
+.Trashes
+ehthumbs.db
+Thumbs.db
+desktop.ini
+
+# ========================================
+# Editor / IDE
+# ========================================
+.idea/
+.vscode/
+*.swp
+*.swo
+*~
+\#*\#
+.\#*
+
+# ========================================
+# Python
+# ========================================
+__pycache__/
+*.pyc
+*.pyo
+*.egg-info/