Rewrite matmul_test for CIC-IEC Stage 3 evaluation
- 5000 groups (N_GROUPS=5000), group 0 all-zero as required - MATMUL_START before computation, MATMUL_DONE after CRC - IEEE CRC32 over 960000-byte result region (little-endian words) - MATMUL_CRC32=XXXXXXXX format, 8 hex digits, no 0x prefix - Uncached ExtRAM access (0xA0000000 segment) - Removed all debug output for minimal UART traffic
This commit is contained in:
@@ -1,174 +1,196 @@
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/**
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* matmul_test - ExtRAM-based flow test for matmul_axi_slave IP
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* matmul_test - CIC-IEC 2026 Stage 3 Evaluation Program
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*
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* Reads source matrices from ExtRAM, computes C = A x B via the IP,
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* writes results back to ExtRAM. Designed to work with matmul_flow_tb.v.
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* Reads 5000 groups of 4x4 unsigned matrix multiplications from ExtRAM,
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* computes C = A x B via the hardware matmul IP, writes results back,
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* computes CRC32 over the result region, and outputs the required identifiers.
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*
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* Data layout in ExtRAM (matches testbench & generate_matmul_testdata.py):
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* SRC_BASE = 0 (word offset)
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* DST_BASE = SRC_BASE + N_GROUPS * 32
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* Group i: A_i @ SRC_BASE + i*32 + 0 (16 words)
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* B_i @ SRC_BASE + i*32 + 16 (16 words)
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* C_i @ DST_BASE + i*48 (48 words, 3 per element)
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*
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* Register map (byte offsets from MATMUL_BASE = 0x1f500000):
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* 0x000 CTRL [W] bit0=1 starts computation
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* 0x004 STATUS [R] bit2=error, bit1=done, bit0=busy
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* 0x008 SRC_BASE [R/W] unused (IP has no DMA yet)
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* 0x00c DST_BASE [R/W] unused
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* 0x010 GROUP_NUM [R/W] unused
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* 0x020 A_BASE [R/W] 16 words of matrix A (row-major)
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* 0x060 B_BASE [R/W] 16 words of matrix B (row-major)
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* 0x0a0 C_BASE [R] 48 words of result C (3 words per element)
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* Data layout:
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* Input: ExtRAM word offset 0x00000000, 5000 * 32 = 160000 words
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* Result: ExtRAM word offset 0x0009C400, 5000 * 48 = 240000 words
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* CRC32 over result region byte stream (960000 bytes, little-endian)
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*/
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#include <stdio.h>
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#include <stdint.h>
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/* ─── BSP globals (required by common.mk / picolibc) ─────────────── */
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/* ─── BSP globals ─────────────────────────────────────────────────── */
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unsigned long UART_BASE = 0xbf000000;
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unsigned long CONFREG_TIMER_BASE = 0xbf20f100;
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unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L;
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unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
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/* ─── Memory layout ──────────────────────────────────────────────── */
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/* ExtRAM physical: 0x1c400000 (bit22=1 in RAM controller).
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* Use uncached segment (0xA0000000) to bypass CPU data cache —
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* otherwise writes never reach the SRAM model before testbench checks. */
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/* ─── Memory layout ────────────────────────────────────────────────── */
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#define EXTRAM_BASE_PHYS 0x1c400000
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#define EXTRAM_BASE (0xA0000000 | (EXTRAM_BASE_PHYS & 0x1FFFFFFF))
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#define SRC_BASE 0 /* word offset — source A/B matrices */
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#define N_GROUPS 10 /* must match testbench default */
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#define DST_BASE (SRC_BASE + N_GROUPS * 32) /* result region start */
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#define SRC_BASE 0
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#define N_GROUPS 5000
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#define DST_BASE (SRC_BASE + N_GROUPS * 32) /* word offset 160000 */
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#define RESULT_WORDS (N_GROUPS * 48) /* 240000 words */
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#define RESULT_BYTES (RESULT_WORDS * 4) /* 960000 bytes */
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/* ─── MATMUL IP register map ─────────────────────────────────────── */
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/* ─── MATMUL IP registers ─────────────────────────────────────────── */
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#define MATMUL_BASE 0xbf500000
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#define MATMUL_CTRL (MATMUL_BASE + 0x000)
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#define MATMUL_STATUS (MATMUL_BASE + 0x004)
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#define MATMUL_A_BASE (MATMUL_BASE + 0x020)
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#define MATMUL_B_BASE (MATMUL_BASE + 0x060)
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#define MATMUL_C_BASE (MATMUL_BASE + 0x0a0)
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/* CTRL bits */
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#define CTRL_START 0x1
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/* STATUS bits */
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#define STATUS_BUSY 0x1
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#define STATUS_DONE 0x2
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#define STATUS_ERROR 0x4
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/* ─── Convenience macros ─────────────────────────────────────────── */
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/* ─── Convenience macros ──────────────────────────────────────────── */
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#define REG_WR(addr, val) (*(volatile uint32_t *)(addr) = (uint32_t)(val))
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#define REG_RD(addr) (*(volatile uint32_t *)(addr))
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/* ─── Read N words from IP register space ────────────────────────── */
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/* ─── CRC32 table (IEEE 802.3, polynomial 0xEDB88320) ─────────────── */
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static const uint32_t crc32_table[256] = {
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0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
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0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
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0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
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0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
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0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
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0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
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0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
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0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
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0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
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0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
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0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
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0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
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0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
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0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
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0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
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0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
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0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
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0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
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0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
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0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
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0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
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0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
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0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
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0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
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0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
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0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
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0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
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0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
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0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
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0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
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0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
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0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
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0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
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0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
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0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
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0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
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0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
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0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
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0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
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0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
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0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
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0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
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0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
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0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
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0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
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0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
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0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB30A04,
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0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
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0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
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0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
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0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
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0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
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0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
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0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
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0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
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0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
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0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
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0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
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0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
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0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
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0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
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0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
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0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
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0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
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};
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/* ─── Read N words from IP register space ─────────────────────────── */
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static void read_ip(uint32_t base, volatile uint32_t *dst, int n)
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{
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int i;
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for (i = 0; i < n; i++)
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for (int i = 0; i < n; i++)
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dst[i] = REG_RD(base + i * 4);
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}
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/* ─── Write N words to IP register space ─────────────────────────── */
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/* ─── Write N words to IP register space ──────────────────────────── */
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static void write_ip(uint32_t base, const volatile uint32_t *src, int n)
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{
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int i;
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for (i = 0; i < n; i++)
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for (int i = 0; i < n; i++)
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REG_WR(base + i * 4, src[i]);
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}
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/* ─── Wait until IP is done, return 0 on success, -1 on error ────── */
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static int wait_done(void)
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/* ─── Poll IP STATUS until done or error ──────────────────────────── */
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static void wait_done(void)
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{
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while (1) {
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uint32_t status = REG_RD(MATMUL_STATUS);
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if (status & STATUS_ERROR) {
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printf("[ERROR] matmul IP error (status=0x%08lx)\n",
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(unsigned long)status);
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return -1;
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}
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if (status & STATUS_DONE)
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return 0;
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}
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uint32_t status;
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do {
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status = REG_RD(MATMUL_STATUS);
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} while (!(status & (STATUS_DONE | STATUS_ERROR)));
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}
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/* ─── Main ────────────────────────────────────────────────────────── */
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/* ─── CRC32 over ExtRAM result region (little-endian word → byte stream) ─ */
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static uint32_t compute_crc32(volatile uint32_t *extram)
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{
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uint32_t crc = 0xFFFFFFFF;
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uint32_t i, w;
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for (i = 0; i < RESULT_WORDS; i++) {
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w = extram[DST_BASE + i];
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crc = crc32_table[(crc ^ (w & 0xFF)) & 0xFF] ^ (crc >> 8);
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crc = crc32_table[(crc ^ ((w >> 8) & 0xFF)) & 0xFF] ^ (crc >> 8);
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crc = crc32_table[(crc ^ ((w >> 16) & 0xFF)) & 0xFF] ^ (crc >> 8);
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crc = crc32_table[(crc ^ (w >> 24) ) & 0xFF] ^ (crc >> 8);
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}
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return crc ^ 0xFFFFFFFF;
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}
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/* ═══════════════════════════════════════════════════════════════════ */
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int main(void)
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{
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volatile uint32_t *extram = (volatile uint32_t *)EXTRAM_BASE;
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uint32_t a_buf[16], b_buf[16], c_buf[48];
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int g, pass = 0, fail = 0;
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uint32_t crc;
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int g, i;
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printf("\n===== MATMUL ExtRAM Flow Test =====\n");
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printf("ExtRAM base: 0x%08lx\n", (unsigned long)EXTRAM_BASE);
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printf("Groups: %d SRC_BASE=%d DST_BASE=%d\n", N_GROUPS, SRC_BASE, DST_BASE);
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printf("====================================\n");
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/* ── Start marker (must be first output) ──────────────────── */
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printf("MATMUL_START\n");
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/* ── Process all 5000 groups ──────────────────────────────── */
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for (g = 0; g < N_GROUPS; g++) {
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int i;
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printf("\n--- Group %d ---\n", g);
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/* 1. Read A[16] and B[16] from ExtRAM source region */
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/* Read A[16] + B[16] from ExtRAM */
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for (i = 0; i < 16; i++) {
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a_buf[i] = extram[SRC_BASE + g * 32 + i];
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b_buf[i] = extram[SRC_BASE + g * 32 + 16 + i];
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}
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if (g == 0) {
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printf(" A[0..3]: %08lx %08lx %08lx %08lx\n",
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(unsigned long)a_buf[0], (unsigned long)a_buf[1],
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(unsigned long)a_buf[2], (unsigned long)a_buf[3]);
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printf(" B[0..3]: %08lx %08lx %08lx %08lx\n",
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(unsigned long)b_buf[0], (unsigned long)b_buf[1],
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(unsigned long)b_buf[2], (unsigned long)b_buf[3]);
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}
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/* 2. Write A and B to IP registers */
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printf(" Loading A/B into IP...\n");
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/* Load into IP registers */
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write_ip(MATMUL_A_BASE, a_buf, 16);
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write_ip(MATMUL_B_BASE, b_buf, 16);
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/* 3. Clear stale done / error flags */
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/* Clear status flags, start computation */
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REG_WR(MATMUL_STATUS, STATUS_DONE | STATUS_ERROR);
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/* 4. Start computation */
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printf(" Starting computation...\n");
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REG_WR(MATMUL_CTRL, CTRL_START);
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/* 5. Wait for done (poll STATUS) */
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if (wait_done() != 0) {
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printf(" Group %d: FAIL (IP error)\n", g);
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fail++;
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/* zero-fill result area so testbench clearly sees failure */
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for (i = 0; i < 48; i++) c_buf[i] = 0;
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} else {
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/* 6. Read result C[48] from IP */
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read_ip(MATMUL_C_BASE, c_buf, 48);
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if (g == 0) {
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printf(" C[0..2]: %08lx %08lx %08lx\n",
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(unsigned long)c_buf[0], (unsigned long)c_buf[1],
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(unsigned long)c_buf[2]);
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printf(" C[3..5]: %08lx %08lx %08lx\n",
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(unsigned long)c_buf[3], (unsigned long)c_buf[4],
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(unsigned long)c_buf[5]);
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}
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printf(" Group %d: OK\n", g);
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pass++;
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}
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/* 7. Write result C to ExtRAM result region */
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/* Wait for hardware to finish */
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wait_done();
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/* Read C[48] from IP, write to ExtRAM result region */
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read_ip(MATMUL_C_BASE, c_buf, 48);
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for (i = 0; i < 48; i++)
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extram[DST_BASE + g * 48 + i] = c_buf[i];
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}
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/* ── Final report ─────────────────────────────────────────── */
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printf("\n============================\n");
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printf("RESULTS: %d passed, %d failed\n", pass, fail);
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printf("============================\n");
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/* ── CRC32 over result region ─────────────────────────────── */
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crc = compute_crc32(extram);
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/* Signal completion to testbench via UART */
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/* ── Final markers ────────────────────────────────────────── */
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printf("MATMUL_CRC32=%08lx\n", (unsigned long)crc);
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printf("MATMUL_DONE\n");
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return 0;
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