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18
fpga/vivado_reports/impl_cdc.rpt
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:52 2026
| Host : fedora running 64-bit unknown
| Command : report_cdc -file ./vivado_reports/impl_cdc.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
------------------------------------------------------------------------------------
CDC Report
Severity Source Clock Destination Clock CDC Type Exceptions Endpoints Safe Unsafe Unknown No ASYNC_REG
-------- ------------ ----------------- ------------ ------------------- --------- ---- ------ ------- ------------
Critical sys_clk cpu_clk User Ignored Asynch Clock Groups 57 55 2 0 1
Warning cpu_clk sys_clk User Ignored Asynch Clock Groups 153 153 0 0 0

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fpga/vivado_reports/impl_clock_networks.rpt
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:51 2026
| Host : fedora running 64-bit unknown
| Command : report_clock_networks -file ./vivado_reports/impl_clock_networks.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
--------------------------------------------------------------------------------------
Clock Networks Report
Constrained Clocks
-------------------
Clock clk (50MHz)(endpoints: 17477 clock, 2 nonclock)
Port clk
Unconstrained Clocks
-------------------
Clock Q (endpoints: 23490 clock, 1 nonclock)
FDCE/Q (u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg)

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fpga/vivado_reports/impl_clock_utilization.rpt
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:50 2026
| Host : fedora running 64-bit unknown
| Command : report_clock_utilization -file ./vivado_reports/impl_clock_utilization.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
| Design State : Synthesized
--------------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Device Cell Placement Summary for Global Clock g1
8. Device Cell Placement Summary for Global Clock g2
9. Device Cell Placement Summary for Global Clock g3
10. Clock Region Cell Placement per Global Clock: Region X0Y3
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 4 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 120 | 0 | 0 | 0 |
| BUFIO | 0 | 40 | 0 | 0 | 0 |
| BUFMR | 0 | 20 | 0 | 0 | 0 |
| BUFR | 0 | 40 | 0 | 0 | 0 |
| MMCM | 0 | 10 | 0 | 0 | 0 |
| PLL | 1 | 10 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
| g0 | src0 | BUFG/O | None | | n/a | 0 | 23490 | 0 | | | r_wb_reg[7]_i_3/O | u_mlkem_axi_slave/mlkem_clk |
| g1 | src1 | BUFG/O | None | | n/a | 1 | 10604 | 1 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/clkout2_buf/O | pll_clk.u_clk_pll/inst/sys_clk |
| g2 | src1 | BUFG/O | None | | n/a | 0 | 5859 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/clkout1_buf/O | pll_clk.u_clk_pll/inst/cpu_clk |
| g3 | src1 | BUFG/O | None | | n/a | 0 | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkf_buf/O | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+--------------------+------------+------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+--------------------+------------+------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
| src0 | g0 | FDCE/Q | None | | n/a | 1 | 1 | | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg/Q | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg_0 |
| src1 | g3 | PLLE2_ADV/CLKFBOUT | None | | n/a | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT | pll_clk.u_clk_pll/inst/clkfbout_clk_pll |
| src1 | g2 | PLLE2_ADV/CLKOUT0 | None | | n/a | 1 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll |
| src1 | g1 | PLLE2_ADV/CLKOUT1 | None | | n/a | 1 | 0 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 | pll_clk.u_clk_pll/inst/sys_clk_clk_pll |
+-----------+-----------+--------------------+------------+------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 800 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4200 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
| X0Y3 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
| X1Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 1 | 0 | 50 | 0 | 50 | 0 | 2550 | 0 | 750 | 0 | 50 | 0 | 25 | 0 | 60 |
| X1Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 1 | 0 |
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
| g0 | BUFG/O | n/a | | | | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
7. Device Cell Placement Summary for Global Clock g1
----------------------------------------------------
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
| g1 | BUFG/O | n/a | sys_clk | 20.000 | {0.000 10.000} | 0 | 1 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 1 | 0 |
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
8. Device Cell Placement Summary for Global Clock g2
----------------------------------------------------
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
| g2 | BUFG/O | n/a | cpu_clk | 30.323 | {0.000 15.161} | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
9. Device Cell Placement Summary for Global Clock g3
----------------------------------------------------
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
| g3 | BUFG/O | n/a | clkfbout_clk_pll | 20.000 | {0.000 10.000} | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
10. Clock Region Cell Placement per Global Clock: Region X0Y3
-------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
| g1 | n/a | BUFG/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of IO Primitives which is load of clock spine
set_property LOC IOB_X0Y173 [get_cells video_clk_OBUF_inst]
# Location of clock ports
set_property LOC IOB_X0Y176 [get_ports clk]

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fpga/vivado_reports/impl_control_sets.rpt
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fpga/vivado_reports/impl_design_analysis.rpt
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:38:45 2026
| Host : fedora running 64-bit unknown
| Command : report_design_analysis -timing -logic_level_distribution -file ./vivado_reports/impl_design_analysis.rpt
| Design : soc_top
| Device : xc7a200t
| Design State : Synthesized
--------------------------------------------------------------------------------------------------------------------------
Report Design Analysis
Table of Contents
-----------------
1. Setup Path Characteristics 1-1
2. Logic Level Distribution
1. Setup Path Characteristics 1-1
---------------------------------
+---------------------------+-----------------------------------------------------------------------------------------------------------+
| Characteristics | Path #1 |
+---------------------------+-----------------------------------------------------------------------------------------------------------+
| Requirement | 20.000 |
| Path Delay | 17.702 |
| Logic Delay | 4.444(26%) |
| Net Delay | 13.258(74%) |
| Clock Skew | -0.145 |
| Slack | 2.111 |
| Clock Relationship | Safely Timed |
| Logic Levels | 18 |
| Routes | 0 |
| Logical Path | FDRE LUT2 CARRY4 CARRY4 LUT2 CARRY4 LUT6 LUT6 LUT6 LUT6 LUT6 LUT5 LUT6 LUT5 LUT5 LUT5 LUT5 LUT6 LUT6 FDSE |
| Start Point Clock | sys_clk |
| End Point Clock | sys_clk |
| DSP Block | None |
| BRAM | None |
| IO Crossings | 0 |
| Config Crossings | 0 |
| SLR Crossings | 0 |
| PBlocks | 0 |
| High Fanout | 16 |
| Dont Touch | 0 |
| Mark Debug | 0 |
| Start Point Pin Primitive | FDRE/C |
| End Point Pin Primitive | FDSE/D |
| Start Point Pin | p_reg[1]/C |
| End Point Pin | crc_reg_reg[18]/D |
+---------------------------+-----------------------------------------------------------------------------------------------------------+
* Bounding box calculated as % of dimensions for the target device (436, 500)
2. Logic Level Distribution
---------------------------
+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
| End Point Clock | Requirement | 10 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 29 | 30 | 31 | 32 |
+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
| cpu_clk | 30.323ns | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 65 | 40 | 34 | 62 |
| sys_clk | 20.000ns | 2 | 120 | 72 | 122 | 348 | 89 | 7 | 37 | 1 | 1 | 0 | 0 | 0 | 0 |
+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
* Columns represent the logic levels per end point clock
** Distribution is for top worst 1000 paths

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fpga/vivado_reports/impl_drc.rpt
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:54 2026
| Host : fedora running 64-bit unknown
| Command : report_drc -file ./vivado_reports/impl_drc.rpt
| Design : soc_top
| Device : xc7a200tfbg676-1
| Speed File : -1
| Design State : Synthesized
------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 42
+-----------+----------+----------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+----------------------------+------------+
| CHECK-3 | Warning | Report rule limit reached | 2 |
| REQP-1839 | Warning | RAMB36 async control check | 20 |
| REQP-1840 | Warning | RAMB18 async control check | 20 |
+-----------+----------+----------------------------+------------+
2. REPORT DETAILS
-----------------
CHECK-3#1 Warning
Report rule limit reached
REQP-1839 rule limit reached: 20 violations have been found.
Related violations: <none>
CHECK-3#2 Warning
Report rule limit reached
REQP-1840 rule limit reached: 20 violations have been found.
Related violations: <none>
REQP-1839#1 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#2 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#3 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#4 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#5 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#6 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#7 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#8 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#9 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#10 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#11 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#12 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#13 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#14 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#15 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#16 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#17 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#18 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#19 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#20 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#1 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#2 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#3 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#4 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#5 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#6 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#7 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#8 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#9 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#10 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#11 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#12 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#13 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#14 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#15 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#16 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#17 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#18 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#19 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#20 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

121
fpga/vivado_reports/impl_high_fanout_nets.rpt
View File

@@ -1,121 +0,0 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:38:35 2026
| Host : fedora running 64-bit unknown
| Command : report_high_fanout_nets -max_nets 100 -file ./vivado_reports/impl_high_fanout_nets.rpt
| Design : soc_top
| Device : xc7a200t
--------------------------------------------------------------------------------------------------------
High Fan-out Nets Information
1. Summary
----------
+---------------------------------------------------------------------------------------+--------+-------------+
| Net Name | Fanout | Driver Type |
+---------------------------------------------------------------------------------------+--------+-------------+
| pll_clk.u_rst_sys/p_0_in | 28767 | LUT1 |
| pll_clk.u_clk_pll/inst/sys_clk | 10994 | BUFG |
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_0 | 2097 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 | 1614 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1608 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/sha3_ack_reg | 1604 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sel_snt | 1602 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] | 1601 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_snt/state_next[1] | 1601 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_snt/state_next[2] | 1601 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_2 | 1122 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[1]_rep__0_13 | 1088 | LUT5 |
| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[2] | 1080 | FDRE |
| u_matmul_axi_slave/w_addr[2] | 879 | FDRE |
| u_matmul_axi_slave/w_addr[3] | 874 | FDRE |
| u_cpu/reset | 799 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg_n_0_[0] | 788 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg_n_0_[1] | 787 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr1[0] | 774 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr1[1] | 774 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[3] | 773 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1] | 772 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2] | 771 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/comp_k_reg[0]_rep_n_0 | 771 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/comp_k_reg[1]_rep_n_0 | 771 | FDCE |
| u_cpu/u_mul/E[0] | 716 | LUT1 |
| u_matmul_axi_slave/current_r_offset[2] | 525 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/r_r | 512 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 |
| u_matmul_axi_slave/w_addr[4] | 438 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr1[2] | 390 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[4] | 388 | FDCE |
| u_cpu/wb_stage/w_index[0] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[1] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[2] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[3] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[4] | 358 | LUT6 |
| u_matmul_axi_slave/acc_idx_d4[0] | 354 | FDRE |
| u_matmul_axi_slave/acc_idx_d4[1] | 354 | FDRE |
| u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE |
| u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 352 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4] | 329 | LUT3 |
| u_cpu/wb_stage/we_0 | 324 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3] | 321 | LUT3 |
| u_matmul_axi_slave/w_addr[5] | 303 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rho_r1 | 294 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/pre_addr_l_reg[7]_0[0] | 288 | CARRY4 |
| u_matmul_axi_slave/sel0[0] | 262 | FDRE |
| u_matmul_axi_slave/sel0[1] | 261 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 260 | LUT5 |
| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 260 | LUT2 |
| u_matmul_axi_slave/pipe_cnt_reg_n_0_[2] | 260 | FDRE |
| u_matmul_axi_slave/pipe_cnt_reg_n_0_[3] | 259 | FDRE |
| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 258 | LUT3 |
| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0 | 257 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_phase_reg[1]_1[0] | 256 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 |
| u_matmul_axi_slave/m_in_b[0][31]_i_1_n_0 | 256 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 |
| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT2 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 239 | RAMB18E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 239 | RAMB18E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 238 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 237 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 237 | RAMB18E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 237 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 237 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 237 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 235 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 235 | RAMB36E1 |
| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 |
| u_cpu/mem_stage/E[0] | 232 | LUT1 |
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 |
| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 |
+---------------------------------------------------------------------------------------+--------+-------------+

718
fpga/vivado_reports/impl_io.rpt
View File

@@ -1,718 +0,0 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:36:08 2026
| Host : fedora running 64-bit unknown
| Command : report_io -file ./vivado_reports/impl_io.rpt
| Design : soc_top
| Device : xc7a200t
| Speed File : -1
| Package : fbg676
| Package Version : FINAL 2012-06-20
| Package Pin Delay Version : FINAL VERS. 2.0 2012-06-20
-------------------------------------------------------------------------------------------------
IO Information
Table of Contents
-----------------
1. Summary
2. IO Assignments by Package Pin
1. Summary
----------
+---------------+
| Total User IO |
+---------------+
| 202 |
+---------------+
2. IO Assignments by Package Pin
--------------------------------
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| A1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| A2 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| A3 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| A4 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| A5 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| A6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A7 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | |
| A8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A9 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | |
| A10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A11 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | |
| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A13 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | |
| A14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A15 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | |
| A16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A17 | dpy1[0] | High Range | IO_L9P_T1_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A18 | leds[11] | High Range | IO_L9N_T1_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A19 | dpy0[3] | High Range | IO_L10N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A20 | leds[14] | High Range | IO_L15N_T2_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| A22 | leds[13] | High Range | IO_L17N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A23 | leds[9] | High Range | IO_L21P_T3_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A24 | leds[2] | High Range | IO_L21N_T3_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A25 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| A26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA1 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| AA2 | | High Range | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA3 | | High Range | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA4 | | High Range | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA5 | | High Range | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA7 | | High Range | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA8 | | High Range | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA10 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AA11 | | | MGTREFCLK1P_213 | Gigabit | | | | | | | | | | | | | | | |
| AA12 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AA13 | | | MGTREFCLK0P_213 | Gigabit | | | | | | | | | | | | | | | |
| AA14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA15 | ext_ram_data[23] | High Range | IO_L23N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA17 | ext_ram_addr[8] | High Range | IO_L19P_T3_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA18 | ext_ram_addr[7] | High Range | IO_L17N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA19 | ext_ram_data[30] | High Range | IO_L13P_T2_MRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA20 | | High Range | IO_L12P_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
| AA21 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| AA22 | base_ram_addr[14] | High Range | IO_L8P_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA23 | base_ram_addr[11] | High Range | IO_L8N_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA24 | base_ram_data[8] | High Range | IO_L7P_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA25 | ext_ram_addr[10] | High Range | IO_L5N_T0_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB1 | | High Range | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB2 | | High Range | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB4 | | High Range | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB5 | | High Range | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB6 | | High Range | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
| AB8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB11 | | | MGTREFCLK1N_213 | Gigabit | | | | | | | | | | | | | | | |
| AB12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB13 | | | MGTREFCLK0N_213 | Gigabit | | | | | | | | | | | | | | | |
| AB14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB15 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | |
| AB16 | ext_ram_data[16] | High Range | IO_L22P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB17 | ext_ram_data[18] | High Range | IO_L19N_T3_VREF_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB18 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| AB19 | ext_ram_oe_n | High Range | IO_L13N_T2_MRCC_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB20 | | High Range | IO_L12N_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
| AB21 | ext_ram_data[27] | High Range | IO_L11P_T1_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB22 | ext_ram_be_n[3] | High Range | IO_0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB24 | base_ram_addr[10] | High Range | IO_L9P_T1_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB25 | ext_ram_addr[12] | High Range | IO_L7N_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB26 | ext_ram_addr[11] | High Range | IO_L3P_T0_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC1 | | High Range | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC2 | | High Range | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC3 | | High Range | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC4 | | High Range | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC5 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| AC6 | | High Range | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AC8 | | | MGTPTXP2_213 | Gigabit | | | | | | | | | | | | | | | |
| AC9 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AC10 | | | MGTPTXP0_213 | Gigabit | | | | | | | | | | | | | | | |
| AC11 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AC12 | | | MGTPRXP0_213 | Gigabit | | | | | | | | | | | | | | | |
| AC13 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AC14 | | | MGTPRXP2_213 | Gigabit | | | | | | | | | | | | | | | |
| AC15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AC16 | ext_ram_data[21] | High Range | IO_L22N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC17 | ext_ram_data[25] | High Range | IO_L20P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC18 | ext_ram_data[19] | High Range | IO_L15P_T2_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC19 | ext_ram_data[17] | High Range | IO_L14P_T2_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AC21 | ext_ram_data[29] | High Range | IO_L11N_T1_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC22 | ext_ram_addr[5] | High Range | IO_L2P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC23 | ext_ram_data[31] | High Range | IO_L2N_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC24 | ext_ram_addr[14] | High Range | IO_L9N_T1_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC25 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| AC26 | ext_ram_addr[13] | High Range | IO_L3N_T0_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD1 | | High Range | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AD2 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| AD3 | | High Range | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AD4 | | High Range | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AD5 | | High Range | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AD6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD7 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AD8 | | | MGTPTXN2_213 | Gigabit | | | | | | | | | | | | | | | |
| AD9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD10 | | | MGTPTXN0_213 | Gigabit | | | | | | | | | | | | | | | |
| AD11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD12 | | | MGTPRXN0_213 | Gigabit | | | | | | | | | | | | | | | |
| AD13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD14 | | | MGTPRXN2_213 | Gigabit | | | | | | | | | | | | | | | |
| AD15 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AD16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD17 | ext_ram_data[24] | High Range | IO_L20N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD18 | ext_ram_data[20] | High Range | IO_L15N_T2_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD19 | ext_ram_we_n | High Range | IO_L14N_T2_SRCC_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD20 | ext_ram_data[26] | High Range | IO_L10P_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD21 | ext_ram_data[28] | High Range | IO_L7P_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD22 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| AD23 | ext_ram_ce_n | High Range | IO_L6P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD24 | ext_ram_be_n[2] | High Range | IO_L6N_T0_VREF_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD25 | ext_ram_addr[3] | High Range | IO_L4P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD26 | ext_ram_addr[4] | High Range | IO_L4N_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE1 | | High Range | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AE2 | | High Range | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| AE3 | | High Range | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AE4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AE5 | | High Range | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AE6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AE7 | | | MGTPTXP3_213 | Gigabit | | | | | | | | | | | | | | | |
| AE8 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AE9 | | | MGTPTXP1_213 | Gigabit | | | | | | | | | | | | | | | |
| AE10 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AE11 | | | MGTPRXP3_213 | Gigabit | | | | | | | | | | | | | | | |
| AE12 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AE13 | | | MGTPRXP1_213 | Gigabit | | | | | | | | | | | | | | | |
| AE14 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AE15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AE16 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
| AE17 | ext_ram_addr[16] | High Range | IO_L18P_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE18 | ext_ram_addr[18] | High Range | IO_L16P_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE19 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| AE20 | ext_ram_data[6] | High Range | IO_L10N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE21 | ext_ram_data[5] | High Range | IO_L7N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE22 | ext_ram_data[3] | High Range | IO_L9P_T1_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE23 | ext_ram_data[1] | High Range | IO_L5P_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AE25 | ext_ram_addr[1] | High Range | IO_L1P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE26 | ext_ram_addr[2] | High Range | IO_L1N_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF2 | | High Range | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| AF3 | | High Range | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AF4 | | High Range | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AF5 | | High Range | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AF6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF7 | | | MGTPTXN3_213 | Gigabit | | | | | | | | | | | | | | | |
| AF8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF9 | | | MGTPTXN1_213 | Gigabit | | | | | | | | | | | | | | | |
| AF10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF11 | | | MGTPRXN3_213 | Gigabit | | | | | | | | | | | | | | | |
| AF12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF13 | | | MGTPRXN1_213 | Gigabit | | | | | | | | | | | | | | | |
| AF14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF15 | | | MGTRREF_213 | Gigabit | | | | | | | | | | | | | | | |
| AF16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF17 | ext_ram_addr[15] | High Range | IO_L18N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF18 | ext_ram_addr[17] | High Range | IO_L16N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF19 | ext_ram_addr[19] | High Range | IO_L8P_T1_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF20 | ext_ram_data[7] | High Range | IO_L8N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF22 | ext_ram_data[4] | High Range | IO_L9N_T1_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF23 | ext_ram_data[2] | High Range | IO_L5N_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF24 | ext_ram_data[0] | High Range | IO_L3P_T0_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF25 | ext_ram_addr[0] | High Range | IO_L3N_T0_DQS_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF26 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| B1 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| B2 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B4 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| B5 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| B6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B7 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | |
| B8 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| B9 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | |
| B10 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| B11 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | |
| B12 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| B13 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | |
| B14 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B17 | dpy0[6] | High Range | IO_L7N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| B19 | dpy0[0] | High Range | IO_L10P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B20 | leds[15] | High Range | IO_L15P_T2_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B21 | dpy0[2] | High Range | IO_L16N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B22 | leds[7] | High Range | IO_L17P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B24 | leds[0] | High Range | IO_L23N_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B25 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B26 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| C1 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| C2 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| C3 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| C4 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| C5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C7 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| C8 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | |
| C9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C10 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | |
| C11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C12 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | |
| C13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C14 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | |
| C15 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C17 | dpy0[7] | High Range | IO_L7P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C18 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| C19 | dpy0[5] | High Range | IO_L13N_T2_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C21 | leds[5] | High Range | IO_L16P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C22 | leds[4] | High Range | IO_L19P_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C23 | leds[8] | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C24 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| C25 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| C26 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| D1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| D2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| D3 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| D4 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| D5 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| D6 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D8 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | |
| D9 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| D10 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | |
| D11 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| D12 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | |
| D13 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| D14 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | |
| D15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D16 | dpy1[1] | High Range | IO_L8N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D18 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| D19 | dpy0[1] | High Range | IO_L13P_T2_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D20 | leds[12] | High Range | IO_L14N_T2_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D21 | leds[10] | High Range | IO_L18N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| D23 | leds[3] | High Range | IO_L24P_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D24 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| D25 | video_blue[1] | High Range | IO_L20N_T3_A19_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D26 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
| E1 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| E2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| E3 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E5 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| E6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E11 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | |
| E12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E13 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | |
| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E16 | dpy1[4] | High Range | IO_L8P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E17 | dpy1[2] | High Range | IO_L11P_T1_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E18 | dpy0[4] | High Range | IO_L11N_T1_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| E20 | leds[6] | High Range | IO_L14P_T2_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E21 | leds[1] | High Range | IO_L18P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E22 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | |
| E23 | video_green[1] | High Range | IO_L17N_T2_A25_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E25 | video_blue[0] | High Range | IO_L20P_T3_A20_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E26 | video_red[2] | High Range | IO_L21P_T3_DQS_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| F3 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| F4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| F5 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| F6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| F7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| F8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F10 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| F11 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | |
| F12 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| F13 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | |
| F14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F15 | dpy1[6] | High Range | IO_L4N_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F16 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| F17 | dpy1[3] | High Range | IO_L2N_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F18 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| F19 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| F20 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| F21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| F23 | video_green[2] | High Range | IO_L17P_T2_A26_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F24 | video_red[1] | High Range | IO_L19N_T3_A21_VREF_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F25 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| F26 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| G1 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| G2 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| G3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| G4 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| G5 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| G6 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
| G7 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
| G8 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
| G9 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G14 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
| G15 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| G16 | dpy1[5] | High Range | IO_L6N_T0_VREF_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G17 | dpy1[7] | High Range | IO_L2P_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G19 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| G20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| G21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| G22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| G23 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| G24 | video_de | High Range | IO_L19P_T3_A22_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G25 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| G26 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
| H1 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| H2 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| H3 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
| H4 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
| H7 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
| H8 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
| H9 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| H10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
| H11 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
| H12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
| H13 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
| H14 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| H15 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| H16 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| H17 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | |
| H18 | UART_TX | High Range | IO_L10N_T1_AD11N_15 | BIDIR | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| H19 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
| H20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| H21 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| H22 | video_clk | High Range | IO_L13N_T2_MRCC_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| H23 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| H24 | video_vsync | High Range | IO_L16N_T2_A27_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| H25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H26 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
| J1 | dip_sw[14] | High Range | IO_L7N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J3 | dip_sw[1] | High Range | IO_L1N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| J4 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
| J5 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
| J6 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| J8 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
| J9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| J10 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J14 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
| J15 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
| J16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
| J17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| J18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
| J19 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
| J20 | UART_RX | High Range | IO_L9N_T1_DQS_AD3N_15 | BIDIR | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| J21 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| J22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J23 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| J24 | video_hsync | High Range | IO_L16P_T2_A28_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| J25 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
| J26 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
| K1 | dip_sw[17] | High Range | IO_L7P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| K2 | dip_sw[16] | High Range | IO_L8N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| K3 | dip_sw[13] | High Range | IO_L1P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| K5 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K6 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
| K7 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
| K8 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| K15 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
| K16 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
| K17 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
| K18 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
| K19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K20 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
| K21 | clk | High Range | IO_L12P_T1_MRCC_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
| K22 | video_green[0] | High Range | IO_L18P_T2_A24_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| K23 | video_red[0] | High Range | IO_L18N_T2_A23_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| K24 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| K25 | base_ram_be_n[3] | High Range | IO_L7P_T1_D09_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| K26 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
| L1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| L2 | dip_sw[15] | High Range | IO_L11N_T1_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L3 | dip_sw[6] | High Range | IO_L8P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L4 | dip_sw[19] | High Range | IO_L3N_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L5 | dip_sw[5] | High Range | IO_L4P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L7 | dip_sw[11] | High Range | IO_L2N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L8 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
| L9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L14 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| L15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
| L16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L17 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
| L18 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
| L19 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
| L20 | base_ram_be_n[0] | High Range | IO_L8N_T1_D12_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| L22 | base_ram_be_n[1] | High Range | IO_L11P_T1_SRCC_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L23 | base_ram_be_n[2] | High Range | IO_L11N_T1_SRCC_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L24 | base_ram_data[0] | High Range | IO_L9P_T1_DQS_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L25 | base_ram_data[1] | High Range | IO_L9N_T1_DQS_D13_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M1 | touch_btn[1] | High Range | IO_L9N_T1_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M2 | dip_sw[2] | High Range | IO_L11P_T1_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M4 | dip_sw[20] | High Range | IO_L3P_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M5 | dip_sw[12] | High Range | IO_L6N_T0_VREF_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M6 | dip_sw[8] | High Range | IO_L6P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M7 | dip_sw[10] | High Range | IO_L2P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| M12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M14 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| M15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
| M16 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| M17 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| M18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| M19 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
| M20 | base_ram_data[21] | High Range | IO_L8P_T1_D11_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M21 | base_ram_data[17] | High Range | IO_L12P_T1_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M22 | base_ram_data[31] | High Range | IO_L12N_T1_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M24 | base_ram_data[30] | High Range | IO_L10P_T1_D14_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M25 | base_ram_data[3] | High Range | IO_L10N_T1_D15_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M26 | base_ram_data[2] | High Range | IO_L20N_T3_A07_D23_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N1 | dip_sw[23] | High Range | IO_L9P_T1_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N2 | dip_sw[21] | High Range | IO_L12N_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N3 | dip_sw[18] | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N4 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| N5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| N6 | dip_sw[7] | High Range | IO_L5N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N7 | dip_sw[9] | High Range | IO_L5P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N8 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
| N12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| N14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
| N15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| N16 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
| N17 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
| N18 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| N19 | base_ram_data[20] | High Range | IO_L16N_T2_A15_D31_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N21 | base_ram_data[23] | High Range | IO_L13P_T2_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N22 | base_ram_data[28] | High Range | IO_L13N_T2_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N23 | base_ram_data[29] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N24 | base_ram_data[22] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N25 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| N26 | base_ram_data[4] | High Range | IO_L20P_T3_A08_D24_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P1 | dip_sw[3] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| P3 | touch_btn[2] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P4 | dip_sw[4] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P5 | dip_sw[24] | High Range | IO_L19N_T3_VREF_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P6 | dip_sw[22] | High Range | IO_L19P_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| P11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
| P12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
| P15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| P16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P18 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| P19 | base_ram_data[19] | High Range | IO_L16P_T2_CSI_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P20 | base_ram_data[27] | High Range | IO_L14P_T2_SRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P21 | base_ram_data[16] | High Range | IO_L14N_T2_SRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| P23 | base_ram_data[18] | High Range | IO_L17P_T2_A14_D30_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P24 | base_ram_data[5] | High Range | IO_L17N_T2_A13_D29_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P25 | base_ram_data[7] | High Range | IO_L19N_T3_A09_D25_VREF_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P26 | base_ram_data[6] | High Range | IO_L22N_T3_A04_D20_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R1 | dip_sw[27] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R2 | dip_sw[31] | High Range | IO_L17N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R3 | dip_sw[25] | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R5 | dip_sw[28] | High Range | IO_L20N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R6 | dip_sw[30] | High Range | IO_L23N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| R8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| R12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| R14 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
| R15 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
| R16 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
| R17 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
| R18 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
| R19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| R20 | base_ram_addr[5] | High Range | IO_L18P_T2_A12_D28_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R21 | base_ram_data[26] | High Range | IO_L18N_T2_A11_D27_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R22 | base_ram_data[25] | High Range | IO_L23N_T3_A02_D18_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R23 | base_ram_addr[6] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R25 | ext_ram_be_n[1] | High Range | IO_L19P_T3_A10_D26_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R26 | ext_ram_be_n[0] | High Range | IO_L22P_T3_A05_D21_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T2 | touch_btn[0] | High Range | IO_L17P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T3 | dip_sw[0] | High Range | IO_L16N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T4 | dip_sw[26] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T5 | dip_sw[29] | High Range | IO_L20P_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| T7 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| T8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T14 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| T15 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| T16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| T17 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| T18 | base_ram_addr[2] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T19 | base_ram_addr[0] | High Range | IO_L17P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T20 | base_ram_oe_n | High Range | IO_L15P_T2_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T22 | base_ram_data[24] | High Range | IO_L23P_T3_A03_D19_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T23 | base_ram_addr[7] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T24 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| T25 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
| T26 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| U1 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| U2 | touch_btn[3] | High Range | IO_L18P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| U3 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| U4 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
| U5 | reset | High Range | IO_L21N_T3_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| U6 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| U7 | | High Range | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| U8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| U12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| U14 | | High Range | IO_L23P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U15 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U16 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U17 | base_ram_addr[4] | High Range | IO_25_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U19 | base_ram_ce_n | High Range | IO_L17N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U20 | base_ram_we_n | High Range | IO_L15N_T2_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U21 | base_ram_data[15] | High Range | IO_L13P_T2_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U22 | base_ram_addr[8] | High Range | IO_L12P_T1_MRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U23 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| U24 | ext_ram_data[15] | High Range | IO_0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U25 | ext_ram_data[13] | High Range | IO_L1P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U26 | ext_ram_data[14] | High Range | IO_L1N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V1 | | High Range | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| V2 | | High Range | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V3 | | High Range | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V4 | | High Range | IO_0_33 | User IO | | 33 | | | | | | | | | | | | | |
| V5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V6 | | High Range | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| V7 | | High Range | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| V8 | | High Range | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V9 | | High Range | IO_25_33 | User IO | | 33 | | | | | | | | | | | | | |
| V10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| V11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
| V12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V14 | | High Range | IO_L23N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| V15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V16 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| V17 | base_ram_addr[3] | High Range | IO_L24N_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V18 | base_ram_addr[1] | High Range | IO_L19P_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V19 | base_ram_addr[19] | High Range | IO_L18P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| V21 | base_ram_data[10] | High Range | IO_L13N_T2_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V22 | base_ram_data[13] | High Range | IO_L12N_T1_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V23 | base_ram_data[14] | High Range | IO_L10P_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V24 | ext_ram_data[11] | High Range | IO_L6P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V26 | ext_ram_data[12] | High Range | IO_L2P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W1 | | High Range | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W3 | | High Range | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W4 | | High Range | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W5 | | High Range | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W6 | | High Range | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W7 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| W8 | | High Range | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| W9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
| W10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
| W11 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| W14 | | High Range | IO_L24P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
| W15 | | High Range | IO_L24N_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
| W16 | | High Range | IO_25_12 | User IO | | 12 | | | | | | | | | | | | | |
| W17 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| W18 | base_ram_addr[18] | High Range | IO_L19N_T3_VREF_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W19 | base_ram_addr[15] | High Range | IO_L18N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W20 | base_ram_addr[17] | High Range | IO_L16P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W21 | base_ram_addr[16] | High Range | IO_L14P_T2_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W23 | base_ram_data[12] | High Range | IO_L10N_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W24 | base_ram_data[11] | High Range | IO_L6N_T0_VREF_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W25 | ext_ram_data[9] | High Range | IO_L4P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W26 | ext_ram_data[10] | High Range | IO_L2N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y1 | | High Range | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y2 | | High Range | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y3 | | High Range | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y4 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| Y5 | | High Range | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y6 | | High Range | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y7 | | High Range | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y8 | | High Range | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y9 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
| Y10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y14 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
| Y15 | ext_ram_data[22] | High Range | IO_L23P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y16 | | High Range | IO_L21P_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
| Y17 | ext_ram_addr[6] | High Range | IO_L21N_T3_DQS_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y18 | | High Range | IO_L17P_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
| Y19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y20 | base_ram_addr[13] | High Range | IO_L16N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y21 | base_ram_addr[12] | High Range | IO_L14N_T2_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y22 | base_ram_addr[9] | High Range | IO_L11P_T1_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y23 | base_ram_data[9] | High Range | IO_L11N_T1_SRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y24 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| Y25 | ext_ram_addr[9] | High Range | IO_L5P_T0_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y26 | ext_ram_data[8] | High Range | IO_L4N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
* Default value
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.

5531
fpga/vivado_reports/impl_methodology.rpt
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50
fpga/vivado_reports/impl_route_status.rpt
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Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 158000 :
# of nets with no placed pins.......... : 157584 :
# of nets not needing routing.......... : 202 :
# of internally routed nets........ : 202 :
# of routable nets..................... : 0 :
# of nets with routing errors.......... : 214 :
# of nets with some unplaced pins.. : 214 :
# of nets with some unrouted pins.. : 160 :
------------------------------------------- : ----------- :
Nets with Routing Errors: (only the first 10 nets are listed)
GLOBAL_LOGIC0
Unplaced Pins -- only the first 10 are listed, use -show_all to get the full list:
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/RADR2
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/RADR3
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/RADR4
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR2
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR3
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR4
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/RADR2
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/RADR3
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/RADR4
axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR2
UART_RX_IOBUF_inst/O
Unplaced Pin: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/I3
UART_TX_IOBUF_inst/O
Unplaced Pins:
u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/I2
u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/I0
u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/I1
u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/I2
base_ram_data_IOBUF[0]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_251__0/I4
base_ram_data_IOBUF[10]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_182/I4
base_ram_data_IOBUF[11]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_177__0/I4
base_ram_data_IOBUF[12]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_169__0/I4
base_ram_data_IOBUF[13]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_159__0/I4
base_ram_data_IOBUF[14]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_152__0/I4
base_ram_data_IOBUF[15]_inst/O
Unplaced Pin: u_axi_ram/u_axi_sram_sp/mem_reg_i_355__0/I4

93512
fpga/vivado_reports/impl_timing_summary_hold.rpt
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93999
fpga/vivado_reports/impl_timing_summary_setup.rpt
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203
fpga/vivado_reports/impl_utilization.rpt
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:22 2026
| Host : fedora running 64-bit unknown
| Command : report_utilization -file ./vivado_reports/impl_utilization.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs* | 74980 | 0 | 134600 | 55.71 |
| LUT as Logic | 73234 | 0 | 134600 | 54.41 |
| LUT as Memory | 1746 | 0 | 46200 | 3.78 |
| LUT as Distributed RAM | 652 | 0 | | |
| LUT as Shift Register | 1094 | 0 | | |
| Slice Registers | 38603 | 0 | 269200 | 14.34 |
| Register as Flip Flop | 38603 | 0 | 269200 | 14.34 |
| Register as Latch | 0 | 0 | 269200 | 0.00 |
| F7 Muxes | 4263 | 0 | 67300 | 6.33 |
| F8 Muxes | 1403 | 0 | 33650 | 4.17 |
+----------------------------+-------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 101 | Yes | - | Set |
| 25523 | Yes | - | Reset |
| 134 | Yes | Set | - |
| 12845 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 25.5 | 0 | 365 | 6.99 |
| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
| RAMB36E1 only | 10 | | | |
| RAMB18 | 31 | 0 | 730 | 4.25 |
| RAMB18E1 only | 31 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 740 | 0.00 |
+-----------+------+-------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 202 | 202 | 400 | 50.50 |
| IOB Master Pads | 97 | | | |
| IOB Slave Pads | 102 | | | |
| Bonded IPADs | 0 | 0 | 26 | 0.00 |
| Bonded OPADs | 0 | 0 | 16 | 0.00 |
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
| PHASER_REF | 0 | 0 | 10 | 0.00 |
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
| IN_FIFO | 0 | 0 | 40 | 0.00 |
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
| IBUFDS | 0 | 0 | 384 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
| ILOGIC | 0 | 0 | 400 | 0.00 |
| OLOGIC | 0 | 0 | 400 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
| BUFIO | 0 | 0 | 40 | 0.00 |
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
| BUFMRCE | 0 | 0 | 20 | 0.00 |
| BUFHCE | 0 | 0 | 120 | 0.00 |
| BUFR | 0 | 0 | 40 | 0.00 |
+------------+------+-------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
7. Primitives
-------------
+-----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+-----------+-------+---------------------+
| LUT6 | 36042 | LUT |
| FDCE | 25523 | Flop & Latch |
| LUT5 | 16007 | LUT |
| LUT3 | 13060 | LUT |
| FDRE | 12845 | Flop & Latch |
| LUT4 | 11977 | LUT |
| LUT2 | 9006 | LUT |
| MUXF7 | 4263 | MuxFx |
| CARRY4 | 3590 | CarryLogic |
| MUXF8 | 1403 | MuxFx |
| SRLC32E | 992 | Distributed Memory |
| RAMD32 | 892 | Distributed Memory |
| LUT1 | 816 | LUT |
| RAMS32 | 272 | Distributed Memory |
| FDSE | 134 | Flop & Latch |
| IBUF | 104 | IO |
| SRL16E | 102 | Distributed Memory |
| FDPE | 101 | Flop & Latch |
| OBUF | 98 | IO |
| OBUFT | 66 | IO |
| RAMD64E | 32 | Distributed Memory |
| RAMB18E1 | 31 | Block Memory |
| RAMB36E1 | 10 | Block Memory |
| BUFG | 4 | Clock |
| PLLE2_ADV | 1 | Clock |
+-----------+-------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
| clk_pll | 1 |
+----------+------+

5980
fpga/vivado_reports/impl_worst_hold_paths.rpt
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11494
fpga/vivado_reports/impl_worst_setup_paths.rpt
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914
fpga/vivado_reports/synth_timing_summary.rpt
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@@ -1,914 +0,0 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:34:34 2026
| Host : fedora running 64-bit unknown
| Command : report_timing_summary -file ./vivado_reports/synth_timing_summary.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
---------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 23490 register/latch pins with no clock driven by root clock pin: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg/Q (HIGH)
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 69061 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There are 38 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 40 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
2.111 0.000 0 43229 0.011 0.000 0 43229 7.000 0.000 0 17485
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
clk {0.000 10.000} 20.000 50.000
clkfbout_clk_pll {0.000 10.000} 20.000 50.000
cpu_clk {0.000 15.161} 30.323 32.979
sys_clk {0.000 10.000} 20.000 50.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
clk 7.000 0.000 0 1
clkfbout_clk_pll 17.845 0.000 0 3
cpu_clk 6.897 0.000 0 17197 0.011 0.000 0 17197 13.911 0.000 0 6486
sys_clk 2.111 0.000 0 23819 0.011 0.000 0 23819 8.750 0.000 0 10995
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
**async_default** cpu_clk cpu_clk 27.780 0.000 0 67 0.676 0.000 0 67
**async_default** sys_clk sys_clk 17.299 0.000 0 2146 0.679 0.000 0 2146
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: clk
To Clock: clk
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { clk }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: clkfbout_clk_pll
To Clock: clkfbout_clk_pll
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clkfbout_clk_pll
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 20.000 17.845 pll_clk.u_clk_pll/inst/clkf_buf/I
Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: cpu_clk
To Clock: cpu_clk
Setup : 0 Failing Endpoints, Worst Slack 6.897ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 6.897ns (required time - arrival time)
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[25]/C
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Path Group: cpu_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
Data Path Delay: 23.236ns (logic 6.978ns (30.031%) route 16.258ns (69.969%))
Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=7 LUT6=12 MUXF7=1 MUXF8=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -2.918ns = ( 27.404 - 30.323 )
Source Clock Delay (SCD): -3.241ns
Clock Pessimism Removal (CPR): -0.468ns
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.130ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.584 -3.241 u_cpu/addr_trans/cpu_clk
FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[25]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.456 -2.785 r u_cpu/addr_trans/data_vaddr_buffer_reg[25]/Q
net (fo=65, unplaced) 1.054 -1.731 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[13]
LUT6 (Prop_lut6_I0_O) 0.295 -1.436 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_105/O
net (fo=1, unplaced) 0.000 -1.436 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_105_n_0
CARRY4 (Prop_carry4_S[1]_CO[3])
0.550 -0.886 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_30/CO[3]
net (fo=1, unplaced) 0.900 0.014 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_30_n_0
LUT6 (Prop_lut6_I3_O) 0.124 0.138 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_8/O
net (fo=4, unplaced) 0.926 1.064 u_cpu/addr_trans/tlb_entry/match1[31]
LUT4 (Prop_lut4_I1_O) 0.150 1.214 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
net (fo=2, unplaced) 0.460 1.674 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
LUT5 (Prop_lut5_I0_O) 0.118 1.792 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
net (fo=2, unplaced) 0.460 2.252 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
LUT6 (Prop_lut6_I0_O) 0.124 2.376 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
net (fo=89, unplaced) 0.571 2.947 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
MUXF7 (Prop_muxf7_S_O) 0.296 3.243 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O
net (fo=1, unplaced) 0.000 3.243 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0
MUXF8 (Prop_muxf8_I0_O) 0.104 3.347 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O
net (fo=1, unplaced) 0.717 4.064 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0
LUT5 (Prop_lut5_I0_O) 0.319 4.383 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O
net (fo=1, unplaced) 0.449 4.832 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0
LUT6 (Prop_lut6_I5_O) 0.124 4.956 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
net (fo=1, unplaced) 0.449 5.405 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
LUT6 (Prop_lut6_I5_O) 0.124 5.529 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
net (fo=10, unplaced) 0.492 6.021 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
LUT6 (Prop_lut6_I3_O) 0.124 6.145 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[4]_i_1__0/O
net (fo=6, unplaced) 0.934 7.079 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[16]
LUT6 (Prop_lut6_I0_O) 0.124 7.203 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O
net (fo=1, unplaced) 0.000 7.203 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0
CARRY4 (Prop_carry4_S[1]_CO[3])
0.550 7.753 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3]
net (fo=1, unplaced) 0.009 7.762 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0
CARRY4 (Prop_carry4_CI_CO[2])
0.250 8.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2]
net (fo=5, unplaced) 0.480 8.492 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0]
LUT3 (Prop_lut3_I0_O) 0.310 8.802 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O
net (fo=32, unplaced) 0.520 9.322 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4
LUT6 (Prop_lut6_I5_O) 0.124 9.446 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O
net (fo=3, unplaced) 0.920 10.366 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22]
LUT6 (Prop_lut6_I1_O) 0.124 10.490 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O
net (fo=3, unplaced) 0.467 10.957 u_cpu/mem_stage/p_5_in6_in[0]
LUT4 (Prop_lut4_I0_O) 0.118 11.075 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O
net (fo=8, unplaced) 0.487 11.562 u_cpu/u_div/ms_to_ws_bus_r_reg[40]
LUT5 (Prop_lut5_I4_O) 0.124 11.686 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O
net (fo=1, unplaced) 0.449 12.135 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40]
LUT4 (Prop_lut4_I2_O) 0.124 12.259 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O
net (fo=4, unplaced) 0.473 12.732 u_cpu/id_stage/ms_to_ds_forward_bus[8]
LUT5 (Prop_lut5_I2_O) 0.124 12.856 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O
net (fo=1, unplaced) 0.000 12.856 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0
CARRY4 (Prop_carry4_S[1]_CO[3])
0.550 13.406 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3]
net (fo=1, unplaced) 0.000 13.406 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0
CARRY4 (Prop_carry4_CI_O[1])
0.348 13.754 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1]
net (fo=1, unplaced) 0.611 14.365 u_cpu/id_stage/rd_csr_addr0[12]
LUT5 (Prop_lut5_I0_O) 0.332 14.697 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O
net (fo=1, unplaced) 0.449 15.146 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0
LUT5 (Prop_lut5_I1_O) 0.124 15.270 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O
net (fo=3, unplaced) 0.467 15.737 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0
LUT4 (Prop_lut4_I3_O) 0.124 15.861 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O
net (fo=7, unplaced) 0.484 16.345 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0
LUT6 (Prop_lut6_I5_O) 0.124 16.469 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O
net (fo=19, unplaced) 0.508 16.977 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0
LUT5 (Prop_lut5_I4_O) 0.124 17.101 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_24/O
net (fo=20, unplaced) 0.509 17.610 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_10
LUT4 (Prop_lut4_I2_O) 0.124 17.734 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_7/O
net (fo=1, unplaced) 1.111 18.845 u_cpu/id_stage/ds_to_es_bus_r[180]_i_7_n_0
LUT6 (Prop_lut6_I0_O) 0.124 18.969 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_2/O
net (fo=1, unplaced) 0.902 19.871 u_cpu/id_stage/ds_to_es_bus_r[180]_i_2_n_0
LUT6 (Prop_lut6_I1_O) 0.124 19.995 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/O
net (fo=1, unplaced) 0.000 19.995 u_cpu/exe_stage/ds_to_es_bus[130]
FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 30.323 30.323 r
K21 0.000 30.323 r clk (IN)
net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.439 32.154 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-6.040 26.114 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.760 26.874 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.091 26.965 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.439 27.404 u_cpu/exe_stage/cpu_clk
FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/C
clock pessimism -0.468 26.936
clock uncertainty -0.074 26.862
FDRE (Setup_fdre_C_D) 0.029 26.891 u_cpu/exe_stage/ds_to_es_bus_r_reg[180]
-------------------------------------------------------------------
required time 26.891
arrival time -19.995
-------------------------------------------------------------------
slack 6.897
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.011ns (arrival time - required time)
Source: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Path Group: cpu_clk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): -0.650ns
Source Clock Delay (SCD): -0.978ns
Clock Pessimism Removal (CPR): 0.183ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0[0]
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
clock pessimism -0.183 -0.833
FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]
-------------------------------------------------------------------
required time 0.763
arrival time -0.752
-------------------------------------------------------------------
slack 0.011
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: cpu_clk
Waveform(ns): { 0.000 15.161 }
Period(ns): 30.323
Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK
Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/RAMA/CLK
High Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: sys_clk
To Clock: sys_clk
Setup : 0 Failing Endpoints, Worst Slack 2.111ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 2.111ns (required time - arrival time)
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_matmul_axi_slave/crc_reg_reg[18]/D
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: sys_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
Data Path Delay: 17.702ns (logic 4.444ns (25.105%) route 13.258ns (74.895%))
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT5=5 LUT6=8)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
Source Clock Delay (SCD): -3.025ns
Clock Pessimism Removal (CPR): -0.468ns
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.122ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
CARRY4 (Prop_carry4_S[1]_CO[3])
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
CARRY4 (Prop_carry4_CI_O[1])
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
CARRY4 (Prop_carry4_S[1]_O[3])
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
LUT5 (Prop_lut5_I1_O) 0.150 9.989 r u_matmul_axi_slave/crc_reg[30]_i_10/O
net (fo=1, unplaced) 1.111 11.100 u_matmul_axi_slave/crc32_word_next0_return0[22]
LUT5 (Prop_lut5_I0_O) 0.152 11.252 r u_matmul_axi_slave/crc_reg[30]_i_4/O
net (fo=1, unplaced) 0.902 12.154 u_matmul_axi_slave/p_0_in0_in[8]
LUT5 (Prop_lut5_I2_O) 0.124 12.278 r u_matmul_axi_slave/crc_reg[30]_i_2/O
net (fo=9, unplaced) 1.005 13.283 u_matmul_axi_slave/crc32_word_next1_return1[0]
LUT6 (Prop_lut6_I0_O) 0.124 13.407 r u_matmul_axi_slave/crc_reg[28]_i_2/O
net (fo=7, unplaced) 1.146 14.553 u_matmul_axi_slave/crc_reg[28]_i_2_n_0
LUT6 (Prop_lut6_I1_O) 0.124 14.677 r u_matmul_axi_slave/crc_reg[18]_i_1/O
net (fo=1, unplaced) 0.000 14.677 u_matmul_axi_slave/crc32_word_next1_return[18]
FDSE r u_matmul_axi_slave/crc_reg_reg[18]/D
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 20.000 20.000 r
K21 0.000 20.000 r clk (IN)
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
FDSE r u_matmul_axi_slave/crc_reg_reg[18]/C
clock pessimism -0.468 16.830
clock uncertainty -0.071 16.759
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[18]
-------------------------------------------------------------------
required time 16.788
arrival time -14.677
-------------------------------------------------------------------
slack 2.111
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.011ns (arrival time - required time)
Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: sys_clk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): -0.555ns
Source Clock Delay (SCD): -0.882ns
Clock Pessimism Removal (CPR): 0.183ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0]
FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
clock pessimism -0.183 -0.737
FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]
-------------------------------------------------------------------
required time 0.667
arrival time -0.657
-------------------------------------------------------------------
slack 0.011
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: sys_clk
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK
Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: cpu_clk
To Clock: cpu_clk
Setup : 0 Failing Endpoints, Worst Slack 27.780ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.676ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 27.780ns (required time - arrival time)
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
(recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
Data Path Delay: 1.915ns (logic 0.751ns (39.217%) route 1.164ns (60.783%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -2.918ns = ( 27.404 - 30.323 )
Source Clock Delay (SCD): -3.241ns
Clock Pessimism Removal (CPR): -0.468ns
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.130ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.584 -3.241 pll_clk.u_rst_cpu/cpu_clk
FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.456 -2.785 r pll_clk.u_rst_cpu/delay_reg[1]/Q
net (fo=1, unplaced) 0.311 -2.474 pll_clk.u_rst_cpu/cpu_resetn
LUT1 (Prop_lut1_I0_O) 0.295 -2.179 f pll_clk.u_rst_cpu/reset_i_1/O
net (fo=40, unplaced) 0.853 -1.326 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in
FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 30.323 30.323 r
K21 0.000 30.323 r clk (IN)
net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.439 32.154 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-6.040 26.114 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.760 26.874 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.091 26.965 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.439 27.404 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
clock pessimism -0.468 26.936
clock uncertainty -0.074 26.862
FDCE (Recov_fdce_C_CLR) -0.409 26.453 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]
-------------------------------------------------------------------
required time 26.453
arrival time 1.326
-------------------------------------------------------------------
slack 27.780
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.676ns (arrival time - required time)
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
Data Path Delay: 0.727ns (logic 0.239ns (32.888%) route 0.488ns (67.112%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): -0.650ns
Source Clock Delay (SCD): -0.978ns
Clock Pessimism Removal (CPR): 0.183ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
net (fo=1, unplaced) 0.131 -0.706 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
LUT1 (Prop_lut1_I0_O) 0.098 -0.608 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
net (fo=30, unplaced) 0.357 -0.251 u_Axi_CDC/bFifo/buffers_1_reg
FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR
------------------------------------------------------------------- -------------------
(clock cpu_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O
net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/bFifo/cpu_clk
FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C
clock pessimism -0.183 -0.833
FDCE (Remov_fdce_C_CLR) -0.094 -0.927 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg
-------------------------------------------------------------------
required time 0.927
arrival time -0.251
-------------------------------------------------------------------
slack 0.676
---------------------------------------------------------------------------------------------------
Path Group: **async_default**
From Clock: sys_clk
To Clock: sys_clk
Setup : 0 Failing Endpoints, Worst Slack 17.299ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.679ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 17.299ns (required time - arrival time)
Source: pll_clk.u_rst_sys/delay_reg[1]/C
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg/CLR
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
Data Path Delay: 2.076ns (logic 0.745ns (35.886%) route 1.331ns (64.114%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
Source Clock Delay (SCD): -3.025ns
Clock Pessimism Removal (CPR): -0.468ns
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.122ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.800 -3.025 pll_clk.u_rst_sys/sys_clk
FDCE r pll_clk.u_rst_sys/delay_reg[1]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.456 -2.569 r pll_clk.u_rst_sys/delay_reg[1]/Q
net (fo=119, unplaced) 0.415 -2.154 pll_clk.u_rst_sys/Q[0]
LUT1 (Prop_lut1_I0_O) 0.289 -1.865 f pll_clk.u_rst_sys/r_wb[7]_i_4/O
net (fo=28767, unplaced) 0.916 -0.949 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/p_0_in
FDCE f u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg/CLR
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 20.000 20.000 r
K21 0.000 20.000 r clk (IN)
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.655 17.297 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/sys_clk
FDCE r u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg/C
clock pessimism -0.468 16.830
clock uncertainty -0.071 16.759
FDCE (Recov_fdce_C_CLR) -0.409 16.350 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg
-------------------------------------------------------------------
required time 16.350
arrival time 0.949
-------------------------------------------------------------------
slack 17.299
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.679ns (arrival time - required time)
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg/CLR
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
Data Path Delay: 0.730ns (logic 0.239ns (32.718%) route 0.491ns (67.282%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): -0.555ns
Source Clock Delay (SCD): -0.882ns
Clock Pessimism Removal (CPR): 0.183ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
net (fo=1, unplaced) 0.131 -0.610 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
LUT1 (Prop_lut1_I0_O) 0.098 -0.512 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
net (fo=43, unplaced) 0.360 -0.152 u_Axi_CDC/arFifo/buffers_0_reg[2]
FDCE f u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg/CLR
------------------------------------------------------------------- -------------------
(clock sys_clk rise edge) 0.000 0.000 r
K21 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
-1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O
net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/arFifo/sys_clk
FDCE r u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg/C
clock pessimism -0.183 -0.737
FDCE (Remov_fdce_C_CLR) -0.094 -0.831 u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg
-------------------------------------------------------------------
required time 0.831
arrival time -0.152
-------------------------------------------------------------------
slack 0.679

255
fpga/vivado_reports/synth_utilization_hier.rpt
View File

@@ -1,255 +0,0 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:34:18 2026
| Host : fedora running 64-bit unknown
| Command : report_utilization -hierarchical -hierarchical_depth 10 -file ./vivado_reports/synth_utilization_hier.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Utilization by Hierarchy
1. Utilization by Hierarchy
---------------------------
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| soc_top | (top) | 74980 | 73234 | 652 | 1094 | 38603 | 10 | 31 | 0 |
| (soc_top) | (top) | 2116 | 2060 | 56 | 0 | 4 | 0 | 0 | 0 |
| pll_clk.u_clk_pll | clk_pll | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| inst | clk_pll_clk_pll_clk_wiz | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| pll_clk.u_rst_sys | rst_sync_0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 519 | 519 | 0 | 0 | 151 | 0 | 0 | 0 |
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_67 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_50 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_66 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_51 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_65 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_52 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_64 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 32 | 32 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_61 | 25 | 25 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_62 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_63 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_58 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_59 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_60 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_55 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_56 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_57 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 61 | 61 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7 | 48 | 48 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3 | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 |
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 89 | 89 | 0 | 0 | 25 | 0 | 0 | 0 |
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 73 | 73 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1_54 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 |
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 |
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1_53 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 |
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 181 | 181 | 0 | 0 | 17 | 0 | 0 | 0 |
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 165 | 165 | 0 | 0 | 8 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 |
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 25 | 25 | 0 | 0 | 14 | 0 | 0 | 0 |
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_Axi_CDC | Axi_CDC | 505 | 377 | 128 | 0 | 309 | 0 | 0 | 0 |
| arFifo | StreamFifoCC_3 | 262 | 226 | 36 | 0 | 73 | 0 | 0 | 0 |
| (arFifo) | StreamFifoCC_3 | 256 | 220 | 36 | 0 | 61 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_48 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_49 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
| awFifo | StreamFifoCC | 112 | 76 | 36 | 0 | 75 | 0 | 0 | 0 |
| (awFifo) | StreamFifoCC | 105 | 69 | 36 | 0 | 61 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| bFifo | StreamFifoCC_2 | 16 | 16 | 0 | 0 | 26 | 0 | 0 | 0 |
| (bFifo) | StreamFifoCC_2 | 9 | 9 | 0 | 0 | 12 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_4 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_6 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| rFifo | StreamFifoCC_4 | 46 | 18 | 28 | 0 | 66 | 0 | 0 | 0 |
| (rFifo) | StreamFifoCC_4 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_1 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| wFifo | StreamFifoCC_1 | 69 | 41 | 28 | 0 | 69 | 0 | 0 | 0 |
| (wFifo) | StreamFifoCC_1 | 64 | 36 | 28 | 0 | 53 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_8 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| u_axi_axil_adapter | axi_axil_adapter | 1355 | 1355 | 0 | 0 | 161 | 0 | 0 | 0 |
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 648 | 648 | 0 | 0 | 81 | 0 | 0 | 0 |
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 707 | 707 | 0 | 0 | 80 | 0 | 0 | 0 |
| u_axi_dvi | axi_dvi | 285 | 285 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_axi_ram | axi_wrap_ram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_sram_sp | axi2sram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_uart_controller | axi_uart_controller | 693 | 677 | 16 | 0 | 457 | 0 | 0 | 0 |
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 252 | 252 | 0 | 0 | 120 | 0 | 0 | 0 |
| uart0 | UART_TOP | 441 | 425 | 16 | 0 | 337 | 0 | 0 | 0 |
| regs | uart_regs | 441 | 425 | 16 | 0 | 337 | 0 | 0 | 0 |
| (regs) | uart_regs | 121 | 121 | 0 | 0 | 155 | 0 | 0 | 0 |
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
| receiver | uart_receiver | 231 | 223 | 8 | 0 | 124 | 0 | 0 | 0 |
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
| fifo_rx | uart_rfifo | 163 | 155 | 8 | 0 | 70 | 0 | 0 | 0 |
| (fifo_rx) | uart_rfifo | 144 | 144 | 0 | 0 | 62 | 0 | 0 | 0 |
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
| transmitter | uart_transmitter | 86 | 78 | 8 | 0 | 56 | 0 | 0 | 0 |
| (transmitter) | uart_transmitter | 42 | 42 | 0 | 0 | 35 | 0 | 0 | 0 |
| fifo_tx | uart_tfifo | 44 | 36 | 8 | 0 | 21 | 0 | 0 | 0 |
| (fifo_tx) | uart_tfifo | 25 | 25 | 0 | 0 | 13 | 0 | 0 | 0 |
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
| u_cdma_matmul_bridge | cdma_matmul_bridge | 250 | 250 | 0 | 0 | 578 | 0 | 0 | 0 |
| u_confreg | confreg | 391 | 391 | 0 | 0 | 460 | 0 | 0 | 0 |
| (u_confreg) | confreg | 231 | 231 | 0 | 0 | 383 | 0 | 0 | 0 |
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
| u_cpu | core_top | 8656 | 8380 | 276 | 0 | 5591 | 0 | 20 | 0 |
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
| addr_trans | addr_trans | 2264 | 2100 | 164 | 0 | 1244 | 0 | 0 | 0 |
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
| tlb_entry | tlb_entry | 2264 | 2100 | 164 | 0 | 1204 | 0 | 0 | 0 |
| axi_bridge | axi_bridge | 40 | 40 | 0 | 0 | 214 | 0 | 0 | 0 |
| btb | btb | 1064 | 984 | 80 | 0 | 1611 | 0 | 0 | 0 |
| (btb) | btb | 1061 | 981 | 80 | 0 | 1611 | 0 | 0 | 0 |
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
| dcache | dcache | 569 | 537 | 32 | 0 | 146 | 0 | 10 | 0 |
| (dcache) | dcache | 92 | 60 | 32 | 0 | 138 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_46 | 46 | 46 | 0 | 0 | 0 | 0 | 1 | 0 |
| exe_stage | exe_stage | 681 | 681 | 0 | 0 | 233 | 0 | 0 | 0 |
| (exe_stage) | exe_stage | 650 | 650 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
| icache | icache | 239 | 239 | 0 | 0 | 55 | 0 | 10 | 0 |
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_35 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
| id_stage | id_stage | 1058 | 1058 | 0 | 0 | 108 | 0 | 0 | 0 |
| if_stage | if_stage | 135 | 135 | 0 | 0 | 173 | 0 | 0 | 0 |
| mem_stage | mem_stage | 116 | 116 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
| u_div | div | 143 | 143 | 0 | 0 | 107 | 0 | 0 | 0 |
| u_mul | mul | 943 | 943 | 0 | 0 | 592 | 0 | 0 | 0 |
| wb_stage | wb_stage | 685 | 685 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 48074 | 46986 | 0 | 1088 | 25915 | 10 | 10 | 0 |
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 17 | 17 | 0 | 0 | 6 | 0 | 0 | 0 |
| u_fft_controller | fft_controller | 6966 | 5878 | 0 | 1088 | 1087 | 8 | 4 | 0 |
| (u_fft_controller) | fft_controller | 90 | 90 | 0 | 0 | 104 | 0 | 0 | 0 |
| u_FFT | FFT | 6855 | 5767 | 0 | 1088 | 983 | 8 | 0 | 0 |
| SU1 | SdfUnit | 2150 | 1382 | 0 | 768 | 197 | 2 | 0 | 0 |
| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 |
| MU | Multiply_26 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_27 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU2 | SdfUnit__parameterized0 | 1571 | 1379 | 0 | 192 | 197 | 2 | 0 | 0 |
| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_21 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
| MU | Multiply_22 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_23 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU3 | SdfUnit__parameterized1 | 1439 | 1375 | 0 | 64 | 197 | 2 | 0 | 0 |
| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_16 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_17 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized4 | 96 | 64 | 0 | 32 | 32 | 0 | 0 | 0 |
| MU | Multiply_18 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_19 | 540 | 540 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU4 | SdfUnit__parameterized2 | 1436 | 1372 | 0 | 64 | 197 | 2 | 0 | 0 |
| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_14 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_15 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized5 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized6 | 96 | 64 | 0 | 32 | 32 | 0 | 0 | 0 |
| MU | Multiply | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle | 538 | 538 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU5 | SdfUnit__parameterized3 | 259 | 259 | 0 | 0 | 195 | 0 | 0 | 0 |
| (SU5) | SdfUnit__parameterized3 | 35 | 35 | 0 | 0 | 99 | 0 | 0 | 0 |
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_in1 | my_bram0_11 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out0 | my_bram0_12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out1 | my_bram0_13 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_mlkem_axi_slave | mlkem_axi_slave | 40589 | 40589 | 0 | 0 | 24484 | 2 | 6 | 0 |
| (u_mlkem_axi_slave) | mlkem_axi_slave | 3642 | 3642 | 0 | 0 | 1021 | 0 | 0 | 0 |
| u_mlkem | mlkem_top | 36975 | 36975 | 0 | 0 | 23463 | 2 | 6 | 0 |
| (u_mlkem) | mlkem_top | 2550 | 2550 | 0 | 0 | 4907 | 0 | 0 | 0 |
| u_bank_a | sd_bram__parameterized0 | 39 | 39 | 0 | 0 | 0 | 1 | 1 | 0 |
| u_bank_se | sd_bram__parameterized1 | 62 | 62 | 0 | 0 | 0 | 1 | 0 | 0 |
| u_bank_t | sd_bram__parameterized2 | 484 | 484 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_c_in_bram | sd_bram | 1291 | 1291 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_cbd | sample_cbd_sync_shared | 2469 | 2469 | 0 | 0 | 3199 | 0 | 0 | 0 |
| u_comp | comp_decomp_sync | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
| u_pipe | pipeline_reg | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
| u_ct_bram | sd_bram_4 | 20 | 20 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_dkp_bram | sd_bram_5 | 101 | 101 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_ek_bram | sd_bram_6 | 226 | 226 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_keccak | keccak_core | 5251 | 5251 | 0 | 0 | 1619 | 0 | 0 | 0 |
| u_ntt | ntt_core | 13498 | 13498 | 0 | 0 | 3354 | 0 | 0 | 0 |
| u_pmul | poly_mul_sync | 7392 | 7392 | 0 | 0 | 6314 | 0 | 0 | 0 |
| (u_pmul) | poly_mul_sync | 5013 | 5013 | 0 | 0 | 6314 | 0 | 0 | 0 |
| u_bc | basecase_mul | 2379 | 2379 | 0 | 0 | 0 | 0 | 0 | 0 |
| (u_bc) | basecase_mul | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul1 | barrett_mul | 969 | 969 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul2 | barrett_mul_7 | 118 | 118 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul3 | barrett_mul_8 | 561 | 561 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul4 | barrett_mul_9 | 549 | 549 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul_zeta | barrett_mul_10 | 130 | 130 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_sha3 | sha3_top_shared | 1983 | 1983 | 0 | 0 | 2388 | 0 | 0 | 0 |
| u_snt | sample_ntt_sync_shared | 1433 | 1433 | 0 | 0 | 1669 | 0 | 0 | 0 |
| u_prng_axi_slave | prng_axi_slave | 502 | 502 | 0 | 0 | 338 | 0 | 0 | 0 |
| u_matmul_axi_slave | matmul_axi_slave | 9974 | 9792 | 176 | 6 | 3208 | 0 | 0 | 0 |
| (u_matmul_axi_slave) | matmul_axi_slave | 5758 | 5576 | 176 | 6 | 2440 | 0 | 0 | 0 |
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1086 | 1086 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[1].u_mult | pipelined_mult_32x32_1 | 1022 | 1022 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[2].u_mult | pipelined_mult_32x32_2 | 1086 | 1086 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[3].u_mult | pipelined_mult_32x32_3 | 1022 | 1022 | 0 | 0 | 192 | 0 | 0 | 0 |
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1823 | 1823 | 0 | 0 | 1476 | 0 | 1 | 0 |
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 605 | 605 | 0 | 0 | 1180 | 0 | 0 | 0 |
| u_core_engine | snix_axi_mm2mm | 1218 | 1218 | 0 | 0 | 296 | 0 | 1 | 0 |
| (u_core_engine) | snix_axi_mm2mm | 776 | 776 | 0 | 0 | 243 | 0 | 0 | 0 |
| axis_fifo_u0 | snix_axis_fifo | 442 | 442 | 0 | 0 | 53 | 0 | 1 | 0 |
| u_fifo | snix_sync_fifo | 442 | 442 | 0 | 0 | 53 | 0 | 1 | 0 |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+

438
fpga/vivado_reports_impl/routed_clock_utilization.rpt
View File

@@ -1,438 +0,0 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:46:27 2026
| Host : fedora running 64-bit unknown
| Command : report_clock_utilization -file ./vivado_reports_impl/routed_clock_utilization.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
| Design State : Routed
---------------------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Device Cell Placement Summary for Global Clock g1
8. Device Cell Placement Summary for Global Clock g2
9. Device Cell Placement Summary for Global Clock g3
10. Device Cell Placement Summary for Global Clock g4
11. Clock Region Cell Placement per Global Clock: Region X0Y0
12. Clock Region Cell Placement per Global Clock: Region X1Y0
13. Clock Region Cell Placement per Global Clock: Region X0Y1
14. Clock Region Cell Placement per Global Clock: Region X1Y1
15. Clock Region Cell Placement per Global Clock: Region X0Y2
16. Clock Region Cell Placement per Global Clock: Region X1Y2
17. Clock Region Cell Placement per Global Clock: Region X0Y3
18. Clock Region Cell Placement per Global Clock: Region X1Y3
19. Clock Region Cell Placement per Global Clock: Region X0Y4
20. Clock Region Cell Placement per Global Clock: Region X1Y4
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 5 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 120 | 0 | 0 | 0 |
| BUFIO | 0 | 40 | 0 | 0 | 0 |
| BUFMR | 0 | 20 | 0 | 0 | 0 |
| BUFR | 0 | 40 | 0 | 0 | 0 |
| MMCM | 0 | 10 | 0 | 0 | 0 |
| PLL | 1 | 10 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 8 | 23490 | 0 | | | r_wb_reg[7]_i_3/O | u_mlkem_axi_slave/mlkem_clk |
| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 7 | 10620 | 1 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/clkout2_buf/O | pll_clk.u_clk_pll/inst/sys_clk |
| g2 | src1 | BUFG/O | None | BUFGCTRL_X0Y17 | n/a | 4 | 5859 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/clkout1_buf/O | pll_clk.u_clk_pll/inst/cpu_clk |
| g3 | src1 | BUFG/O | None | BUFGCTRL_X0Y18 | n/a | 1 | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkf_buf/O | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
| g4 | src2 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 10 | 0 | 28783 | n/a | n/a | pll_clk.u_rst_sys/p_0_in_BUFG_inst/O | pll_clk.u_rst_sys/p_0_in_BUFG |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
| src0 | g0 | FDCE/Q | None | SLICE_X84Y146 | X1Y2 | 1 | 1 | | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg/Q | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg_0 |
| src1 | g3 | PLLE2_ADV/CLKFBOUT | None | PLLE2_ADV_X0Y3 | X0Y3 | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT | pll_clk.u_clk_pll/inst/clkfbout_clk_pll |
| src1 | g2 | PLLE2_ADV/CLKOUT0 | None | PLLE2_ADV_X0Y3 | X0Y3 | 1 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll |
| src1 | g1 | PLLE2_ADV/CLKOUT1 | None | PLLE2_ADV_X0Y3 | X0Y3 | 1 | 0 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 | pll_clk.u_clk_pll/inst/sys_clk_clk_pll |
| src2 | g4 | LUT1/O | None | SLICE_X132Y68 | X1Y1 | 1 | 0 | | | pll_clk.u_rst_sys/r_wb[7]_i_4/O | pll_clk.u_rst_sys/p_0_in |
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 5680 | 2700 | 1523 | 800 | 8 | 60 | 0 | 30 | 0 | 60 |
| X1Y0 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 922 | 2500 | 677 | 800 | 0 | 40 | 6 | 20 | 0 | 40 |
| X0Y1 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 8433 | 4200 | 2794 | 1400 | 1 | 100 | 0 | 50 | 0 | 100 |
| X1Y1 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 6621 | 4000 | 2851 | 1400 | 3 | 80 | 2 | 40 | 0 | 80 |
| X0Y2 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3500 | 3600 | 1397 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
| X1Y2 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4349 | 4000 | 1624 | 1400 | 1 | 80 | 2 | 40 | 0 | 80 |
| X0Y3 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 5614 | 3600 | 2576 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
| X1Y3 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2775 | 4000 | 1183 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
| X0Y4 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 1 | 0 | 50 | 0 | 50 | 671 | 2550 | 155 | 750 | 0 | 50 | 0 | 25 | 0 | 60 |
| X1Y4 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 54 | 2500 | 18 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 2 | 2 |
| Y3 | 4 | 2 |
| Y2 | 3 | 3 |
| Y1 | 4 | 4 |
| Y0 | 3 | 3 |
+----+----+----+
6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
| g0 | BUFG/O | n/a | | | | 23482 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+-------+-------+
| | X0 | X1 |
+----+-------+-------+
| Y4 | 671 | 54 |
| Y3 | 5614 | 2775 |
| Y2 | 2763 | 4352 |
| Y1 | 1435 | 5818 |
| Y0 | 0 | 0 |
+----+-------+-------+
7. Device Cell Placement Summary for Global Clock g1
----------------------------------------------------
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
| g1 | BUFG/O | n/a | sys_clk | 20.000 | {0.000 10.000} | 10556 | 1 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+-------+-------+
| | X0 | X1 |
+----+-------+-------+
| Y4 | 0 | 0 |
| Y3 | 1 | 0 |
| Y2 | 737 | 1 |
| Y1 | 6977 | 1518 |
| Y0 | 174 | 1149 |
+----+-------+-------+
8. Device Cell Placement Summary for Global Clock g2
----------------------------------------------------
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
| g2 | BUFG/O | n/a | cpu_clk | 30.323 | {0.000 15.161} | 5716 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+-------+-----+
| | X0 | X1 |
+----+-------+-----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 86 | 9 |
| Y0 | 5526 | 95 |
+----+-------+-----+
9. Device Cell Placement Summary for Global Clock g3
----------------------------------------------------
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
| g3 | BUFG/O | n/a | clkfbout_clk_pll | 20.000 | {0.000 10.000} | 0 | 0 | 1 | 0 | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 1 | 0 |
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
10. Device Cell Placement Summary for Global Clock g4
-----------------------------------------------------
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------+
| g4 | BUFG/O | n/a | | | | 28783 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+-------+-------+
| | X0 | X1 |
+----+-------+-------+
| Y4 | 671 | 54 |
| Y3 | 5614 | 2775 |
| Y2 | 3295 | 4349 |
| Y1 | 5550 | 6266 |
| Y0 | 61 | 148 |
+----+-------+-------+
11. Clock Region Cell Placement per Global Clock: Region X0Y0
-------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
| g1 | n/a | BUFG/O | None | 174 | 0 | 174 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
| g2 | n/a | BUFG/O | None | 5526 | 0 | 5506 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
| g4 | n/a | BUFG/O | None | 0 | 61 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
12. Clock Region Cell Placement per Global Clock: Region X1Y0
-------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+--------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+--------------------------------+
| g1 | n/a | BUFG/O | None | 1149 | 0 | 827 | 316 | 6 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
| g2 | n/a | BUFG/O | None | 95 | 0 | 95 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
| g4 | n/a | BUFG/O | None | 0 | 148 | 148 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+--------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
13. Clock Region Cell Placement per Global Clock: Region X0Y1
-------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
| g0 | n/a | BUFG/O | None | 1435 | 0 | 1435 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
| g1 | n/a | BUFG/O | None | 6977 | 0 | 6912 | 62 | 1 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
| g2 | n/a | BUFG/O | None | 86 | 0 | 86 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
| g4 | n/a | BUFG/O | None | 0 | 5550 | 5550 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
14. Clock Region Cell Placement per Global Clock: Region X1Y1
-------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
| g0 | n/a | BUFG/O | None | 5818 | 0 | 5814 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
| g1 | n/a | BUFG/O | None | 1518 | 0 | 798 | 716 | 3 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
| g2 | n/a | BUFG/O | None | 9 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
| g4 | n/a | BUFG/O | None | 0 | 6266 | 6266 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
15. Clock Region Cell Placement per Global Clock: Region X0Y2
-------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
| g0 | n/a | BUFG/O | None | 2763 | 0 | 2763 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
| g1 | n/a | BUFG/O | None | 737 | 0 | 737 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
| g4 | n/a | BUFG/O | None | 0 | 3295 | 3295 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
16. Clock Region Cell Placement per Global Clock: Region X1Y2
-------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
| g0 | n/a | BUFG/O | None | 4352 | 0 | 4348 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
| g1 | n/a | BUFG/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
| g4 | n/a | BUFG/O | None | 0 | 4349 | 4349 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
17. Clock Region Cell Placement per Global Clock: Region X0Y3
-------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+---------------------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+---------------------------------------------+
| g0 | n/a | BUFG/O | None | 5614 | 0 | 5614 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
| g1 | n/a | BUFG/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
| g3 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
| g4 | n/a | BUFG/O | None | 0 | 5614 | 5614 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+---------------------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
18. Clock Region Cell Placement per Global Clock: Region X1Y3
-------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------+
| g0 | n/a | BUFG/O | None | 2775 | 0 | 2775 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
| g4 | n/a | BUFG/O | None | 0 | 2775 | 2775 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
19. Clock Region Cell Placement per Global Clock: Region X0Y4
-------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------------------+
| g0 | n/a | BUFG/O | None | 671 | 0 | 671 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
| g4 | n/a | BUFG/O | None | 0 | 671 | 671 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
20. Clock Region Cell Placement per Global Clock: Region X1Y4
-------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------+
| g0 | n/a | BUFG/O | None | 54 | 0 | 54 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
| g4 | n/a | BUFG/O | None | 0 | 54 | 54 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of BUFG Primitives
set_property LOC BUFGCTRL_X0Y1 [get_cells r_wb_reg[7]_i_3]
set_property LOC BUFGCTRL_X0Y0 [get_cells pll_clk.u_rst_sys/p_0_in_BUFG_inst]
set_property LOC BUFGCTRL_X0Y16 [get_cells pll_clk.u_clk_pll/inst/clkout2_buf]
set_property LOC BUFGCTRL_X0Y17 [get_cells pll_clk.u_clk_pll/inst/clkout1_buf]
set_property LOC BUFGCTRL_X0Y18 [get_cells pll_clk.u_clk_pll/inst/clkf_buf]
# Location of IO Primitives which is load of clock spine
set_property LOC IOB_X0Y173 [get_cells video_clk_OBUF_inst]
# Location of clock ports
set_property LOC IOB_X0Y176 [get_ports clk]
# Clock net "u_mlkem_axi_slave/mlkem_clk" driven by instance "r_wb_reg[7]_i_3" located at site "BUFGCTRL_X0Y1"
#startgroup
create_pblock {CLKAG_u_mlkem_axi_slave/mlkem_clk}
add_cells_to_pblock [get_pblocks {CLKAG_u_mlkem_axi_slave/mlkem_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="u_mlkem_axi_slave/mlkem_clk"}]]]
resize_pblock [get_pblocks {CLKAG_u_mlkem_axi_slave/mlkem_clk}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
#endgroup
# Clock net "pll_clk.u_rst_sys/p_0_in_BUFG" driven by instance "pll_clk.u_rst_sys/p_0_in_BUFG_inst" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock {CLKAG_pll_clk.u_rst_sys/p_0_in_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_pll_clk.u_rst_sys/p_0_in_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pll_clk.u_rst_sys/p_0_in_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_pll_clk.u_rst_sys/p_0_in_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
#endgroup
# Clock net "pll_clk.u_clk_pll/inst/sys_clk" driven by instance "pll_clk.u_clk_pll/inst/clkout2_buf" located at site "BUFGCTRL_X0Y16"
#startgroup
create_pblock {CLKAG_pll_clk.u_clk_pll/inst/sys_clk}
add_cells_to_pblock [get_pblocks {CLKAG_pll_clk.u_clk_pll/inst/sys_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=video_clk_OBUF_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pll_clk.u_clk_pll/inst/sys_clk"}]]]
resize_pblock [get_pblocks {CLKAG_pll_clk.u_clk_pll/inst/sys_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup
# Clock net "pll_clk.u_clk_pll/inst/cpu_clk" driven by instance "pll_clk.u_clk_pll/inst/clkout1_buf" located at site "BUFGCTRL_X0Y17"
#startgroup
create_pblock {CLKAG_pll_clk.u_clk_pll/inst/cpu_clk}
add_cells_to_pblock [get_pblocks {CLKAG_pll_clk.u_clk_pll/inst/cpu_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pll_clk.u_clk_pll/inst/cpu_clk"}]]]
resize_pblock [get_pblocks {CLKAG_pll_clk.u_clk_pll/inst/cpu_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
#endgroup

718
fpga/vivado_reports_impl/routed_io.rpt
View File

@@ -1,718 +0,0 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:46:27 2026
| Host : fedora running 64-bit unknown
| Command : report_io -file ./vivado_reports_impl/routed_io.rpt
| Design : soc_top
| Device : xc7a200t
| Speed File : -1
| Package : fbg676
| Package Version : FINAL 2012-06-20
| Package Pin Delay Version : FINAL VERS. 2.0 2012-06-20
-------------------------------------------------------------------------------------------------
IO Information
Table of Contents
-----------------
1. Summary
2. IO Assignments by Package Pin
1. Summary
----------
+---------------+
| Total User IO |
+---------------+
| 202 |
+---------------+
2. IO Assignments by Package Pin
--------------------------------
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| A1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| A2 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| A3 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| A4 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| A5 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| A6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A7 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | |
| A8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A9 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | |
| A10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A11 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | |
| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A13 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | |
| A14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A15 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | |
| A16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A17 | dpy1[0] | High Range | IO_L9P_T1_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A18 | leds[11] | High Range | IO_L9N_T1_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A19 | dpy0[3] | High Range | IO_L10N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A20 | leds[14] | High Range | IO_L15N_T2_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| A22 | leds[13] | High Range | IO_L17N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A23 | leds[9] | High Range | IO_L21P_T3_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A24 | leds[2] | High Range | IO_L21N_T3_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A25 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| A26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA1 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| AA2 | | High Range | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA3 | | High Range | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA4 | | High Range | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA5 | | High Range | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA7 | | High Range | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA8 | | High Range | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA10 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AA11 | | | MGTREFCLK1P_213 | Gigabit | | | | | | | | | | | | | | | |
| AA12 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AA13 | | | MGTREFCLK0P_213 | Gigabit | | | | | | | | | | | | | | | |
| AA14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA15 | ext_ram_data[23] | High Range | IO_L23N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA17 | ext_ram_addr[8] | High Range | IO_L19P_T3_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA18 | ext_ram_addr[7] | High Range | IO_L17N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA19 | ext_ram_data[30] | High Range | IO_L13P_T2_MRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA20 | | High Range | IO_L12P_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
| AA21 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| AA22 | base_ram_addr[14] | High Range | IO_L8P_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA23 | base_ram_addr[11] | High Range | IO_L8N_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA24 | base_ram_data[8] | High Range | IO_L7P_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA25 | ext_ram_addr[10] | High Range | IO_L5N_T0_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AA26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB1 | | High Range | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB2 | | High Range | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB4 | | High Range | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB5 | | High Range | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB6 | | High Range | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
| AB8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB11 | | | MGTREFCLK1N_213 | Gigabit | | | | | | | | | | | | | | | |
| AB12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB13 | | | MGTREFCLK0N_213 | Gigabit | | | | | | | | | | | | | | | |
| AB14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB15 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | |
| AB16 | ext_ram_data[16] | High Range | IO_L22P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB17 | ext_ram_data[18] | High Range | IO_L19N_T3_VREF_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB18 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| AB19 | ext_ram_oe_n | High Range | IO_L13N_T2_MRCC_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB20 | | High Range | IO_L12N_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
| AB21 | ext_ram_data[27] | High Range | IO_L11P_T1_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB22 | ext_ram_be_n[3] | High Range | IO_0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB24 | base_ram_addr[10] | High Range | IO_L9P_T1_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB25 | ext_ram_addr[12] | High Range | IO_L7N_T1_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AB26 | ext_ram_addr[11] | High Range | IO_L3P_T0_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC1 | | High Range | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC2 | | High Range | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC3 | | High Range | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC4 | | High Range | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC5 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| AC6 | | High Range | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AC7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AC8 | | | MGTPTXP2_213 | Gigabit | | | | | | | | | | | | | | | |
| AC9 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AC10 | | | MGTPTXP0_213 | Gigabit | | | | | | | | | | | | | | | |
| AC11 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AC12 | | | MGTPRXP0_213 | Gigabit | | | | | | | | | | | | | | | |
| AC13 | | | MGTAVCC_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AC14 | | | MGTPRXP2_213 | Gigabit | | | | | | | | | | | | | | | |
| AC15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AC16 | ext_ram_data[21] | High Range | IO_L22N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC17 | ext_ram_data[25] | High Range | IO_L20P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC18 | ext_ram_data[19] | High Range | IO_L15P_T2_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC19 | ext_ram_data[17] | High Range | IO_L14P_T2_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AC21 | ext_ram_data[29] | High Range | IO_L11N_T1_SRCC_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC22 | ext_ram_addr[5] | High Range | IO_L2P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC23 | ext_ram_data[31] | High Range | IO_L2N_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC24 | ext_ram_addr[14] | High Range | IO_L9N_T1_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AC25 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| AC26 | ext_ram_addr[13] | High Range | IO_L3N_T0_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD1 | | High Range | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AD2 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| AD3 | | High Range | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| AD4 | | High Range | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AD5 | | High Range | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AD6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD7 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AD8 | | | MGTPTXN2_213 | Gigabit | | | | | | | | | | | | | | | |
| AD9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD10 | | | MGTPTXN0_213 | Gigabit | | | | | | | | | | | | | | | |
| AD11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD12 | | | MGTPRXN0_213 | Gigabit | | | | | | | | | | | | | | | |
| AD13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD14 | | | MGTPRXN2_213 | Gigabit | | | | | | | | | | | | | | | |
| AD15 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AD16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AD17 | ext_ram_data[24] | High Range | IO_L20N_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD18 | ext_ram_data[20] | High Range | IO_L15N_T2_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD19 | ext_ram_we_n | High Range | IO_L14N_T2_SRCC_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD20 | ext_ram_data[26] | High Range | IO_L10P_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD21 | ext_ram_data[28] | High Range | IO_L7P_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD22 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| AD23 | ext_ram_ce_n | High Range | IO_L6P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD24 | ext_ram_be_n[2] | High Range | IO_L6N_T0_VREF_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD25 | ext_ram_addr[3] | High Range | IO_L4P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AD26 | ext_ram_addr[4] | High Range | IO_L4N_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE1 | | High Range | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AE2 | | High Range | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| AE3 | | High Range | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AE4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AE5 | | High Range | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AE6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AE7 | | | MGTPTXP3_213 | Gigabit | | | | | | | | | | | | | | | |
| AE8 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AE9 | | | MGTPTXP1_213 | Gigabit | | | | | | | | | | | | | | | |
| AE10 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AE11 | | | MGTPRXP3_213 | Gigabit | | | | | | | | | | | | | | | |
| AE12 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AE13 | | | MGTPRXP1_213 | Gigabit | | | | | | | | | | | | | | | |
| AE14 | | | MGTAVTT_G10 | Gigabit Power | | | | | | | | | | | | | | | |
| AE15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AE16 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
| AE17 | ext_ram_addr[16] | High Range | IO_L18P_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE18 | ext_ram_addr[18] | High Range | IO_L16P_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE19 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| AE20 | ext_ram_data[6] | High Range | IO_L10N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE21 | ext_ram_data[5] | High Range | IO_L7N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE22 | ext_ram_data[3] | High Range | IO_L9P_T1_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE23 | ext_ram_data[1] | High Range | IO_L5P_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AE25 | ext_ram_addr[1] | High Range | IO_L1P_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AE26 | ext_ram_addr[2] | High Range | IO_L1N_T0_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF2 | | High Range | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| AF3 | | High Range | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AF4 | | High Range | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AF5 | | High Range | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| AF6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF7 | | | MGTPTXN3_213 | Gigabit | | | | | | | | | | | | | | | |
| AF8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF9 | | | MGTPTXN1_213 | Gigabit | | | | | | | | | | | | | | | |
| AF10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF11 | | | MGTPRXN3_213 | Gigabit | | | | | | | | | | | | | | | |
| AF12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF13 | | | MGTPRXN1_213 | Gigabit | | | | | | | | | | | | | | | |
| AF14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF15 | | | MGTRREF_213 | Gigabit | | | | | | | | | | | | | | | |
| AF16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF17 | ext_ram_addr[15] | High Range | IO_L18N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF18 | ext_ram_addr[17] | High Range | IO_L16N_T2_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF19 | ext_ram_addr[19] | High Range | IO_L8P_T1_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF20 | ext_ram_data[7] | High Range | IO_L8N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AF22 | ext_ram_data[4] | High Range | IO_L9N_T1_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF23 | ext_ram_data[2] | High Range | IO_L5N_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF24 | ext_ram_data[0] | High Range | IO_L3P_T0_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF25 | ext_ram_addr[0] | High Range | IO_L3N_T0_DQS_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| AF26 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| B1 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| B2 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B4 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| B5 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| B6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B7 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | |
| B8 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| B9 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | |
| B10 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| B11 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | |
| B12 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| B13 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | |
| B14 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B17 | dpy0[6] | High Range | IO_L7N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| B19 | dpy0[0] | High Range | IO_L10P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B20 | leds[15] | High Range | IO_L15P_T2_DQS_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B21 | dpy0[2] | High Range | IO_L16N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B22 | leds[7] | High Range | IO_L17P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B24 | leds[0] | High Range | IO_L23N_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B25 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B26 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| C1 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| C2 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| C3 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| C4 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| C5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C7 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| C8 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | |
| C9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C10 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | |
| C11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C12 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | |
| C13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C14 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | |
| C15 | | | MGTAVTT_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C17 | dpy0[7] | High Range | IO_L7P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C18 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| C19 | dpy0[5] | High Range | IO_L13N_T2_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C21 | leds[5] | High Range | IO_L16P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C22 | leds[4] | High Range | IO_L19P_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C23 | leds[8] | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C24 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| C25 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| C26 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| D1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| D2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| D3 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| D4 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| D5 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| D6 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D8 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | |
| D9 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| D10 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | |
| D11 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| D12 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | |
| D13 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| D14 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | |
| D15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D16 | dpy1[1] | High Range | IO_L8N_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D18 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| D19 | dpy0[1] | High Range | IO_L13P_T2_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D20 | leds[12] | High Range | IO_L14N_T2_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D21 | leds[10] | High Range | IO_L18N_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| D23 | leds[3] | High Range | IO_L24P_T3_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D24 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| D25 | video_blue[1] | High Range | IO_L20N_T3_A19_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D26 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
| E1 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| E2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| E3 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E5 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| E6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E11 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | |
| E12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E13 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | |
| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E16 | dpy1[4] | High Range | IO_L8P_T1_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E17 | dpy1[2] | High Range | IO_L11P_T1_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E18 | dpy0[4] | High Range | IO_L11N_T1_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| E20 | leds[6] | High Range | IO_L14P_T2_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E21 | leds[1] | High Range | IO_L18P_T2_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E22 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | |
| E23 | video_green[1] | High Range | IO_L17N_T2_A25_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E25 | video_blue[0] | High Range | IO_L20P_T3_A20_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E26 | video_red[2] | High Range | IO_L21P_T3_DQS_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| F3 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
| F4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| F5 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| F6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| F7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| F8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F10 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| F11 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | |
| F12 | | | MGTAVCC_G11 | Gigabit Power | | | | | | | | | | | | | | | |
| F13 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | |
| F14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F15 | dpy1[6] | High Range | IO_L4N_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F16 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
| F17 | dpy1[3] | High Range | IO_L2N_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F18 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| F19 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| F20 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| F21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| F23 | video_green[2] | High Range | IO_L17P_T2_A26_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F24 | video_red[1] | High Range | IO_L19N_T3_A21_VREF_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F25 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| F26 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| G1 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| G2 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| G3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| G4 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| G5 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
| G6 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
| G7 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
| G8 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
| G9 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G14 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
| G15 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| G16 | dpy1[5] | High Range | IO_L6N_T0_VREF_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G17 | dpy1[7] | High Range | IO_L2P_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G19 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| G20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| G21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| G22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| G23 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| G24 | video_de | High Range | IO_L19P_T3_A22_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G25 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| G26 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
| H1 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| H2 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| H3 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
| H4 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
| H7 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
| H8 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
| H9 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| H10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
| H11 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
| H12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
| H13 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
| H14 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| H15 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| H16 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| H17 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | |
| H18 | UART_TX | High Range | IO_L10N_T1_AD11N_15 | BIDIR | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| H19 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
| H20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| H21 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| H22 | video_clk | High Range | IO_L13N_T2_MRCC_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| H23 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| H24 | video_vsync | High Range | IO_L16N_T2_A27_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| H25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H26 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
| J1 | dip_sw[14] | High Range | IO_L7N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J3 | dip_sw[1] | High Range | IO_L1N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| J4 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
| J5 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
| J6 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
| J8 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
| J9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| J10 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J14 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
| J15 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
| J16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
| J17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| J18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
| J19 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
| J20 | UART_RX | High Range | IO_L9N_T1_DQS_AD3N_15 | BIDIR | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| J21 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| J22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J23 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| J24 | video_hsync | High Range | IO_L16P_T2_A28_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| J25 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
| J26 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
| K1 | dip_sw[17] | High Range | IO_L7P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| K2 | dip_sw[16] | High Range | IO_L8N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| K3 | dip_sw[13] | High Range | IO_L1P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| K5 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K6 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
| K7 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
| K8 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| K15 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
| K16 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
| K17 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
| K18 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
| K19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K20 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
| K21 | clk | High Range | IO_L12P_T1_MRCC_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
| K22 | video_green[0] | High Range | IO_L18P_T2_A24_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| K23 | video_red[0] | High Range | IO_L18N_T2_A23_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| K24 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| K25 | base_ram_be_n[3] | High Range | IO_L7P_T1_D09_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| K26 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
| L1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| L2 | dip_sw[15] | High Range | IO_L11N_T1_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L3 | dip_sw[6] | High Range | IO_L8P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L4 | dip_sw[19] | High Range | IO_L3N_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L5 | dip_sw[5] | High Range | IO_L4P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L7 | dip_sw[11] | High Range | IO_L2N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| L8 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
| L9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L14 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| L15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
| L16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L17 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
| L18 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
| L19 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
| L20 | base_ram_be_n[0] | High Range | IO_L8N_T1_D12_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| L22 | base_ram_be_n[1] | High Range | IO_L11P_T1_SRCC_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L23 | base_ram_be_n[2] | High Range | IO_L11N_T1_SRCC_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L24 | base_ram_data[0] | High Range | IO_L9P_T1_DQS_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L25 | base_ram_data[1] | High Range | IO_L9N_T1_DQS_D13_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M1 | touch_btn[1] | High Range | IO_L9N_T1_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M2 | dip_sw[2] | High Range | IO_L11P_T1_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M4 | dip_sw[20] | High Range | IO_L3P_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M5 | dip_sw[12] | High Range | IO_L6N_T0_VREF_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M6 | dip_sw[8] | High Range | IO_L6P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M7 | dip_sw[10] | High Range | IO_L2P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| M12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M14 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| M15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
| M16 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| M17 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| M18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
| M19 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
| M20 | base_ram_data[21] | High Range | IO_L8P_T1_D11_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M21 | base_ram_data[17] | High Range | IO_L12P_T1_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M22 | base_ram_data[31] | High Range | IO_L12N_T1_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M24 | base_ram_data[30] | High Range | IO_L10P_T1_D14_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M25 | base_ram_data[3] | High Range | IO_L10N_T1_D15_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| M26 | base_ram_data[2] | High Range | IO_L20N_T3_A07_D23_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N1 | dip_sw[23] | High Range | IO_L9P_T1_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N2 | dip_sw[21] | High Range | IO_L12N_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N3 | dip_sw[18] | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N4 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| N5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| N6 | dip_sw[7] | High Range | IO_L5N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N7 | dip_sw[9] | High Range | IO_L5P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| N8 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
| N12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| N14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
| N15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| N16 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
| N17 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
| N18 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| N19 | base_ram_data[20] | High Range | IO_L16N_T2_A15_D31_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N21 | base_ram_data[23] | High Range | IO_L13P_T2_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N22 | base_ram_data[28] | High Range | IO_L13N_T2_MRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N23 | base_ram_data[29] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N24 | base_ram_data[22] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N25 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| N26 | base_ram_data[4] | High Range | IO_L20P_T3_A08_D24_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P1 | dip_sw[3] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| P3 | touch_btn[2] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P4 | dip_sw[4] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P5 | dip_sw[24] | High Range | IO_L19N_T3_VREF_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P6 | dip_sw[22] | High Range | IO_L19P_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| P11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
| P12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
| P15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| P16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P18 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| P19 | base_ram_data[19] | High Range | IO_L16P_T2_CSI_B_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P20 | base_ram_data[27] | High Range | IO_L14P_T2_SRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P21 | base_ram_data[16] | High Range | IO_L14N_T2_SRCC_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| P23 | base_ram_data[18] | High Range | IO_L17P_T2_A14_D30_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P24 | base_ram_data[5] | High Range | IO_L17N_T2_A13_D29_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P25 | base_ram_data[7] | High Range | IO_L19N_T3_A09_D25_VREF_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P26 | base_ram_data[6] | High Range | IO_L22N_T3_A04_D20_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R1 | dip_sw[27] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R2 | dip_sw[31] | High Range | IO_L17N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R3 | dip_sw[25] | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R5 | dip_sw[28] | High Range | IO_L20N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R6 | dip_sw[30] | High Range | IO_L23N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| R8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| R12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| R14 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
| R15 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
| R16 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
| R17 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
| R18 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
| R19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| R20 | base_ram_addr[5] | High Range | IO_L18P_T2_A12_D28_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R21 | base_ram_data[26] | High Range | IO_L18N_T2_A11_D27_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R22 | base_ram_data[25] | High Range | IO_L23N_T3_A02_D18_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R23 | base_ram_addr[6] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R25 | ext_ram_be_n[1] | High Range | IO_L19P_T3_A10_D26_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| R26 | ext_ram_be_n[0] | High Range | IO_L22P_T3_A05_D21_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T2 | touch_btn[0] | High Range | IO_L17P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T3 | dip_sw[0] | High Range | IO_L16N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T4 | dip_sw[26] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T5 | dip_sw[29] | High Range | IO_L20P_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| T7 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| T8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T14 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| T15 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| T16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| T17 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| T18 | base_ram_addr[2] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T19 | base_ram_addr[0] | High Range | IO_L17P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T20 | base_ram_oe_n | High Range | IO_L15P_T2_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T22 | base_ram_data[24] | High Range | IO_L23P_T3_A03_D19_14 | BIDIR | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T23 | base_ram_addr[7] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| T24 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| T25 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
| T26 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| U1 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| U2 | touch_btn[3] | High Range | IO_L18P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| U3 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| U4 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
| U5 | reset | High Range | IO_L21N_T3_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| U6 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| U7 | | High Range | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| U8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| U12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| U14 | | High Range | IO_L23P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U15 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U16 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U17 | base_ram_addr[4] | High Range | IO_25_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U19 | base_ram_ce_n | High Range | IO_L17N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U20 | base_ram_we_n | High Range | IO_L15N_T2_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U21 | base_ram_data[15] | High Range | IO_L13P_T2_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U22 | base_ram_addr[8] | High Range | IO_L12P_T1_MRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U23 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| U24 | ext_ram_data[15] | High Range | IO_0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U25 | ext_ram_data[13] | High Range | IO_L1P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U26 | ext_ram_data[14] | High Range | IO_L1N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V1 | | High Range | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| V2 | | High Range | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V3 | | High Range | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V4 | | High Range | IO_0_33 | User IO | | 33 | | | | | | | | | | | | | |
| V5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V6 | | High Range | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| V7 | | High Range | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| V8 | | High Range | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V9 | | High Range | IO_25_33 | User IO | | 33 | | | | | | | | | | | | | |
| V10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| V11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
| V12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V14 | | High Range | IO_L23N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| V15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V16 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| V17 | base_ram_addr[3] | High Range | IO_L24N_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V18 | base_ram_addr[1] | High Range | IO_L19P_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V19 | base_ram_addr[19] | High Range | IO_L18P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| V21 | base_ram_data[10] | High Range | IO_L13N_T2_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V22 | base_ram_data[13] | High Range | IO_L12N_T1_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V23 | base_ram_data[14] | High Range | IO_L10P_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V24 | ext_ram_data[11] | High Range | IO_L6P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V26 | ext_ram_data[12] | High Range | IO_L2P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W1 | | High Range | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W3 | | High Range | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W4 | | High Range | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W5 | | High Range | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W6 | | High Range | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W7 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| W8 | | High Range | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| W9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
| W10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
| W11 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| W14 | | High Range | IO_L24P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
| W15 | | High Range | IO_L24N_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
| W16 | | High Range | IO_25_12 | User IO | | 12 | | | | | | | | | | | | | |
| W17 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
| W18 | base_ram_addr[18] | High Range | IO_L19N_T3_VREF_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W19 | base_ram_addr[15] | High Range | IO_L18N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W20 | base_ram_addr[17] | High Range | IO_L16P_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W21 | base_ram_addr[16] | High Range | IO_L14P_T2_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W23 | base_ram_data[12] | High Range | IO_L10N_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W24 | base_ram_data[11] | High Range | IO_L6N_T0_VREF_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W25 | ext_ram_data[9] | High Range | IO_L4P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W26 | ext_ram_data[10] | High Range | IO_L2N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y1 | | High Range | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y2 | | High Range | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y3 | | High Range | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y4 | | High Range | VCCO_33 | VCCO | | 33 | | | | | any** | | | | | | | | |
| Y5 | | High Range | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y6 | | High Range | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y7 | | High Range | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y8 | | High Range | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y9 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
| Y10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y14 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
| Y15 | ext_ram_data[22] | High Range | IO_L23P_T3_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y16 | | High Range | IO_L21P_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
| Y17 | ext_ram_addr[6] | High Range | IO_L21N_T3_DQS_12 | OUTPUT | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y18 | | High Range | IO_L17P_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
| Y19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y20 | base_ram_addr[13] | High Range | IO_L16N_T2_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y21 | base_ram_addr[12] | High Range | IO_L14N_T2_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y22 | base_ram_addr[9] | High Range | IO_L11P_T1_SRCC_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y23 | base_ram_data[9] | High Range | IO_L11N_T1_SRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y24 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
| Y25 | ext_ram_addr[9] | High Range | IO_L5P_T0_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| Y26 | ext_ram_data[8] | High Range | IO_L4N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+------------+-------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
* Default value
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.

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fpga/vivado_reports_impl/routed_methodology.rpt
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fpga/vivado_reports_impl/routed_route_status.rpt
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Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 148231 :
# of nets not needing routing.......... : 49221 :
# of internally routed nets........ : 48840 :
# of nets with no loads............ : 381 :
# of routable nets..................... : 99010 :
# of fully routed nets............. : 99010 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

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fpga/vivado_reports_impl/routed_timing_summary_hold.rpt
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fpga/vivado_reports_impl/routed_timing_summary_setup.rpt
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fpga/vivado_reports_impl/routed_worst_hold_paths.rpt
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fpga/vivado_reports_impl/routed_worst_setup_paths.rpt
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fpga/vivado_reports_nodsp/clock_interaction.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 03:34:13 2026
| Host : fedora running 64-bit unknown
| Command : report_clock_interaction -file /home/fallensigh/vivado_reports_nodsp/clock_interaction.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
------------------------------------------------------------------------------------------------------------
Clock Interaction Report
Clock Interaction Table
-----------------------
WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock
From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints
----------------- ----------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- -------------------
cpu_clk cpu_clk rise - rise 2.72 0.00 0 17264 30.32 Clean Timed
cpu_clk sys_clk 0 162 Ignored Asynchronous Groups
mlkem_clk_clk_pll mlkem_clk_clk_pll rise - rise 10.81 0.00 0 74168 40.00 Clean Timed
mlkem_clk_clk_pll sys_clk rise - rise 11.25 0.00 0 61 20.00 Clean Timed
sys_clk cpu_clk 0 59 Ignored Asynchronous Groups
sys_clk mlkem_clk_clk_pll rise - rise 9.16 0.00 0 112 20.00 Clean Timed
sys_clk sys_clk rise - rise 0.17 0.00 0 23704 20.00 Clean Timed

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fpga/vivado_reports_nodsp/clocks.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 03:34:13 2026
| Host : fedora running 64-bit unknown
| Command : report_clocks -file /home/fallensigh/vivado_reports_nodsp/clocks.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
--------------------------------------------------------------------------------------
Clock Report
Attributes
P: Propagated
G: Generated
A: Auto-derived
R: Renamed
V: Virtual
I: Inverted
S: Pin phase-shifted with Latency mode
Clock Period(ns) Waveform(ns) Attributes Sources
clk 20.000 {0.000 10.000} P {clk}
clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
mlkem_clk_clk_pll 40.000 {0.000 20.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
====================================================
Generated Clocks
====================================================
Generated Clock : clkfbout_clk_pll
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk
Multiply By : 1
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
Generated Clock : cpu_clk
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 5.161 10.323}
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
Generated Clock : mlkem_clk_clk_pll
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 10.000 20.000}
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
Generated Clock : sys_clk
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk
Multiply By : 1
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
====================================================
User Uncertainty
====================================================
====================================================
User Jitter
====================================================
Clock Jitter(ns)
clk 0.200

37
fpga/vivado_reports_nodsp/design_analysis_complexity.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 03:35:00 2026
| Host : fedora running 64-bit unknown
| Command : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_nodsp/design_analysis_complexity.rpt
| Design : soc_top
| Device : xc7a200t
| Design State : Routed
-------------------------------------------------------------------------------------------------------------------------------
Report Design Analysis
Table of Contents
-----------------
1. Complexity Characteristics (Cells)
1. Complexity Characteristics (Cells)
-------------------------------------
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM |
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
| (top) | soc_top | 0.34 | 3.77 | 118528 | 801(1.2%) | 6978(10.2%) | 9384(13.7%) | 7294(10.7%) | 8477(12.4%) | 35413(51.8%) | 1175 | 16 | 39 | 6020 | 0 |
| u_axi_axil_adapter | axi_axil_adapter | 0.50 | 5.92 | 1309 | 0(0.0%) | 8(0.7%) | 43(3.8%) | 100(8.9%) | 200(17.7%) | 776(68.9%) | 0 | 0 | 0 | 0 | 0 |
| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 |
| u_cdma_matmul_bridge | cdma_matmul_bridge | 0.46 | 2.22 | 1002 | 1(0.3%) | 65(17.1%) | 39(10.3%) | 174(45.8%) | 13(3.4%) | 88(23.2%) | 0 | 0 | 0 | 0 | 0 |
| u_cpu | core_top | 0.56 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 |
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.56 | 3.75 | 74954 | 362(0.9%) | 3923(9.7%) | 6649(16.4%) | 4109(10.2%) | 4490(11.1%) | 20899(51.7%) | 1169 | 16 | 18 | 5286 | 0 |
| u_matmul_axi_slave | matmul_axi_slave | 0.63 | 3.76 | 15159 | 18(0.2%) | 1646(15.2%) | 357(3.3%) | 830(7.6%) | 974(9.0%) | 7026(64.7%) | 6 | 0 | 0 | 413 | 0 |
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.36 | 3.45 | 3680 | 136(6.5%) | 181(8.6%) | 405(19.3%) | 255(12.2%) | 342(16.3%) | 776(37.0%) | 0 | 0 | 1 | 4 | 0 |
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
* Complexity Ranges
** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal, 0.65 - 0.85 -> high, 0.85 - 1.0 -> very high
*** -* -> Not computable as cell size is very small

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fpga/vivado_reports_nodsp/design_analysis_timing.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 03:34:29 2026
| Host : fedora running 64-bit unknown
| Command : report_design_analysis -timing -file /home/fallensigh/vivado_reports_nodsp/design_analysis_timing.rpt
| Design : soc_top
| Device : xc7a200t
| Design State : Routed
-----------------------------------------------------------------------------------------------------------------------
Report Design Analysis
Table of Contents
-----------------
1. Setup Path Characteristics 1-1
1. Setup Path Characteristics 1-1
---------------------------------
+---------------------------+------------------------------------------------------+
| Characteristics | Path #1 |
+---------------------------+------------------------------------------------------+
| Requirement | 20.000 |
| Path Delay | 15.605 |
| Logic Delay | 5.343(35%) |
| Net Delay | 10.263(65%) |
| Clock Skew | -3.858 |
| Slack | 0.167 |
| Clock Relationship | Safely Timed |
| Logic Levels | 9 |
| Routes | 9 |
| Logical Path | FDRE LUT4 LUT6 LUT5 LUT6 RAMD32 LUT6 LUT5 LUT3 OBUFT |
| Start Point Clock | sys_clk |
| End Point Clock | sys_clk |
| DSP Block | None |
| BRAM | None |
| IO Crossings | 3 |
| Config Crossings | 0 |
| SLR Crossings | 0 |
| PBlocks | 0 |
| High Fanout | 130 |
| Dont Touch | 0 |
| Mark Debug | 0 |
| Start Point Pin Primitive | FDRE/C |
| End Point Pin Primitive | ext_ram_data[18] |
| Start Point Pin | FSM_sequential_ext_wr_state_reg[1]/C |
| End Point Pin | ext_ram_data[18] |
+---------------------------+------------------------------------------------------+
* Bounding box calculated as % of dimensions for the target device (436, 500)

249
fpga/vivado_reports_impl/routed_drc.rpt → fpga/vivado_reports_nodsp/drc.rpt
View File

@@ -1,9 +1,9 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:46:12 2026
| Date : Wed Jul 8 03:33:58 2026
| Host : fedora running 64-bit unknown
| Command : report_drc -file ./vivado_reports_impl/routed_drc.rpt
| Command : report_drc -file /home/fallensigh/vivado_reports_nodsp/drc.rpt
| Design : soc_top
| Device : xc7a200tfbg676-1
| Speed File : -1
@@ -24,11 +24,14 @@ Table of Contents
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 42
Violations found: 90
+-----------+----------+----------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+----------------------------+------------+
| CHECK-3 | Warning | Report rule limit reached | 2 |
| DPIP-1 | Warning | Input pipelining | 16 |
| DPOP-1 | Warning | PREG Output pipelining | 16 |
| DPOP-2 | Warning | MREG Output pipelining | 16 |
| REQP-1839 | Warning | RAMB36 async control check | 20 |
| REQP-1840 | Warning | RAMB18 async control check | 20 |
+-----------+----------+----------------------------+------------+
@@ -45,6 +48,246 @@ Report rule limit reached
REQP-1840 rule limit reached: 20 violations have been found.
Related violations: <none>
DPIP-1#1 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#2 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#3 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#4 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#5 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#6 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#7 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#8 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#9 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#10 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#11 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#12 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#13 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#14 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#15 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#16 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPOP-1#1 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#2 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#3 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#4 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#5 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#6 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#7 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#8 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#9 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#10 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#11 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#12 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#13 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#14 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#15 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#16 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-2#1 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#2 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#3 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#4 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#5 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#6 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#7 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#8 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#9 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#10 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#11 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#12 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#13 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#14 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#15 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#16 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
REQP-1839#1 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.

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fpga/vivado_reports_nodsp/high_fanout.rpt Normal file
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@@ -0,0 +1,221 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 03:34:13 2026
| Host : fedora running 64-bit unknown
| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/vivado_reports_nodsp/high_fanout.rpt
| Design : soc_top
| Device : xc7a200t
--------------------------------------------------------------------------------------------------------------------------------------------
High Fan-out Nets Information
1. Summary
----------
+---------------------------------------------------------------------------------------+--------+-------------+
| Net Name | Fanout | Driver Type |
+---------------------------------------------------------------------------------------+--------+-------------+
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1] | 24598 | LUT5 |
| pll_clk.u_clk_pll/inst/sys_clk | 10004 | BUFG |
| pll_clk.u_rst_sys/p_0_in | 4130 | LUT1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT2 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_n_0 | 1619 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0] | 1608 | LUT2 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 | 1608 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state[2]_i_3_n_0 | 1604 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sel_cbd | 1603 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 | 1601 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 | 1601 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_6_n_0 | 1601 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_7_n_0 | 1601 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1] | 1543 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2] | 1542 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1109 | LUT2 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE |
| pll_clk.u_rst_mlkem/delay_reg[1]_0 | 1069 | LUT1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0 | 936 | LUT5 |
| u_cpu/reset | 799 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0] | 769 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1] | 769 | CARRY4 |
| u_matmul_axi_slave/w_addr[2] | 724 | FDRE |
| u_cpu/u_mul/E[0] | 716 | LUT1 |
| u_matmul_axi_slave/w_addr[3] | 628 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1 | 528 | LUT6 |
| u_matmul_axi_slave/current_r_offset[2] | 522 | LUT5 |
| u_matmul_axi_slave/current_r_offset[3] | 520 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0] | 516 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1] | 516 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[0]_rep_2[0] | 512 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[2] | 390 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2] | 385 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_vld_reg_n_0 | 370 | FDCE |
| u_cpu/wb_stage/w_index[0] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[1] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[2] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[3] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[4] | 358 | LUT6 |
| u_matmul_axi_slave/acc_idx_d4[0] | 354 | FDRE |
| u_matmul_axi_slave/acc_idx_d4[1] | 354 | FDRE |
| u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE |
| u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE |
| u_cpu/wb_stage/we_0 | 324 | LUT4 |
| u_matmul_axi_slave/w_addr[4] | 317 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 290 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3] | 284 | FDCE |
| u_matmul_axi_slave/cur_bank_reg_n_0 | 277 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 263 | RAMB18E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 263 | RAMB18E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 262 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 261 | RAMB18E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 261 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[4] | 260 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 259 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 259 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 259 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 259 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 259 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 259 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 259 | RAMB36E1 |
| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0 | 259 | FDRE |
| u_matmul_axi_slave/pipe_cnt_reg[1]_rep_n_0 | 257 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[0] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[10] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[11] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[1] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[2] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[5] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[6] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[7] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[8] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[9] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_active_reg_rep__7[0] | 256 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 |
| u_matmul_axi_slave/m_in_b[0][31]_i_1_n_0 | 256 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 |
| u_matmul_axi_slave/w_addr[5] | 246 | FDRE |
| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT3 |
| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 |
| u_cpu/mem_stage/E[0] | 234 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 234 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 234 | FDCE |
| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 229 | LUT3 |
| u_matmul_axi_slave/m_in_b[0][31]_i_7_n_0 | 228 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 227 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 224 | LUT4 |
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 |
| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 |
| u_cpu/u_csr/tlbw_r_tlbidx[2] | 210 | FDRE |
| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0] | 203 | FDRE |
| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[1] | 203 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[6] | 200 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 200 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[3] | 197 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2] | 196 | FDCE |
| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 196 | LUT6 |
| u_cpu/wb_stage/Q[33] | 194 | FDRE |
| u_cpu/wb_stage/Q[34] | 194 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5] | 194 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3] | 193 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r_reg[4]_rep_n_0 | 191 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[2] | 187 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[3] | 187 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 187 | FDCE |
| u_matmul_axi_slave/current_r_offset[4] | 187 | LUT5 |
| u_matmul_axi_slave/s_axi_wready_reg_1 | 181 | LUT3 |
| u_cpu/wb_stage/ws_valid_reg_0 | 180 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3] | 180 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 177 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[0] | 176 | FDCE |
| u_matmul_axi_slave/p_0_in__0 | 176 | LUT4 |
| u_matmul_axi_slave/p_0_in__0__0 | 176 | LUT4 |
| u_cpu/wb_stage/Q[37] | 173 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7] | 173 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]_i_4_n_7 | 171 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[127]_i_2_n_0 | 169 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[383]_i_2_n_0 | 169 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[639]_i_2_n_0 | 169 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[895]_i_2_n_0 | 169 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 169 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5] | 166 | FDCE |
| u_cpu/wb_stage/Q[32] | 164 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 164 | FDCE |
| u_cpu/wb_stage/Q[35] | 163 | FDRE |
| u_cpu/wb_stage/Q[36] | 162 | FDRE |
| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0 | 161 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1023]_i_2_n_0 | 160 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[255]_i_2_n_0 | 160 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[511]_i_2_n_0 | 160 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[767]_i_2_n_0 | 160 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3] | 155 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[6] | 153 | FDCE |
| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 153 | LUT3 |
| u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0 | 151 | FDRE |
| u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1 | 150 | CARRY4 |
| u_cpu/dcache/awaddr[31]_i_3_n_0 | 148 | LUT2 |
| u_cpu/dcache/awaddr[31]_i_4_n_0 | 148 | LUT2 |
| u_matmul_axi_slave/s_axi_wready_reg_0 | 148 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0] | 145 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_63_n_0 | 144 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6] | 143 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 143 | FDCE |
| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0 | 143 | LUT3 |
| u_matmul_axi_slave/pipe_cnt[3]_i_4_n_0 | 143 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep_n_0 | 142 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4] | 141 | FDCE |
| u_cpu/dcache/write_buffer_state | 140 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_reg_rep__6_n_0 | 140 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5] | 140 | FDCE |
| u_cpu/u_csr/tlbw_r_tlbidx[0] | 139 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_37_n_0 | 139 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep__3_n_0 | 139 | FDCE |
+---------------------------------------------------------------------------------------+--------+-------------+

542
fpga/vivado_reports_nodsp/methodology.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 03:34:05 2026
| Host : fedora running 64-bit unknown
| Command : report_methodology -file /home/fallensigh/vivado_reports_nodsp/methodology.rpt
| Design : soc_top
| Device : xc7a200tfbg676-1
| Speed File : -1
| Design State : Fully Routed
------------------------------------------------------------------------------------------------
Report Methodology
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: impl_1
Design limits: <entire design considered>
Max violations: <unlimited>
Violations found: 99
+-----------+----------+-------------------------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+-------------------------------------------------------------------+------------+
| LUTAR-1 | Warning | LUT drives async reset alert | 1 |
| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 8 |
| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 1 |
| SYNTH-16 | Warning | Address collision | 8 |
| TIMING-10 | Warning | Missing property on synchronizer | 1 |
| TIMING-18 | Warning | Missing input or output delay | 76 |
| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 2 |
| XDCC-1 | Warning | Scoped Clock constraint overwritten with the same name | 1 |
| XDCC-7 | Warning | Scoped Clock constraint overwritten on the same source | 1 |
+-----------+----------+-------------------------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
LUTAR-1#1 Warning
LUT drives async reset alert
LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24584 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>
SYNTH-5#1 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#2 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#3 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#4 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#5 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#6 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#7 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-5#8 Warning
Mapped onto distributed RAM because of timing constraints
The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
Related violations: <none>
SYNTH-6#1 Warning
Timing of a block RAM might be sub-optimal
The timing for the instance u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>
SYNTH-16#1 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#2 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#3 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#4 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#5 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#6 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#7 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
SYNTH-16#8 Warning
Address collision
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
Related violations: <none>
TIMING-10#1 Warning
Missing property on synchronizer
One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage
Related violations: <none>
TIMING-18#1 Warning
Missing input or output delay
An input delay is missing on UART_RX relative to clock(s) clk
Related violations: <none>
TIMING-18#2 Warning
Missing input or output delay
An input delay is missing on UART_TX relative to clock(s) clk
Related violations: <none>
TIMING-18#3 Warning
Missing input or output delay
An input delay is missing on dip_sw[0] relative to clock(s) clk
Related violations: <none>
TIMING-18#4 Warning
Missing input or output delay
An input delay is missing on dip_sw[10] relative to clock(s) clk
Related violations: <none>
TIMING-18#5 Warning
Missing input or output delay
An input delay is missing on dip_sw[11] relative to clock(s) clk
Related violations: <none>
TIMING-18#6 Warning
Missing input or output delay
An input delay is missing on dip_sw[12] relative to clock(s) clk
Related violations: <none>
TIMING-18#7 Warning
Missing input or output delay
An input delay is missing on dip_sw[13] relative to clock(s) clk
Related violations: <none>
TIMING-18#8 Warning
Missing input or output delay
An input delay is missing on dip_sw[14] relative to clock(s) clk
Related violations: <none>
TIMING-18#9 Warning
Missing input or output delay
An input delay is missing on dip_sw[15] relative to clock(s) clk
Related violations: <none>
TIMING-18#10 Warning
Missing input or output delay
An input delay is missing on dip_sw[16] relative to clock(s) clk
Related violations: <none>
TIMING-18#11 Warning
Missing input or output delay
An input delay is missing on dip_sw[17] relative to clock(s) clk
Related violations: <none>
TIMING-18#12 Warning
Missing input or output delay
An input delay is missing on dip_sw[18] relative to clock(s) clk
Related violations: <none>
TIMING-18#13 Warning
Missing input or output delay
An input delay is missing on dip_sw[19] relative to clock(s) clk
Related violations: <none>
TIMING-18#14 Warning
Missing input or output delay
An input delay is missing on dip_sw[1] relative to clock(s) clk
Related violations: <none>
TIMING-18#15 Warning
Missing input or output delay
An input delay is missing on dip_sw[20] relative to clock(s) clk
Related violations: <none>
TIMING-18#16 Warning
Missing input or output delay
An input delay is missing on dip_sw[21] relative to clock(s) clk
Related violations: <none>
TIMING-18#17 Warning
Missing input or output delay
An input delay is missing on dip_sw[22] relative to clock(s) clk
Related violations: <none>
TIMING-18#18 Warning
Missing input or output delay
An input delay is missing on dip_sw[23] relative to clock(s) clk
Related violations: <none>
TIMING-18#19 Warning
Missing input or output delay
An input delay is missing on dip_sw[24] relative to clock(s) clk
Related violations: <none>
TIMING-18#20 Warning
Missing input or output delay
An input delay is missing on dip_sw[25] relative to clock(s) clk
Related violations: <none>
TIMING-18#21 Warning
Missing input or output delay
An input delay is missing on dip_sw[26] relative to clock(s) clk
Related violations: <none>
TIMING-18#22 Warning
Missing input or output delay
An input delay is missing on dip_sw[27] relative to clock(s) clk
Related violations: <none>
TIMING-18#23 Warning
Missing input or output delay
An input delay is missing on dip_sw[28] relative to clock(s) clk
Related violations: <none>
TIMING-18#24 Warning
Missing input or output delay
An input delay is missing on dip_sw[29] relative to clock(s) clk
Related violations: <none>
TIMING-18#25 Warning
Missing input or output delay
An input delay is missing on dip_sw[2] relative to clock(s) clk
Related violations: <none>
TIMING-18#26 Warning
Missing input or output delay
An input delay is missing on dip_sw[30] relative to clock(s) clk
Related violations: <none>
TIMING-18#27 Warning
Missing input or output delay
An input delay is missing on dip_sw[31] relative to clock(s) clk
Related violations: <none>
TIMING-18#28 Warning
Missing input or output delay
An input delay is missing on dip_sw[3] relative to clock(s) clk
Related violations: <none>
TIMING-18#29 Warning
Missing input or output delay
An input delay is missing on dip_sw[4] relative to clock(s) clk
Related violations: <none>
TIMING-18#30 Warning
Missing input or output delay
An input delay is missing on dip_sw[5] relative to clock(s) clk
Related violations: <none>
TIMING-18#31 Warning
Missing input or output delay
An input delay is missing on dip_sw[6] relative to clock(s) clk
Related violations: <none>
TIMING-18#32 Warning
Missing input or output delay
An input delay is missing on dip_sw[7] relative to clock(s) clk
Related violations: <none>
TIMING-18#33 Warning
Missing input or output delay
An input delay is missing on dip_sw[8] relative to clock(s) clk
Related violations: <none>
TIMING-18#34 Warning
Missing input or output delay
An input delay is missing on dip_sw[9] relative to clock(s) clk
Related violations: <none>
TIMING-18#35 Warning
Missing input or output delay
An input delay is missing on touch_btn[0] relative to clock(s) clk
Related violations: <none>
TIMING-18#36 Warning
Missing input or output delay
An input delay is missing on touch_btn[1] relative to clock(s) clk
Related violations: <none>
TIMING-18#37 Warning
Missing input or output delay
An input delay is missing on touch_btn[2] relative to clock(s) clk
Related violations: <none>
TIMING-18#38 Warning
Missing input or output delay
An input delay is missing on touch_btn[3] relative to clock(s) clk
Related violations: <none>
TIMING-18#39 Warning
Missing input or output delay
An output delay is missing on dpy0[0] relative to clock(s) clk
Related violations: <none>
TIMING-18#40 Warning
Missing input or output delay
An output delay is missing on dpy0[1] relative to clock(s) clk
Related violations: <none>
TIMING-18#41 Warning
Missing input or output delay
An output delay is missing on dpy0[2] relative to clock(s) clk
Related violations: <none>
TIMING-18#42 Warning
Missing input or output delay
An output delay is missing on dpy0[3] relative to clock(s) clk
Related violations: <none>
TIMING-18#43 Warning
Missing input or output delay
An output delay is missing on dpy0[4] relative to clock(s) clk
Related violations: <none>
TIMING-18#44 Warning
Missing input or output delay
An output delay is missing on dpy0[5] relative to clock(s) clk
Related violations: <none>
TIMING-18#45 Warning
Missing input or output delay
An output delay is missing on dpy0[6] relative to clock(s) clk
Related violations: <none>
TIMING-18#46 Warning
Missing input or output delay
An output delay is missing on dpy0[7] relative to clock(s) clk
Related violations: <none>
TIMING-18#47 Warning
Missing input or output delay
An output delay is missing on dpy1[0] relative to clock(s) clk
Related violations: <none>
TIMING-18#48 Warning
Missing input or output delay
An output delay is missing on dpy1[1] relative to clock(s) clk
Related violations: <none>
TIMING-18#49 Warning
Missing input or output delay
An output delay is missing on dpy1[2] relative to clock(s) clk
Related violations: <none>
TIMING-18#50 Warning
Missing input or output delay
An output delay is missing on dpy1[3] relative to clock(s) clk
Related violations: <none>
TIMING-18#51 Warning
Missing input or output delay
An output delay is missing on dpy1[4] relative to clock(s) clk
Related violations: <none>
TIMING-18#52 Warning
Missing input or output delay
An output delay is missing on dpy1[5] relative to clock(s) clk
Related violations: <none>
TIMING-18#53 Warning
Missing input or output delay
An output delay is missing on dpy1[6] relative to clock(s) clk
Related violations: <none>
TIMING-18#54 Warning
Missing input or output delay
An output delay is missing on dpy1[7] relative to clock(s) clk
Related violations: <none>
TIMING-18#55 Warning
Missing input or output delay
An output delay is missing on leds[0] relative to clock(s) clk
Related violations: <none>
TIMING-18#56 Warning
Missing input or output delay
An output delay is missing on leds[10] relative to clock(s) clk
Related violations: <none>
TIMING-18#57 Warning
Missing input or output delay
An output delay is missing on leds[11] relative to clock(s) clk
Related violations: <none>
TIMING-18#58 Warning
Missing input or output delay
An output delay is missing on leds[12] relative to clock(s) clk
Related violations: <none>
TIMING-18#59 Warning
Missing input or output delay
An output delay is missing on leds[13] relative to clock(s) clk
Related violations: <none>
TIMING-18#60 Warning
Missing input or output delay
An output delay is missing on leds[14] relative to clock(s) clk
Related violations: <none>
TIMING-18#61 Warning
Missing input or output delay
An output delay is missing on leds[15] relative to clock(s) clk
Related violations: <none>
TIMING-18#62 Warning
Missing input or output delay
An output delay is missing on leds[1] relative to clock(s) clk
Related violations: <none>
TIMING-18#63 Warning
Missing input or output delay
An output delay is missing on leds[2] relative to clock(s) clk
Related violations: <none>
TIMING-18#64 Warning
Missing input or output delay
An output delay is missing on leds[3] relative to clock(s) clk
Related violations: <none>
TIMING-18#65 Warning
Missing input or output delay
An output delay is missing on leds[4] relative to clock(s) clk
Related violations: <none>
TIMING-18#66 Warning
Missing input or output delay
An output delay is missing on leds[5] relative to clock(s) clk
Related violations: <none>
TIMING-18#67 Warning
Missing input or output delay
An output delay is missing on leds[6] relative to clock(s) clk
Related violations: <none>
TIMING-18#68 Warning
Missing input or output delay
An output delay is missing on leds[7] relative to clock(s) clk
Related violations: <none>
TIMING-18#69 Warning
Missing input or output delay
An output delay is missing on leds[8] relative to clock(s) clk
Related violations: <none>
TIMING-18#70 Warning
Missing input or output delay
An output delay is missing on leds[9] relative to clock(s) clk
Related violations: <none>
TIMING-18#71 Warning
Missing input or output delay
An output delay is missing on video_de relative to clock(s) clk
Related violations: <none>
TIMING-18#72 Warning
Missing input or output delay
An output delay is missing on video_hsync relative to clock(s) clk
Related violations: <none>
TIMING-18#73 Warning
Missing input or output delay
An output delay is missing on video_red[0] relative to clock(s) clk
Related violations: <none>
TIMING-18#74 Warning
Missing input or output delay
An output delay is missing on video_red[1] relative to clock(s) clk
Related violations: <none>
TIMING-18#75 Warning
Missing input or output delay
An output delay is missing on video_red[2] relative to clock(s) clk
Related violations: <none>
TIMING-18#76 Warning
Missing input or output delay
An output delay is missing on video_vsync relative to clock(s) clk
Related violations: <none>
TIMING-47#1 Warning
False path or asynchronous clock group between synchronous clocks
A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
Related violations: <none>
TIMING-47#2 Warning
False path or asynchronous clock group between synchronous clocks
A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
Related violations: <none>
XDCC-1#1 Warning
Scoped Clock constraint overwritten with the same name
A new clock constraint create_clock overrides a previous scoped clock constraint with the same name. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
Related violations: <none>
XDCC-7#1 Warning
Scoped Clock constraint overwritten on the same source
A new clock constraint create_clock overrides a previous scoped clock constraint defined on the same source. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
Related violations: <none>

5216
fpga/vivado_reports_nodsp/mlkem_clk_timing.rpt Normal file
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134
fpga/vivado_reports/impl_power.rpt → fpga/vivado_reports_nodsp/power.rpt
View File

@@ -1,16 +1,16 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:41 2026
| Date : Wed Jul 8 03:34:25 2026
| Host : fedora running 64-bit unknown
| Command : report_power -file ./vivado_reports/impl_power.rpt
| Command : report_power -file /home/fallensigh/vivado_reports_nodsp/power.rpt
| Design : soc_top
| Device : xc7a200tfbg676-1
| Design State : synthesized
| Design State : routed
| Grade : commercial
| Process : typical
| Characterization : Production
----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
Power Report
@@ -30,14 +30,14 @@ Table of Contents
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 0.727 |
| Total On-Chip Power (W) | 0.549 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.586 |
| Dynamic (W) | 0.409 |
| Device Static (W) | 0.141 |
| Effective TJA (C/W) | 1.9 |
| Max Ambient (C) | 83.6 |
| Junction Temperature (C) | 26.4 |
| Max Ambient (C) | 84.0 |
| Junction Temperature (C) | 26.0 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
@@ -52,22 +52,22 @@ Table of Contents
+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks | 0.030 | 6 | --- | --- |
| Slice Logic | 0.180 | 137345 | --- | --- |
| LUT as Logic | 0.172 | 73234 | 134600 | 54.41 |
| CARRY4 | 0.005 | 3590 | 33650 | 10.67 |
| LUT as Distributed RAM | 0.001 | 652 | 46200 | 1.41 |
| Register | 0.001 | 38603 | 269200 | 14.34 |
| LUT as Shift Register | <0.001 | 1094 | 46200 | 2.37 |
| F7/F8 Muxes | <0.001 | 5666 | 134600 | 4.21 |
| BUFG | <0.001 | 1 | 32 | 3.13 |
| Others | 0.000 | 287 | --- | --- |
| Signals | 0.190 | 113832 | --- | --- |
| Block RAM | 0.020 | 25.5 | 365 | 6.99 |
| PLL | 0.137 | 1 | 10 | 10.00 |
| I/O | 0.029 | 202 | 400 | 50.50 |
| Clocks | 0.042 | 7 | --- | --- |
| Slice Logic | 0.069 | 120086 | --- | --- |
| LUT as Logic | 0.064 | 63754 | 133800 | 47.65 |
| CARRY4 | 0.002 | 2859 | 33450 | 8.55 |
| LUT as Distributed RAM | <0.001 | 740 | 46200 | 1.60 |
| Register | <0.001 | 39931 | 267600 | 14.92 |
| LUT as Shift Register | <0.001 | 1175 | 46200 | 2.54 |
| F7/F8 Muxes | <0.001 | 6036 | 133800 | 4.51 |
| Others | 0.000 | 318 | --- | --- |
| Signals | 0.115 | 85084 | --- | --- |
| Block RAM | 0.019 | 23.5 | 365 | 6.44 |
| PLL | 0.132 | 1 | 10 | 10.00 |
| DSPs | 0.009 | 16 | 740 | 2.16 |
| I/O | 0.023 | 202 | 400 | 50.50 |
| Static Power | 0.141 | | | |
| Total | 0.727 | | | |
| Total | 0.549 | | | |
+--------------------------+-----------+----------+-----------+-----------------+
@@ -77,9 +77,9 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 1.000 | 0.465 | 0.432 | 0.032 |
| Vccaux | 1.800 | 0.101 | 0.070 | 0.031 |
| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 |
| Vccint | 1.000 | 0.294 | 0.262 | 0.032 |
| Vccaux | 1.800 | 0.099 | 0.069 | 0.031 |
| Vcco33 | 3.300 | 0.011 | 0.006 | 0.005 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
@@ -96,17 +96,17 @@ Table of Contents
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | Low | Design is synthesized | Accuracy of the tool is not optimal until design is fully placed and routed |
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
2. Settings
@@ -130,14 +130,15 @@ Table of Contents
2.2 Clock Constraints
---------------------
+------------------+-----------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+------------------+-----------------------------------------+-----------------+
| clk | clk | 20.0 |
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
+------------------+-----------------------------------------+-----------------+
+-------------------+------------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------------------+------------------------------------------+-----------------+
| clk | clk | 20.0 |
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 40.0 |
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
+-------------------+------------------------------------------+-----------------+
3. Detailed Reports
@@ -149,40 +150,31 @@ Table of Contents
+----------------------------+-----------+
| Name | Power (W) |
+----------------------------+-----------+
| soc_top | 0.586 |
| pll_clk.u_clk_pll | 0.138 |
| inst | 0.138 |
| u_AxiCrossbar_2x8 | 0.001 |
| u_Axi_CDC | 0.003 |
| u_axi_uart_controller | 0.002 |
| soc_top | 0.409 |
| pll_clk.u_clk_pll | 0.133 |
| inst | 0.133 |
| u_Axi_CDC | 0.002 |
| u_axi_uart_controller | 0.001 |
| uart0 | 0.001 |
| regs | 0.001 |
| u_cdma_matmul_bridge | 0.001 |
| u_confreg | 0.001 |
| u_cpu | 0.026 |
| u_cpu | 0.018 |
| addr_trans | 0.002 |
| tlb_entry | 0.002 |
| btb | 0.003 |
| btb | 0.002 |
| dcache | 0.004 |
| icache | 0.005 |
| u_csr | 0.001 |
| u_mul | 0.006 |
| u_fft_mlkem_axi_slave | 0.285 |
| u_csr | 0.002 |
| u_fft_mlkem_axi_slave | 0.148 |
| u_fft_controller | 0.032 |
| u_FFT | 0.029 |
| u_out0 | 0.001 |
| u_out1 | 0.001 |
| u_mlkem_axi_slave | 0.250 |
| u_mlkem | 0.227 |
| u_prng_axi_slave | 0.004 |
| u_matmul_axi_slave | 0.072 |
| mult_inst[0].u_mult | 0.002 |
| mult_inst[1].u_mult | 0.002 |
| mult_inst[2].u_mult | 0.002 |
| mult_inst[3].u_mult | 0.002 |
| u_snix_axil_cdma_mux_8ch | 0.010 |
| u_core_engine | 0.005 |
| axis_fifo_u0 | 0.004 |
| u_mlkem_axi_cdc | 0.002 |
| u_mlkem_axi_slave | 0.115 |
| u_mlkem | 0.113 |
| u_matmul_axi_slave | 0.065 |
| u_snix_axil_cdma_mux_8ch | 0.009 |
| u_core_engine | 0.004 |
| axis_fifo_u0 | 0.003 |
+----------------------------+-----------+

12
fpga/vivado_reports_nodsp/route_status.rpt Normal file
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@@ -0,0 +1,12 @@
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 128919 :
# of nets not needing routing.......... : 43824 :
# of internally routed nets........ : 43359 :
# of nets with no loads............ : 465 :
# of routable nets..................... : 85095 :
# of fully routed nets............. : 85095 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

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31976
fpga/vivado_reports_nodsp/timing_setup_paths.rpt Normal file
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38485
fpga/vivado_reports_nodsp/timing_summary_full.rpt Normal file
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32214
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158
fpga/vivado_reports/synth_utilization.rpt → fpga/vivado_reports_nodsp/utilization.rpt
View File

@@ -1,13 +1,13 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:34:12 2026
| Date : Wed Jul 8 03:34:05 2026
| Host : fedora running 64-bit unknown
| Command : report_utilization -file ./vivado_reports/synth_utilization.rpt
| Command : report_utilization -file /home/fallensigh/vivado_reports_nodsp/utilization.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Synthesized
------------------------------------------------------------------------------------
| Design State : Routed
------------------------------------------------------------------------------------------------
Utilization Design Information
@@ -15,14 +15,15 @@ Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
@@ -30,18 +31,17 @@ Table of Contents
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs* | 74980 | 0 | 134600 | 55.71 |
| LUT as Logic | 73234 | 0 | 134600 | 54.41 |
| LUT as Memory | 1746 | 0 | 46200 | 3.78 |
| LUT as Distributed RAM | 652 | 0 | | |
| LUT as Shift Register | 1094 | 0 | | |
| Slice Registers | 38603 | 0 | 269200 | 14.34 |
| Register as Flip Flop | 38603 | 0 | 269200 | 14.34 |
| Register as Latch | 0 | 0 | 269200 | 0.00 |
| F7 Muxes | 4263 | 0 | 67300 | 6.33 |
| F8 Muxes | 1403 | 0 | 33650 | 4.17 |
| Slice LUTs | 60995 | 0 | 133800 | 45.59 |
| LUT as Logic | 59140 | 0 | 133800 | 44.20 |
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
| LUT as Distributed RAM | 740 | 0 | | |
| LUT as Shift Register | 1115 | 0 | | |
| Slice Registers | 39931 | 0 | 267600 | 14.92 |
| Register as Flip Flop | 39931 | 0 | 267600 | 14.92 |
| Register as Latch | 0 | 0 | 267600 | 0.00 |
| F7 Muxes | 4480 | 0 | 66900 | 6.70 |
| F8 Muxes | 1556 | 0 | 33450 | 4.65 |
+----------------------------+-------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
@@ -56,39 +56,72 @@ Table of Contents
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 101 | Yes | - | Set |
| 25523 | Yes | - | Reset |
| 134 | Yes | Set | - |
| 12845 | Yes | Reset | - |
| 24 | Yes | - | Set |
| 26637 | Yes | - | Reset |
| 139 | Yes | Set | - |
| 13131 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
2. Slice Logic Distribution
---------------------------
+--------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------------------------------------+-------+-------+-----------+-------+
| Slice | 20066 | 0 | 33450 | 59.99 |
| SLICEL | 13210 | 0 | | |
| SLICEM | 6856 | 0 | | |
| LUT as Logic | 59140 | 0 | 133800 | 44.20 |
| using O5 output only | 2 | | | |
| using O6 output only | 49931 | | | |
| using O5 and O6 | 9207 | | | |
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
| LUT as Distributed RAM | 740 | 0 | | |
| using O5 output only | 0 | | | |
| using O6 output only | 60 | | | |
| using O5 and O6 | 680 | | | |
| LUT as Shift Register | 1115 | 0 | | |
| using O5 output only | 47 | | | |
| using O6 output only | 1008 | | | |
| using O5 and O6 | 60 | | | |
| Slice Registers | 39931 | 0 | 267600 | 14.92 |
| Register driven from within the Slice | 20433 | | | |
| Register driven from outside the Slice | 19498 | | | |
| LUT in front of the register is unused | 10788 | | | |
| LUT in front of the register is used | 8710 | | | |
| Unique Control Sets | 1304 | | 33450 | 3.90 |
+--------------------------------------------+-------+-------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 25.5 | 0 | 365 | 6.99 |
| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
| RAMB36E1 only | 10 | | | |
| Block RAM Tile | 23.5 | 0 | 365 | 6.44 |
| RAMB36/FIFO* | 8 | 0 | 365 | 2.19 |
| RAMB36E1 only | 8 | | | |
| RAMB18 | 31 | 0 | 730 | 4.25 |
| RAMB18E1 only | 31 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
4. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 740 | 0.00 |
+-----------+------+-------+-----------+-------+
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 16 | 0 | 740 | 2.16 |
| DSP48E1 only | 16 | | | |
+----------------+------+-------+-----------+-------+
4. IO and GT Specific
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
@@ -115,7 +148,7 @@ Table of Contents
+-----------------------------+------+-------+-----------+-------+
5. Clocking
6. Clocking
-----------
+------------+------+-------+-----------+-------+
@@ -131,7 +164,7 @@ Table of Contents
+------------+------+-------+-----------+-------+
6. Specific Feature
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
@@ -149,41 +182,42 @@ Table of Contents
+-------------+------+-------+-----------+-------+
7. Primitives
8. Primitives
-------------
+-----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+-----------+-------+---------------------+
| LUT6 | 36042 | LUT |
| FDCE | 25523 | Flop & Latch |
| LUT5 | 16007 | LUT |
| LUT3 | 13060 | LUT |
| FDRE | 12845 | Flop & Latch |
| LUT4 | 11977 | LUT |
| LUT2 | 9006 | LUT |
| MUXF7 | 4263 | MuxFx |
| CARRY4 | 3590 | CarryLogic |
| MUXF8 | 1403 | MuxFx |
| LUT6 | 35413 | LUT |
| FDCE | 26637 | Flop & Latch |
| FDRE | 13131 | Flop & Latch |
| LUT3 | 9384 | LUT |
| LUT5 | 8477 | LUT |
| LUT4 | 7294 | LUT |
| LUT2 | 6978 | LUT |
| MUXF7 | 4480 | MuxFx |
| CARRY4 | 2859 | CarryLogic |
| MUXF8 | 1556 | MuxFx |
| RAMD32 | 1060 | Distributed Memory |
| SRLC32E | 992 | Distributed Memory |
| RAMD32 | 892 | Distributed Memory |
| LUT1 | 816 | LUT |
| RAMS32 | 272 | Distributed Memory |
| FDSE | 134 | Flop & Latch |
| LUT1 | 801 | LUT |
| RAMS32 | 328 | Distributed Memory |
| SRL16E | 183 | Distributed Memory |
| FDSE | 139 | Flop & Latch |
| IBUF | 104 | IO |
| SRL16E | 102 | Distributed Memory |
| FDPE | 101 | Flop & Latch |
| OBUF | 98 | IO |
| OBUFT | 66 | IO |
| RAMD64E | 32 | Distributed Memory |
| RAMB18E1 | 31 | Block Memory |
| RAMB36E1 | 10 | Block Memory |
| FDPE | 24 | Flop & Latch |
| DSP48E1 | 16 | Block Arithmetic |
| RAMB36E1 | 8 | Block Memory |
| BUFG | 4 | Clock |
| PLLE2_ADV | 1 | Clock |
+-----------+-------+---------------------+
8. Black Boxes
9. Black Boxes
--------------
+----------+------+
@@ -191,8 +225,8 @@ Table of Contents
+----------+------+
9. Instantiated Netlists
------------------------
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |

389
fpga/vivado_reports/impl_utilization_hier.rpt → fpga/vivado_reports_nodsp/utilization_hier.rpt
View File

@@ -1,13 +1,13 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:35:23 2026
| Date : Wed Jul 8 03:34:06 2026
| Host : fedora running 64-bit unknown
| Command : report_utilization -hierarchical -hierarchical_depth 10 -file ./vivado_reports/impl_utilization_hier.rpt
| Command : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_nodsp/utilization_hier.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Synthesized
--------------------------------------------------------------------------------------------------------------------------
| Design State : Routed
-------------------------------------------------------------------------------------------------------------------
Utilization Design Information
@@ -21,114 +21,115 @@ Table of Contents
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| soc_top | (top) | 74980 | 73234 | 652 | 1094 | 38603 | 10 | 31 | 0 |
| (soc_top) | (top) | 2116 | 2060 | 56 | 0 | 4 | 0 | 0 | 0 |
| pll_clk.u_clk_pll | clk_pll | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| inst | clk_pll_clk_pll_clk_wiz | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| soc_top | (top) | 60995 | 59140 | 740 | 1115 | 39931 | 8 | 31 | 16 |
| (soc_top) | (top) | 878 | 822 | 56 | 0 | 4 | 0 | 0 | 0 |
| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| inst | clk_pll__clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| pll_clk.u_rst_sys | rst_sync_0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 519 | 519 | 0 | 0 | 151 | 0 | 0 | 0 |
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_67 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_50 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_66 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_51 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_65 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_52 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_64 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 32 | 32 | 0 | 0 | 11 | 0 | 0 | 0 |
| pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 459 | 459 | 0 | 0 | 151 | 0 | 0 | 0 |
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 6 | 6 | 0 | 0 | 24 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_82 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_65 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_81 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_66 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_80 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_67 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_79 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_61 | 25 | 25 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_62 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_63 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_76 | 27 | 27 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_77 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_78 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_58 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_59 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_60 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_73 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_74 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_75 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_55 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_56 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_57 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 61 | 61 | 0 | 0 | 11 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_70 | 20 | 20 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_71 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_72 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 23 | 23 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7 | 48 | 48 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3 | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 |
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 89 | 89 | 0 | 0 | 25 | 0 | 0 | 0 |
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 73 | 73 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1_54 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 |
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 |
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1_53 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 |
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 181 | 181 | 0 | 0 | 17 | 0 | 0 | 0 |
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 165 | 165 | 0 | 0 | 8 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 |
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 25 | 25 | 0 | 0 | 14 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 96 | 96 | 0 | 0 | 25 | 0 | 0 | 0 |
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 75 | 75 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1_69 | 21 | 21 | 0 | 0 | 13 | 0 | 0 | 0 |
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 40 | 40 | 0 | 0 | 18 | 0 | 0 | 0 |
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1_68 | 21 | 21 | 0 | 0 | 2 | 0 | 0 | 0 |
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 133 | 133 | 0 | 0 | 17 | 0 | 0 | 0 |
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 118 | 118 | 0 | 0 | 8 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 30 | 30 | 0 | 0 | 14 | 0 | 0 | 0 |
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_Axi_CDC | Axi_CDC | 505 | 377 | 128 | 0 | 309 | 0 | 0 | 0 |
| arFifo | StreamFifoCC_3 | 262 | 226 | 36 | 0 | 73 | 0 | 0 | 0 |
| (arFifo) | StreamFifoCC_3 | 256 | 220 | 36 | 0 | 61 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_48 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_49 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
| awFifo | StreamFifoCC | 112 | 76 | 36 | 0 | 75 | 0 | 0 | 0 |
| (awFifo) | StreamFifoCC | 105 | 69 | 36 | 0 | 61 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| bFifo | StreamFifoCC_2 | 16 | 16 | 0 | 0 | 26 | 0 | 0 | 0 |
| (bFifo) | StreamFifoCC_2 | 9 | 9 | 0 | 0 | 12 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_4 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_6 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| rFifo | StreamFifoCC_4 | 46 | 18 | 28 | 0 | 66 | 0 | 0 | 0 |
| (rFifo) | StreamFifoCC_4 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_1 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| wFifo | StreamFifoCC_1 | 69 | 41 | 28 | 0 | 69 | 0 | 0 | 0 |
| (wFifo) | StreamFifoCC_1 | 64 | 36 | 28 | 0 | 53 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_8 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| u_axi_axil_adapter | axi_axil_adapter | 1355 | 1355 | 0 | 0 | 161 | 0 | 0 | 0 |
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 648 | 648 | 0 | 0 | 81 | 0 | 0 | 0 |
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 707 | 707 | 0 | 0 | 80 | 0 | 0 | 0 |
| u_axi_dvi | axi_dvi | 285 | 285 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_axi_ram | axi_wrap_ram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_sram_sp | axi2sram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_uart_controller | axi_uart_controller | 693 | 677 | 16 | 0 | 457 | 0 | 0 | 0 |
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 252 | 252 | 0 | 0 | 120 | 0 | 0 | 0 |
| uart0 | UART_TOP | 441 | 425 | 16 | 0 | 337 | 0 | 0 | 0 |
| regs | uart_regs | 441 | 425 | 16 | 0 | 337 | 0 | 0 | 0 |
| (regs) | uart_regs | 121 | 121 | 0 | 0 | 155 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_Axi_CDC | Axi_CDC | 410 | 282 | 128 | 0 | 317 | 0 | 0 | 0 |
| arFifo | StreamFifoCC_3_48 | 181 | 145 | 36 | 0 | 77 | 0 | 0 | 0 |
| (arFifo) | StreamFifoCC_3_48 | 176 | 140 | 36 | 0 | 65 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_63 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_64 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| awFifo | StreamFifoCC_49 | 103 | 67 | 36 | 0 | 79 | 0 | 0 | 0 |
| (awFifo) | StreamFifoCC_49 | 99 | 63 | 36 | 0 | 65 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_10_60 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_61 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_62 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| bFifo | StreamFifoCC_2_50 | 15 | 15 | 0 | 0 | 26 | 0 | 0 | 0 |
| (bFifo) | StreamFifoCC_2_50 | 8 | 8 | 0 | 0 | 12 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_5_57 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_4_58 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_6_59 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| rFifo | StreamFifoCC_4_51 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 |
| (rFifo) | StreamFifoCC_4_51 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_55 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_1_56 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| wFifo | StreamFifoCC_1_52 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 |
| (wFifo) | StreamFifoCC_1_52 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_7_53 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_8_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| u_axi_axil_adapter | axi_axil_adapter | 1073 | 1073 | 0 | 0 | 173 | 0 | 0 | 0 |
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 498 | 498 | 0 | 0 | 85 | 0 | 0 | 0 |
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 575 | 575 | 0 | 0 | 88 | 0 | 0 | 0 |
| u_axi_dvi | axi_dvi | 283 | 283 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_axi_ram | axi_wrap_ram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_sram_sp | axi2sram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_uart_controller | axi_uart_controller | 683 | 667 | 16 | 0 | 457 | 0 | 0 | 0 |
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 251 | 251 | 0 | 0 | 120 | 0 | 0 | 0 |
| uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
| regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
| (regs) | uart_regs | 119 | 119 | 0 | 0 | 155 | 0 | 0 | 0 |
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
| receiver | uart_receiver | 231 | 223 | 8 | 0 | 124 | 0 | 0 | 0 |
| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 |
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
| fifo_rx | uart_rfifo | 163 | 155 | 8 | 0 | 70 | 0 | 0 | 0 |
| (fifo_rx) | uart_rfifo | 144 | 144 | 0 | 0 | 62 | 0 | 0 | 0 |
| fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 |
| (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 |
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
| transmitter | uart_transmitter | 86 | 78 | 8 | 0 | 56 | 0 | 0 | 0 |
| (transmitter) | uart_transmitter | 42 | 42 | 0 | 0 | 35 | 0 | 0 | 0 |
| fifo_tx | uart_tfifo | 44 | 36 | 8 | 0 | 21 | 0 | 0 | 0 |
| (fifo_tx) | uart_tfifo | 25 | 25 | 0 | 0 | 13 | 0 | 0 | 0 |
| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 |
| (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 |
| fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 |
| (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 |
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
| u_cdma_matmul_bridge | cdma_matmul_bridge | 250 | 250 | 0 | 0 | 578 | 0 | 0 | 0 |
| u_confreg | confreg | 391 | 391 | 0 | 0 | 460 | 0 | 0 | 0 |
| (u_confreg) | confreg | 231 | 231 | 0 | 0 | 383 | 0 | 0 | 0 |
| u_cdma_matmul_bridge | cdma_matmul_bridge | 251 | 251 | 0 | 0 | 578 | 0 | 0 | 0 |
| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 |
| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 |
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
| u_cpu | core_top | 8656 | 8380 | 276 | 0 | 5591 | 0 | 20 | 0 |
| u_cpu | core_top | 8551 | 8299 | 252 | 0 | 5591 | 0 | 20 | 0 |
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
| addr_trans | addr_trans | 2264 | 2100 | 164 | 0 | 1244 | 0 | 0 | 0 |
| addr_trans | addr_trans | 2247 | 2107 | 140 | 0 | 1244 | 0 | 0 | 0 |
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
| tlb_entry | tlb_entry | 2264 | 2100 | 164 | 0 | 1204 | 0 | 0 | 0 |
| tlb_entry | tlb_entry | 2247 | 2107 | 140 | 0 | 1204 | 0 | 0 | 0 |
| axi_bridge | axi_bridge | 40 | 40 | 0 | 0 | 214 | 0 | 0 | 0 |
| btb | btb | 1064 | 984 | 80 | 0 | 1611 | 0 | 0 | 0 |
| (btb) | btb | 1061 | 981 | 80 | 0 | 1611 | 0 | 0 | 0 |
| btb | btb | 1046 | 966 | 80 | 0 | 1611 | 0 | 0 | 0 |
| (btb) | btb | 1044 | 964 | 80 | 0 | 1611 | 0 | 0 | 0 |
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
| dcache | dcache | 569 | 537 | 32 | 0 | 146 | 0 | 10 | 0 |
| (dcache) | dcache | 92 | 60 | 32 | 0 | 138 | 0 | 0 | 0 |
| dcache | dcache | 552 | 520 | 32 | 0 | 146 | 0 | 10 | 0 |
| (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
@@ -139,11 +140,11 @@ Table of Contents
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_46 | 46 | 46 | 0 | 0 | 0 | 0 | 1 | 0 |
| exe_stage | exe_stage | 681 | 681 | 0 | 0 | 233 | 0 | 0 | 0 |
| (exe_stage) | exe_stage | 650 | 650 | 0 | 0 | 233 | 0 | 0 | 0 |
| tagv_ram_way[1].u | tagv_sram_46 | 41 | 41 | 0 | 0 | 0 | 0 | 1 | 0 |
| exe_stage | exe_stage | 663 | 663 | 0 | 0 | 233 | 0 | 0 | 0 |
| (exe_stage) | exe_stage | 632 | 632 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
| icache | icache | 239 | 239 | 0 | 0 | 55 | 0 | 10 | 0 |
| icache | icache | 235 | 235 | 0 | 0 | 55 | 0 | 10 | 0 |
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
@@ -155,101 +156,121 @@ Table of Contents
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_35 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
| id_stage | id_stage | 1058 | 1058 | 0 | 0 | 108 | 0 | 0 | 0 |
| tagv_ram_way[1].u | tagv_sram_35 | 87 | 87 | 0 | 0 | 0 | 0 | 1 | 0 |
| id_stage | id_stage | 1054 | 1054 | 0 | 0 | 108 | 0 | 0 | 0 |
| if_stage | if_stage | 135 | 135 | 0 | 0 | 173 | 0 | 0 | 0 |
| mem_stage | mem_stage | 116 | 116 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
| u_div | div | 143 | 143 | 0 | 0 | 107 | 0 | 0 | 0 |
| u_mul | mul | 943 | 943 | 0 | 0 | 592 | 0 | 0 | 0 |
| wb_stage | wb_stage | 685 | 685 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 48074 | 46986 | 0 | 1088 | 25915 | 10 | 10 | 0 |
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 17 | 17 | 0 | 0 | 6 | 0 | 0 | 0 |
| u_fft_controller | fft_controller | 6966 | 5878 | 0 | 1088 | 1087 | 8 | 4 | 0 |
| (u_fft_controller) | fft_controller | 90 | 90 | 0 | 0 | 104 | 0 | 0 | 0 |
| u_FFT | FFT | 6855 | 5767 | 0 | 1088 | 983 | 8 | 0 | 0 |
| SU1 | SdfUnit | 2150 | 1382 | 0 | 768 | 197 | 2 | 0 | 0 |
| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 |
| u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 |
| u_mul | mul | 936 | 936 | 0 | 0 | 592 | 0 | 0 | 0 |
| wb_stage | wb_stage | 680 | 680 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 36148 | 34927 | 112 | 1109 | 27165 | 8 | 10 | 16 |
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| u_fft_controller | fft_controller | 2646 | 1606 | 0 | 1040 | 1083 | 6 | 4 | 16 |
| (u_fft_controller) | fft_controller | 123 | 123 | 0 | 0 | 100 | 0 | 0 | 0 |
| u_FFT | FFT | 2496 | 1456 | 0 | 1040 | 983 | 6 | 0 | 16 |
| SU1 | SdfUnit | 1071 | 303 | 0 | 768 | 197 | 2 | 0 | 4 |
| (SU1) | SdfUnit | 205 | 205 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 |
| MU | Multiply_26 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_27 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU2 | SdfUnit__parameterized0 | 1571 | 1379 | 0 | 192 | 197 | 2 | 0 | 0 |
| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_25 | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer | 562 | 50 | 0 | 512 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized0 | 256 | 0 | 0 | 256 | 32 | 0 | 0 | 0 |
| MU | Multiply_26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 |
| TW | Twiddle_27 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU2 | SdfUnit__parameterized0 | 492 | 300 | 0 | 192 | 197 | 2 | 0 | 4 |
| (SU2) | SdfUnit__parameterized0 | 73 | 73 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_21 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
| MU | Multiply_22 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_23 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU3 | SdfUnit__parameterized1 | 1439 | 1375 | 0 | 64 | 197 | 2 | 0 | 0 |
| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_16 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_17 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| MU | Multiply_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
| TW | Twiddle_23 | 3 | 3 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU3 | SdfUnit__parameterized1 | 346 | 298 | 0 | 48 | 197 | 0 | 0 | 4 |
| (SU3) | SdfUnit__parameterized1 | 74 | 74 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized4 | 96 | 64 | 0 | 32 | 32 | 0 | 0 | 0 |
| MU | Multiply_18 | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_19 | 540 | 540 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU4 | SdfUnit__parameterized2 | 1436 | 1372 | 0 | 64 | 197 | 2 | 0 | 0 |
| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_14 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_15 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized5 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized6 | 96 | 64 | 0 | 32 | 32 | 0 | 0 | 0 |
| MU | Multiply | 616 | 616 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle | 538 | 538 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU5 | SdfUnit__parameterized3 | 259 | 259 | 0 | 0 | 195 | 0 | 0 | 0 |
| (SU5) | SdfUnit__parameterized3 | 35 | 35 | 0 | 0 | 99 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
| MU | Multiply_19 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
| SU4 | SdfUnit__parameterized2 | 327 | 295 | 0 | 32 | 197 | 2 | 0 | 4 |
| (SU4) | SdfUnit__parameterized2 | 69 | 69 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_15 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
| MU | Multiply | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
| TW | Twiddle | 2 | 2 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU5 | SdfUnit__parameterized3 | 260 | 260 | 0 | 0 | 195 | 0 | 0 | 0 |
| (SU5) | SdfUnit__parameterized3 | 68 | 68 | 0 | 0 | 99 | 0 | 0 | 0 |
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_in1 | my_bram0_11 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out0 | my_bram0_12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out1 | my_bram0_13 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_mlkem_axi_slave | mlkem_axi_slave | 40589 | 40589 | 0 | 0 | 24484 | 2 | 6 | 0 |
| (u_mlkem_axi_slave) | mlkem_axi_slave | 3642 | 3642 | 0 | 0 | 1021 | 0 | 0 | 0 |
| u_mlkem | mlkem_top | 36975 | 36975 | 0 | 0 | 23463 | 2 | 6 | 0 |
| (u_mlkem) | mlkem_top | 2550 | 2550 | 0 | 0 | 4907 | 0 | 0 | 0 |
| u_bank_a | sd_bram__parameterized0 | 39 | 39 | 0 | 0 | 0 | 1 | 1 | 0 |
| u_bank_se | sd_bram__parameterized1 | 62 | 62 | 0 | 0 | 0 | 1 | 0 | 0 |
| u_bank_t | sd_bram__parameterized2 | 484 | 484 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_c_in_bram | sd_bram | 1291 | 1291 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_cbd | sample_cbd_sync_shared | 2469 | 2469 | 0 | 0 | 3199 | 0 | 0 | 0 |
| u_comp | comp_decomp_sync | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
| u_pipe | pipeline_reg | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
| u_ct_bram | sd_bram_4 | 20 | 20 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_dkp_bram | sd_bram_5 | 101 | 101 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_ek_bram | sd_bram_6 | 226 | 226 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_keccak | keccak_core | 5251 | 5251 | 0 | 0 | 1619 | 0 | 0 | 0 |
| u_ntt | ntt_core | 13498 | 13498 | 0 | 0 | 3354 | 0 | 0 | 0 |
| u_pmul | poly_mul_sync | 7392 | 7392 | 0 | 0 | 6314 | 0 | 0 | 0 |
| (u_pmul) | poly_mul_sync | 5013 | 5013 | 0 | 0 | 6314 | 0 | 0 | 0 |
| u_bc | basecase_mul | 2379 | 2379 | 0 | 0 | 0 | 0 | 0 | 0 |
| (u_bc) | basecase_mul | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul1 | barrett_mul | 969 | 969 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul2 | barrett_mul_7 | 118 | 118 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul3 | barrett_mul_8 | 561 | 561 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul4 | barrett_mul_9 | 549 | 549 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul_zeta | barrett_mul_10 | 130 | 130 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_sha3 | sha3_top_shared | 1983 | 1983 | 0 | 0 | 2388 | 0 | 0 | 0 |
| u_snt | sample_ntt_sync_shared | 1433 | 1433 | 0 | 0 | 1669 | 0 | 0 | 0 |
| u_prng_axi_slave | prng_axi_slave | 502 | 502 | 0 | 0 | 338 | 0 | 0 | 0 |
| u_matmul_axi_slave | matmul_axi_slave | 9974 | 9792 | 176 | 6 | 3208 | 0 | 0 | 0 |
| (u_matmul_axi_slave) | matmul_axi_slave | 5758 | 5576 | 176 | 6 | 2440 | 0 | 0 | 0 |
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1086 | 1086 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[1].u_mult | pipelined_mult_32x32_1 | 1022 | 1022 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[2].u_mult | pipelined_mult_32x32_2 | 1086 | 1086 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[3].u_mult | pipelined_mult_32x32_3 | 1022 | 1022 | 0 | 0 | 192 | 0 | 0 | 0 |
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1823 | 1823 | 0 | 0 | 1476 | 0 | 1 | 0 |
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 605 | 605 | 0 | 0 | 1180 | 0 | 0 | 0 |
| u_core_engine | snix_axi_mm2mm | 1218 | 1218 | 0 | 0 | 296 | 0 | 1 | 0 |
| (u_core_engine) | snix_axi_mm2mm | 776 | 776 | 0 | 0 | 243 | 0 | 0 | 0 |
| axis_fifo_u0 | snix_axis_fifo | 442 | 442 | 0 | 0 | 53 | 0 | 1 | 0 |
| u_fifo | snix_sync_fifo | 442 | 442 | 0 | 0 | 53 | 0 | 1 | 0 |
| u_in0 | my_bram0 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_in1 | my_bram0_12 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out0 | my_bram0_13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out1 | my_bram0_14 | 25 | 25 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_mlkem_axi_cdc | Axi_CDC_5 | 421 | 309 | 112 | 0 | 272 | 0 | 0 | 0 |
| arFifo | StreamFifoCC_3 | 53 | 25 | 28 | 0 | 55 | 0 | 0 | 0 |
| (arFifo) | StreamFifoCC_3 | 44 | 16 | 28 | 0 | 43 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_10 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| awFifo | StreamFifoCC | 40 | 16 | 24 | 0 | 49 | 0 | 0 | 0 |
| (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 |
| (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
| rFifo | StreamFifoCC_4 | 57 | 29 | 28 | 0 | 72 | 0 | 0 | 0 |
| (rFifo) | StreamFifoCC_4 | 49 | 21 | 28 | 0 | 56 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 |
| wFifo | StreamFifoCC_1 | 253 | 225 | 28 | 0 | 69 | 0 | 0 | 0 |
| (wFifo) | StreamFifoCC_1 | 248 | 220 | 28 | 0 | 53 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| u_mlkem_axi_slave | mlkem_axi_slave | 33082 | 33013 | 0 | 69 | 25804 | 2 | 6 | 0 |
| (u_mlkem_axi_slave) | mlkem_axi_slave | 1202 | 1202 | 0 | 0 | 1068 | 0 | 0 | 0 |
| u_mlkem | mlkem_top | 31884 | 31815 | 0 | 69 | 24736 | 2 | 6 | 0 |
| (u_mlkem) | mlkem_top | 2738 | 2738 | 0 | 0 | 4960 | 0 | 0 | 0 |
| u_bank_a | sd_bram__parameterized0 | 50 | 50 | 0 | 0 | 0 | 1 | 1 | 0 |
| u_bank_se | sd_bram__parameterized1 | 70 | 70 | 0 | 0 | 0 | 1 | 0 | 0 |
| u_bank_t | sd_bram__parameterized2 | 654 | 654 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_c_in_bram | sd_bram | 1312 | 1312 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_cbd | sample_cbd_sync_shared | 2741 | 2741 | 0 | 0 | 3186 | 0 | 0 | 0 |
| u_comp | comp_decomp_sync | 467 | 466 | 0 | 1 | 323 | 0 | 0 | 0 |
| u_ct_bram | sd_bram_6 | 13 | 13 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_dkp_bram | sd_bram_7 | 82 | 82 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_ek_bram | sd_bram_8 | 2121 | 2121 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_keccak | keccak_core | 5274 | 5274 | 0 | 0 | 1606 | 0 | 0 | 0 |
| u_ntt | ntt_core | 8625 | 8582 | 0 | 43 | 3861 | 0 | 0 | 0 |
| (u_ntt) | ntt_core | 6101 | 6085 | 0 | 16 | 3358 | 0 | 0 | 0 |
| u_bf | butterfly_unit_pipe | 2260 | 2234 | 0 | 26 | 286 | 0 | 0 | 0 |
| (u_bf) | butterfly_unit_pipe | 69 | 44 | 0 | 25 | 75 | 0 | 0 | 0 |
| u_barrett | barrett_mul_pipe_9 | 2192 | 2191 | 0 | 1 | 211 | 0 | 0 | 0 |
| u_scl | barrett_mul_pipe | 265 | 264 | 0 | 1 | 217 | 0 | 0 | 0 |
| u_pmul | poly_mul_sync | 3881 | 3856 | 0 | 25 | 6743 | 0 | 0 | 0 |
| (u_pmul) | poly_mul_sync | 2434 | 2434 | 0 | 0 | 6280 | 0 | 0 | 0 |
| u_bc | basecase_mul_pipe | 1447 | 1422 | 0 | 25 | 463 | 0 | 0 | 0 |
| u_sha3 | sha3_top_shared | 1766 | 1766 | 0 | 0 | 2388 | 0 | 0 | 0 |
| u_snt | sample_ntt_sync_shared | 2109 | 2109 | 0 | 0 | 1669 | 0 | 0 | 0 |
| u_matmul_axi_slave | matmul_axi_slave | 9758 | 9576 | 176 | 6 | 3248 | 0 | 0 | 0 |
| (u_matmul_axi_slave) | matmul_axi_slave | 5637 | 5455 | 176 | 6 | 2480 | 0 | 0 | 0 |
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1063 | 1063 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[1].u_mult | pipelined_mult_32x32_2 | 999 | 999 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[3].u_mult | pipelined_mult_32x32_4 | 997 | 997 | 0 | 0 | 192 | 0 | 0 | 0 |
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1788 | 1788 | 0 | 0 | 1476 | 0 | 1 | 0 |
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 751 | 751 | 0 | 0 | 1180 | 0 | 0 | 0 |
| u_core_engine | snix_axi_mm2mm | 1038 | 1038 | 0 | 0 | 296 | 0 | 1 | 0 |
| (u_core_engine) | snix_axi_mm2mm | 762 | 762 | 0 | 0 | 243 | 0 | 0 | 0 |
| axis_fifo_u0 | snix_axis_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 |
| u_fifo | snix_sync_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining

28
fpga/vivado_reports_withdsp/clock_interaction.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 02:57:58 2026
| Host : fedora running 64-bit unknown
| Command : report_clock_interaction -file /home/fallensigh/vivado_reports_withdsp/clock_interaction.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
--------------------------------------------------------------------------------------------------------------
Clock Interaction Report
Clock Interaction Table
-----------------------
WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock
From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints
----------------- ----------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- -------------------
cpu_clk cpu_clk rise - rise 1.14 0.00 0 17264 30.32 Clean Timed
cpu_clk sys_clk 0 162 Ignored Asynchronous Groups
mlkem_clk_clk_pll mlkem_clk_clk_pll rise - rise 12.91 0.00 0 74882 40.00 Clean Timed
mlkem_clk_clk_pll sys_clk rise - rise 16.72 0.00 0 61 20.00 Clean Timed
sys_clk cpu_clk 0 59 Ignored Asynchronous Groups
sys_clk mlkem_clk_clk_pll rise - rise 8.52 0.00 0 112 20.00 Clean Timed
sys_clk sys_clk rise - rise 0.42 0.00 0 23732 20.00 Clean Timed

76
fpga/vivado_reports_withdsp/clocks.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 02:57:58 2026
| Host : fedora running 64-bit unknown
| Command : report_clocks -file /home/fallensigh/vivado_reports_withdsp/clocks.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
----------------------------------------------------------------------------------------
Clock Report
Attributes
P: Propagated
G: Generated
A: Auto-derived
R: Renamed
V: Virtual
I: Inverted
S: Pin phase-shifted with Latency mode
Clock Period(ns) Waveform(ns) Attributes Sources
clk 20.000 {0.000 10.000} P {clk}
clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
mlkem_clk_clk_pll 40.000 {0.000 20.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
====================================================
Generated Clocks
====================================================
Generated Clock : clkfbout_clk_pll
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk
Multiply By : 1
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
Generated Clock : cpu_clk
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 5.161 10.323}
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
Generated Clock : mlkem_clk_clk_pll
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 10.000 20.000}
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
Generated Clock : sys_clk
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk
Multiply By : 1
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
====================================================
User Uncertainty
====================================================
====================================================
User Jitter
====================================================
Clock Jitter(ns)
clk 0.200

37
fpga/vivado_reports_withdsp/design_analysis_complexity.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 02:58:45 2026
| Host : fedora running 64-bit unknown
| Command : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_withdsp/design_analysis_complexity.rpt
| Design : soc_top
| Device : xc7a200t
| Design State : Routed
---------------------------------------------------------------------------------------------------------------------------------
Report Design Analysis
Table of Contents
-----------------
1. Complexity Characteristics (Cells)
1. Complexity Characteristics (Cells)
-------------------------------------
+---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM |
+---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
| (top) | soc_top | 0.49 | 3.76 | 108219 | 710(1.2%) | 5229(8.7%) | 8166(13.7%) | 8097(13.5%) | 8459(14.1%) | 29130(48.7%) | 1175 | 56 | 39 | 6074 | 0 |
| u_axi_axil_adapter | axi_axil_adapter | 0.50 | 5.92 | 1309 | 0(0.0%) | 8(0.7%) | 43(3.8%) | 100(8.9%) | 200(17.7%) | 776(68.9%) | 0 | 0 | 0 | 0 | 0 |
| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 |
| u_cdma_matmul_bridge | cdma_matmul_bridge | 0.56 | 2.22 | 1003 | 1(0.3%) | 66(17.3%) | 39(10.2%) | 174(45.7%) | 13(3.4%) | 88(23.1%) | 0 | 0 | 0 | 0 | 0 |
| u_cpu | core_top | 0.56 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 |
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.53 | 3.70 | 70959 | 286(0.8%) | 3478(9.4%) | 4960(13.4%) | 5940(16.0%) | 4261(11.5%) | 18098(48.9%) | 1169 | 40 | 18 | 5241 | 0 |
| u_matmul_axi_slave | matmul_axi_slave | 0.69 | 3.39 | 10715 | 18(0.2%) | 465(6.4%) | 1463(20.2%) | 312(4.3%) | 1333(18.4%) | 3646(50.4%) | 6 | 16 | 0 | 512 | 0 |
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.45 | 3.68 | 3535 | 136(7.0%) | 181(9.3%) | 328(16.8%) | 258(13.2%) | 297(15.2%) | 750(38.5%) | 0 | 0 | 1 | 4 | 0 |
+---------------------------+---------------------+------+----------------+-----------------+-----------+------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
* Complexity Ranges
** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal, 0.65 - 0.85 -> high, 0.85 - 1.0 -> very high
*** -* -> Not computable as cell size is very small

52
fpga/vivado_reports_withdsp/design_analysis_timing.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 02:58:13 2026
| Host : fedora running 64-bit unknown
| Command : report_design_analysis -timing -file /home/fallensigh/vivado_reports_withdsp/design_analysis_timing.rpt
| Design : soc_top
| Device : xc7a200t
| Design State : Routed
-------------------------------------------------------------------------------------------------------------------------
Report Design Analysis
Table of Contents
-----------------
1. Setup Path Characteristics 1-1
1. Setup Path Characteristics 1-1
---------------------------------
+---------------------------+----------------------------------------------------------------------------------------+
| Characteristics | Path #1 |
+---------------------------+----------------------------------------------------------------------------------------+
| Requirement | 20.000 |
| Path Delay | 15.252 |
| Logic Delay | 7.003(46%) |
| Net Delay | 8.249(54%) |
| Clock Skew | -3.954 |
| Slack | 0.424 |
| Clock Relationship | Safely Timed |
| Logic Levels | 14 |
| Routes | 12 |
| Logical Path | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 CARRY4 LUT6 CARRY4 LUT6 LUT6 LUT6 OBUF |
| Start Point Clock | sys_clk |
| End Point Clock | sys_clk |
| DSP Block | None |
| BRAM | None |
| IO Crossings | 3 |
| Config Crossings | 0 |
| SLR Crossings | 0 |
| PBlocks | 0 |
| High Fanout | 80 |
| Dont Touch | 0 |
| Mark Debug | 0 |
| Start Point Pin Primitive | FDCE/C |
| End Point Pin Primitive | base_ram_be_n[3] |
| Start Point Pin | ax_req_q_len_reg[1]/C |
| End Point Pin | base_ram_be_n[3] |
+---------------------------+----------------------------------------------------------------------------------------+
* Bounding box calculated as % of dimensions for the target device (436, 500)

911
fpga/vivado_reports_withdsp/drc.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 02:57:43 2026
| Host : fedora running 64-bit unknown
| Command : report_drc -file /home/fallensigh/vivado_reports_withdsp/drc.rpt
| Design : soc_top
| Device : xc7a200tfbg676-1
| Speed File : -1
| Design State : Fully Routed
------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: impl_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 174
+-----------+----------+----------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+----------------------------+------------+
| CHECK-3 | Warning | Report rule limit reached | 2 |
| DPIP-1 | Warning | Input pipelining | 47 |
| DPOP-1 | Warning | PREG Output pipelining | 29 |
| DPOP-2 | Warning | MREG Output pipelining | 56 |
| REQP-1839 | Warning | RAMB36 async control check | 20 |
| REQP-1840 | Warning | RAMB18 async control check | 20 |
+-----------+----------+----------------------------+------------+
2. REPORT DETAILS
-----------------
CHECK-3#1 Warning
Report rule limit reached
REQP-1839 rule limit reached: 20 violations have been found.
Related violations: <none>
CHECK-3#2 Warning
Report rule limit reached
REQP-1840 rule limit reached: 20 violations have been found.
Related violations: <none>
DPIP-1#1 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#2 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#3 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#4 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#5 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#6 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#7 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#8 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#9 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#10 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#11 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#12 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#13 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#14 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#15 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#16 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#17 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#18 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#19 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#20 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#21 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#22 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#23 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#24 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#25 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#26 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#27 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#28 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#29 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#30 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#31 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#32 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#33 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#34 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#35 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#36 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#37 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#38 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#39 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#40 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#41 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#42 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#43 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#44 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#45 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#46 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPIP-1#47 Warning
Input pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPOP-1#1 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#2 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#3 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#4 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#5 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#6 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#7 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#8 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#9 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#10 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#11 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#12 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#13 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#14 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#15 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#16 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#17 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#18 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#19 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#20 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#21 Warning
PREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7 output u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#22 Warning
PREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16 output u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#23 Warning
PREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#24 Warning
PREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0 output u_matmul_axi_slave/mult_inst[1].u_mult/prod0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#25 Warning
PREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#26 Warning
PREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0 output u_matmul_axi_slave/mult_inst[2].u_mult/prod0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#27 Warning
PREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#28 Warning
PREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0 output u_matmul_axi_slave/mult_inst[3].u_mult/prod0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-1#29 Warning
PREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17 output u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-2#1 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#2 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#3 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#4 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#5 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#6 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#7 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#8 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#9 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#10 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#11 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#12 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#13 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#14 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#15 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#16 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#17 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#18 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#19 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#20 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#21 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#22 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#23 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#24 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#25 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#26 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#27 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#28 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#29 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#30 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#31 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce0_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#32 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce1_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#33 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce2_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#34 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce3_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#35 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_reduce_return7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#36 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#37 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#38 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#39 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#40 Warning
MREG Output pipelining
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 multiplier stage u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#41 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16 multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#42 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#43 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#44 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#45 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0 multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#46 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#47 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#48 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#49 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0 multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#50 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#51 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#52 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#53 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0 multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#54 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17 multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#55 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
DPOP-2#56 Warning
MREG Output pipelining
DSP u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg__0 multiplier stage u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
REQP-1839#1 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#2 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#3 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#4 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#5 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#6 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#7 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#8 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#9 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#10 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#11 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#12 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#13 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#14 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#15 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#16 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#17 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#18 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#19 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#20 Warning
RAMB36 async control check
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#1 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#2 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#3 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#4 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#5 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#6 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#7 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#8 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#9 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#10 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#11 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#12 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#13 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#14 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#15 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#16 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#17 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#18 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#19 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1840#20 Warning
RAMB18 async control check
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

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fpga/vivado_reports_withdsp/high_fanout.rpt Normal file
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 02:57:58 2026
| Host : fedora running 64-bit unknown
| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/vivado_reports_withdsp/high_fanout.rpt
| Design : soc_top
| Device : xc7a200t
----------------------------------------------------------------------------------------------------------------------------------------------
High Fan-out Nets Information
1. Summary
----------
+---------------------------------------------------------------------------------------+--------+-------------+
| Net Name | Fanout | Driver Type |
+---------------------------------------------------------------------------------------+--------+-------------+
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/delay_reg[1] | 24229 | LUT5 |
| pll_clk.u_clk_pll/inst/sys_clk | 9603 | BUFG |
| pll_clk.u_rst_sys/prst | 3749 | LUT1 |
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_0 | 2140 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mb_en | 2121 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 | 1611 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0] | 1608 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state[2]_i_3_n_0 | 1604 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 | 1601 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] | 1601 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[1] | 1601 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[2] | 1601 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1122 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE |
| pll_clk.u_rst_mlkem/delay_reg[1]_0 | 1066 | LUT1 |
| u_cpu/reset | 799 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sel0[3] | 773 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0] | 769 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1] | 769 | CARRY4 |
| u_cpu/u_mul/E[0] | 716 | LUT1 |
| u_matmul_axi_slave/w_addr[2] | 667 | FDRE |
| u_matmul_axi_slave/w_addr[3] | 604 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[0]_0[0] | 512 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sel0[4] | 388 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2] | 385 | CARRY4 |
| u_cpu/wb_stage/w_index[0] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[1] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[2] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[3] | 358 | LUT6 |
| u_cpu/wb_stage/w_index[4] | 358 | LUT6 |
| u_matmul_axi_slave/Q[0] | 354 | FDRE |
| u_matmul_axi_slave/acc_idx_d4[0] | 354 | FDRE |
| u_matmul_axi_slave/acc_idx_d4[1] | 354 | FDRE |
| u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE |
| u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE |
| u_cpu/wb_stage/we_0 | 324 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 290 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_4 | 288 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[4] | 272 | FDCE |
| u_matmul_axi_slave/sel0[1] | 264 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 263 | RAMB18E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 263 | RAMB18E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 262 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 262 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 261 | RAMB18E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 261 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 259 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 259 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 259 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 259 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 259 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 259 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 259 | RAMB36E1 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[0] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[10] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[11] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[1] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[2] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[5] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[6] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[7] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[8] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[9] | 256 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/E[0] | 256 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 |
| u_matmul_axi_slave/mult_inst[0].u_mult/E[0] | 256 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 |
| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT3 |
| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[0] | 244 | FDSE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[7] | 239 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[2] | 238 | FDCE |
| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 |
| u_cpu/mem_stage/E[0] | 234 | LUT6 |
| u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/axiOut_7_wstrb[0] | 232 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 231 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 224 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[5] | 223 | FDCE |
| u_matmul_axi_slave/w_addr[5] | 223 | FDRE |
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 |
| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 |
| u_cpu/u_csr/tlbw_r_tlbidx[2] | 210 | FDRE |
| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0] | 203 | FDRE |
| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[1] | 203 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2] | 196 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[6] | 195 | FDCE |
| u_cpu/wb_stage/Q[33] | 194 | FDRE |
| u_cpu/wb_stage/Q[34] | 194 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5] | 194 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3] | 193 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 188 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r_reg[3]_rep_n_0 | 187 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 184 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 184 | FDCE |
| u_snix_axil_cdma_mux_8ch/u_core_engine/_zz_ram_port1_reg[32] | 182 | LUT4 |
| u_cpu/wb_stage/ws_valid_reg_0 | 180 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r_reg[5]_rep_n_0 | 180 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 179 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[0] | 177 | FDCE |
| u_matmul_axi_slave/p_0_in__0 | 176 | LUT4 |
| u_matmul_axi_slave/p_0_in__0__0 | 176 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 174 | FDCE |
| u_cpu/wb_stage/Q[37] | 173 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_out[0] | 169 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[2]_rep__0_n_0 | 168 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[4] | 165 | FDCE |
| u_cpu/wb_stage/Q[32] | 164 | FDRE |
| u_cpu/wb_stage/Q[35] | 163 | FDRE |
| u_cpu/wb_stage/Q[36] | 162 | FDRE |
| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0 | 161 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[6] | 161 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 160 | FDCE |
| u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]_0 | 160 | LUT5 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[3] | 158 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3] | 156 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_5 | 153 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[0] | 153 | FDCE |
| u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0 | 151 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep_n_0 | 151 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[7] | 151 | FDCE |
| u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1 | 150 | CARRY4 |
| u_cpu/dcache/awaddr[31]_i_3_n_0 | 148 | LUT2 |
| u_cpu/dcache/awaddr[31]_i_4_n_0 | 148 | LUT2 |
| u_matmul_axi_slave/mult_inst[3].u_mult/FSM_sequential_state_reg | 148 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 146 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_57_n_0 | 144 | LUT4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[1] | 142 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[4] | 141 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[5] | 141 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[6] | 141 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[7] | 141 | FDCE |
| u_cpu/dcache/write_buffer_state | 140 | FDRE |
| u_matmul_axi_slave/mult_inst[3].u_mult/cur_bank_reg_rep | 140 | LUT3 |
| u_matmul_axi_slave/mult_inst[3].u_mult/req_0_reg | 140 | LUT3 |
| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 140 | LUT6 |
| u_cpu/u_csr/tlbw_r_tlbidx[0] | 139 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[3] | 139 | FDCE |
| u_matmul_axi_slave/sel0[0] | 139 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[3] | 138 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[2] | 138 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]_i_5_n_7 | 137 | CARRY4 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_6_11_i_34_n_0 | 137 | LUT4 |
| u_cpu/u_csr/tlbw_r_tlbidx[1] | 136 | FDRE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1080]_i_5_n_0 | 136 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1081]_i_5_n_0 | 136 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1082]_i_5_n_0 | 136 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1083]_i_5_n_0 | 136 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1084]_i_6_n_0 | 136 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_3_n_0 | 136 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_9_n_0 | 136 | LUT6 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1087]_i_3_n_0 | 136 | LUT3 |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/rl_idx[3] | 136 | FDCE |
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 | 136 | FDCE |
+---------------------------------------------------------------------------------------+--------+-------------+

1653
fpga/vivado_reports_withdsp/methodology.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

5918
fpga/vivado_reports_withdsp/mlkem_clk_timing.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

165
fpga/vivado_reports_impl/routed_power.rpt → fpga/vivado_reports_withdsp/power.rpt
View File

@@ -1,16 +1,16 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:46:05 2026
| Date : Wed Jul 8 02:58:09 2026
| Host : fedora running 64-bit unknown
| Command : report_power -file ./vivado_reports_impl/routed_power.rpt
| Command : report_power -file /home/fallensigh/vivado_reports_withdsp/power.rpt
| Design : soc_top
| Device : xc7a200tfbg676-1
| Design State : routed
| Grade : commercial
| Process : typical
| Characterization : Production
----------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
Power Report
@@ -30,14 +30,14 @@ Table of Contents
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 0.918 |
| Total On-Chip Power (W) | 0.512 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.777 |
| Device Static (W) | 0.142 |
| Dynamic (W) | 0.371 |
| Device Static (W) | 0.141 |
| Effective TJA (C/W) | 1.9 |
| Max Ambient (C) | 83.3 |
| Junction Temperature (C) | 26.7 |
| Max Ambient (C) | 84.0 |
| Junction Temperature (C) | 26.0 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
@@ -52,22 +52,22 @@ Table of Contents
+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks | 0.028 | 6 | --- | --- |
| Slice Logic | 0.200 | 137329 | --- | --- |
| LUT as Logic | 0.193 | 79570 | 133800 | 59.47 |
| CARRY4 | 0.003 | 3590 | 33450 | 10.73 |
| Register | 0.002 | 38619 | 267600 | 14.43 |
| LUT as Distributed RAM | 0.001 | 628 | 46200 | 1.36 |
| LUT as Shift Register | <0.001 | 1094 | 46200 | 2.37 |
| F7/F8 Muxes | <0.001 | 5664 | 133800 | 4.23 |
| BUFG | <0.001 | 2 | 32 | 6.25 |
| Others | 0.000 | 302 | --- | --- |
| Signals | 0.368 | 99001 | --- | --- |
| Block RAM | 0.016 | 25.5 | 365 | 6.99 |
| PLL | 0.137 | 1 | 10 | 10.00 |
| I/O | 0.028 | 202 | 400 | 50.50 |
| Static Power | 0.142 | | | |
| Total | 0.918 | | | |
| Clocks | 0.037 | 7 | --- | --- |
| Slice Logic | 0.056 | 109753 | --- | --- |
| LUT as Logic | 0.052 | 56469 | 133800 | 42.20 |
| CARRY4 | 0.001 | 1802 | 33450 | 5.39 |
| Register | <0.001 | 39141 | 267600 | 14.63 |
| LUT as Shift Register | <0.001 | 1175 | 46200 | 2.54 |
| LUT as Distributed RAM | <0.001 | 740 | 46200 | 1.60 |
| F7/F8 Muxes | <0.001 | 6090 | 133800 | 4.55 |
| Others | 0.000 | 334 | --- | --- |
| Signals | 0.095 | 78236 | --- | --- |
| Block RAM | 0.018 | 23.5 | 365 | 6.44 |
| PLL | 0.132 | 1 | 10 | 10.00 |
| DSPs | 0.010 | 56 | 740 | 7.57 |
| I/O | 0.023 | 202 | 400 | 50.50 |
| Static Power | 0.141 | | | |
| Total | 0.512 | | | |
+--------------------------+-----------+----------+-----------+-----------------+
@@ -77,16 +77,16 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 1.000 | 0.657 | 0.624 | 0.033 |
| Vccaux | 1.800 | 0.101 | 0.070 | 0.031 |
| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 |
| Vccint | 1.000 | 0.257 | 0.225 | 0.032 |
| Vccaux | 1.800 | 0.099 | 0.069 | 0.031 |
| Vcco33 | 3.300 | 0.011 | 0.006 | 0.005 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 1.000 | 0.002 | 0.001 | 0.001 |
| Vccbram | 1.000 | 0.003 | 0.001 | 0.001 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
@@ -96,17 +96,17 @@ Table of Contents
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
2. Settings
@@ -130,14 +130,15 @@ Table of Contents
2.2 Clock Constraints
---------------------
+------------------+-----------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+------------------+-----------------------------------------+-----------------+
| clk | clk | 20.0 |
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
+------------------+-----------------------------------------+-----------------+
+-------------------+------------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------------------+------------------------------------------+-----------------+
| clk | clk | 20.0 |
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 40.0 |
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
+-------------------+------------------------------------------+-----------------+
3. Detailed Reports
@@ -146,45 +147,33 @@ Table of Contents
3.1 By Hierarchy
----------------
+------------------------------+-----------+
| Name | Power (W) |
+------------------------------+-----------+
| soc_top | 0.777 |
| pll_clk.u_clk_pll | 0.138 |
| inst | 0.138 |
| u_Axi_CDC | 0.003 |
| u_axi_axil_adapter | 0.002 |
| axi_axil_adapter_wr_inst | 0.001 |
| u_axi_uart_controller | 0.002 |
| uart0 | 0.001 |
| regs | 0.001 |
| u_cdma_matmul_bridge | 0.001 |
| u_confreg | 0.001 |
| u_cpu | 0.027 |
| addr_trans | 0.002 |
| tlb_entry | 0.002 |
| btb | 0.003 |
| dcache | 0.004 |
| icache | 0.005 |
| u_csr | 0.001 |
| u_mul | 0.007 |
| wb_stage | 0.001 |
| u_fft_mlkem_axi_slave | 0.467 |
| u_fft_controller | 0.027 |
| u_FFT | 0.024 |
| u_out0 | 0.001 |
| u_out1 | 0.001 |
| u_mlkem_axi_slave | 0.436 |
| u_mlkem | 0.411 |
| u_prng_axi_slave | 0.004 |
| u_matmul_axi_slave | 0.081 |
| mult_inst[0].u_mult | 0.003 |
| mult_inst[1].u_mult | 0.003 |
| mult_inst[2].u_mult | 0.003 |
| mult_inst[3].u_mult | 0.003 |
| u_snix_axil_cdma_mux_8ch | 0.011 |
| u_core_engine | 0.006 |
| axis_fifo_u0 | 0.005 |
+------------------------------+-----------+
+----------------------------+-----------+
| Name | Power (W) |
+----------------------------+-----------+
| soc_top | 0.371 |
| pll_clk.u_clk_pll | 0.133 |
| inst | 0.133 |
| u_Axi_CDC | 0.002 |
| wFifo | 0.001 |
| u_axi_uart_controller | 0.001 |
| u_cdma_matmul_bridge | 0.001 |
| u_cpu | 0.017 |
| addr_trans | 0.002 |
| tlb_entry | 0.002 |
| btb | 0.003 |
| dcache | 0.004 |
| icache | 0.005 |
| u_csr | 0.001 |
| u_fft_mlkem_axi_slave | 0.134 |
| u_fft_controller | 0.032 |
| u_FFT | 0.030 |
| u_mlkem_axi_cdc | 0.001 |
| u_mlkem_axi_slave | 0.101 |
| u_mlkem | 0.098 |
| u_matmul_axi_slave | 0.047 |
| u_snix_axil_cdma_mux_8ch | 0.008 |
| u_core_engine | 0.004 |
| axis_fifo_u0 | 0.002 |
+----------------------------+-----------+

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fpga/vivado_reports_withdsp/route_status.rpt Normal file
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@@ -0,0 +1,12 @@
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 116330 :
# of nets not needing routing.......... : 38083 :
# of internally routed nets........ : 37618 :
# of nets with no loads............ : 465 :
# of routable nets..................... : 78247 :
# of fully routed nets............. : 78247 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

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fpga/vivado_reports_impl/routed_utilization.rpt → fpga/vivado_reports_withdsp/utilization.rpt
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@@ -1,13 +1,13 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:45:45 2026
| Date : Wed Jul 8 02:57:49 2026
| Host : fedora running 64-bit unknown
| Command : report_utilization -file ./vivado_reports_impl/routed_utilization.rpt
| Command : report_utilization -file /home/fallensigh/vivado_reports_withdsp/utilization.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Routed
---------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
Utilization Design Information
@@ -31,16 +31,16 @@ Table of Contents
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 74191 | 0 | 133800 | 55.45 |
| LUT as Logic | 72517 | 0 | 133800 | 54.20 |
| LUT as Memory | 1674 | 0 | 46200 | 3.62 |
| LUT as Distributed RAM | 628 | 0 | | |
| LUT as Shift Register | 1046 | 0 | | |
| Slice Registers | 38619 | 0 | 267600 | 14.43 |
| Register as Flip Flop | 38619 | 0 | 267600 | 14.43 |
| Slice LUTs | 53691 | 0 | 133800 | 40.13 |
| LUT as Logic | 51836 | 0 | 133800 | 38.74 |
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
| LUT as Distributed RAM | 740 | 0 | | |
| LUT as Shift Register | 1115 | 0 | | |
| Slice Registers | 39141 | 0 | 267600 | 14.63 |
| Register as Flip Flop | 39141 | 0 | 267600 | 14.63 |
| Register as Latch | 0 | 0 | 267600 | 0.00 |
| F7 Muxes | 4261 | 0 | 66900 | 6.37 |
| F8 Muxes | 1403 | 0 | 33450 | 4.19 |
| F7 Muxes | 4519 | 0 | 66900 | 6.75 |
| F8 Muxes | 1571 | 0 | 33450 | 4.70 |
+----------------------------+-------+-------+-----------+-------+
@@ -56,10 +56,10 @@ Table of Contents
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 101 | Yes | - | Set |
| 25523 | Yes | - | Reset |
| 134 | Yes | Set | - |
| 12861 | Yes | Reset | - |
| 24 | Yes | - | Set |
| 26265 | Yes | - | Reset |
| 126 | Yes | Set | - |
| 12726 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -69,28 +69,28 @@ Table of Contents
+--------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------------------------------------+-------+-------+-----------+-------+
| Slice | 21994 | 0 | 33450 | 65.75 |
| SLICEL | 14311 | 0 | | |
| SLICEM | 7683 | 0 | | |
| LUT as Logic | 72517 | 0 | 133800 | 54.20 |
| Slice | 18732 | 0 | 33450 | 56.00 |
| SLICEL | 12122 | 0 | | |
| SLICEM | 6610 | 0 | | |
| LUT as Logic | 51836 | 0 | 133800 | 38.74 |
| using O5 output only | 4 | | | |
| using O6 output only | 58168 | | | |
| using O5 and O6 | 14345 | | | |
| LUT as Memory | 1674 | 0 | 46200 | 3.62 |
| LUT as Distributed RAM | 628 | 0 | | |
| using O6 output only | 43877 | | | |
| using O5 and O6 | 7955 | | | |
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
| LUT as Distributed RAM | 740 | 0 | | |
| using O5 output only | 0 | | | |
| using O6 output only | 60 | | | |
| using O5 and O6 | 568 | | | |
| LUT as Shift Register | 1046 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 996 | | | |
| using O5 and O6 | 48 | | | |
| Slice Registers | 38619 | 0 | 267600 | 14.43 |
| Register driven from within the Slice | 24282 | | | |
| Register driven from outside the Slice | 14337 | | | |
| LUT in front of the register is unused | 5492 | | | |
| LUT in front of the register is used | 8845 | | | |
| Unique Control Sets | 1413 | | 33450 | 4.22 |
| using O5 and O6 | 680 | | | |
| LUT as Shift Register | 1115 | 0 | | |
| using O5 output only | 47 | | | |
| using O6 output only | 1008 | | | |
| using O5 and O6 | 60 | | | |
| Slice Registers | 39141 | 0 | 267600 | 14.63 |
| Register driven from within the Slice | 19059 | | | |
| Register driven from outside the Slice | 20082 | | | |
| LUT in front of the register is unused | 11401 | | | |
| LUT in front of the register is used | 8681 | | | |
| Unique Control Sets | 1440 | | 33450 | 4.30 |
+--------------------------------------------+-------+-------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
@@ -101,9 +101,9 @@ Table of Contents
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 25.5 | 0 | 365 | 6.99 |
| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
| RAMB36E1 only | 10 | | | |
| Block RAM Tile | 23.5 | 0 | 365 | 6.44 |
| RAMB36/FIFO* | 8 | 0 | 365 | 2.19 |
| RAMB36E1 only | 8 | | | |
| RAMB18 | 31 | 0 | 730 | 4.25 |
| RAMB18E1 only | 31 | | | |
+-------------------+------+-------+-----------+-------+
@@ -113,11 +113,12 @@ Table of Contents
4. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 740 | 0.00 |
+-----------+------+-------+-----------+-------+
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 56 | 0 | 740 | 7.57 |
| DSP48E1 only | 56 | | | |
+----------------+------+-------+-----------+-------+
5. IO and GT Specific
@@ -153,7 +154,7 @@ Table of Contents
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 5 | 0 | 32 | 15.63 |
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
| BUFIO | 0 | 0 | 40 | 0.00 |
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
@@ -187,30 +188,31 @@ Table of Contents
+-----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+-----------+-------+---------------------+
| LUT6 | 35769 | LUT |
| FDCE | 25523 | Flop & Latch |
| LUT5 | 15462 | LUT |
| LUT3 | 13062 | LUT |
| FDRE | 12861 | Flop & Latch |
| LUT4 | 12795 | LUT |
| LUT2 | 9006 | LUT |
| MUXF7 | 4261 | MuxFx |
| CARRY4 | 3590 | CarryLogic |
| MUXF8 | 1403 | MuxFx |
| LUT6 | 29130 | LUT |
| FDCE | 26265 | Flop & Latch |
| FDRE | 12726 | Flop & Latch |
| LUT5 | 8459 | LUT |
| LUT3 | 8166 | LUT |
| LUT4 | 8097 | LUT |
| LUT2 | 5229 | LUT |
| MUXF7 | 4519 | MuxFx |
| CARRY4 | 1802 | CarryLogic |
| MUXF8 | 1571 | MuxFx |
| RAMD32 | 1060 | Distributed Memory |
| SRLC32E | 992 | Distributed Memory |
| RAMD32 | 892 | Distributed Memory |
| LUT1 | 768 | LUT |
| RAMS32 | 272 | Distributed Memory |
| FDSE | 134 | Flop & Latch |
| LUT1 | 710 | LUT |
| RAMS32 | 328 | Distributed Memory |
| SRL16E | 183 | Distributed Memory |
| FDSE | 126 | Flop & Latch |
| IBUF | 104 | IO |
| SRL16E | 102 | Distributed Memory |
| FDPE | 101 | Flop & Latch |
| OBUF | 98 | IO |
| OBUFT | 66 | IO |
| DSP48E1 | 56 | Block Arithmetic |
| RAMD64E | 32 | Distributed Memory |
| RAMB18E1 | 31 | Block Memory |
| RAMB36E1 | 10 | Block Memory |
| BUFG | 5 | Clock |
| FDPE | 24 | Flop & Latch |
| RAMB36E1 | 8 | Block Memory |
| BUFG | 4 | Clock |
| PLLE2_ADV | 1 | Clock |
+-----------+-------+---------------------+

350
fpga/vivado_reports_impl/routed_utilization_hier.rpt → fpga/vivado_reports_withdsp/utilization_hier.rpt
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@@ -1,13 +1,13 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Sun Jul 5 23:45:46 2026
| Date : Wed Jul 8 02:57:50 2026
| Host : fedora running 64-bit unknown
| Command : report_utilization -hierarchical -hierarchical_depth 10 -file ./vivado_reports_impl/routed_utilization_hier.rpt
| Command : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_withdsp/utilization_hier.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Routed
---------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------
Utilization Design Information
@@ -21,114 +21,115 @@ Table of Contents
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| soc_top | (top) | 74191 | 72517 | 628 | 1046 | 38619 | 10 | 31 | 0 |
| (soc_top) | (top) | 2094 | 2038 | 56 | 0 | 4 | 0 | 0 | 0 |
| soc_top | (top) | 53691 | 51836 | 740 | 1115 | 39141 | 8 | 31 | 56 |
| (soc_top) | (top) | 102 | 46 | 56 | 0 | 9 | 0 | 0 | 0 |
| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| inst | clk_pll_clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| inst | clk_pll__clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| pll_clk.u_rst_sys | rst_sync_0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 518 | 518 | 0 | 0 | 151 | 0 | 0 | 0 |
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_67 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_50 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_66 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_51 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_65 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_52 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_64 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 31 | 31 | 0 | 0 | 11 | 0 | 0 | 0 |
| pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 381 | 381 | 0 | 0 | 151 | 0 | 0 | 0 |
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 6 | 6 | 0 | 0 | 24 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_82 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_65 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_81 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_66 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_80 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_67 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_79 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_61 | 25 | 25 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_62 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_63 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_76 | 27 | 27 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_77 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_78 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_58 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_59 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_60 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_73 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_74 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_75 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_55 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_56 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_57 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 60 | 60 | 0 | 0 | 11 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7_70 | 20 | 20 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_71 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3_72 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 23 | 23 | 0 | 0 | 11 | 0 | 0 | 0 |
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7 | 48 | 48 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 |
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 89 | 89 | 0 | 0 | 25 | 0 | 0 | 0 |
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 73 | 73 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1_54 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 |
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 |
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1_53 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 |
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 181 | 181 | 0 | 0 | 17 | 0 | 0 | 0 |
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 165 | 165 | 0 | 0 | 8 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 |
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 26 | 26 | 0 | 0 | 14 | 0 | 0 | 0 |
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 19 | 19 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_Axi_CDC | Axi_CDC | 495 | 367 | 128 | 0 | 309 | 0 | 0 | 0 |
| arFifo | StreamFifoCC_3 | 257 | 221 | 36 | 0 | 73 | 0 | 0 | 0 |
| (arFifo) | StreamFifoCC_3 | 251 | 215 | 36 | 0 | 61 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_48 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_49 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
| awFifo | StreamFifoCC | 111 | 75 | 36 | 0 | 75 | 0 | 0 | 0 |
| (awFifo) | StreamFifoCC | 104 | 68 | 36 | 0 | 61 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| bFifo | StreamFifoCC_2 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 |
| (bFifo) | StreamFifoCC_2 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_4 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_6 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| rFifo | StreamFifoCC_4 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 |
| (rFifo) | StreamFifoCC_4 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_1 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| wFifo | StreamFifoCC_1 | 68 | 40 | 28 | 0 | 69 | 0 | 0 | 0 |
| (wFifo) | StreamFifoCC_1 | 64 | 36 | 28 | 0 | 53 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_8 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| u_axi_axil_adapter | axi_axil_adapter | 1339 | 1339 | 0 | 0 | 161 | 0 | 0 | 0 |
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 635 | 635 | 0 | 0 | 81 | 0 | 0 | 0 |
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 704 | 704 | 0 | 0 | 80 | 0 | 0 | 0 |
| cmdArbiter | StreamArbiter_7 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 96 | 96 | 0 | 0 | 25 | 0 | 0 | 0 |
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 75 | 75 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1_69 | 21 | 21 | 0 | 0 | 13 | 0 | 0 | 0 |
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 40 | 40 | 0 | 0 | 18 | 0 | 0 | 0 |
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1_68 | 21 | 21 | 0 | 0 | 2 | 0 | 0 | 0 |
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 53 | 53 | 0 | 0 | 17 | 0 | 0 | 0 |
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 38 | 38 | 0 | 0 | 8 | 0 | 0 | 0 |
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 32 | 32 | 0 | 0 | 14 | 0 | 0 | 0 |
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 20 | 20 | 0 | 0 | 12 | 0 | 0 | 0 |
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 |
| u_Axi_CDC | Axi_CDC | 412 | 284 | 128 | 0 | 317 | 0 | 0 | 0 |
| arFifo | StreamFifoCC_3_48 | 185 | 149 | 36 | 0 | 77 | 0 | 0 | 0 |
| (arFifo) | StreamFifoCC_3_48 | 180 | 144 | 36 | 0 | 65 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_63 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_64 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| awFifo | StreamFifoCC_49 | 102 | 66 | 36 | 0 | 79 | 0 | 0 | 0 |
| (awFifo) | StreamFifoCC_49 | 98 | 62 | 36 | 0 | 65 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_10_60 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_61 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_62 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| bFifo | StreamFifoCC_2_50 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 |
| (bFifo) | StreamFifoCC_2_50 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_5_57 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_4_58 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_6_59 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| rFifo | StreamFifoCC_4_51 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 |
| (rFifo) | StreamFifoCC_4_51 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_55 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_1_56 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| wFifo | StreamFifoCC_1_52 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 |
| (wFifo) | StreamFifoCC_1_52 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_7_53 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_8_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| u_axi_axil_adapter | axi_axil_adapter | 1072 | 1072 | 0 | 0 | 173 | 0 | 0 | 0 |
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 497 | 497 | 0 | 0 | 85 | 0 | 0 | 0 |
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 575 | 575 | 0 | 0 | 88 | 0 | 0 | 0 |
| u_axi_dvi | axi_dvi | 284 | 284 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_axi_ram | axi_wrap_ram_sp_external | 355 | 355 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_sram_sp | axi2sram_sp_external | 355 | 355 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_uart_controller | axi_uart_controller | 686 | 670 | 16 | 0 | 457 | 0 | 0 | 0 |
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 252 | 252 | 0 | 0 | 120 | 0 | 0 | 0 |
| uart0 | UART_TOP | 434 | 418 | 16 | 0 | 337 | 0 | 0 | 0 |
| regs | uart_regs | 434 | 418 | 16 | 0 | 337 | 0 | 0 | 0 |
| (regs) | uart_regs | 118 | 118 | 0 | 0 | 155 | 0 | 0 | 0 |
| u_axi_ram | axi_wrap_ram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_sram_sp | axi2sram_sp_external | 351 | 351 | 0 | 0 | 78 | 0 | 0 | 0 |
| u_axi_uart_controller | axi_uart_controller | 683 | 667 | 16 | 0 | 457 | 0 | 0 | 0 |
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 251 | 251 | 0 | 0 | 120 | 0 | 0 | 0 |
| uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
| regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
| (regs) | uart_regs | 119 | 119 | 0 | 0 | 155 | 0 | 0 | 0 |
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 |
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
| fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 |
| (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 |
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
| transmitter | uart_transmitter | 84 | 76 | 8 | 0 | 56 | 0 | 0 | 0 |
| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 |
| (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 |
| fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 |
| (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 |
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
| u_cdma_matmul_bridge | cdma_matmul_bridge | 247 | 247 | 0 | 0 | 578 | 0 | 0 | 0 |
| u_cdma_matmul_bridge | cdma_matmul_bridge | 250 | 250 | 0 | 0 | 578 | 0 | 0 | 0 |
| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 |
| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 |
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
| u_cpu | core_top | 8552 | 8300 | 252 | 0 | 5591 | 0 | 20 | 0 |
| u_cpu | core_top | 8556 | 8304 | 252 | 0 | 5591 | 0 | 20 | 0 |
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
| addr_trans | addr_trans | 2246 | 2106 | 140 | 0 | 1244 | 0 | 0 | 0 |
| addr_trans | addr_trans | 2247 | 2107 | 140 | 0 | 1244 | 0 | 0 | 0 |
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
| tlb_entry | tlb_entry | 2246 | 2106 | 140 | 0 | 1204 | 0 | 0 | 0 |
| tlb_entry | tlb_entry | 2247 | 2107 | 140 | 0 | 1204 | 0 | 0 | 0 |
| axi_bridge | axi_bridge | 39 | 39 | 0 | 0 | 214 | 0 | 0 | 0 |
| btb | btb | 1048 | 968 | 80 | 0 | 1611 | 0 | 0 | 0 |
| (btb) | btb | 1045 | 965 | 80 | 0 | 1611 | 0 | 0 | 0 |
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
| dcache | dcache | 553 | 521 | 32 | 0 | 146 | 0 | 10 | 0 |
| (dcache) | dcache | 88 | 56 | 32 | 0 | 138 | 0 | 0 | 0 |
| dcache | dcache | 552 | 520 | 32 | 0 | 146 | 0 | 10 | 0 |
| (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
@@ -139,11 +140,11 @@ Table of Contents
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_46 | 42 | 42 | 0 | 0 | 0 | 0 | 1 | 0 |
| exe_stage | exe_stage | 664 | 664 | 0 | 0 | 233 | 0 | 0 | 0 |
| (exe_stage) | exe_stage | 633 | 633 | 0 | 0 | 233 | 0 | 0 | 0 |
| tagv_ram_way[1].u | tagv_sram_46 | 43 | 43 | 0 | 0 | 0 | 0 | 1 | 0 |
| exe_stage | exe_stage | 665 | 665 | 0 | 0 | 233 | 0 | 0 | 0 |
| (exe_stage) | exe_stage | 634 | 634 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
| icache | icache | 235 | 235 | 0 | 0 | 55 | 0 | 10 | 0 |
| icache | icache | 234 | 234 | 0 | 0 | 55 | 0 | 10 | 0 |
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
@@ -156,100 +157,119 @@ Table of Contents
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
| tagv_ram_way[1].u | tagv_sram_35 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
| id_stage | id_stage | 1050 | 1050 | 0 | 0 | 108 | 0 | 0 | 0 |
| id_stage | id_stage | 1052 | 1052 | 0 | 0 | 108 | 0 | 0 | 0 |
| if_stage | if_stage | 134 | 134 | 0 | 0 | 173 | 0 | 0 | 0 |
| mem_stage | mem_stage | 115 | 115 | 0 | 0 | 211 | 0 | 0 | 0 |
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
| u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 |
| u_mul | mul | 935 | 935 | 0 | 0 | 592 | 0 | 0 | 0 |
| wb_stage | wb_stage | 684 | 684 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 47584 | 46544 | 0 | 1040 | 25915 | 10 | 10 | 0 |
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 17 | 17 | 0 | 0 | 6 | 0 | 0 | 0 |
| u_fft_controller | fft_controller | 6890 | 5850 | 0 | 1040 | 1087 | 8 | 4 | 0 |
| (u_fft_controller) | fft_controller | 90 | 90 | 0 | 0 | 104 | 0 | 0 | 0 |
| u_FFT | FFT | 6781 | 5741 | 0 | 1040 | 983 | 8 | 0 | 0 |
| SU1 | SdfUnit | 2145 | 1377 | 0 | 768 | 197 | 2 | 0 | 0 |
| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 |
| u_mul | mul | 933 | 933 | 0 | 0 | 592 | 0 | 0 | 0 |
| wb_stage | wb_stage | 689 | 689 | 0 | 0 | 233 | 0 | 0 | 0 |
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 32945 | 31724 | 112 | 1109 | 26787 | 8 | 10 | 40 |
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| u_fft_controller | fft_controller | 2647 | 1607 | 0 | 1040 | 1083 | 6 | 4 | 16 |
| (u_fft_controller) | fft_controller | 123 | 123 | 0 | 0 | 100 | 0 | 0 | 0 |
| u_FFT | FFT | 2495 | 1455 | 0 | 1040 | 983 | 6 | 0 | 16 |
| SU1 | SdfUnit | 1070 | 302 | 0 | 768 | 197 | 2 | 0 | 4 |
| (SU1) | SdfUnit | 205 | 205 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 |
| MU | Multiply_26 | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_27 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU2 | SdfUnit__parameterized0 | 1566 | 1374 | 0 | 192 | 197 | 2 | 0 | 0 |
| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 |
| DB1 | DelayBuffer | 562 | 50 | 0 | 512 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized0 | 256 | 0 | 0 | 256 | 32 | 0 | 0 | 0 |
| MU | Multiply_26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 |
| TW | Twiddle_27 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU2 | SdfUnit__parameterized0 | 492 | 300 | 0 | 192 | 197 | 2 | 0 | 4 |
| (SU2) | SdfUnit__parameterized0 | 73 | 73 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_21 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
| MU | Multiply_22 | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_23 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU3 | SdfUnit__parameterized1 | 1415 | 1367 | 0 | 48 | 197 | 2 | 0 | 0 |
| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_16 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_17 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| MU | Multiply_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
| TW | Twiddle_23 | 3 | 3 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU3 | SdfUnit__parameterized1 | 347 | 299 | 0 | 48 | 197 | 0 | 0 | 4 |
| (SU3) | SdfUnit__parameterized1 | 75 | 75 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
| MU | Multiply_18 | 609 | 609 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle_19 | 539 | 539 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU4 | SdfUnit__parameterized2 | 1397 | 1365 | 0 | 32 | 197 | 2 | 0 | 0 |
| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_14 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_15 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| MU | Multiply_19 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
| SU4 | SdfUnit__parameterized2 | 327 | 295 | 0 | 32 | 197 | 2 | 0 | 4 |
| (SU4) | SdfUnit__parameterized2 | 69 | 69 | 0 | 0 | 133 | 0 | 0 | 0 |
| BF1 | Butterfly_15 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0_16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
| MU | Multiply | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
| TW | Twiddle | 536 | 536 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU5 | SdfUnit__parameterized3 | 259 | 259 | 0 | 0 | 195 | 0 | 0 | 0 |
| (SU5) | SdfUnit__parameterized3 | 35 | 35 | 0 | 0 | 99 | 0 | 0 | 0 |
| MU | Multiply | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
| TW | Twiddle | 2 | 2 | 0 | 0 | 0 | 2 | 0 | 0 |
| SU5 | SdfUnit__parameterized3 | 260 | 260 | 0 | 0 | 195 | 0 | 0 | 0 |
| (SU5) | SdfUnit__parameterized3 | 68 | 68 | 0 | 0 | 99 | 0 | 0 | 0 |
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
| BF2 | Butterfly__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_in1 | my_bram0_11 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out0 | my_bram0_12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out1 | my_bram0_13 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_mlkem_axi_slave | mlkem_axi_slave | 40179 | 40179 | 0 | 0 | 24484 | 2 | 6 | 0 |
| (u_mlkem_axi_slave) | mlkem_axi_slave | 3620 | 3620 | 0 | 0 | 1021 | 0 | 0 | 0 |
| u_mlkem | mlkem_top | 36605 | 36605 | 0 | 0 | 23463 | 2 | 6 | 0 |
| (u_mlkem) | mlkem_top | 2505 | 2505 | 0 | 0 | 4907 | 0 | 0 | 0 |
| u_bank_a | sd_bram__parameterized0 | 39 | 39 | 0 | 0 | 0 | 1 | 1 | 0 |
| u_bank_se | sd_bram__parameterized1 | 62 | 62 | 0 | 0 | 0 | 1 | 0 | 0 |
| u_bank_t | sd_bram__parameterized2 | 468 | 468 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_in0 | my_bram0 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_in1 | my_bram0_12 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out0 | my_bram0_13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_out1 | my_bram0_14 | 25 | 25 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_mlkem_axi_cdc | Axi_CDC_5 | 256 | 144 | 112 | 0 | 272 | 0 | 0 | 0 |
| arFifo | StreamFifoCC_3 | 51 | 23 | 28 | 0 | 55 | 0 | 0 | 0 |
| (arFifo) | StreamFifoCC_3 | 42 | 14 | 28 | 0 | 43 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9_10 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| awFifo | StreamFifoCC | 40 | 16 | 24 | 0 | 49 | 0 | 0 | 0 |
| (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_9 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
| bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 |
| (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 |
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
| rFifo | StreamFifoCC_4 | 56 | 28 | 28 | 0 | 72 | 0 | 0 | 0 |
| (rFifo) | StreamFifoCC_4 | 49 | 21 | 28 | 0 | 56 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 |
| wFifo | StreamFifoCC_1 | 91 | 63 | 28 | 0 | 69 | 0 | 0 | 0 |
| (wFifo) | StreamFifoCC_1 | 86 | 58 | 28 | 0 | 53 | 0 | 0 | 0 |
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
| u_mlkem_axi_slave | mlkem_axi_slave | 30043 | 29974 | 0 | 69 | 25426 | 2 | 6 | 24 |
| (u_mlkem_axi_slave) | mlkem_axi_slave | 1278 | 1278 | 0 | 0 | 1064 | 0 | 0 | 0 |
| u_mlkem | mlkem_top | 28768 | 28699 | 0 | 69 | 24362 | 2 | 6 | 24 |
| (u_mlkem) | mlkem_top | 2326 | 2326 | 0 | 0 | 4911 | 0 | 0 | 0 |
| u_bank_a | sd_bram__parameterized0 | 49 | 49 | 0 | 0 | 0 | 1 | 1 | 0 |
| u_bank_se | sd_bram__parameterized1 | 61 | 61 | 0 | 0 | 0 | 1 | 0 | 0 |
| u_bank_t | sd_bram__parameterized2 | 488 | 488 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_c_in_bram | sd_bram | 1291 | 1291 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_cbd | sample_cbd_sync_shared | 2459 | 2459 | 0 | 0 | 3199 | 0 | 0 | 0 |
| u_comp | comp_decomp_sync | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
| u_pipe | pipeline_reg | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
| u_ct_bram | sd_bram_4 | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_dkp_bram | sd_bram_5 | 100 | 100 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_ek_bram | sd_bram_6 | 225 | 225 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_keccak | keccak_core | 5240 | 5240 | 0 | 0 | 1619 | 0 | 0 | 0 |
| u_ntt | ntt_core | 13299 | 13299 | 0 | 0 | 3354 | 0 | 0 | 0 |
| u_pmul | poly_mul_sync | 7336 | 7336 | 0 | 0 | 6314 | 0 | 0 | 0 |
| (u_pmul) | poly_mul_sync | 4958 | 4958 | 0 | 0 | 6314 | 0 | 0 | 0 |
| u_bc | basecase_mul | 2378 | 2378 | 0 | 0 | 0 | 0 | 0 | 0 |
| (u_bc) | basecase_mul | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul1 | barrett_mul | 969 | 969 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul2 | barrett_mul_7 | 118 | 118 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul3 | barrett_mul_8 | 561 | 561 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul4 | barrett_mul_9 | 549 | 549 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_mul_zeta | barrett_mul_10 | 129 | 129 | 0 | 0 | 0 | 0 | 0 | 0 |
| u_sha3 | sha3_top_shared | 1970 | 1970 | 0 | 0 | 2388 | 0 | 0 | 0 |
| u_snt | sample_ntt_sync_shared | 1433 | 1433 | 0 | 0 | 1669 | 0 | 0 | 0 |
| u_prng_axi_slave | prng_axi_slave | 500 | 500 | 0 | 0 | 338 | 0 | 0 | 0 |
| u_matmul_axi_slave | matmul_axi_slave | 9858 | 9676 | 176 | 6 | 3208 | 0 | 0 | 0 |
| (u_matmul_axi_slave) | matmul_axi_slave | 5742 | 5560 | 176 | 6 | 2440 | 0 | 0 | 0 |
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[1].u_mult | pipelined_mult_32x32_1 | 998 | 998 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[2].u_mult | pipelined_mult_32x32_2 | 1061 | 1061 | 0 | 0 | 192 | 0 | 0 | 0 |
| mult_inst[3].u_mult | pipelined_mult_32x32_3 | 996 | 996 | 0 | 0 | 192 | 0 | 0 | 0 |
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1813 | 1813 | 0 | 0 | 1476 | 0 | 1 | 0 |
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 604 | 604 | 0 | 0 | 1180 | 0 | 0 | 0 |
| u_core_engine | snix_axi_mm2mm | 1211 | 1211 | 0 | 0 | 296 | 0 | 1 | 0 |
| (u_core_engine) | snix_axi_mm2mm | 773 | 773 | 0 | 0 | 243 | 0 | 0 | 0 |
| axis_fifo_u0 | snix_axis_fifo | 438 | 438 | 0 | 0 | 53 | 0 | 1 | 0 |
| u_fifo | snix_sync_fifo | 438 | 438 | 0 | 0 | 53 | 0 | 1 | 0 |
| u_cbd | sample_cbd_sync_shared | 2512 | 2512 | 0 | 0 | 3199 | 0 | 0 | 0 |
| u_comp | comp_decomp_sync | 322 | 321 | 0 | 1 | 269 | 0 | 0 | 3 |
| u_ct_bram | sd_bram_6 | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_dkp_bram | sd_bram_7 | 73 | 73 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_ek_bram | sd_bram_8 | 388 | 388 | 0 | 0 | 0 | 0 | 1 | 0 |
| u_keccak | keccak_core | 5622 | 5622 | 0 | 0 | 1606 | 0 | 0 | 0 |
| u_ntt | ntt_core | 8192 | 8149 | 0 | 43 | 3743 | 0 | 0 | 6 |
| (u_ntt) | ntt_core | 6140 | 6124 | 0 | 16 | 3364 | 0 | 0 | 0 |
| u_bf | butterfly_unit_pipe | 1922 | 1896 | 0 | 26 | 224 | 0 | 0 | 3 |
| (u_bf) | butterfly_unit_pipe | 69 | 44 | 0 | 25 | 75 | 0 | 0 | 0 |
| u_barrett | barrett_mul_pipe_9 | 1854 | 1853 | 0 | 1 | 149 | 0 | 0 | 3 |
| u_scl | barrett_mul_pipe | 131 | 130 | 0 | 1 | 155 | 0 | 0 | 3 |
| u_pmul | poly_mul_sync | 2830 | 2805 | 0 | 25 | 6577 | 0 | 0 | 15 |
| (u_pmul) | poly_mul_sync | 2474 | 2474 | 0 | 0 | 6299 | 0 | 0 | 0 |
| u_bc | basecase_mul_pipe | 421 | 396 | 0 | 25 | 278 | 0 | 0 | 15 |
| u_sha3 | sha3_top_shared | 3175 | 3175 | 0 | 0 | 2388 | 0 | 0 | 0 |
| u_snt | sample_ntt_sync_shared | 1439 | 1439 | 0 | 0 | 1669 | 0 | 0 | 0 |
| u_matmul_axi_slave | matmul_axi_slave | 6600 | 6418 | 176 | 6 | 2831 | 0 | 0 | 16 |
| (u_matmul_axi_slave) | matmul_axi_slave | 5796 | 5614 | 176 | 6 | 2303 | 0 | 0 | 0 |
| mult_inst[0].u_mult | pipelined_mult_32x32 | 203 | 203 | 0 | 0 | 132 | 0 | 0 | 4 |
| mult_inst[1].u_mult | pipelined_mult_32x32_2 | 202 | 202 | 0 | 0 | 132 | 0 | 0 | 4 |
| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 202 | 202 | 0 | 0 | 132 | 0 | 0 | 4 |
| mult_inst[3].u_mult | pipelined_mult_32x32_4 | 200 | 200 | 0 | 0 | 132 | 0 | 0 | 4 |
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1673 | 1673 | 0 | 0 | 1476 | 0 | 1 | 0 |
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 687 | 687 | 0 | 0 | 1180 | 0 | 0 | 0 |
| u_core_engine | snix_axi_mm2mm | 988 | 988 | 0 | 0 | 296 | 0 | 1 | 0 |
| (u_core_engine) | snix_axi_mm2mm | 763 | 763 | 0 | 0 | 243 | 0 | 0 | 0 |
| axis_fifo_u0 | snix_axis_fifo | 225 | 225 | 0 | 0 | 53 | 0 | 1 | 0 |
| u_fifo | snix_sync_fifo | 225 | 225 | 0 | 0 | 53 | 0 | 1 | 0 |
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining