28 lines
872 B
Plaintext
28 lines
872 B
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Sun Jul 5 23:35:51 2026
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| Host : fedora running 64-bit unknown
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| Command : report_clock_networks -file ./vivado_reports/impl_clock_networks.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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Clock Networks Report
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Constrained Clocks
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-------------------
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Clock clk (50MHz)(endpoints: 17477 clock, 2 nonclock)
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Port clk
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Unconstrained Clocks
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-------------------
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Clock Q (endpoints: 23490 clock, 1 nonclock)
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FDCE/Q (u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg)
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