Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache

The open-la500 core has USE_CACHE enabled. Writes to 0x1c400000
go to the write-back data cache and never reach the SRAM model
before the testbench checks ExtRAM. Use the 0xA0000000 uncached
segment (same pattern as fft_dma/main.c).

sdk/software/examples/matmul_test/main.c

@@ -32,7 +32,11 @@ unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L;
 unsigned long CORE_CLOCKS_PER_SEC   = 33000000L;
 
 /* ─── Memory layout ──────────────────────────────────────────────── */
-#define EXTRAM_BASE       0x1c400000   /* ExtRAM: bit22=1 in RAM controller */
+/* ExtRAM physical: 0x1c400000 (bit22=1 in RAM controller).
+ * Use uncached segment (0xA0000000) to bypass CPU data cache —
+ * otherwise writes never reach the SRAM model before testbench checks. */
+#define EXTRAM_BASE_PHYS  0x1c400000
+#define EXTRAM_BASE       (0xA0000000 | (EXTRAM_BASE_PHYS & 0x1FFFFFFF))
 
 #define SRC_BASE          0             /* word offset — source A/B matrices  */
 #define N_GROUPS          10            /* must match testbench default       */