Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache

The open-la500 core has USE_CACHE enabled. Writes to 0x1c400000
go to the write-back data cache and never reach the SRAM model
before the testbench checks ExtRAM. Use the 0xA0000000 uncached
segment (same pattern as fft_dma/main.c).

sdk/software/bsp/include/dma.h

@@ -0,0 +1,30 @@
+#pragma once
+
+#include <stdint.h>
+
+
+typedef struct {
+    volatile uint32_t SRC_ADDR;  // 0x00: 源地址
+    volatile uint32_t DST_ADDR;  // 0x04: 目的地址
+    volatile uint32_t LENGTH;    // 0x08: 传输总字节数
+    volatile uint32_t TAG;       // 0x0C: 软件 Tag (硬件不处理，留给软件标记任务用)
+    volatile uint32_t CTRL;      // 0x10: 控制寄存器 (配置 Burst 属性 + 启动)
+    volatile uint32_t STATUS;    // 0x14: 状态寄存器 (Busy, Done)
+    volatile uint32_t RESV[10];  // 0x18 ~ 0x3C: 保留空间，凑齐 0x40 字节
+} dma_ch_regs_t;
+
+// DMA 控制器基地址
+#define CDMA_MUX_BASE 0xbf300000
+#define DMA_CH(i)     ((volatile dma_ch_regs_t*)(CDMA_MUX_BASE + (i) * 0x40))
+
+// CTRL 寄存器位定义
+#define CTRL_START_BIT       (1 << 0)
+#define CTRL_BURST_SIZE(x)   (((x) & 0x7) << 3)  // Bits [5:3]: AXI AxSIZE (0=1B, 1=2B, 2=4B, 3=8B)
+#define CTRL_BURST_LEN(x)    (((x) & 0xFF) << 6) // Bits [13:6]: AXI AxLEN (0=1 beat, 15=16 beats)
+
+// STATUS 寄存器位定义
+#define STATUS_BUSY_BIT      (1 << 0)
+#define STATUS_DONE_BIT      (1 << 1)
+
+void dma_start_transfer(int ch_id, uint32_t src, uint32_t dst, uint32_t bytes, uint32_t tag);
+void dma_wait_polling(int ch_id);

sdk/software/bsp/include/fft.h

@@ -0,0 +1,16 @@
+#pragma once
+
+#define FFT_BASE          0xbf400000
+#define FFT_IN_RE_BASE    (FFT_BASE + 0x1000)
+#define FFT_IN_IM_BASE    (FFT_BASE + 0x2000)
+#define FFT_OUT_RE_BASE   (FFT_BASE + 0x3000)
+#define FFT_OUT_IM_BASE   (FFT_BASE + 0x4000)
+#define FFT_CSR_REG       (FFT_BASE + 0xF000)
+#define FFT_CTRL_START    (1 << 4)
+#define FFT_STAT_DONE     (1 << 1)
+#define FFT_STAT_BUSY     (1 << 0)
+#define FFT_POINT_NUM     1024
+
+void fft_start();
+void fft_wait();
+unsigned int fft_get_csr();