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fix(asm): add uart_putdec and confreg_time.h to user-sample

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Ultraworked with [Sisyphus](https://github.com/code-yeongyu/oh-my-openagent)

Co-authored-by: Sisyphus <clio-agent@sisyphuslabs.ai>
This commit is contained in:
FallenSigh
2026-07-01 21:17:55 +08:00
parent 38f2051f04
commit dde6a46b49
1 changed files with 28 additions and 0 deletions
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28
sdk/software/examples/asm/user-sample.c
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@@ -11,6 +11,7 @@
*/ */
#include <dma.h> #include <dma.h>
#include <confreg_time.h>
/* ─── UART 16550 direct access (bypasses slow printf/picolibc) ──────── */ /* ─── UART 16550 direct access (bypasses slow printf/picolibc) ──────── */
#define UART_THR (*(volatile unsigned char *)0xbf000000) #define UART_THR (*(volatile unsigned char *)0xbf000000)
@@ -34,6 +35,24 @@ static void uart_puthex(unsigned int val) {
} }
} }
static void uart_putdec(unsigned int val) {
char buf[10];
int i = 0;
if (val == 0) {
uart_tx('0');
return;
}
while (val != 0) {
buf[i++] = (char)('0' + (val % 10));
val /= 10;
}
while (i > 0) {
uart_tx((unsigned char)buf[--i]);
}
}
/* ─── Configurable group count (default 5000) ──────────────────────── */ /* ─── Configurable group count (default 5000) ──────────────────────── */
#ifndef MATMUL_GROUP_NUM #ifndef MATMUL_GROUP_NUM
#define MATMUL_GROUP_NUM 5000 #define MATMUL_GROUP_NUM 5000
@@ -88,12 +107,14 @@ int main(void)
volatile dma_ch_regs_t *ch1 = DMA_CH(1); volatile dma_ch_regs_t *ch1 = DMA_CH(1);
unsigned int crc; unsigned int crc;
unsigned int cycle_start, cycle_end, cycles, time_us;
int g, bank; int g, bank;
unsigned int ctrl_start[2] = {CTRL_START_B0, CTRL_START_B1}; unsigned int ctrl_start[2] = {CTRL_START_B0, CTRL_START_B1};
/* ── Start marker (must be first output) ──────────────────── */ /* ── Start marker (must be first output) ──────────────────── */
uart_puts("MATMUL_START\r\n"); uart_puts("MATMUL_START\r\n");
cycle_start = get_clock_count();
// Reset IP state // Reset IP state
*mat_status = STATUS_DONE | STATUS_ERROR; *mat_status = STATUS_DONE | STATUS_ERROR;
@@ -205,12 +226,19 @@ int main(void)
ch1->CTRL = DMA_CTRL_VAL; ch1->CTRL = DMA_CTRL_VAL;
while (!(ch1->STATUS & STATUS_DONE_BIT)) {} while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
ch1->STATUS = STATUS_DONE_BIT; ch1->STATUS = STATUS_DONE_BIT;
cycle_end = get_clock_count();
cycles = cycle_end - cycle_start;
time_us = cycles / (CORE_CLOCKS_PER_SEC / 1000000UL);
/* ── Read hardware CRC32 ──────────────────────────────────── */ /* ── Read hardware CRC32 ──────────────────────────────────── */
crc = *mat_crc; crc = *mat_crc;
uart_puts("MATMUL_CRC32="); uart_puts("MATMUL_CRC32=");
uart_puthex(crc); uart_puthex(crc);
uart_puts("\r\nMATMUL_CYCLES=");
uart_putdec(cycles);
uart_puts("\r\nMATMUL_TIME_US=");
uart_putdec(time_us);
uart_puts("\r\nMATMUL_DONE\r\n"); uart_puts("\r\nMATMUL_DONE\r\n");
return 0; return 0;