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fix: typo

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FallenSigh
2026-07-14 22:50:34 +08:00
parent 459d08fa65
commit c4f34426e6
2 changed files with 17 additions and 13 deletions
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6
rtl/ip/APB_UART/URT/uart_defines.h
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@@ -113,7 +113,7 @@ THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// FIFO parameter defines // FIFO parameter defines
`define UART_FIFO_WIDTH 8 `define UART_FIFO_WIDTH 8
`define UART_FIFO_DEPTH 16 `define UART_FIFO_DEPTH 32
`define UART_FIFO_POINTER_W 4 `define UART_FIFO_POINTER_W 5
`define UART_FIFO_COUNTER_W 5 `define UART_FIFO_COUNTER_W 6
`define UART_FIFO_REC_WIDTH 11 `define UART_FIFO_REC_WIDTH 11

24
rtl/ip/ram_wrap/axi_wrap_ram_sp_external.v
View File

@@ -75,17 +75,21 @@ module axi_wrap_ram_sp_external (
output axi_bvalid , output axi_bvalid ,
input axi_bready , input axi_bready ,
//BaseRAM\Uffffffff\Uffffffff\Uffffffff inout [31:0] base_ram_data, //BaseRAM\Uffffffff\Uffffffff\u0763\Uffffffff\Uffffffff\Uffffffff\u03bb\UffffffffCPLD\Uffffffff\Uffffffff\Uffffffff\u06bf\Uffffffff\Uffffffff\Uffffffff\Uffffffff output [19:0] base_ram_addr, //BaseRAM\Uffffffff\Uffffffff\Uffffffff // BaseRAM
output [ 3:0] base_ram_be_n, //BaseRAM\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff0 inout [31:0] base_ram_data,
output base_ram_ce_n, //BaseRAM\u01ac\u0461\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff output [19:0] base_ram_addr,
output base_ram_oe_n, //BaseRAM\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff output [ 3:0] base_ram_be_n,
output base_ram_we_n, //BaseRAM\u0434\u02b9\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff output base_ram_ce_n,
output base_ram_oe_n,
output base_ram_we_n,
//ExtRAM\Uffffffff\Uffffffff\Uffffffff inout [31:0] ext_ram_data, //ExtRAM\Uffffffff\Uffffffff\Uffffffff output [19:0] ext_ram_addr, //ExtRAM\Uffffffff\Uffffffff\Uffffffff // ExtRAM
output [ 3:0] ext_ram_be_n, //ExtRAM\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff0 inout [31:0] ext_ram_data,
output ext_ram_ce_n, //ExtRAM\u01ac\u0461\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff output [19:0] ext_ram_addr,
output ext_ram_oe_n, //ExtRAM\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff output [ 3:0] ext_ram_be_n,
output ext_ram_we_n //ExtRAM\u0434\u02b9\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff output ext_ram_ce_n,
output ext_ram_oe_n,
output ext_ram_we_n
); );