From c4f34426e609673f7b11146d56c8c85abd9942f8 Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Tue, 14 Jul 2026 22:50:34 +0800 Subject: [PATCH] fix: typo --- rtl/ip/APB_UART/URT/uart_defines.h | 6 +++--- rtl/ip/ram_wrap/axi_wrap_ram_sp_external.v | 24 +++++++++++++--------- 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/rtl/ip/APB_UART/URT/uart_defines.h b/rtl/ip/APB_UART/URT/uart_defines.h index 02bc376..c6ab962 100644 --- a/rtl/ip/APB_UART/URT/uart_defines.h +++ b/rtl/ip/APB_UART/URT/uart_defines.h @@ -113,7 +113,7 @@ THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // FIFO parameter defines `define UART_FIFO_WIDTH 8 -`define UART_FIFO_DEPTH 16 -`define UART_FIFO_POINTER_W 4 -`define UART_FIFO_COUNTER_W 5 +`define UART_FIFO_DEPTH 32 +`define UART_FIFO_POINTER_W 5 +`define UART_FIFO_COUNTER_W 6 `define UART_FIFO_REC_WIDTH 11 diff --git a/rtl/ip/ram_wrap/axi_wrap_ram_sp_external.v b/rtl/ip/ram_wrap/axi_wrap_ram_sp_external.v index 4d5c6b2..3bc102a 100644 --- a/rtl/ip/ram_wrap/axi_wrap_ram_sp_external.v +++ b/rtl/ip/ram_wrap/axi_wrap_ram_sp_external.v @@ -75,17 +75,21 @@ module axi_wrap_ram_sp_external ( output axi_bvalid , input axi_bready , - //BaseRAM\Uffffffff\Uffffffff\Uffffffff inout [31:0] base_ram_data, //BaseRAM\Uffffffff\Uffffffff\u0763\Uffffffff\Uffffffff\Uffffffff\u03bb\UffffffffCPLD\Uffffffff\Uffffffff\Uffffffff\u06bf\Uffffffff\Uffffffff\Uffffffff\Uffffffff output [19:0] base_ram_addr, //BaseRAM\Uffffffff\Uffffffff\Uffffffff - output [ 3:0] base_ram_be_n, //BaseRAM\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff0 - output base_ram_ce_n, //BaseRAM\u01ac\u0461\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff - output base_ram_oe_n, //BaseRAM\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff - output base_ram_we_n, //BaseRAM\u0434\u02b9\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff + // BaseRAM + inout [31:0] base_ram_data, + output [19:0] base_ram_addr, + output [ 3:0] base_ram_be_n, + output base_ram_ce_n, + output base_ram_oe_n, + output base_ram_we_n, - //ExtRAM\Uffffffff\Uffffffff\Uffffffff inout [31:0] ext_ram_data, //ExtRAM\Uffffffff\Uffffffff\Uffffffff output [19:0] ext_ram_addr, //ExtRAM\Uffffffff\Uffffffff\Uffffffff - output [ 3:0] ext_ram_be_n, //ExtRAM\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff0 - output ext_ram_ce_n, //ExtRAM\u01ac\u0461\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff - output ext_ram_oe_n, //ExtRAM\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff - output ext_ram_we_n //ExtRAM\u0434\u02b9\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff\Uffffffff + // ExtRAM + inout [31:0] ext_ram_data, + output [19:0] ext_ram_addr, + output [ 3:0] ext_ram_be_n, + output ext_ram_ce_n, + output ext_ram_oe_n, + output ext_ram_we_n );