fallensigh/ciciec2026
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fix samples ntt bugs & set PLL & optimize matmul

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FallenSigh
2026-07-15 10:36:38 +08:00
parent fc91511950
commit c4d36515cc
7 changed files with 274 additions and 120 deletions
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17
rtl/soc_top.v
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@@ -635,9 +635,10 @@ wire [31:0] matmul_ep_rd_data;
wire matmul_ep_rd_ready;
wire matmul_direct_start_valid;
wire matmul_direct_start_bank;
wire matmul_direct_done_clear;
wire matmul_direct_crc_clear;
wire matmul_direct_done;
wire matmul_direct_done_clear;
wire matmul_direct_crc_clear;
wire matmul_direct_done;
wire matmul_direct_crc_idle;
wire mlkem_intr;
AxiCrossbar_2x8 u_AxiCrossbar_2x8 (
@@ -1577,8 +1578,9 @@ matmul_axi_slave u_matmul_axi_slave (
.mat_start_valid(matmul_direct_start_valid),
.mat_start_bank (matmul_direct_start_bank),
.mat_done_clear (matmul_direct_done_clear),
.mat_crc_clear (matmul_direct_crc_clear),
.mat_done (matmul_direct_done),
.mat_crc_clear (matmul_direct_crc_clear),
.mat_done (matmul_direct_done),
.mat_crc_idle (matmul_direct_crc_idle),
.intr (matmul_intr)
);
@@ -1828,8 +1830,9 @@ cdma_matmul_bridge #(
.mat_start_valid (matmul_direct_start_valid),
.mat_start_bank (matmul_direct_start_bank),
.mat_done_clear (matmul_direct_done_clear),
.mat_crc_clear (matmul_direct_crc_clear),
.mat_done (matmul_direct_done),
.mat_crc_clear (matmul_direct_crc_clear),
.mat_done (matmul_direct_done),
.mat_crc_idle (matmul_direct_crc_idle),
.seq_done_irq (cdma_matmul_seq_irq)
);