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Fix SRAM model: level-sensitive write for burst support

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FallenSigh
2026-06-25 15:40:28 +08:00
parent a24b5cff6e
commit b331301584
1 changed files with 9 additions and 18 deletions
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25
sim/sram.v
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@@ -28,24 +28,15 @@ module sram_sp #(
assign write_enable[3:0] = (~ram_be_n) & {4{(~ram_ce_n) & (~ram_we_n)}};
always@(posedge write_enable[0]) begin
#10;
if(~ram_be_n[0]) begin
BRAM[ram_addr][7:0] <= ram_data[7:0];
if (ram_addr >= 10'd320 && ram_addr < 10'd400)
$display("SRAM WR addr=%d data=%08x be0=%b", ram_addr, ram_data, ram_be_n[0]);
// Level-sensitive write (supports burst writes)
always @(*) begin
#1;
if (!ram_ce_n && !ram_we_n) begin
if (!ram_be_n[0]) BRAM[ram_addr][7:0] = ram_data[7:0];
if (!ram_be_n[1]) BRAM[ram_addr][15:8] = ram_data[15:8];
if (!ram_be_n[2]) BRAM[ram_addr][23:16] = ram_data[23:16];
if (!ram_be_n[3]) BRAM[ram_addr][31:24] = ram_data[31:24];
end
always@(posedge write_enable[1]) begin
#10;
if(~ram_be_n[1]) BRAM[ram_addr][15:8] <= ram_data[15:8];
end
always@(posedge write_enable[2]) begin
#10;
if(~ram_be_n[2]) BRAM[ram_addr][23:16] <= ram_data[23:16];
end
always@(posedge write_enable[3]) begin
#10;
if(~ram_be_n[3]) BRAM[ram_addr][31:24] <= ram_data[31:24];
end
wire [31:0] RDATA = BRAM[ram_addr];