From b3313015841941250faee72bab9eb76dc7ed8907 Mon Sep 17 00:00:00 2001
From: FallenSigh <fallensigh@gmail.com>
Date: Thu, 25 Jun 2026 15:40:28 +0800
Subject: [PATCH] Fix SRAM model: level-sensitive write for burst support

---
 sim/sram.v | 27 +++++++++------------------
 1 file changed, 9 insertions(+), 18 deletions(-)

diff --git a/sim/sram.v b/sim/sram.v
index 14033c7..b52d40f 100644
--- a/sim/sram.v
+++ b/sim/sram.v
@@ -28,24 +28,15 @@ module sram_sp #(
     assign write_enable[3:0] = (~ram_be_n) & {4{(~ram_ce_n) & (~ram_we_n)}};
 
 
-    always@(posedge write_enable[0]) begin
-        #10;
-        if(~ram_be_n[0]) begin
-            BRAM[ram_addr][7:0] <= ram_data[7:0];
-            if (ram_addr >= 10'd320 && ram_addr < 10'd400)
-                $display("SRAM WR addr=%d data=%08x be0=%b", ram_addr, ram_data, ram_be_n[0]);
-    end
-    always@(posedge write_enable[1]) begin
-		#10;
-        if(~ram_be_n[1]) BRAM[ram_addr][15:8] <= ram_data[15:8];
-    end
-    always@(posedge write_enable[2]) begin
-		#10;
-        if(~ram_be_n[2]) BRAM[ram_addr][23:16] <= ram_data[23:16];
-    end
-    always@(posedge write_enable[3]) begin
-		#10;
-        if(~ram_be_n[3]) BRAM[ram_addr][31:24] <= ram_data[31:24];
+    // Level-sensitive write (supports burst writes)
+    always @(*) begin
+        #1;
+        if (!ram_ce_n && !ram_we_n) begin
+            if (!ram_be_n[0]) BRAM[ram_addr][7:0]   = ram_data[7:0];
+            if (!ram_be_n[1]) BRAM[ram_addr][15:8]  = ram_data[15:8];
+            if (!ram_be_n[2]) BRAM[ram_addr][23:16] = ram_data[23:16];
+            if (!ram_be_n[3]) BRAM[ram_addr][31:24] = ram_data[31:24];
+        end
     end
 
     wire [31:0] RDATA  = BRAM[ram_addr];