fallensigh/ciciec2026
Archived
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

update vivado reports

Browse Source
This commit is contained in:
FallenSigh
2026-07-10 04:47:36 +08:00
parent 03b3415e76
commit b052b12885
32 changed files with 76444 additions and 236658 deletions
Download Patch File Download Diff File Expand all files Collapse all files

108
fpga/vivado_reports_nodsp/utilization.rpt
View File

@@ -1,13 +1,13 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 03:34:05 2026
| Date : Fri Jul 10 04:14:47 2026
| Host : fedora running 64-bit unknown
| Command : report_utilization -file /home/fallensigh/vivado_reports_nodsp/utilization.rpt
| Command : report_utilization -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization.rpt
| Design : soc_top
| Device : 7a200tfbg676-1
| Design State : Routed
------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
@@ -31,16 +31,16 @@ Table of Contents
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 60995 | 0 | 133800 | 45.59 |
| LUT as Logic | 59140 | 0 | 133800 | 44.20 |
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
| LUT as Distributed RAM | 740 | 0 | | |
| Slice LUTs | 71196 | 0 | 133800 | 53.21 |
| LUT as Logic | 69453 | 0 | 133800 | 51.91 |
| LUT as Memory | 1743 | 0 | 46200 | 3.77 |
| LUT as Distributed RAM | 628 | 0 | | |
| LUT as Shift Register | 1115 | 0 | | |
| Slice Registers | 39931 | 0 | 267600 | 14.92 |
| Register as Flip Flop | 39931 | 0 | 267600 | 14.92 |
| Slice Registers | 39690 | 0 | 267600 | 14.83 |
| Register as Flip Flop | 39690 | 0 | 267600 | 14.83 |
| Register as Latch | 0 | 0 | 267600 | 0.00 |
| F7 Muxes | 4480 | 0 | 66900 | 6.70 |
| F8 Muxes | 1556 | 0 | 33450 | 4.65 |
| F7 Muxes | 4565 | 0 | 66900 | 6.82 |
| F8 Muxes | 1520 | 0 | 33450 | 4.54 |
+----------------------------+-------+-------+-----------+-------+
@@ -57,9 +57,9 @@ Table of Contents
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 24 | Yes | - | Set |
| 26637 | Yes | - | Reset |
| 26562 | Yes | - | Reset |
| 139 | Yes | Set | - |
| 13131 | Yes | Reset | - |
| 12965 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -69,28 +69,28 @@ Table of Contents
+--------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------------------------------------+-------+-------+-----------+-------+
| Slice | 20066 | 0 | 33450 | 59.99 |
| SLICEL | 13210 | 0 | | |
| SLICEM | 6856 | 0 | | |
| LUT as Logic | 59140 | 0 | 133800 | 44.20 |
| Slice | 21289 | 0 | 33450 | 63.64 |
| SLICEL | 13965 | 0 | | |
| SLICEM | 7324 | 0 | | |
| LUT as Logic | 69453 | 0 | 133800 | 51.91 |
| using O5 output only | 2 | | | |
| using O6 output only | 49931 | | | |
| using O5 and O6 | 9207 | | | |
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
| LUT as Distributed RAM | 740 | 0 | | |
| using O6 output only | 57661 | | | |
| using O5 and O6 | 11790 | | | |
| LUT as Memory | 1743 | 0 | 46200 | 3.77 |
| LUT as Distributed RAM | 628 | 0 | | |
| using O5 output only | 0 | | | |
| using O6 output only | 60 | | | |
| using O5 and O6 | 680 | | | |
| using O5 and O6 | 568 | | | |
| LUT as Shift Register | 1115 | 0 | | |
| using O5 output only | 47 | | | |
| using O6 output only | 1008 | | | |
| using O5 and O6 | 60 | | | |
| Slice Registers | 39931 | 0 | 267600 | 14.92 |
| Register driven from within the Slice | 20433 | | | |
| Register driven from outside the Slice | 19498 | | | |
| LUT in front of the register is unused | 10788 | | | |
| LUT in front of the register is used | 8710 | | | |
| Unique Control Sets | 1304 | | 33450 | 3.90 |
| Slice Registers | 39690 | 0 | 267600 | 14.83 |
| Register driven from within the Slice | 24917 | | | |
| Register driven from outside the Slice | 14773 | | | |
| LUT in front of the register is unused | 6243 | | | |
| LUT in front of the register is used | 8530 | | | |
| Unique Control Sets | 1278 | | 33450 | 3.82 |
+--------------------------------------------+-------+-------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
@@ -101,9 +101,9 @@ Table of Contents
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 23.5 | 0 | 365 | 6.44 |
| RAMB36/FIFO* | 8 | 0 | 365 | 2.19 |
| RAMB36E1 only | 8 | | | |
| Block RAM Tile | 25.5 | 0 | 365 | 6.99 |
| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
| RAMB36E1 only | 10 | | | |
| RAMB18 | 31 | 0 | 730 | 4.25 |
| RAMB18E1 only | 31 | | | |
+-------------------+------+-------+-----------+-------+
@@ -113,12 +113,11 @@ Table of Contents
4. DSP
------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 16 | 0 | 740 | 2.16 |
| DSP48E1 only | 16 | | | |
+----------------+------+-------+-----------+-------+
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 740 | 0.00 |
+-----------+------+-------+-----------+-------+
5. IO and GT Specific
@@ -154,7 +153,7 @@ Table of Contents
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
| BUFGCTRL | 3 | 0 | 32 | 9.38 |
| BUFIO | 0 | 0 | 40 | 0.00 |
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
@@ -188,20 +187,20 @@ Table of Contents
+-----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+-----------+-------+---------------------+
| LUT6 | 35413 | LUT |
| FDCE | 26637 | Flop & Latch |
| FDRE | 13131 | Flop & Latch |
| LUT3 | 9384 | LUT |
| LUT5 | 8477 | LUT |
| LUT4 | 7294 | LUT |
| LUT2 | 6978 | LUT |
| MUXF7 | 4480 | MuxFx |
| CARRY4 | 2859 | CarryLogic |
| MUXF8 | 1556 | MuxFx |
| RAMD32 | 1060 | Distributed Memory |
| LUT6 | 37981 | LUT |
| FDCE | 26562 | Flop & Latch |
| FDRE | 12965 | Flop & Latch |
| LUT5 | 12781 | LUT |
| LUT4 | 10316 | LUT |
| LUT3 | 10135 | LUT |
| LUT2 | 9228 | LUT |
| MUXF7 | 4565 | MuxFx |
| CARRY4 | 3546 | CarryLogic |
| MUXF8 | 1520 | MuxFx |
| SRLC32E | 992 | Distributed Memory |
| LUT1 | 801 | LUT |
| RAMS32 | 328 | Distributed Memory |
| RAMD32 | 892 | Distributed Memory |
| LUT1 | 802 | LUT |
| RAMS32 | 272 | Distributed Memory |
| SRL16E | 183 | Distributed Memory |
| FDSE | 139 | Flop & Latch |
| IBUF | 104 | IO |
@@ -210,9 +209,8 @@ Table of Contents
| RAMD64E | 32 | Distributed Memory |
| RAMB18E1 | 31 | Block Memory |
| FDPE | 24 | Flop & Latch |
| DSP48E1 | 16 | Block Arithmetic |
| RAMB36E1 | 8 | Block Memory |
| BUFG | 4 | Clock |
| RAMB36E1 | 10 | Block Memory |
| BUFG | 3 | Clock |
| PLLE2_ADV | 1 | Clock |
+-----------+-------+---------------------+