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update vivado reports

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FallenSigh
2026-07-10 04:47:36 +08:00
parent 03b3415e76
commit b052b12885
32 changed files with 76444 additions and 236658 deletions
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66
fpga/vivado_reports_nodsp/design_analysis_timing.rpt
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@@ -1,13 +1,13 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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-------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 03:34:29 2026
| Date : Fri Jul 10 04:15:09 2026
| Host : fedora running 64-bit unknown
| Command : report_design_analysis -timing -file /home/fallensigh/vivado_reports_nodsp/design_analysis_timing.rpt
| Command : report_design_analysis -timing -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_timing.rpt
| Design : soc_top
| Device : xc7a200t
| Design State : Routed
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Report Design Analysis
@@ -18,35 +18,35 @@ Table of Contents
1. Setup Path Characteristics 1-1
---------------------------------
+---------------------------+------------------------------------------------------+
| Characteristics | Path #1 |
+---------------------------+------------------------------------------------------+
| Requirement | 20.000 |
| Path Delay | 15.605 |
| Logic Delay | 5.343(35%) |
| Net Delay | 10.263(65%) |
| Clock Skew | -3.858 |
| Slack | 0.167 |
| Clock Relationship | Safely Timed |
| Logic Levels | 9 |
| Routes | 9 |
| Logical Path | FDRE LUT4 LUT6 LUT5 LUT6 RAMD32 LUT6 LUT5 LUT3 OBUFT |
| Start Point Clock | sys_clk |
| End Point Clock | sys_clk |
| DSP Block | None |
| BRAM | None |
| IO Crossings | 3 |
| Config Crossings | 0 |
| SLR Crossings | 0 |
| PBlocks | 0 |
| High Fanout | 130 |
| Dont Touch | 0 |
| Mark Debug | 0 |
| Start Point Pin Primitive | FDRE/C |
| End Point Pin Primitive | ext_ram_data[18] |
| Start Point Pin | FSM_sequential_ext_wr_state_reg[1]/C |
| End Point Pin | ext_ram_data[18] |
+---------------------------+------------------------------------------------------+
+---------------------------+----------------------------------------------------------------------------------------+
| Characteristics | Path #1 |
+---------------------------+----------------------------------------------------------------------------------------+
| Requirement | 20.000 |
| Path Delay | 15.529 |
| Logic Delay | 6.868(45%) |
| Net Delay | 8.661(55%) |
| Clock Skew | -3.955 |
| Slack | 0.146 |
| Clock Relationship | Safely Timed |
| Logic Levels | 14 |
| Routes | 12 |
| Logical Path | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 LUT4 CARRY4 CARRY4 LUT6 LUT6 LUT6 OBUF |
| Start Point Clock | sys_clk |
| End Point Clock | sys_clk |
| DSP Block | None |
| BRAM | None |
| IO Crossings | 3 |
| Config Crossings | 0 |
| SLR Crossings | 0 |
| PBlocks | 0 |
| High Fanout | 80 |
| Dont Touch | 0 |
| Mark Debug | 0 |
| Start Point Pin Primitive | FDCE/C |
| End Point Pin Primitive | base_ram_be_n[3] |
| Start Point Pin | ax_req_q_len_reg[3]/C |
| End Point Pin | base_ram_be_n[3] |
+---------------------------+----------------------------------------------------------------------------------------+
* Bounding box calculated as % of dimensions for the target device (436, 500)