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update vivado reports

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FallenSigh
2026-07-10 04:47:36 +08:00
parent 03b3415e76
commit b052b12885
32 changed files with 76444 additions and 236658 deletions
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26
fpga/vivado_reports_nodsp/clocks.rpt
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@@ -1,13 +1,13 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 03:34:13 2026
| Date : Fri Jul 10 04:14:54 2026
| Host : fedora running 64-bit unknown
| Command : report_clocks -file /home/fallensigh/vivado_reports_nodsp/clocks.rpt
| Command : report_clocks -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clocks.rpt
| Design : soc_top
| Device : 7a200t-fbg676
| Speed File : -1 PRODUCTION 1.23 2018-06-13
--------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------
Clock Report
@@ -21,12 +21,11 @@ Attributes
I: Inverted
S: Pin phase-shifted with Latency mode
Clock Period(ns) Waveform(ns) Attributes Sources
clk 20.000 {0.000 10.000} P {clk}
clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
mlkem_clk_clk_pll 40.000 {0.000 20.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
Clock Period(ns) Waveform(ns) Attributes Sources
clk 20.000 {0.000 10.000} P {clk}
clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
====================================================
@@ -46,13 +45,6 @@ Edges : {1 2 3}
Edge Shifts(ns) : {0.000 5.161 10.323}
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
Generated Clock : mlkem_clk_clk_pll
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk
Edges : {1 2 3}
Edge Shifts(ns) : {0.000 10.000 20.000}
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
Generated Clock : sys_clk
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
Master Clock : clk