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chore: untrack auto-generated PLL files, add .gitignore

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FallenSigh
2026-06-30 02:10:29 +08:00
parent 542495cb52
commit 99e6c884d7
5 changed files with 1 additions and 449 deletions
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32
rtl/ip/PLL_2019_2/clk_pll_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-- Date : Tue Jun 30 01:14:25 2026
-- Host : fedora running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl
-- Design : clk_pll
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a200tfbg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_pll is
Port (
cpu_clk : out STD_LOGIC;
sys_clk : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end clk_pll;
architecture stub of clk_pll is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "cpu_clk,sys_clk,resetn,locked,clk_in1";
begin
end;