From 99e6c884d7f645047688783c35b20202c1a31ea7 Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Tue, 30 Jun 2026 02:10:29 +0800 Subject: [PATCH] chore: untrack auto-generated PLL files, add .gitignore --- rtl/ip/PLL_2019_2/.gitignore | 1 + rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v | 224 --------------------- rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl | 170 ---------------- rtl/ip/PLL_2019_2/clk_pll_stub.v | 23 --- rtl/ip/PLL_2019_2/clk_pll_stub.vhdl | 32 --- 5 files changed, 1 insertion(+), 449 deletions(-) create mode 100644 rtl/ip/PLL_2019_2/.gitignore delete mode 100644 rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v delete mode 100644 rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl delete mode 100644 rtl/ip/PLL_2019_2/clk_pll_stub.v delete mode 100644 rtl/ip/PLL_2019_2/clk_pll_stub.vhdl diff --git a/rtl/ip/PLL_2019_2/.gitignore b/rtl/ip/PLL_2019_2/.gitignore new file mode 100644 index 0000000..3fbcd97 --- /dev/null +++ b/rtl/ip/PLL_2019_2/.gitignore @@ -0,0 +1 @@ +PLL_* diff --git a/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v b/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v deleted file mode 100644 index c2599a1..0000000 --- a/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v +++ /dev/null @@ -1,224 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -// Date : Tue Jun 30 01:14:25 2026 -// Host : fedora running 64-bit unknown -// Command : write_verilog -force -mode funcsim -// /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.v -// Design : clk_pll -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xc7a200tfbg676-1 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* NotValidForBitStream *) -module clk_pll - (cpu_clk, - sys_clk, - resetn, - locked, - clk_in1); - output cpu_clk; - output sys_clk; - input resetn; - output locked; - input clk_in1; - - (* IBUF_LOW_PWR *) wire clk_in1; - wire cpu_clk; - wire locked; - wire resetn; - wire sys_clk; - - clk_pll_clk_pll_clk_wiz inst - (.clk_in1(clk_in1), - .cpu_clk(cpu_clk), - .locked(locked), - .resetn(resetn), - .sys_clk(sys_clk)); -endmodule - -(* ORIG_REF_NAME = "clk_pll_clk_wiz" *) -module clk_pll_clk_pll_clk_wiz - (cpu_clk, - sys_clk, - resetn, - locked, - clk_in1); - output cpu_clk; - output sys_clk; - input resetn; - output locked; - input clk_in1; - - wire clk_in1; - wire clk_in1_clk_pll; - wire clkfbout_buf_clk_pll; - wire clkfbout_clk_pll; - wire cpu_clk; - wire cpu_clk_clk_pll; - wire locked; - wire reset_high; - wire resetn; - wire sys_clk; - wire sys_clk_clk_pll; - wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED; - wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED; - wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED; - wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED; - wire NLW_plle2_adv_inst_DRDY_UNCONNECTED; - wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED; - - (* BOX_TYPE = "PRIMITIVE" *) - BUFG clkf_buf - (.I(clkfbout_clk_pll), - .O(clkfbout_buf_clk_pll)); - (* BOX_TYPE = "PRIMITIVE" *) - (* CAPACITANCE = "DONT_CARE" *) - (* IBUF_DELAY_VALUE = "0" *) - (* IFD_DELAY_VALUE = "AUTO" *) - IBUF #( - .IOSTANDARD("DEFAULT")) - clkin1_ibufg - (.I(clk_in1), - .O(clk_in1_clk_pll)); - (* BOX_TYPE = "PRIMITIVE" *) - BUFG clkout1_buf - (.I(cpu_clk_clk_pll), - .O(cpu_clk)); - (* BOX_TYPE = "PRIMITIVE" *) - BUFG clkout2_buf - (.I(sys_clk_clk_pll), - .O(sys_clk)); - (* BOX_TYPE = "PRIMITIVE" *) - PLLE2_ADV #( - .BANDWIDTH("OPTIMIZED"), - .CLKFBOUT_MULT(31), - .CLKFBOUT_PHASE(0.000000), - .CLKIN1_PERIOD(20.000000), - .CLKIN2_PERIOD(0.000000), - .CLKOUT0_DIVIDE(47), - .CLKOUT0_DUTY_CYCLE(0.500000), - .CLKOUT0_PHASE(0.000000), - .CLKOUT1_DIVIDE(31), - .CLKOUT1_DUTY_CYCLE(0.500000), - .CLKOUT1_PHASE(0.000000), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.500000), - .CLKOUT2_PHASE(0.000000), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.500000), - .CLKOUT3_PHASE(0.000000), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.500000), - .CLKOUT4_PHASE(0.000000), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.500000), - .CLKOUT5_PHASE(0.000000), - .COMPENSATION("ZHOLD"), - .DIVCLK_DIVIDE(1), - .IS_CLKINSEL_INVERTED(1'b0), - .IS_PWRDWN_INVERTED(1'b0), - .IS_RST_INVERTED(1'b0), - .REF_JITTER1(0.010000), - .REF_JITTER2(0.010000), - .STARTUP_WAIT("FALSE")) - plle2_adv_inst - (.CLKFBIN(clkfbout_buf_clk_pll), - .CLKFBOUT(clkfbout_clk_pll), - .CLKIN1(clk_in1_clk_pll), - .CLKIN2(1'b0), - .CLKINSEL(1'b1), - .CLKOUT0(cpu_clk_clk_pll), - .CLKOUT1(sys_clk_clk_pll), - .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED), - .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED), - .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED), - .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED), - .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DCLK(1'b0), - .DEN(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]), - .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED), - .DWE(1'b0), - .LOCKED(locked), - .PWRDWN(1'b0), - .RST(reset_high)); - LUT1 #( - .INIT(2'h1)) - plle2_adv_inst_i_1 - (.I0(resetn), - .O(reset_high)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl b/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl deleted file mode 100644 index 4a1367f..0000000 --- a/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl +++ /dev/null @@ -1,170 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 --- Date : Tue Jun 30 01:14:25 2026 --- Host : fedora running 64-bit unknown --- Command : write_vhdl -force -mode funcsim --- /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_sim_netlist.vhdl --- Design : clk_pll --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xc7a200tfbg676-1 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity clk_pll_clk_pll_clk_wiz is - port ( - cpu_clk : out STD_LOGIC; - sys_clk : out STD_LOGIC; - resetn : in STD_LOGIC; - locked : out STD_LOGIC; - clk_in1 : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of clk_pll_clk_pll_clk_wiz : entity is "clk_pll_clk_wiz"; -end clk_pll_clk_pll_clk_wiz; - -architecture STRUCTURE of clk_pll_clk_pll_clk_wiz is - signal clk_in1_clk_pll : STD_LOGIC; - signal clkfbout_buf_clk_pll : STD_LOGIC; - signal clkfbout_clk_pll : STD_LOGIC; - signal cpu_clk_clk_pll : STD_LOGIC; - signal reset_high : STD_LOGIC; - signal sys_clk_clk_pll : STD_LOGIC; - signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; - signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; - signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; - signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; - signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; - signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); - attribute BOX_TYPE : string; - attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; - attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; - attribute CAPACITANCE : string; - attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; - attribute IBUF_DELAY_VALUE : string; - attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; - attribute IFD_DELAY_VALUE : string; - attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; - attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; - attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE"; - attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE"; -begin -clkf_buf: unisim.vcomponents.BUFG - port map ( - I => clkfbout_clk_pll, - O => clkfbout_buf_clk_pll - ); -clkin1_ibufg: unisim.vcomponents.IBUF - generic map( - IOSTANDARD => "DEFAULT" - ) - port map ( - I => clk_in1, - O => clk_in1_clk_pll - ); -clkout1_buf: unisim.vcomponents.BUFG - port map ( - I => cpu_clk_clk_pll, - O => cpu_clk - ); -clkout2_buf: unisim.vcomponents.BUFG - port map ( - I => sys_clk_clk_pll, - O => sys_clk - ); -plle2_adv_inst: unisim.vcomponents.PLLE2_ADV - generic map( - BANDWIDTH => "OPTIMIZED", - CLKFBOUT_MULT => 31, - CLKFBOUT_PHASE => 0.000000, - CLKIN1_PERIOD => 20.000000, - CLKIN2_PERIOD => 0.000000, - CLKOUT0_DIVIDE => 47, - CLKOUT0_DUTY_CYCLE => 0.500000, - CLKOUT0_PHASE => 0.000000, - CLKOUT1_DIVIDE => 31, - CLKOUT1_DUTY_CYCLE => 0.500000, - CLKOUT1_PHASE => 0.000000, - CLKOUT2_DIVIDE => 1, - CLKOUT2_DUTY_CYCLE => 0.500000, - CLKOUT2_PHASE => 0.000000, - CLKOUT3_DIVIDE => 1, - CLKOUT3_DUTY_CYCLE => 0.500000, - CLKOUT3_PHASE => 0.000000, - CLKOUT4_DIVIDE => 1, - CLKOUT4_DUTY_CYCLE => 0.500000, - CLKOUT4_PHASE => 0.000000, - CLKOUT5_DIVIDE => 1, - CLKOUT5_DUTY_CYCLE => 0.500000, - CLKOUT5_PHASE => 0.000000, - COMPENSATION => "ZHOLD", - DIVCLK_DIVIDE => 1, - IS_CLKINSEL_INVERTED => '0', - IS_PWRDWN_INVERTED => '0', - IS_RST_INVERTED => '0', - REF_JITTER1 => 0.010000, - REF_JITTER2 => 0.010000, - STARTUP_WAIT => "FALSE" - ) - port map ( - CLKFBIN => clkfbout_buf_clk_pll, - CLKFBOUT => clkfbout_clk_pll, - CLKIN1 => clk_in1_clk_pll, - CLKIN2 => '0', - CLKINSEL => '1', - CLKOUT0 => cpu_clk_clk_pll, - CLKOUT1 => sys_clk_clk_pll, - CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED, - CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED, - CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED, - CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED, - DADDR(6 downto 0) => B"0000000", - DCLK => '0', - DEN => '0', - DI(15 downto 0) => B"0000000000000000", - DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0), - DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED, - DWE => '0', - LOCKED => locked, - PWRDWN => '0', - RST => reset_high - ); -plle2_adv_inst_i_1: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => resetn, - O => reset_high - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity clk_pll is - port ( - cpu_clk : out STD_LOGIC; - sys_clk : out STD_LOGIC; - resetn : in STD_LOGIC; - locked : out STD_LOGIC; - clk_in1 : in STD_LOGIC - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of clk_pll : entity is true; -end clk_pll; - -architecture STRUCTURE of clk_pll is -begin -inst: entity work.clk_pll_clk_pll_clk_wiz - port map ( - clk_in1 => clk_in1, - cpu_clk => cpu_clk, - locked => locked, - resetn => resetn, - sys_clk => sys_clk - ); -end STRUCTURE; diff --git a/rtl/ip/PLL_2019_2/clk_pll_stub.v b/rtl/ip/PLL_2019_2/clk_pll_stub.v deleted file mode 100644 index 60b6bce..0000000 --- a/rtl/ip/PLL_2019_2/clk_pll_stub.v +++ /dev/null @@ -1,23 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -// Date : Tue Jun 30 01:14:25 2026 -// Host : fedora running 64-bit unknown -// Command : write_verilog -force -mode synth_stub -// /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.v -// Design : clk_pll -// Purpose : Stub declaration of top-level module interface -// Device : xc7a200tfbg676-1 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -module clk_pll(cpu_clk, sys_clk, resetn, locked, clk_in1) -/* synthesis syn_black_box black_box_pad_pin="cpu_clk,sys_clk,resetn,locked,clk_in1" */; - output cpu_clk; - output sys_clk; - input resetn; - output locked; - input clk_in1; -endmodule diff --git a/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl b/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl deleted file mode 100644 index b645f97..0000000 --- a/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl +++ /dev/null @@ -1,32 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 --- Date : Tue Jun 30 01:14:25 2026 --- Host : fedora running 64-bit unknown --- Command : write_vhdl -force -mode synth_stub --- /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.vhdl --- Design : clk_pll --- Purpose : Stub declaration of top-level module interface --- Device : xc7a200tfbg676-1 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity clk_pll is - Port ( - cpu_clk : out STD_LOGIC; - sys_clk : out STD_LOGIC; - resetn : in STD_LOGIC; - locked : out STD_LOGIC; - clk_in1 : in STD_LOGIC - ); - -end clk_pll; - -architecture stub of clk_pll is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "cpu_clk,sys_clk,resetn,locked,clk_in1"; -begin -end;