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Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

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FallenSigh
2026-06-25 20:03:53 +08:00
parent 57ba5d271d
commit 956cd67773
9 changed files with 476 additions and 382 deletions
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59
sdk/software/examples/asm/user-sample.c
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@@ -99,16 +99,43 @@ static const uint32_t crc32_table[256] = {
0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
};
/* ─── Poll IP STATUS until done and clear it (W1C) ────────────────── */
static void wait_matmul_done(void)
static volatile int matmul_done_flag = 0;
static volatile int dma0_done_flag = 0;
static volatile int dma1_done_flag = 0;
void MATMUL_IntrHandler(void)
{
uint32_t status;
do {
status = REG_RD(MATMUL_STATUS);
} while (!(status & (STATUS_DONE | STATUS_ERROR)));
// Write 1 to Clear the DONE bit
REG_WR(MATMUL_STATUS, STATUS_DONE);
matmul_done_flag = 1;
REG_WR(MATMUL_STATUS, STATUS_DONE); // W1C: deassert intr
}
void DMA_IntrHandler(void)
{
if (DMA_CH(0)->STATUS & STATUS_DONE_BIT) {
dma0_done_flag = 1;
DMA_CH(0)->STATUS = STATUS_DONE_BIT;
}
if (DMA_CH(1)->STATUS & STATUS_DONE_BIT) {
dma1_done_flag = 1;
DMA_CH(1)->STATUS = STATUS_DONE_BIT;
}
}
static void wait_matmul_done_intr(void)
{
while (!matmul_done_flag) { }
matmul_done_flag = 0;
}
static void wait_dma_done_intr(int ch)
{
if (ch == 0) {
while (!dma0_done_flag) { }
dma0_done_flag = 0;
} else {
while (!dma1_done_flag) { }
dma1_done_flag = 0;
}
}
/* ─── CRC32 over ExtRAM result region ─────────────────────────────── */
@@ -152,7 +179,7 @@ int main(void)
/* ── Prologue: 第0组数据初始化 ────────────────────────── */
// DMA Ch0: 从 ExtRAM 将 Group 0 的 A、B (128 bytes) 搬入 IP 的 Bank 0
dma_start_transfer(0, EXTRAM_PHYS_AB(0), phys_bank_AB[0], 128, 10);
dma_wait_polling(0); // 必须等待首个数据加载完成
wait_dma_done_intr(0);
// 启动 IP Bank 0 计算
REG_WR(MATMUL_CTRL, ctrl_start[0]);
@@ -170,30 +197,30 @@ int main(void)
dma_start_transfer(0, EXTRAM_PHYS_AB(g), phys_bank_AB[cur_bank], 128, 10);
// 2. 等待上一组在 IP 中的计算完成
wait_matmul_done();
wait_matmul_done_intr();
// 3. 确保上一次的结果写回 (Channel 1) 已经空闲
if (g > 1) {
dma_wait_polling(1);
wait_dma_done_intr(1);
}
// 4. 发起写回刚才计算完成的结果 (Channel 1: IP -> Memory)
dma_start_transfer(1, phys_bank_C[prev_bank], EXTRAM_PHYS_C(g - 1), 192, 20);
// 5. 确保当前要计算的输入数据 (Channel 0) 已经加载完毕
dma_wait_polling(0);
wait_dma_done_intr(0);
// 6. 立即启动当前组在 IP 中的计算
REG_WR(MATMUL_CTRL, ctrl_start[cur_bank]);
}
/* ── Epilogue: 收尾最后一组 ───────────────────────────── */
wait_matmul_done(); // 等待最后一次计算完成
dma_wait_polling(1); // 确保之前的 DMA CH1 空闲
wait_matmul_done_intr(); // 等待最后一次计算完成
wait_dma_done_intr(1); // 确保之前的 DMA CH1 空闲
// DMA CH1 将最后一组结果写回
dma_start_transfer(1, phys_bank_C[(MATMUL_GROUP_NUM - 1) % 2], EXTRAM_PHYS_C(MATMUL_GROUP_NUM - 1), 192, 20);
dma_wait_polling(1); // 必须等待最后一组写回完成
wait_dma_done_intr(1);
/* ── CRC32 over result region ─────────────────────────────── */
crc = compute_crc32(extram);