Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

2026-06-25 20:03:53 +08:00
parent 57ba5d271d
commit 956cd67773
9 changed files with 476 additions and 382 deletions
--- a/rtl/ip/matmul/matmul_axi_slave.v
+++ b/rtl/ip/matmul/matmul_axi_slave.v
@@ -103,7 +103,10 @@ module matmul_axi_slave (
    output     [1:0]  s_axi_rresp,
    output reg        s_axi_rlast,
    output reg        s_axi_rvalid,
-    input             s_axi_rready
+    input             s_axi_rready,
+
+    // Interrupt output (active high level, pulsed by calc_done)
+    output            intr
 );

    // ==========================================
@@ -459,4 +462,7 @@ module matmul_axi_slave (
        end
    end

+    // Interrupt: driven by done, cleared when software writes STATUS[1]
+    assign intr = done;
+
 endmodule