Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

2026-06-25 20:03:53 +08:00
parent 57ba5d271d
commit 956cd67773
9 changed files with 476 additions and 382 deletions
--- a/rtl/ip/confreg/confreg.v
+++ b/rtl/ip/confreg/confreg.v
@@ -91,7 +91,6 @@ module confreg #(
    input      [3 :0] touch_btn,

    input             uart0_int,
-    input             dma_finish,
    input             fft_finish,
    output            confreg_int
 );
@@ -384,7 +383,7 @@ always @(posedge aclk) begin
    end
 end

-assign int_in = {24'b0, dma_finish, fft_finish, uart0_int, timer_int, touch_btn_data};
+assign int_in = {24'b0, 1'b0, fft_finish, uart0_int, timer_int, touch_btn_data};

 int_ctrl u_int_ctrl (
    .clk       (aclk),