fallensigh/ciciec2026
Archived
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

Browse Source
This commit is contained in:
FallenSigh
2026-06-25 20:03:53 +08:00
parent 57ba5d271d
commit 956cd67773
9 changed files with 476 additions and 382 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
rtl/ip/confreg/confreg.v
View File

@@ -91,7 +91,6 @@ module confreg #(
input [3 :0] touch_btn,
input uart0_int,
input dma_finish,
input fft_finish,
output confreg_int
);
@@ -384,7 +383,7 @@ always @(posedge aclk) begin
end
end
assign int_in = {24'b0, dma_finish, fft_finish, uart0_int, timer_int, touch_btn_data};
assign int_in = {24'b0, 1'b0, fft_finish, uart0_int, timer_int, touch_btn_data};
int_ctrl u_int_ctrl (
.clk (aclk),

8
rtl/ip/matmul/matmul_axi_slave.v
View File

@@ -103,7 +103,10 @@ module matmul_axi_slave (
output [1:0] s_axi_rresp,
output reg s_axi_rlast,
output reg s_axi_rvalid,
input s_axi_rready
input s_axi_rready,
// Interrupt output (active high level, pulsed by calc_done)
output intr
);
// ==========================================
@@ -459,4 +462,7 @@ module matmul_axi_slave (
end
end
// Interrupt: driven by done, cleared when software writes STATUS[1]
assign intr = done;
endmodule

12
rtl/soc_top.v
View File

@@ -603,6 +603,7 @@ wire axiOut_7_bvalid ;
wire axiOut_7_bready ;
wire confreg_int;
wire matmul_intr;
AxiCrossbar_2x8 u_AxiCrossbar_2x8 (
.clk ( sys_clk ),
@@ -1031,10 +1032,11 @@ AxiCrossbar_2x8 u_AxiCrossbar_2x8 (
);
core_top u_cpu(
.intrpt ({7'b0, confreg_int}), //high active
.intrpt ({5'd0, matmul_intr, dma_finish, confreg_int}), //high active
// intrpt[2]=matmul, intrpt[1]=dma, intrpt[0]=confreg
.aclk (cpu_clk ),
.aresetn (cpu_resetn ), //low active
@@ -1370,7 +1372,6 @@ confreg #(
// 中断与状态信号
.uart0_int (uart0_int), // UART0中断
.dma_finish (dma_finish), // DMA完成信号
.fft_finish (fft_finish), // FFT完成信号
.confreg_int(confreg_int) // 输出中断给CPU
);
@@ -1436,7 +1437,7 @@ assign fft_arready = 1'b1;
assign fft_awready = 1'b1;
assign fft_wready = 1'b1;
//slave 7 - matmul accelerator
//slave 7 - matmul accelerator
matmul_axi_slave u_matmul_axi_slave (
.clk (sys_clk),
.resetn (sys_resetn),
@@ -1480,7 +1481,8 @@ matmul_axi_slave u_matmul_axi_slave (
.s_axi_rresp (axiOut_7_rresp ),
.s_axi_rlast (axiOut_7_rlast ),
.s_axi_rvalid (axiOut_7_rvalid),
.s_axi_rready (axiOut_7_rready)
.s_axi_rready (axiOut_7_rready),
.intr (matmul_intr)
);
wire [31:0] cdma_s_awaddr;