add vivado reports
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fpga/vivado_reports/impl_drc.rpt
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248
fpga/vivado_reports/impl_drc.rpt
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Sun Jul 5 23:35:54 2026
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| Host : fedora running 64-bit unknown
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| Command : report_drc -file ./vivado_reports/impl_drc.rpt
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| Design : soc_top
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| Device : xc7a200tfbg676-1
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| Speed File : -1
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| Design State : Synthesized
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------------------------------------------------------------------------------------
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Report DRC
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: design_1
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Design limits: <entire design considered>
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Ruledeck: default
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Max violations: <unlimited>
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Violations found: 42
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+-----------+----------+----------------------------+------------+
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| Rule | Severity | Description | Violations |
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+-----------+----------+----------------------------+------------+
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| CHECK-3 | Warning | Report rule limit reached | 2 |
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| REQP-1839 | Warning | RAMB36 async control check | 20 |
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| REQP-1840 | Warning | RAMB18 async control check | 20 |
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+-----------+----------+----------------------------+------------+
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2. REPORT DETAILS
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-----------------
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CHECK-3#1 Warning
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Report rule limit reached
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REQP-1839 rule limit reached: 20 violations have been found.
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Related violations: <none>
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CHECK-3#2 Warning
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Report rule limit reached
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REQP-1840 rule limit reached: 20 violations have been found.
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Related violations: <none>
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REQP-1839#1 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#2 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#3 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#4 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#5 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#6 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#7 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#8 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#9 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#10 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#11 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#12 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#13 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#14 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#15 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#16 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1839#17 Warning
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RAMB36 async control check
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
|
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REQP-1839#18 Warning
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RAMB36 async control check
|
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The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#19 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#20 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#1 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
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||||
REQP-1840#2 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#3 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#4 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#5 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#6 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#7 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#8 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#9 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#10 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#11 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#12 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#13 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#14 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#15 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#16 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#17 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#18 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#19 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#20 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
Reference in New Issue
Block a user