add vivado reports

2026-07-06 00:03:57 +08:00
parent 34ce639f69
commit 65607badd2
32 changed files with 427000 additions and 0 deletions
--- a/fpga/vivado_reports/impl_clock_networks.rpt
+++ b/fpga/vivado_reports/impl_clock_networks.rpt
@@ -0,0 +1,27 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
+| Date         : Sun Jul  5 23:35:51 2026
+| Host         : fedora running 64-bit unknown
+| Command      : report_clock_networks -file ./vivado_reports/impl_clock_networks.rpt
+| Design       : soc_top
+| Device       : 7a200t-fbg676
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+--------------------------------------------------------------------------------------
+
+Clock Networks Report
+
+
+Constrained Clocks
+-------------------
+
+Clock clk (50MHz)(endpoints: 17477 clock, 2 nonclock)
+Port clk
+
+
+Unconstrained Clocks
+-------------------
+
+Clock Q (endpoints: 23490 clock, 1 nonclock)
+FDCE/Q (u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg)
+