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remove mlkem CDC; mlkem can now run at 50MHz

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FallenSigh
2026-07-08 17:52:16 +08:00
parent 6a1b374bc1
commit 5f9cb1c883
4 changed files with 68 additions and 145 deletions
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53
rtl/soc_top.v
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@@ -83,8 +83,6 @@ wire cpu_clk;
wire cpu_resetn;
wire sys_clk;
wire sys_resetn;
wire mlkem_clk;
wire mlkem_resetn;
wire pll_locked;
generate if(SIMULATION) begin: sim_clk
@@ -93,32 +91,25 @@ generate if(SIMULATION) begin: sim_clk
initial begin
clk_sim = 1'b0;
end
always #15 clk_sim = ~clk_sim;
assign cpu_clk = clk_sim;
assign sys_clk = clk;
assign mlkem_clk = sys_clk;
rst_sync u_rst_sys(
.clk(sys_clk),
.rst_n_in(~reset),
.rst_n_out(sys_resetn)
);
always #15 clk_sim = ~clk_sim;
assign cpu_clk = clk_sim;
assign sys_clk = clk;
rst_sync u_rst_sys(
.clk(sys_clk),
.rst_n_in(~reset),
.rst_n_out(sys_resetn)
);
rst_sync u_rst_cpu(
.clk(cpu_clk),
.rst_n_in(sys_resetn),
.rst_n_out(cpu_resetn)
);
rst_sync u_rst_mlkem(
.clk(mlkem_clk),
.rst_n_in(sys_resetn),
.rst_n_out(mlkem_resetn)
);
end
else begin: pll_clk
.rst_n_in(sys_resetn),
.rst_n_out(cpu_resetn)
);
end
else begin: pll_clk
clk_pll u_clk_pll(
.cpu_clk (cpu_clk),
.sys_clk (sys_clk),
.mlkem_clk (mlkem_clk),
.resetn (~reset),
.locked (pll_locked),
.clk_in1 (clk)
@@ -133,11 +124,6 @@ else begin: pll_clk
.rst_n_in(sys_resetn),
.rst_n_out(cpu_resetn)
);
rst_sync u_rst_mlkem(
.clk(mlkem_clk),
.rst_n_in(sys_resetn),
.rst_n_out(mlkem_resetn)
);
end
endgenerate
@@ -1459,16 +1445,13 @@ axi_dvi u_axi_dvi (
.video_blue ( video_blue )
);
// slave 6 - shared FFT / ML-KEM accelerator window (0x1f400000, virtual 0xbf400000)
// ML-KEM: 0x0000..0x3fff
// FFT: 0x8000..0xcfff
fft_mlkem_axi_slave u_fft_mlkem_axi_slave (
// slave 6 - shared FFT / ML-KEM accelerator window (0x1f400000, virtual 0xbf400000)
// ML-KEM: 0x0000..0x3fff
// FFT: 0x8000..0xcfff
fft_mlkem_axi_slave u_fft_mlkem_axi_slave (
.clk (sys_clk),
.resetn (sys_resetn),
.mlkem_clk (mlkem_clk),
.mlkem_resetn (mlkem_resetn),
.s_axi_awid (fft_awid ),
.s_axi_awaddr (fft_awaddr ),
.s_axi_awlen (fft_awlen ),