diff --git a/rtl/ip/PLL_2019_2/clk_pll.xci b/rtl/ip/PLL_2019_2/clk_pll.xci
index 113f373..cb0a48d 100644
--- a/rtl/ip/PLL_2019_2/clk_pll.xci
+++ b/rtl/ip/PLL_2019_2/clk_pll.xci
@@ -35,12 +35,6 @@
100000000
0
0.000
-
-
-
- 100000000
- 0
- 0.000
1
LEVEL_HIGH
@@ -142,7 +136,7 @@
50
0.000
1
- 1
+ 0
0000
0000
100.000
@@ -265,7 +259,7 @@
0.500
0.000
FALSE
- 31
+ 1
0.500
0.000
FALSE
@@ -295,12 +289,12 @@
FALSE
64.000
2.000
- 3
+ 2
Output Output Phase Duty Cycle Pk-to-Pk Phase
Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
_cpu_clk__32.97872______0.000______50.0______130.093____123.600
_sys_clk__50.00000______0.000______50.0______122.035____123.600
- mlkem_clk__50.00000______0.000______50.0______122.035____123.600
+ no_CLK_OUT3_output
no_CLK_OUT4_output
no_CLK_OUT5_output
no_CLK_OUT6_output
@@ -445,7 +439,7 @@
50
0.000
1
- true
+ false
BUFG
0.0
false
@@ -544,7 +538,7 @@
0.500
0.000
false
- 31
+ 1
0.500
0.000
false
@@ -572,7 +566,7 @@
0.010
0.010
false
- 3
+ 2
false
false
WAVEFORM
diff --git a/rtl/ip/mlkem/top/fft_mlkem_axi_slave.v b/rtl/ip/mlkem/top/fft_mlkem_axi_slave.v
index bc21602..fd42132 100644
--- a/rtl/ip/mlkem/top/fft_mlkem_axi_slave.v
+++ b/rtl/ip/mlkem/top/fft_mlkem_axi_slave.v
@@ -5,14 +5,11 @@
// ML-KEM: 0x0000..0x3fff
// FFT: 0x8000..0xcfff
// Route the low ML-KEM block to ML-KEM and the remaining accelerator window to
-// FFT.
+// FFT. ML-KEM runs in the same clock domain as this AXI slave.
(* use_dsp = "no" *) module fft_mlkem_axi_slave (
input clk,
input resetn,
- input mlkem_clk,
- input mlkem_resetn,
-
input [4:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
@@ -116,7 +113,6 @@
wire [1:0] mlkem_m_rresp;
wire mlkem_m_rlast;
wire mlkem_intr_m;
- (* async_reg = "true" *) reg [1:0] mlkem_intr_sync;
wire fft_awready, fft_wready, fft_bvalid;
wire [4:0] fft_bid;
@@ -178,97 +174,48 @@
end
end
- always @(posedge clk or negedge resetn) begin
- if (!resetn)
- mlkem_intr_sync <= 2'b00;
- else
- mlkem_intr_sync <= {mlkem_intr_sync[0], mlkem_intr_m};
- end
+ assign mlkem_intr = mlkem_intr_m;
- assign mlkem_intr = mlkem_intr_sync[1];
+ assign mlkem_awready = mlkem_m_awready;
+ assign mlkem_wready = mlkem_m_wready;
+ assign mlkem_bvalid = mlkem_m_bvalid;
+ assign mlkem_bid = mlkem_m_bid;
+ assign mlkem_bresp = mlkem_m_bresp;
+ assign mlkem_arready = mlkem_m_arready;
+ assign mlkem_rvalid = mlkem_m_rvalid;
+ assign mlkem_rlast = mlkem_m_rlast;
+ assign mlkem_rid = mlkem_m_rid;
+ assign mlkem_rdata = mlkem_m_rdata;
+ assign mlkem_rresp = mlkem_m_rresp;
- Axi_CDC u_mlkem_axi_cdc (
- .axiInClk (clk),
- .axiInRstn (resetn),
- .axiOutClk (mlkem_clk),
- .axiOutRstn (mlkem_resetn),
-
- .axiIn_awvalid (s_axi_awvalid && !write_active && (aw_sel == SEL_MLKEM)),
- .axiIn_awready (mlkem_awready),
- .axiIn_awaddr (s_axi_awaddr),
- .axiIn_awid (s_axi_awid),
- .axiIn_awlen (s_axi_awlen),
- .axiIn_awsize (s_axi_awsize),
- .axiIn_awburst (s_axi_awburst),
- .axiIn_awlock (s_axi_awlock),
- .axiIn_awcache (s_axi_awcache),
- .axiIn_awprot (s_axi_awprot),
- .axiIn_wvalid (s_axi_wvalid && (sel_w == SEL_MLKEM)),
- .axiIn_wready (mlkem_wready),
- .axiIn_wdata (s_axi_wdata),
- .axiIn_wstrb (s_axi_wstrb),
- .axiIn_wlast (s_axi_wlast),
- .axiIn_bvalid (mlkem_bvalid),
- .axiIn_bready (s_axi_bready && (sel_w == SEL_MLKEM)),
- .axiIn_bid (mlkem_bid),
- .axiIn_bresp (mlkem_bresp),
- .axiIn_arvalid (s_axi_arvalid && !read_active && (ar_sel == SEL_MLKEM)),
- .axiIn_arready (mlkem_arready),
- .axiIn_araddr (s_axi_araddr),
- .axiIn_arid (s_axi_arid),
- .axiIn_arlen (s_axi_arlen),
- .axiIn_arsize (s_axi_arsize),
- .axiIn_arburst (s_axi_arburst),
- .axiIn_arlock (s_axi_arlock),
- .axiIn_arcache (s_axi_arcache),
- .axiIn_arprot (s_axi_arprot),
- .axiIn_rvalid (mlkem_rvalid),
- .axiIn_rready (s_axi_rready && (sel_r == SEL_MLKEM)),
- .axiIn_rdata (mlkem_rdata),
- .axiIn_rid (mlkem_rid),
- .axiIn_rresp (mlkem_rresp),
- .axiIn_rlast (mlkem_rlast),
-
- .axiOut_awvalid (mlkem_m_awvalid),
- .axiOut_awready (mlkem_m_awready),
- .axiOut_awaddr (mlkem_m_awaddr),
- .axiOut_awid (mlkem_m_awid),
- .axiOut_awlen (mlkem_m_awlen),
- .axiOut_awsize (mlkem_m_awsize),
- .axiOut_awburst (mlkem_m_awburst),
- .axiOut_awlock (mlkem_m_awlock),
- .axiOut_awcache (mlkem_m_awcache),
- .axiOut_awprot (mlkem_m_awprot),
- .axiOut_wvalid (mlkem_m_wvalid),
- .axiOut_wready (mlkem_m_wready),
- .axiOut_wdata (mlkem_m_wdata),
- .axiOut_wstrb (mlkem_m_wstrb),
- .axiOut_wlast (mlkem_m_wlast),
- .axiOut_bvalid (mlkem_m_bvalid),
- .axiOut_bready (mlkem_m_bready),
- .axiOut_bid (mlkem_m_bid),
- .axiOut_bresp (mlkem_m_bresp),
- .axiOut_arvalid (mlkem_m_arvalid),
- .axiOut_arready (mlkem_m_arready),
- .axiOut_araddr (mlkem_m_araddr),
- .axiOut_arid (mlkem_m_arid),
- .axiOut_arlen (mlkem_m_arlen),
- .axiOut_arsize (mlkem_m_arsize),
- .axiOut_arburst (mlkem_m_arburst),
- .axiOut_arlock (mlkem_m_arlock),
- .axiOut_arcache (mlkem_m_arcache),
- .axiOut_arprot (mlkem_m_arprot),
- .axiOut_rvalid (mlkem_m_rvalid),
- .axiOut_rready (mlkem_m_rready),
- .axiOut_rdata (mlkem_m_rdata),
- .axiOut_rid (mlkem_m_rid),
- .axiOut_rresp (mlkem_m_rresp),
- .axiOut_rlast (mlkem_m_rlast)
- );
+ assign mlkem_m_awvalid = s_axi_awvalid && !write_active && (aw_sel == SEL_MLKEM);
+ assign mlkem_m_awaddr = s_axi_awaddr;
+ assign mlkem_m_awid = s_axi_awid;
+ assign mlkem_m_awlen = s_axi_awlen;
+ assign mlkem_m_awsize = s_axi_awsize;
+ assign mlkem_m_awburst = s_axi_awburst;
+ assign mlkem_m_awlock = s_axi_awlock;
+ assign mlkem_m_awcache = s_axi_awcache;
+ assign mlkem_m_awprot = s_axi_awprot;
+ assign mlkem_m_wvalid = s_axi_wvalid && (sel_w == SEL_MLKEM);
+ assign mlkem_m_wdata = s_axi_wdata;
+ assign mlkem_m_wstrb = s_axi_wstrb;
+ assign mlkem_m_wlast = s_axi_wlast;
+ assign mlkem_m_bready = s_axi_bready && (sel_w == SEL_MLKEM);
+ assign mlkem_m_arvalid = s_axi_arvalid && !read_active && (ar_sel == SEL_MLKEM);
+ assign mlkem_m_araddr = s_axi_araddr;
+ assign mlkem_m_arid = s_axi_arid;
+ assign mlkem_m_arlen = s_axi_arlen;
+ assign mlkem_m_arsize = s_axi_arsize;
+ assign mlkem_m_arburst = s_axi_arburst;
+ assign mlkem_m_arlock = s_axi_arlock;
+ assign mlkem_m_arcache = s_axi_arcache;
+ assign mlkem_m_arprot = s_axi_arprot;
+ assign mlkem_m_rready = s_axi_rready && (sel_r == SEL_MLKEM);
mlkem_axi_slave u_mlkem_axi_slave (
- .clk (mlkem_clk),
- .resetn (mlkem_resetn),
+ .clk (clk),
+ .resetn (resetn),
.s_axi_awid (mlkem_m_awid),
.s_axi_awaddr (mlkem_m_awaddr),
diff --git a/rtl/ip/mlkem/top/mlkem_axi_slave.v b/rtl/ip/mlkem/top/mlkem_axi_slave.v
index 0b00e78..8bc3978 100644
--- a/rtl/ip/mlkem/top/mlkem_axi_slave.v
+++ b/rtl/ip/mlkem/top/mlkem_axi_slave.v
@@ -1,9 +1,8 @@
// mlkem_axi_slave.v — AXI4 (burst) slave wrapper for the ML-KEM core.
// Makes the ML-KEM accelerator (KeyGen / Encaps / Decaps) CPU-controllable.
//
-// This slave is placed behind an AXI clock-domain converter. Its AXI side and
-// mlkem_top both run in mlkem_clk; sys_clk masters reach it through Axi_CDC in
-// fft_mlkem_axi_slave.
+// This slave and mlkem_top run in the same clock domain as the shared
+// FFT/ML-KEM AXI window.
//
// Register map (byte offsets from base, e.g. virtual 0xbf400000):
// 0x000 CTRL W bit0 = start (launches op selected in CONFIG)
@@ -27,8 +26,8 @@
module mlkem_axi_slave (
- input clk, // mlkem_clk AXI-side clock after Axi_CDC
- input resetn, // mlkem_resetn, active low
+ input clk,
+ input resetn, // active low
// AXI Write Address Channel
input [4:0] s_axi_awid,
diff --git a/rtl/soc_top.v b/rtl/soc_top.v
index 1bb6d80..6ad6d84 100644
--- a/rtl/soc_top.v
+++ b/rtl/soc_top.v
@@ -83,8 +83,6 @@ wire cpu_clk;
wire cpu_resetn;
wire sys_clk;
wire sys_resetn;
-wire mlkem_clk;
-wire mlkem_resetn;
wire pll_locked;
generate if(SIMULATION) begin: sim_clk
@@ -93,32 +91,25 @@ generate if(SIMULATION) begin: sim_clk
initial begin
clk_sim = 1'b0;
end
- always #15 clk_sim = ~clk_sim;
-
- assign cpu_clk = clk_sim;
- assign sys_clk = clk;
- assign mlkem_clk = sys_clk;
- rst_sync u_rst_sys(
- .clk(sys_clk),
- .rst_n_in(~reset),
- .rst_n_out(sys_resetn)
- );
+ always #15 clk_sim = ~clk_sim;
+
+ assign cpu_clk = clk_sim;
+ assign sys_clk = clk;
+ rst_sync u_rst_sys(
+ .clk(sys_clk),
+ .rst_n_in(~reset),
+ .rst_n_out(sys_resetn)
+ );
rst_sync u_rst_cpu(
.clk(cpu_clk),
- .rst_n_in(sys_resetn),
- .rst_n_out(cpu_resetn)
- );
- rst_sync u_rst_mlkem(
- .clk(mlkem_clk),
- .rst_n_in(sys_resetn),
- .rst_n_out(mlkem_resetn)
- );
-end
-else begin: pll_clk
+ .rst_n_in(sys_resetn),
+ .rst_n_out(cpu_resetn)
+ );
+end
+else begin: pll_clk
clk_pll u_clk_pll(
.cpu_clk (cpu_clk),
.sys_clk (sys_clk),
- .mlkem_clk (mlkem_clk),
.resetn (~reset),
.locked (pll_locked),
.clk_in1 (clk)
@@ -133,11 +124,6 @@ else begin: pll_clk
.rst_n_in(sys_resetn),
.rst_n_out(cpu_resetn)
);
- rst_sync u_rst_mlkem(
- .clk(mlkem_clk),
- .rst_n_in(sys_resetn),
- .rst_n_out(mlkem_resetn)
- );
end
endgenerate
@@ -1459,16 +1445,13 @@ axi_dvi u_axi_dvi (
.video_blue ( video_blue )
);
-// slave 6 - shared FFT / ML-KEM accelerator window (0x1f400000, virtual 0xbf400000)
-// ML-KEM: 0x0000..0x3fff
-// FFT: 0x8000..0xcfff
-fft_mlkem_axi_slave u_fft_mlkem_axi_slave (
+// slave 6 - shared FFT / ML-KEM accelerator window (0x1f400000, virtual 0xbf400000)
+// ML-KEM: 0x0000..0x3fff
+// FFT: 0x8000..0xcfff
+fft_mlkem_axi_slave u_fft_mlkem_axi_slave (
.clk (sys_clk),
.resetn (sys_resetn),
- .mlkem_clk (mlkem_clk),
- .mlkem_resetn (mlkem_resetn),
-
.s_axi_awid (fft_awid ),
.s_axi_awaddr (fft_awaddr ),
.s_axi_awlen (fft_awlen ),