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Register mult_p before accumulation to prevent synthesis glitches

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FallenSigh
2026-06-25 03:27:51 +08:00
parent 6c77fa2e38
commit 4e409f870c
1 changed files with 9 additions and 4 deletions
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13
rtl/ip/matmul/matmul_axi_slave.v
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@@ -365,6 +365,7 @@ module matmul_axi_slave (
reg mult_start;
wire mult_done [0:3];
wire [63:0] mult_p [0:3];
reg [63:0] mult_p_r [0:3]; // registered for stable accumulation
reg [31:0] m_in_a [0:3];
reg [31:0] m_in_b [0:3];
@@ -429,17 +430,21 @@ module matmul_axi_slave (
C_WAIT_MULT: begin
mult_start <= 1'b0;
if (mult_done[0] && mult_done[1] && mult_done[2] && mult_done[3]) begin
mult_p_r[0] <= mult_p[0];
mult_p_r[1] <= mult_p[1];
mult_p_r[2] <= mult_p[2];
mult_p_r[3] <= mult_p[3];
state <= C_ACCUM;
end
end
C_ACCUM: begin
if (cur_bank == 1'b0) begin
b0_c[calc_idx] <= {2'b0, mult_p[0]} + {2'b0, mult_p[1]} +
{2'b0, mult_p[2]} + {2'b0, mult_p[3]};
b0_c[calc_idx] <= {2'b0, mult_p_r[0]} + {2'b0, mult_p_r[1]} +
{2'b0, mult_p_r[2]} + {2'b0, mult_p_r[3]};
end else begin
b1_c[calc_idx] <= {2'b0, mult_p[0]} + {2'b0, mult_p[1]} +
{2'b0, mult_p[2]} + {2'b0, mult_p[3]};
b1_c[calc_idx] <= {2'b0, mult_p_r[0]} + {2'b0, mult_p_r[1]} +
{2'b0, mult_p_r[2]} + {2'b0, mult_p_r[3]};
end
if (calc_idx == 4'd15) begin