From 4e409f870ca86d9d5bb4d4c1c75a8416f1a88667 Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Thu, 25 Jun 2026 03:27:51 +0800 Subject: [PATCH] Register mult_p before accumulation to prevent synthesis glitches --- rtl/ip/matmul/matmul_axi_slave.v | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/rtl/ip/matmul/matmul_axi_slave.v b/rtl/ip/matmul/matmul_axi_slave.v index 3821bb5..fe7bbcb 100644 --- a/rtl/ip/matmul/matmul_axi_slave.v +++ b/rtl/ip/matmul/matmul_axi_slave.v @@ -365,6 +365,7 @@ module matmul_axi_slave ( reg mult_start; wire mult_done [0:3]; wire [63:0] mult_p [0:3]; + reg [63:0] mult_p_r [0:3]; // registered for stable accumulation reg [31:0] m_in_a [0:3]; reg [31:0] m_in_b [0:3]; @@ -429,17 +430,21 @@ module matmul_axi_slave ( C_WAIT_MULT: begin mult_start <= 1'b0; if (mult_done[0] && mult_done[1] && mult_done[2] && mult_done[3]) begin + mult_p_r[0] <= mult_p[0]; + mult_p_r[1] <= mult_p[1]; + mult_p_r[2] <= mult_p[2]; + mult_p_r[3] <= mult_p[3]; state <= C_ACCUM; end end C_ACCUM: begin if (cur_bank == 1'b0) begin - b0_c[calc_idx] <= {2'b0, mult_p[0]} + {2'b0, mult_p[1]} + - {2'b0, mult_p[2]} + {2'b0, mult_p[3]}; + b0_c[calc_idx] <= {2'b0, mult_p_r[0]} + {2'b0, mult_p_r[1]} + + {2'b0, mult_p_r[2]} + {2'b0, mult_p_r[3]}; end else begin - b1_c[calc_idx] <= {2'b0, mult_p[0]} + {2'b0, mult_p[1]} + - {2'b0, mult_p[2]} + {2'b0, mult_p[3]}; + b1_c[calc_idx] <= {2'b0, mult_p_r[0]} + {2'b0, mult_p_r[1]} + + {2'b0, mult_p_r[2]} + {2'b0, mult_p_r[3]}; end if (calc_idx == 4'd15) begin